1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DAL_DC_35_SMU_H_ 27 #define DAL_DC_35_SMU_H_ 28 29 #include "os_types.h" 30 31 #ifndef PMFW_DRIVER_IF_H 32 #define PMFW_DRIVER_IF_H 33 #define PMFW_DRIVER_IF_VERSION 4 34 35 typedef enum { 36 DSPCLK_DCFCLK = 0, 37 DSPCLK_DISPCLK, 38 DSPCLK_PIXCLK, 39 DSPCLK_PHYCLK, 40 DSPCLK_COUNT, 41 } DSPCLK_e; 42 43 typedef struct { 44 uint16_t Freq; // in MHz 45 uint16_t Vid; // min voltage in SVI3 VID 46 } DisplayClockTable_t; 47 48 typedef struct { 49 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 50 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 51 uint16_t MinMclk; 52 uint16_t MaxMclk; 53 54 uint8_t WmSetting; 55 uint8_t WmType; // Used for normal pstate change or memory retraining 56 uint8_t Padding[2]; 57 } WatermarkRowGeneric_t; 58 59 #define NUM_WM_RANGES 4 60 #define WM_PSTATE_CHG 0 61 #define WM_RETRAINING 1 62 63 typedef enum { 64 WM_SOCCLK = 0, 65 WM_DCFCLK, 66 WM_COUNT, 67 } WM_CLOCK_e; 68 69 typedef struct { 70 // Watermarks 71 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 72 73 uint32_t MmHubPadding[7]; // SMU internal use 74 } Watermarks_t; 75 76 #define NUM_DCFCLK_DPM_LEVELS 8 77 #define NUM_DISPCLK_DPM_LEVELS 8 78 #define NUM_DPPCLK_DPM_LEVELS 8 79 #define NUM_SOCCLK_DPM_LEVELS 8 80 #define NUM_VCN_DPM_LEVELS 8 81 #define NUM_SOC_VOLTAGE_LEVELS 8 82 #define NUM_VPE_DPM_LEVELS 8 83 #define NUM_FCLK_DPM_LEVELS 8 84 #define NUM_MEM_PSTATE_LEVELS 4 85 86 typedef enum{ 87 WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1; 88 WCK_RATIO_1_2, 89 WCK_RATIO_1_4, 90 WCK_RATIO_MAX 91 } WCK_RATIO_e; 92 93 typedef struct { 94 uint32_t UClk; 95 uint32_t MemClk; 96 uint32_t Voltage; 97 uint8_t WckRatio; 98 uint8_t Spare[3]; 99 } MemPstateTable_t; 100 101 //Freq in MHz 102 //Voltage in milli volts with 2 fractional bits 103 typedef struct { 104 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 105 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; 106 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; 107 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 108 uint32_t VClocks[NUM_VCN_DPM_LEVELS]; 109 uint32_t DClocks[NUM_VCN_DPM_LEVELS]; 110 uint32_t VPEClocks[NUM_VPE_DPM_LEVELS]; 111 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS]; 112 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS]; 113 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; 114 MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS]; 115 116 uint8_t NumDcfClkLevelsEnabled; 117 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk 118 uint8_t NumSocClkLevelsEnabled; 119 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk 120 uint8_t VpeClkLevelsEnabled; 121 uint8_t NumMemPstatesEnabled; 122 uint8_t NumFclkLevelsEnabled; 123 uint8_t spare[2]; 124 125 uint32_t MinGfxClk; 126 uint32_t MaxGfxClk; 127 } DpmClocks_t_dcn35; 128 129 130 // Throttler Status Bitmask 131 132 133 134 135 136 137 138 139 140 141 142 #define TABLE_BIOS_IF 0 // Called by BIOS 143 #define TABLE_WATERMARKS 1 // Called by DAL through VBIOS 144 #define TABLE_CUSTOM_DPM 2 // Called by Driver 145 #define TABLE_SPARE1 3 146 #define TABLE_DPMCLOCKS 4 // Called by Driver 147 #define TABLE_MOMENTARY_PM 5 // Called by Tools 148 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log 149 #define TABLE_SMU_METRICS 7 // Called by Driver 150 #define TABLE_COUNT 8 151 152 #endif 153 154 struct dcn35_watermarks { 155 // Watermarks 156 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 157 158 uint32_t MmHubPadding[7]; // SMU internal use 159 }; 160 161 struct dcn35_smu_dpm_clks { 162 DpmClocks_t_dcn35 *dpm_clks; 163 union large_integer mc_address; 164 }; 165 166 /* TODO: taken from vgh, may not be correct */ 167 struct display_idle_optimization { 168 unsigned int df_request_disabled : 1; 169 unsigned int phy_ref_clk_off : 1; 170 unsigned int s0i2_rdy : 1; 171 unsigned int reserved : 29; 172 }; 173 174 union display_idle_optimization_u { 175 struct display_idle_optimization idle_info; 176 uint32_t data; 177 }; 178 179 int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 180 int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 181 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 182 int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); 183 int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); 184 int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 185 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); 186 void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 187 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); 188 void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 189 void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 190 void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 191 void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 192 193 void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support); 194 void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); 195 void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 196 197 int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr); 198 int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr); 199 int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr); 200 int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr); 201 void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param); 202 uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr); 203 #endif /* DAL_DC_35_SMU_H_ */ 204