1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 /* forward declaration */ 44 struct aux_payload; 45 struct set_config_cmd_payload; 46 struct dmub_notification; 47 48 #define DC_VER "3.2.230" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MIN_VIEWPORT_SIZE 12 54 #define MAX_NUM_EDP 2 55 56 /* Display Core Interfaces */ 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 enum dp_protocol_version { 63 DP_VERSION_1_4, 64 }; 65 66 enum dc_plane_type { 67 DC_PLANE_TYPE_INVALID, 68 DC_PLANE_TYPE_DCE_RGB, 69 DC_PLANE_TYPE_DCE_UNDERLAY, 70 DC_PLANE_TYPE_DCN_UNIVERSAL, 71 }; 72 73 // Sizes defined as multiples of 64KB 74 enum det_size { 75 DET_SIZE_DEFAULT = 0, 76 DET_SIZE_192KB = 3, 77 DET_SIZE_256KB = 4, 78 DET_SIZE_320KB = 5, 79 DET_SIZE_384KB = 6 80 }; 81 82 83 struct dc_plane_cap { 84 enum dc_plane_type type; 85 uint32_t per_pixel_alpha : 1; 86 struct { 87 uint32_t argb8888 : 1; 88 uint32_t nv12 : 1; 89 uint32_t fp16 : 1; 90 uint32_t p010 : 1; 91 uint32_t ayuv : 1; 92 } pixel_format_support; 93 // max upscaling factor x1000 94 // upscaling factors are always >= 1 95 // for example, 1080p -> 8K is 4.0, or 4000 raw value 96 struct { 97 uint32_t argb8888; 98 uint32_t nv12; 99 uint32_t fp16; 100 } max_upscale_factor; 101 // max downscale factor x1000 102 // downscale factors are always <= 1 103 // for example, 8K -> 1080p is 0.25, or 250 raw value 104 struct { 105 uint32_t argb8888; 106 uint32_t nv12; 107 uint32_t fp16; 108 } max_downscale_factor; 109 // minimal width/height 110 uint32_t min_width; 111 uint32_t min_height; 112 }; 113 114 /** 115 * DOC: color-management-caps 116 * 117 * **Color management caps (DPP and MPC)** 118 * 119 * Modules/color calculates various color operations which are translated to 120 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 121 * DCN1, every new generation comes with fairly major differences in color 122 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 123 * decide mapping to HW block based on logical capabilities. 124 */ 125 126 /** 127 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 128 * @srgb: RGB color space transfer func 129 * @bt2020: BT.2020 transfer func 130 * @gamma2_2: standard gamma 131 * @pq: perceptual quantizer transfer function 132 * @hlg: hybrid log–gamma transfer function 133 */ 134 struct rom_curve_caps { 135 uint16_t srgb : 1; 136 uint16_t bt2020 : 1; 137 uint16_t gamma2_2 : 1; 138 uint16_t pq : 1; 139 uint16_t hlg : 1; 140 }; 141 142 /** 143 * struct dpp_color_caps - color pipeline capabilities for display pipe and 144 * plane blocks 145 * 146 * @dcn_arch: all DCE generations treated the same 147 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 148 * just plain 256-entry lookup 149 * @icsc: input color space conversion 150 * @dgam_ram: programmable degamma LUT 151 * @post_csc: post color space conversion, before gamut remap 152 * @gamma_corr: degamma correction 153 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 154 * with MPC by setting mpc:shared_3d_lut flag 155 * @ogam_ram: programmable out/blend gamma LUT 156 * @ocsc: output color space conversion 157 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 158 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 159 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 160 * 161 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 162 */ 163 struct dpp_color_caps { 164 uint16_t dcn_arch : 1; 165 uint16_t input_lut_shared : 1; 166 uint16_t icsc : 1; 167 uint16_t dgam_ram : 1; 168 uint16_t post_csc : 1; 169 uint16_t gamma_corr : 1; 170 uint16_t hw_3d_lut : 1; 171 uint16_t ogam_ram : 1; 172 uint16_t ocsc : 1; 173 uint16_t dgam_rom_for_yuv : 1; 174 struct rom_curve_caps dgam_rom_caps; 175 struct rom_curve_caps ogam_rom_caps; 176 }; 177 178 /** 179 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 180 * plane combined blocks 181 * 182 * @gamut_remap: color transformation matrix 183 * @ogam_ram: programmable out gamma LUT 184 * @ocsc: output color space conversion matrix 185 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 186 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 187 * instance 188 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 189 */ 190 struct mpc_color_caps { 191 uint16_t gamut_remap : 1; 192 uint16_t ogam_ram : 1; 193 uint16_t ocsc : 1; 194 uint16_t num_3dluts : 3; 195 uint16_t shared_3d_lut:1; 196 struct rom_curve_caps ogam_rom_caps; 197 }; 198 199 /** 200 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 201 * @dpp: color pipes caps for DPP 202 * @mpc: color pipes caps for MPC 203 */ 204 struct dc_color_caps { 205 struct dpp_color_caps dpp; 206 struct mpc_color_caps mpc; 207 }; 208 209 struct dc_dmub_caps { 210 bool psr; 211 bool mclk_sw; 212 }; 213 214 struct dc_caps { 215 uint32_t max_streams; 216 uint32_t max_links; 217 uint32_t max_audios; 218 uint32_t max_slave_planes; 219 uint32_t max_slave_yuv_planes; 220 uint32_t max_slave_rgb_planes; 221 uint32_t max_planes; 222 uint32_t max_downscale_ratio; 223 uint32_t i2c_speed_in_khz; 224 uint32_t i2c_speed_in_khz_hdcp; 225 uint32_t dmdata_alloc_size; 226 unsigned int max_cursor_size; 227 unsigned int max_video_width; 228 unsigned int min_horizontal_blanking_period; 229 int linear_pitch_alignment; 230 bool dcc_const_color; 231 bool dynamic_audio; 232 bool is_apu; 233 bool dual_link_dvi; 234 bool post_blend_color_processing; 235 bool force_dp_tps4_for_cp2520; 236 bool disable_dp_clk_share; 237 bool psp_setup_panel_mode; 238 bool extended_aux_timeout_support; 239 bool dmcub_support; 240 bool zstate_support; 241 uint32_t num_of_internal_disp; 242 enum dp_protocol_version max_dp_protocol_version; 243 unsigned int mall_size_per_mem_channel; 244 unsigned int mall_size_total; 245 unsigned int cursor_cache_size; 246 struct dc_plane_cap planes[MAX_PLANES]; 247 struct dc_color_caps color; 248 struct dc_dmub_caps dmub_caps; 249 bool dp_hpo; 250 bool dp_hdmi21_pcon_support; 251 bool edp_dsc_support; 252 bool vbios_lttpr_aware; 253 bool vbios_lttpr_enable; 254 uint32_t max_otg_num; 255 uint32_t max_cab_allocation_bytes; 256 uint32_t cache_line_size; 257 uint32_t cache_num_ways; 258 uint16_t subvp_fw_processing_delay_us; 259 uint8_t subvp_drr_max_vblank_margin_us; 260 uint16_t subvp_prefetch_end_to_mall_start_us; 261 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 262 uint16_t subvp_pstate_allow_width_us; 263 uint16_t subvp_vertical_int_margin_us; 264 bool seamless_odm; 265 uint8_t subvp_drr_vblank_start_margin_us; 266 }; 267 268 struct dc_bug_wa { 269 bool no_connect_phy_config; 270 bool dedcn20_305_wa; 271 bool skip_clock_update; 272 bool lt_early_cr_pattern; 273 }; 274 275 struct dc_dcc_surface_param { 276 struct dc_size surface_size; 277 enum surface_pixel_format format; 278 enum swizzle_mode_values swizzle_mode; 279 enum dc_scan_direction scan; 280 }; 281 282 struct dc_dcc_setting { 283 unsigned int max_compressed_blk_size; 284 unsigned int max_uncompressed_blk_size; 285 bool independent_64b_blks; 286 //These bitfields to be used starting with DCN 287 struct { 288 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 289 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 290 uint32_t dcc_256_128_128 : 1; //available starting with DCN 291 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 292 } dcc_controls; 293 }; 294 295 struct dc_surface_dcc_cap { 296 union { 297 struct { 298 struct dc_dcc_setting rgb; 299 } grph; 300 301 struct { 302 struct dc_dcc_setting luma; 303 struct dc_dcc_setting chroma; 304 } video; 305 }; 306 307 bool capable; 308 bool const_color_support; 309 }; 310 311 struct dc_static_screen_params { 312 struct { 313 bool force_trigger; 314 bool cursor_update; 315 bool surface_update; 316 bool overlay_update; 317 } triggers; 318 unsigned int num_frames; 319 }; 320 321 322 /* Surface update type is used by dc_update_surfaces_and_stream 323 * The update type is determined at the very beginning of the function based 324 * on parameters passed in and decides how much programming (or updating) is 325 * going to be done during the call. 326 * 327 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 328 * logical calculations or hardware register programming. This update MUST be 329 * ISR safe on windows. Currently fast update will only be used to flip surface 330 * address. 331 * 332 * UPDATE_TYPE_MED is used for slower updates which require significant hw 333 * re-programming however do not affect bandwidth consumption or clock 334 * requirements. At present, this is the level at which front end updates 335 * that do not require us to run bw_calcs happen. These are in/out transfer func 336 * updates, viewport offset changes, recout size changes and pixel depth changes. 337 * This update can be done at ISR, but we want to minimize how often this happens. 338 * 339 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 340 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 341 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 342 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 343 * a full update. This cannot be done at ISR level and should be a rare event. 344 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 345 * underscan we don't expect to see this call at all. 346 */ 347 348 enum surface_update_type { 349 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 350 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 351 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 352 }; 353 354 /* Forward declaration*/ 355 struct dc; 356 struct dc_plane_state; 357 struct dc_state; 358 359 360 struct dc_cap_funcs { 361 bool (*get_dcc_compression_cap)(const struct dc *dc, 362 const struct dc_dcc_surface_param *input, 363 struct dc_surface_dcc_cap *output); 364 }; 365 366 struct link_training_settings; 367 368 union allow_lttpr_non_transparent_mode { 369 struct { 370 bool DP1_4A : 1; 371 bool DP2_0 : 1; 372 } bits; 373 unsigned char raw; 374 }; 375 376 /* Structure to hold configuration flags set by dm at dc creation. */ 377 struct dc_config { 378 bool gpu_vm_support; 379 bool disable_disp_pll_sharing; 380 bool fbc_support; 381 bool disable_fractional_pwm; 382 bool allow_seamless_boot_optimization; 383 bool seamless_boot_edp_requested; 384 bool edp_not_connected; 385 bool edp_no_power_sequencing; 386 bool force_enum_edp; 387 bool forced_clocks; 388 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 389 bool multi_mon_pp_mclk_switch; 390 bool disable_dmcu; 391 bool enable_4to1MPC; 392 bool enable_windowed_mpo_odm; 393 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 394 uint32_t allow_edp_hotplug_detection; 395 bool clamp_min_dcfclk; 396 uint64_t vblank_alignment_dto_params; 397 uint8_t vblank_alignment_max_frame_time_diff; 398 bool is_asymmetric_memory; 399 bool is_single_rank_dimm; 400 bool is_vmin_only_asic; 401 bool use_pipe_ctx_sync_logic; 402 bool ignore_dpref_ss; 403 bool enable_mipi_converter_optimization; 404 bool use_default_clock_table; 405 bool force_bios_enable_lttpr; 406 uint8_t force_bios_fixed_vs; 407 int sdpif_request_limit_words_per_umc; 408 bool use_old_fixed_vs_sequence; 409 bool disable_subvp_drr; 410 }; 411 412 enum visual_confirm { 413 VISUAL_CONFIRM_DISABLE = 0, 414 VISUAL_CONFIRM_SURFACE = 1, 415 VISUAL_CONFIRM_HDR = 2, 416 VISUAL_CONFIRM_MPCTREE = 4, 417 VISUAL_CONFIRM_PSR = 5, 418 VISUAL_CONFIRM_SWAPCHAIN = 6, 419 VISUAL_CONFIRM_FAMS = 7, 420 VISUAL_CONFIRM_SWIZZLE = 9, 421 VISUAL_CONFIRM_SUBVP = 14, 422 }; 423 424 enum dc_psr_power_opts { 425 psr_power_opt_invalid = 0x0, 426 psr_power_opt_smu_opt_static_screen = 0x1, 427 psr_power_opt_z10_static_screen = 0x10, 428 psr_power_opt_ds_disable_allow = 0x100, 429 }; 430 431 enum dml_hostvm_override_opts { 432 DML_HOSTVM_NO_OVERRIDE = 0x0, 433 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 434 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 435 }; 436 437 enum dcc_option { 438 DCC_ENABLE = 0, 439 DCC_DISABLE = 1, 440 DCC_HALF_REQ_DISALBE = 2, 441 }; 442 443 /** 444 * enum pipe_split_policy - Pipe split strategy supported by DCN 445 * 446 * This enum is used to define the pipe split policy supported by DCN. By 447 * default, DC favors MPC_SPLIT_DYNAMIC. 448 */ 449 enum pipe_split_policy { 450 /** 451 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 452 * pipe in order to bring the best trade-off between performance and 453 * power consumption. This is the recommended option. 454 */ 455 MPC_SPLIT_DYNAMIC = 0, 456 457 /** 458 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 459 * try any sort of split optimization. 460 */ 461 MPC_SPLIT_AVOID = 1, 462 463 /** 464 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 465 * optimize the pipe utilization when using a single display; if the 466 * user connects to a second display, DC will avoid pipe split. 467 */ 468 MPC_SPLIT_AVOID_MULT_DISP = 2, 469 }; 470 471 enum wm_report_mode { 472 WM_REPORT_DEFAULT = 0, 473 WM_REPORT_OVERRIDE = 1, 474 }; 475 enum dtm_pstate{ 476 dtm_level_p0 = 0,/*highest voltage*/ 477 dtm_level_p1, 478 dtm_level_p2, 479 dtm_level_p3, 480 dtm_level_p4,/*when active_display_count = 0*/ 481 }; 482 483 enum dcn_pwr_state { 484 DCN_PWR_STATE_UNKNOWN = -1, 485 DCN_PWR_STATE_MISSION_MODE = 0, 486 DCN_PWR_STATE_LOW_POWER = 3, 487 }; 488 489 enum dcn_zstate_support_state { 490 DCN_ZSTATE_SUPPORT_UNKNOWN, 491 DCN_ZSTATE_SUPPORT_ALLOW, 492 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 493 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 494 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 495 DCN_ZSTATE_SUPPORT_DISALLOW, 496 }; 497 498 /** 499 * struct dc_clocks - DC pipe clocks 500 * 501 * For any clocks that may differ per pipe only the max is stored in this 502 * structure 503 */ 504 struct dc_clocks { 505 int dispclk_khz; 506 int actual_dispclk_khz; 507 int dppclk_khz; 508 int actual_dppclk_khz; 509 int disp_dpp_voltage_level_khz; 510 int dcfclk_khz; 511 int socclk_khz; 512 int dcfclk_deep_sleep_khz; 513 int fclk_khz; 514 int phyclk_khz; 515 int dramclk_khz; 516 bool p_state_change_support; 517 enum dcn_zstate_support_state zstate_support; 518 bool dtbclk_en; 519 int ref_dtbclk_khz; 520 bool fclk_p_state_change_support; 521 enum dcn_pwr_state pwr_state; 522 /* 523 * Elements below are not compared for the purposes of 524 * optimization required 525 */ 526 bool prev_p_state_change_support; 527 bool fclk_prev_p_state_change_support; 528 int num_ways; 529 530 /* 531 * @fw_based_mclk_switching 532 * 533 * DC has a mechanism that leverage the variable refresh rate to switch 534 * memory clock in cases that we have a large latency to achieve the 535 * memory clock change and a short vblank window. DC has some 536 * requirements to enable this feature, and this field describes if the 537 * system support or not such a feature. 538 */ 539 bool fw_based_mclk_switching; 540 bool fw_based_mclk_switching_shut_down; 541 int prev_num_ways; 542 enum dtm_pstate dtm_level; 543 int max_supported_dppclk_khz; 544 int max_supported_dispclk_khz; 545 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 546 int bw_dispclk_khz; 547 }; 548 549 struct dc_bw_validation_profile { 550 bool enable; 551 552 unsigned long long total_ticks; 553 unsigned long long voltage_level_ticks; 554 unsigned long long watermark_ticks; 555 unsigned long long rq_dlg_ticks; 556 557 unsigned long long total_count; 558 unsigned long long skip_fast_count; 559 unsigned long long skip_pass_count; 560 unsigned long long skip_fail_count; 561 }; 562 563 #define BW_VAL_TRACE_SETUP() \ 564 unsigned long long end_tick = 0; \ 565 unsigned long long voltage_level_tick = 0; \ 566 unsigned long long watermark_tick = 0; \ 567 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 568 dm_get_timestamp(dc->ctx) : 0 569 570 #define BW_VAL_TRACE_COUNT() \ 571 if (dc->debug.bw_val_profile.enable) \ 572 dc->debug.bw_val_profile.total_count++ 573 574 #define BW_VAL_TRACE_SKIP(status) \ 575 if (dc->debug.bw_val_profile.enable) { \ 576 if (!voltage_level_tick) \ 577 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 578 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 579 } 580 581 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 582 if (dc->debug.bw_val_profile.enable) \ 583 voltage_level_tick = dm_get_timestamp(dc->ctx) 584 585 #define BW_VAL_TRACE_END_WATERMARKS() \ 586 if (dc->debug.bw_val_profile.enable) \ 587 watermark_tick = dm_get_timestamp(dc->ctx) 588 589 #define BW_VAL_TRACE_FINISH() \ 590 if (dc->debug.bw_val_profile.enable) { \ 591 end_tick = dm_get_timestamp(dc->ctx); \ 592 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 593 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 594 if (watermark_tick) { \ 595 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 596 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 597 } \ 598 } 599 600 union mem_low_power_enable_options { 601 struct { 602 bool vga: 1; 603 bool i2c: 1; 604 bool dmcu: 1; 605 bool dscl: 1; 606 bool cm: 1; 607 bool mpc: 1; 608 bool optc: 1; 609 bool vpg: 1; 610 bool afmt: 1; 611 } bits; 612 uint32_t u32All; 613 }; 614 615 union root_clock_optimization_options { 616 struct { 617 bool dpp: 1; 618 bool dsc: 1; 619 bool hdmistream: 1; 620 bool hdmichar: 1; 621 bool dpstream: 1; 622 bool symclk32_se: 1; 623 bool symclk32_le: 1; 624 bool symclk_fe: 1; 625 bool physymclk: 1; 626 bool dpiasymclk: 1; 627 uint32_t reserved: 22; 628 } bits; 629 uint32_t u32All; 630 }; 631 632 union dpia_debug_options { 633 struct { 634 uint32_t disable_dpia:1; /* bit 0 */ 635 uint32_t force_non_lttpr:1; /* bit 1 */ 636 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 637 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 638 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 639 uint32_t reserved:27; 640 } bits; 641 uint32_t raw; 642 }; 643 644 /* AUX wake work around options 645 * 0: enable/disable work around 646 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 647 * 15-2: reserved 648 * 31-16: timeout in ms 649 */ 650 union aux_wake_wa_options { 651 struct { 652 uint32_t enable_wa : 1; 653 uint32_t use_default_timeout : 1; 654 uint32_t rsvd: 14; 655 uint32_t timeout_ms : 16; 656 } bits; 657 uint32_t raw; 658 }; 659 660 struct dc_debug_data { 661 uint32_t ltFailCount; 662 uint32_t i2cErrorCount; 663 uint32_t auxErrorCount; 664 }; 665 666 struct dc_phy_addr_space_config { 667 struct { 668 uint64_t start_addr; 669 uint64_t end_addr; 670 uint64_t fb_top; 671 uint64_t fb_offset; 672 uint64_t fb_base; 673 uint64_t agp_top; 674 uint64_t agp_bot; 675 uint64_t agp_base; 676 } system_aperture; 677 678 struct { 679 uint64_t page_table_start_addr; 680 uint64_t page_table_end_addr; 681 uint64_t page_table_base_addr; 682 bool base_addr_is_mc_addr; 683 } gart_config; 684 685 bool valid; 686 bool is_hvm_enabled; 687 uint64_t page_table_default_page_addr; 688 }; 689 690 struct dc_virtual_addr_space_config { 691 uint64_t page_table_base_addr; 692 uint64_t page_table_start_addr; 693 uint64_t page_table_end_addr; 694 uint32_t page_table_block_size_in_bytes; 695 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 696 }; 697 698 struct dc_bounding_box_overrides { 699 int sr_exit_time_ns; 700 int sr_enter_plus_exit_time_ns; 701 int urgent_latency_ns; 702 int percent_of_ideal_drambw; 703 int dram_clock_change_latency_ns; 704 int dummy_clock_change_latency_ns; 705 int fclk_clock_change_latency_ns; 706 /* This forces a hard min on the DCFCLK we use 707 * for DML. Unlike the debug option for forcing 708 * DCFCLK, this override affects watermark calculations 709 */ 710 int min_dcfclk_mhz; 711 }; 712 713 struct dc_state; 714 struct resource_pool; 715 struct dce_hwseq; 716 struct link_service; 717 718 /** 719 * struct dc_debug_options - DC debug struct 720 * 721 * This struct provides a simple mechanism for developers to change some 722 * configurations, enable/disable features, and activate extra debug options. 723 * This can be very handy to narrow down whether some specific feature is 724 * causing an issue or not. 725 */ 726 struct dc_debug_options { 727 bool native422_support; 728 bool disable_dsc; 729 enum visual_confirm visual_confirm; 730 int visual_confirm_rect_height; 731 732 bool sanity_checks; 733 bool max_disp_clk; 734 bool surface_trace; 735 bool timing_trace; 736 bool clock_trace; 737 bool validation_trace; 738 bool bandwidth_calcs_trace; 739 int max_downscale_src_width; 740 741 /* stutter efficiency related */ 742 bool disable_stutter; 743 bool use_max_lb; 744 enum dcc_option disable_dcc; 745 746 /** 747 * @pipe_split_policy: Define which pipe split policy is used by the 748 * display core. 749 */ 750 enum pipe_split_policy pipe_split_policy; 751 bool force_single_disp_pipe_split; 752 bool voltage_align_fclk; 753 bool disable_min_fclk; 754 755 bool disable_dfs_bypass; 756 bool disable_dpp_power_gate; 757 bool disable_hubp_power_gate; 758 bool disable_dsc_power_gate; 759 int dsc_min_slice_height_override; 760 int dsc_bpp_increment_div; 761 bool disable_pplib_wm_range; 762 enum wm_report_mode pplib_wm_report_mode; 763 unsigned int min_disp_clk_khz; 764 unsigned int min_dpp_clk_khz; 765 unsigned int min_dram_clk_khz; 766 int sr_exit_time_dpm0_ns; 767 int sr_enter_plus_exit_time_dpm0_ns; 768 int sr_exit_time_ns; 769 int sr_enter_plus_exit_time_ns; 770 int urgent_latency_ns; 771 uint32_t underflow_assert_delay_us; 772 int percent_of_ideal_drambw; 773 int dram_clock_change_latency_ns; 774 bool optimized_watermark; 775 int always_scale; 776 bool disable_pplib_clock_request; 777 bool disable_clock_gate; 778 bool disable_mem_low_power; 779 bool pstate_enabled; 780 bool disable_dmcu; 781 bool force_abm_enable; 782 bool disable_stereo_support; 783 bool vsr_support; 784 bool performance_trace; 785 bool az_endpoint_mute_only; 786 bool always_use_regamma; 787 bool recovery_enabled; 788 bool avoid_vbios_exec_table; 789 bool scl_reset_length10; 790 bool hdmi20_disable; 791 bool skip_detection_link_training; 792 uint32_t edid_read_retry_times; 793 unsigned int force_odm_combine; //bit vector based on otg inst 794 unsigned int seamless_boot_odm_combine; 795 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 796 int minimum_z8_residency_time; 797 bool disable_z9_mpc; 798 unsigned int force_fclk_khz; 799 bool enable_tri_buf; 800 bool dmub_offload_enabled; 801 bool dmcub_emulation; 802 bool disable_idle_power_optimizations; 803 unsigned int mall_size_override; 804 unsigned int mall_additional_timer_percent; 805 bool mall_error_as_fatal; 806 bool dmub_command_table; /* for testing only */ 807 struct dc_bw_validation_profile bw_val_profile; 808 bool disable_fec; 809 bool disable_48mhz_pwrdwn; 810 /* This forces a hard min on the DCFCLK requested to SMU/PP 811 * watermarks are not affected. 812 */ 813 unsigned int force_min_dcfclk_mhz; 814 int dwb_fi_phase; 815 bool disable_timing_sync; 816 bool cm_in_bypass; 817 int force_clock_mode;/*every mode change.*/ 818 819 bool disable_dram_clock_change_vactive_support; 820 bool validate_dml_output; 821 bool enable_dmcub_surface_flip; 822 bool usbc_combo_phy_reset_wa; 823 bool enable_dram_clock_change_one_display_vactive; 824 /* TODO - remove once tested */ 825 bool legacy_dp2_lt; 826 bool set_mst_en_for_sst; 827 bool disable_uhbr; 828 bool force_dp2_lt_fallback_method; 829 bool ignore_cable_id; 830 union mem_low_power_enable_options enable_mem_low_power; 831 union root_clock_optimization_options root_clock_optimization; 832 bool hpo_optimization; 833 bool force_vblank_alignment; 834 835 /* Enable dmub aux for legacy ddc */ 836 bool enable_dmub_aux_for_legacy_ddc; 837 bool disable_fams; 838 /* FEC/PSR1 sequence enable delay in 100us */ 839 uint8_t fec_enable_delay_in100us; 840 bool enable_driver_sequence_debug; 841 enum det_size crb_alloc_policy; 842 int crb_alloc_policy_min_disp_count; 843 bool disable_z10; 844 bool enable_z9_disable_interface; 845 bool psr_skip_crtc_disable; 846 union dpia_debug_options dpia_debug; 847 bool disable_fixed_vs_aux_timeout_wa; 848 bool force_disable_subvp; 849 bool force_subvp_mclk_switch; 850 bool allow_sw_cursor_fallback; 851 unsigned int force_subvp_num_ways; 852 unsigned int force_mall_ss_num_ways; 853 bool alloc_extra_way_for_cursor; 854 uint32_t subvp_extra_lines; 855 bool force_usr_allow; 856 /* uses value at boot and disables switch */ 857 bool disable_dtb_ref_clk_switch; 858 uint32_t fixed_vs_aux_delay_config_wa; 859 bool extended_blank_optimization; 860 union aux_wake_wa_options aux_wake_wa; 861 uint32_t mst_start_top_delay; 862 uint8_t psr_power_use_phy_fsm; 863 enum dml_hostvm_override_opts dml_hostvm_override; 864 bool dml_disallow_alternate_prefetch_modes; 865 bool use_legacy_soc_bb_mechanism; 866 bool exit_idle_opt_for_cursor_updates; 867 bool enable_single_display_2to1_odm_policy; 868 bool enable_double_buffered_dsc_pg_support; 869 bool enable_dp_dig_pixel_rate_div_policy; 870 enum lttpr_mode lttpr_mode_override; 871 unsigned int dsc_delay_factor_wa_x1000; 872 unsigned int min_prefetch_in_strobe_ns; 873 bool disable_unbounded_requesting; 874 bool dig_fifo_off_in_blank; 875 bool temp_mst_deallocation_sequence; 876 bool override_dispclk_programming; 877 bool disable_fpo_optimizations; 878 bool support_eDP1_5; 879 uint32_t fpo_vactive_margin_us; 880 bool disable_fpo_vactive; 881 bool disable_boot_optimizations; 882 }; 883 884 struct gpu_info_soc_bounding_box_v1_0; 885 struct dc { 886 struct dc_debug_options debug; 887 struct dc_versions versions; 888 struct dc_caps caps; 889 struct dc_cap_funcs cap_funcs; 890 struct dc_config config; 891 struct dc_bounding_box_overrides bb_overrides; 892 struct dc_bug_wa work_arounds; 893 struct dc_context *ctx; 894 struct dc_phy_addr_space_config vm_pa_config; 895 896 uint8_t link_count; 897 struct dc_link *links[MAX_PIPES * 2]; 898 struct link_service *link_srv; 899 900 struct dc_state *current_state; 901 struct resource_pool *res_pool; 902 903 struct clk_mgr *clk_mgr; 904 905 /* Display Engine Clock levels */ 906 struct dm_pp_clock_levels sclk_lvls; 907 908 /* Inputs into BW and WM calculations. */ 909 struct bw_calcs_dceip *bw_dceip; 910 struct bw_calcs_vbios *bw_vbios; 911 struct dcn_soc_bounding_box *dcn_soc; 912 struct dcn_ip_params *dcn_ip; 913 struct display_mode_lib dml; 914 915 /* HW functions */ 916 struct hw_sequencer_funcs hwss; 917 struct dce_hwseq *hwseq; 918 919 /* Require to optimize clocks and bandwidth for added/removed planes */ 920 bool optimized_required; 921 bool wm_optimized_required; 922 bool idle_optimizations_allowed; 923 bool enable_c20_dtm_b0; 924 925 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 926 927 /* FBC compressor */ 928 struct compressor *fbc_compressor; 929 930 struct dc_debug_data debug_data; 931 struct dpcd_vendor_signature vendor_signature; 932 933 const char *build_id; 934 struct vm_helper *vm_helper; 935 936 uint32_t *dcn_reg_offsets; 937 uint32_t *nbio_reg_offsets; 938 939 /* Scratch memory */ 940 struct { 941 struct { 942 /* 943 * For matching clock_limits table in driver with table 944 * from PMFW. 945 */ 946 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 947 } update_bw_bounding_box; 948 } scratch; 949 }; 950 951 enum frame_buffer_mode { 952 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 953 FRAME_BUFFER_MODE_ZFB_ONLY, 954 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 955 } ; 956 957 struct dchub_init_data { 958 int64_t zfb_phys_addr_base; 959 int64_t zfb_mc_base_addr; 960 uint64_t zfb_size_in_byte; 961 enum frame_buffer_mode fb_mode; 962 bool dchub_initialzied; 963 bool dchub_info_valid; 964 }; 965 966 struct dc_init_data { 967 struct hw_asic_id asic_id; 968 void *driver; /* ctx */ 969 struct cgs_device *cgs_device; 970 struct dc_bounding_box_overrides bb_overrides; 971 972 int num_virtual_links; 973 /* 974 * If 'vbios_override' not NULL, it will be called instead 975 * of the real VBIOS. Intended use is Diagnostics on FPGA. 976 */ 977 struct dc_bios *vbios_override; 978 enum dce_environment dce_environment; 979 980 struct dmub_offload_funcs *dmub_if; 981 struct dc_reg_helper_state *dmub_offload; 982 983 struct dc_config flags; 984 uint64_t log_mask; 985 986 struct dpcd_vendor_signature vendor_signature; 987 bool force_smu_not_present; 988 /* 989 * IP offset for run time initializaion of register addresses 990 * 991 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 992 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 993 * before them. 994 */ 995 uint32_t *dcn_reg_offsets; 996 uint32_t *nbio_reg_offsets; 997 }; 998 999 struct dc_callback_init { 1000 struct cp_psp cp_psp; 1001 }; 1002 1003 struct dc *dc_create(const struct dc_init_data *init_params); 1004 void dc_hardware_init(struct dc *dc); 1005 1006 int dc_get_vmid_use_vector(struct dc *dc); 1007 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1008 /* Returns the number of vmids supported */ 1009 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1010 void dc_init_callbacks(struct dc *dc, 1011 const struct dc_callback_init *init_params); 1012 void dc_deinit_callbacks(struct dc *dc); 1013 void dc_destroy(struct dc **dc); 1014 1015 /* Surface Interfaces */ 1016 1017 enum { 1018 TRANSFER_FUNC_POINTS = 1025 1019 }; 1020 1021 struct dc_hdr_static_metadata { 1022 /* display chromaticities and white point in units of 0.00001 */ 1023 unsigned int chromaticity_green_x; 1024 unsigned int chromaticity_green_y; 1025 unsigned int chromaticity_blue_x; 1026 unsigned int chromaticity_blue_y; 1027 unsigned int chromaticity_red_x; 1028 unsigned int chromaticity_red_y; 1029 unsigned int chromaticity_white_point_x; 1030 unsigned int chromaticity_white_point_y; 1031 1032 uint32_t min_luminance; 1033 uint32_t max_luminance; 1034 uint32_t maximum_content_light_level; 1035 uint32_t maximum_frame_average_light_level; 1036 }; 1037 1038 enum dc_transfer_func_type { 1039 TF_TYPE_PREDEFINED, 1040 TF_TYPE_DISTRIBUTED_POINTS, 1041 TF_TYPE_BYPASS, 1042 TF_TYPE_HWPWL 1043 }; 1044 1045 struct dc_transfer_func_distributed_points { 1046 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1047 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1048 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1049 1050 uint16_t end_exponent; 1051 uint16_t x_point_at_y1_red; 1052 uint16_t x_point_at_y1_green; 1053 uint16_t x_point_at_y1_blue; 1054 }; 1055 1056 enum dc_transfer_func_predefined { 1057 TRANSFER_FUNCTION_SRGB, 1058 TRANSFER_FUNCTION_BT709, 1059 TRANSFER_FUNCTION_PQ, 1060 TRANSFER_FUNCTION_LINEAR, 1061 TRANSFER_FUNCTION_UNITY, 1062 TRANSFER_FUNCTION_HLG, 1063 TRANSFER_FUNCTION_HLG12, 1064 TRANSFER_FUNCTION_GAMMA22, 1065 TRANSFER_FUNCTION_GAMMA24, 1066 TRANSFER_FUNCTION_GAMMA26 1067 }; 1068 1069 1070 struct dc_transfer_func { 1071 struct kref refcount; 1072 enum dc_transfer_func_type type; 1073 enum dc_transfer_func_predefined tf; 1074 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1075 uint32_t sdr_ref_white_level; 1076 union { 1077 struct pwl_params pwl; 1078 struct dc_transfer_func_distributed_points tf_pts; 1079 }; 1080 }; 1081 1082 1083 union dc_3dlut_state { 1084 struct { 1085 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1086 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1087 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1088 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1089 uint32_t mpc_rmu1_mux:4; 1090 uint32_t mpc_rmu2_mux:4; 1091 uint32_t reserved:15; 1092 } bits; 1093 uint32_t raw; 1094 }; 1095 1096 1097 struct dc_3dlut { 1098 struct kref refcount; 1099 struct tetrahedral_params lut_3d; 1100 struct fixed31_32 hdr_multiplier; 1101 union dc_3dlut_state state; 1102 }; 1103 /* 1104 * This structure is filled in by dc_surface_get_status and contains 1105 * the last requested address and the currently active address so the called 1106 * can determine if there are any outstanding flips 1107 */ 1108 struct dc_plane_status { 1109 struct dc_plane_address requested_address; 1110 struct dc_plane_address current_address; 1111 bool is_flip_pending; 1112 bool is_right_eye; 1113 }; 1114 1115 union surface_update_flags { 1116 1117 struct { 1118 uint32_t addr_update:1; 1119 /* Medium updates */ 1120 uint32_t dcc_change:1; 1121 uint32_t color_space_change:1; 1122 uint32_t horizontal_mirror_change:1; 1123 uint32_t per_pixel_alpha_change:1; 1124 uint32_t global_alpha_change:1; 1125 uint32_t hdr_mult:1; 1126 uint32_t rotation_change:1; 1127 uint32_t swizzle_change:1; 1128 uint32_t scaling_change:1; 1129 uint32_t position_change:1; 1130 uint32_t in_transfer_func_change:1; 1131 uint32_t input_csc_change:1; 1132 uint32_t coeff_reduction_change:1; 1133 uint32_t output_tf_change:1; 1134 uint32_t pixel_format_change:1; 1135 uint32_t plane_size_change:1; 1136 uint32_t gamut_remap_change:1; 1137 1138 /* Full updates */ 1139 uint32_t new_plane:1; 1140 uint32_t bpp_change:1; 1141 uint32_t gamma_change:1; 1142 uint32_t bandwidth_change:1; 1143 uint32_t clock_change:1; 1144 uint32_t stereo_format_change:1; 1145 uint32_t lut_3d:1; 1146 uint32_t tmz_changed:1; 1147 uint32_t full_update:1; 1148 } bits; 1149 1150 uint32_t raw; 1151 }; 1152 1153 struct dc_plane_state { 1154 struct dc_plane_address address; 1155 struct dc_plane_flip_time time; 1156 bool triplebuffer_flips; 1157 struct scaling_taps scaling_quality; 1158 struct rect src_rect; 1159 struct rect dst_rect; 1160 struct rect clip_rect; 1161 1162 struct plane_size plane_size; 1163 union dc_tiling_info tiling_info; 1164 1165 struct dc_plane_dcc_param dcc; 1166 1167 struct dc_gamma *gamma_correction; 1168 struct dc_transfer_func *in_transfer_func; 1169 struct dc_bias_and_scale *bias_and_scale; 1170 struct dc_csc_transform input_csc_color_matrix; 1171 struct fixed31_32 coeff_reduction_factor; 1172 struct fixed31_32 hdr_mult; 1173 struct colorspace_transform gamut_remap_matrix; 1174 1175 // TODO: No longer used, remove 1176 struct dc_hdr_static_metadata hdr_static_ctx; 1177 1178 enum dc_color_space color_space; 1179 1180 struct dc_3dlut *lut3d_func; 1181 struct dc_transfer_func *in_shaper_func; 1182 struct dc_transfer_func *blend_tf; 1183 1184 struct dc_transfer_func *gamcor_tf; 1185 enum surface_pixel_format format; 1186 enum dc_rotation_angle rotation; 1187 enum plane_stereo_format stereo_format; 1188 1189 bool is_tiling_rotated; 1190 bool per_pixel_alpha; 1191 bool pre_multiplied_alpha; 1192 bool global_alpha; 1193 int global_alpha_value; 1194 bool visible; 1195 bool flip_immediate; 1196 bool horizontal_mirror; 1197 int layer_index; 1198 1199 union surface_update_flags update_flags; 1200 bool flip_int_enabled; 1201 bool skip_manual_trigger; 1202 1203 /* private to DC core */ 1204 struct dc_plane_status status; 1205 struct dc_context *ctx; 1206 1207 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1208 bool force_full_update; 1209 1210 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1211 1212 /* private to dc_surface.c */ 1213 enum dc_irq_source irq_source; 1214 struct kref refcount; 1215 struct tg_color visual_confirm_color; 1216 1217 bool is_statically_allocated; 1218 }; 1219 1220 struct dc_plane_info { 1221 struct plane_size plane_size; 1222 union dc_tiling_info tiling_info; 1223 struct dc_plane_dcc_param dcc; 1224 enum surface_pixel_format format; 1225 enum dc_rotation_angle rotation; 1226 enum plane_stereo_format stereo_format; 1227 enum dc_color_space color_space; 1228 bool horizontal_mirror; 1229 bool visible; 1230 bool per_pixel_alpha; 1231 bool pre_multiplied_alpha; 1232 bool global_alpha; 1233 int global_alpha_value; 1234 bool input_csc_enabled; 1235 int layer_index; 1236 }; 1237 1238 struct dc_scaling_info { 1239 struct rect src_rect; 1240 struct rect dst_rect; 1241 struct rect clip_rect; 1242 struct scaling_taps scaling_quality; 1243 }; 1244 1245 struct dc_surface_update { 1246 struct dc_plane_state *surface; 1247 1248 /* isr safe update parameters. null means no updates */ 1249 const struct dc_flip_addrs *flip_addr; 1250 const struct dc_plane_info *plane_info; 1251 const struct dc_scaling_info *scaling_info; 1252 struct fixed31_32 hdr_mult; 1253 /* following updates require alloc/sleep/spin that is not isr safe, 1254 * null means no updates 1255 */ 1256 const struct dc_gamma *gamma; 1257 const struct dc_transfer_func *in_transfer_func; 1258 1259 const struct dc_csc_transform *input_csc_color_matrix; 1260 const struct fixed31_32 *coeff_reduction_factor; 1261 const struct dc_transfer_func *func_shaper; 1262 const struct dc_3dlut *lut3d_func; 1263 const struct dc_transfer_func *blend_tf; 1264 const struct colorspace_transform *gamut_remap_matrix; 1265 }; 1266 1267 /* 1268 * Create a new surface with default parameters; 1269 */ 1270 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1271 const struct dc_plane_status *dc_plane_get_status( 1272 const struct dc_plane_state *plane_state); 1273 1274 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1275 void dc_plane_state_release(struct dc_plane_state *plane_state); 1276 1277 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1278 void dc_gamma_release(struct dc_gamma **dc_gamma); 1279 struct dc_gamma *dc_create_gamma(void); 1280 1281 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1282 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1283 struct dc_transfer_func *dc_create_transfer_func(void); 1284 1285 struct dc_3dlut *dc_create_3dlut_func(void); 1286 void dc_3dlut_func_release(struct dc_3dlut *lut); 1287 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1288 1289 void dc_post_update_surfaces_to_stream( 1290 struct dc *dc); 1291 1292 #include "dc_stream.h" 1293 1294 /** 1295 * struct dc_validation_set - Struct to store surface/stream associations for validation 1296 */ 1297 struct dc_validation_set { 1298 /** 1299 * @stream: Stream state properties 1300 */ 1301 struct dc_stream_state *stream; 1302 1303 /** 1304 * @plane_state: Surface state 1305 */ 1306 struct dc_plane_state *plane_states[MAX_SURFACES]; 1307 1308 /** 1309 * @plane_count: Total of active planes 1310 */ 1311 uint8_t plane_count; 1312 }; 1313 1314 bool dc_validate_boot_timing(const struct dc *dc, 1315 const struct dc_sink *sink, 1316 struct dc_crtc_timing *crtc_timing); 1317 1318 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1319 1320 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1321 1322 enum dc_status dc_validate_with_context(struct dc *dc, 1323 const struct dc_validation_set set[], 1324 int set_count, 1325 struct dc_state *context, 1326 bool fast_validate); 1327 1328 bool dc_set_generic_gpio_for_stereo(bool enable, 1329 struct gpio_service *gpio_service); 1330 1331 /* 1332 * fast_validate: we return after determining if we can support the new state, 1333 * but before we populate the programming info 1334 */ 1335 enum dc_status dc_validate_global_state( 1336 struct dc *dc, 1337 struct dc_state *new_ctx, 1338 bool fast_validate); 1339 1340 1341 void dc_resource_state_construct( 1342 const struct dc *dc, 1343 struct dc_state *dst_ctx); 1344 1345 bool dc_acquire_release_mpc_3dlut( 1346 struct dc *dc, bool acquire, 1347 struct dc_stream_state *stream, 1348 struct dc_3dlut **lut, 1349 struct dc_transfer_func **shaper); 1350 1351 void dc_resource_state_copy_construct( 1352 const struct dc_state *src_ctx, 1353 struct dc_state *dst_ctx); 1354 1355 void dc_resource_state_copy_construct_current( 1356 const struct dc *dc, 1357 struct dc_state *dst_ctx); 1358 1359 void dc_resource_state_destruct(struct dc_state *context); 1360 1361 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1362 1363 enum dc_status dc_commit_streams(struct dc *dc, 1364 struct dc_stream_state *streams[], 1365 uint8_t stream_count); 1366 1367 struct dc_state *dc_create_state(struct dc *dc); 1368 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1369 void dc_retain_state(struct dc_state *context); 1370 void dc_release_state(struct dc_state *context); 1371 1372 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1373 struct dc_stream_state *stream, 1374 int mpcc_inst); 1375 1376 1377 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1378 1379 /* The function returns minimum bandwidth required to drive a given timing 1380 * return - minimum required timing bandwidth in kbps. 1381 */ 1382 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing); 1383 1384 /* Link Interfaces */ 1385 /* 1386 * A link contains one or more sinks and their connected status. 1387 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1388 */ 1389 struct dc_link { 1390 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1391 unsigned int sink_count; 1392 struct dc_sink *local_sink; 1393 unsigned int link_index; 1394 enum dc_connection_type type; 1395 enum signal_type connector_signal; 1396 enum dc_irq_source irq_source_hpd; 1397 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1398 1399 bool is_hpd_filter_disabled; 1400 bool dp_ss_off; 1401 1402 /** 1403 * @link_state_valid: 1404 * 1405 * If there is no link and local sink, this variable should be set to 1406 * false. Otherwise, it should be set to true; usually, the function 1407 * core_link_enable_stream sets this field to true. 1408 */ 1409 bool link_state_valid; 1410 bool aux_access_disabled; 1411 bool sync_lt_in_progress; 1412 bool skip_stream_reenable; 1413 bool is_internal_display; 1414 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1415 bool is_dig_mapping_flexible; 1416 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1417 bool is_hpd_pending; /* Indicates a new received hpd */ 1418 bool is_automated; /* Indicates automated testing */ 1419 1420 bool edp_sink_present; 1421 1422 struct dp_trace dp_trace; 1423 1424 /* caps is the same as reported_link_cap. link_traing use 1425 * reported_link_cap. Will clean up. TODO 1426 */ 1427 struct dc_link_settings reported_link_cap; 1428 struct dc_link_settings verified_link_cap; 1429 struct dc_link_settings cur_link_settings; 1430 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1431 struct dc_link_settings preferred_link_setting; 1432 /* preferred_training_settings are override values that 1433 * come from DM. DM is responsible for the memory 1434 * management of the override pointers. 1435 */ 1436 struct dc_link_training_overrides preferred_training_settings; 1437 struct dp_audio_test_data audio_test_data; 1438 1439 uint8_t ddc_hw_inst; 1440 1441 uint8_t hpd_src; 1442 1443 uint8_t link_enc_hw_inst; 1444 /* DIG link encoder ID. Used as index in link encoder resource pool. 1445 * For links with fixed mapping to DIG, this is not changed after dc_link 1446 * object creation. 1447 */ 1448 enum engine_id eng_id; 1449 1450 bool test_pattern_enabled; 1451 union compliance_test_state compliance_test_state; 1452 1453 void *priv; 1454 1455 struct ddc_service *ddc; 1456 1457 enum dp_panel_mode panel_mode; 1458 bool aux_mode; 1459 1460 /* Private to DC core */ 1461 1462 const struct dc *dc; 1463 1464 struct dc_context *ctx; 1465 1466 struct panel_cntl *panel_cntl; 1467 struct link_encoder *link_enc; 1468 struct graphics_object_id link_id; 1469 /* Endpoint type distinguishes display endpoints which do not have entries 1470 * in the BIOS connector table from those that do. Helps when tracking link 1471 * encoder to display endpoint assignments. 1472 */ 1473 enum display_endpoint_type ep_type; 1474 union ddi_channel_mapping ddi_channel_mapping; 1475 struct connector_device_tag_info device_tag; 1476 struct dpcd_caps dpcd_caps; 1477 uint32_t dongle_max_pix_clk; 1478 unsigned short chip_caps; 1479 unsigned int dpcd_sink_count; 1480 struct hdcp_caps hdcp_caps; 1481 enum edp_revision edp_revision; 1482 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1483 1484 struct psr_settings psr_settings; 1485 1486 /* Drive settings read from integrated info table */ 1487 struct dc_lane_settings bios_forced_drive_settings; 1488 1489 /* Vendor specific LTTPR workaround variables */ 1490 uint8_t vendor_specific_lttpr_link_rate_wa; 1491 bool apply_vendor_specific_lttpr_link_rate_wa; 1492 1493 /* MST record stream using this link */ 1494 struct link_flags { 1495 bool dp_keep_receiver_powered; 1496 bool dp_skip_DID2; 1497 bool dp_skip_reset_segment; 1498 bool dp_skip_fs_144hz; 1499 bool dp_mot_reset_segment; 1500 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1501 bool dpia_mst_dsc_always_on; 1502 /* Forced DPIA into TBT3 compatibility mode. */ 1503 bool dpia_forced_tbt3_mode; 1504 bool dongle_mode_timing_override; 1505 } wa_flags; 1506 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1507 1508 struct dc_link_status link_status; 1509 struct dprx_states dprx_states; 1510 1511 struct gpio *hpd_gpio; 1512 enum dc_link_fec_state fec_state; 1513 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1514 1515 struct dc_panel_config panel_config; 1516 struct phy_state phy_state; 1517 // BW ALLOCATON USB4 ONLY 1518 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1519 }; 1520 1521 /* Return an enumerated dc_link. 1522 * dc_link order is constant and determined at 1523 * boot time. They cannot be created or destroyed. 1524 * Use dc_get_caps() to get number of links. 1525 */ 1526 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1527 1528 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1529 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1530 const struct dc_link *link, 1531 unsigned int *inst_out); 1532 1533 /* Return an array of link pointers to edp links. */ 1534 void dc_get_edp_links(const struct dc *dc, 1535 struct dc_link **edp_links, 1536 int *edp_num); 1537 1538 /* The function initiates detection handshake over the given link. It first 1539 * determines if there are display connections over the link. If so it initiates 1540 * detection protocols supported by the connected receiver device. The function 1541 * contains protocol specific handshake sequences which are sometimes mandatory 1542 * to establish a proper connection between TX and RX. So it is always 1543 * recommended to call this function as the first link operation upon HPD event 1544 * or power up event. Upon completion, the function will update link structure 1545 * in place based on latest RX capabilities. The function may also cause dpms 1546 * to be reset to off for all currently enabled streams to the link. It is DM's 1547 * responsibility to serialize detection and DPMS updates. 1548 * 1549 * @reason - Indicate which event triggers this detection. dc may customize 1550 * detection flow depending on the triggering events. 1551 * return false - if detection is not fully completed. This could happen when 1552 * there is an unrecoverable error during detection or detection is partially 1553 * completed (detection has been delegated to dm mst manager ie. 1554 * link->connection_type == dc_connection_mst_branch when returning false). 1555 * return true - detection is completed, link has been fully updated with latest 1556 * detection result. 1557 */ 1558 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1559 1560 struct dc_sink_init_data; 1561 1562 /* When link connection type is dc_connection_mst_branch, remote sink can be 1563 * added to the link. The interface creates a remote sink and associates it with 1564 * current link. The sink will be retained by link until remove remote sink is 1565 * called. 1566 * 1567 * @dc_link - link the remote sink will be added to. 1568 * @edid - byte array of EDID raw data. 1569 * @len - size of the edid in byte 1570 * @init_data - 1571 */ 1572 struct dc_sink *dc_link_add_remote_sink( 1573 struct dc_link *dc_link, 1574 const uint8_t *edid, 1575 int len, 1576 struct dc_sink_init_data *init_data); 1577 1578 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1579 * @link - link the sink should be removed from 1580 * @sink - sink to be removed. 1581 */ 1582 void dc_link_remove_remote_sink( 1583 struct dc_link *link, 1584 struct dc_sink *sink); 1585 1586 /* Enable HPD interrupt handler for a given link */ 1587 void dc_link_enable_hpd(const struct dc_link *link); 1588 1589 /* Disable HPD interrupt handler for a given link */ 1590 void dc_link_disable_hpd(const struct dc_link *link); 1591 1592 /* determine if there is a sink connected to the link 1593 * 1594 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1595 * return - false if an unexpected error occurs, true otherwise. 1596 * 1597 * NOTE: This function doesn't detect downstream sink connections i.e 1598 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1599 * return dc_connection_single if the branch device is connected despite of 1600 * downstream sink's connection status. 1601 */ 1602 bool dc_link_detect_connection_type(struct dc_link *link, 1603 enum dc_connection_type *type); 1604 1605 /* query current hpd pin value 1606 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1607 * 1608 */ 1609 bool dc_link_get_hpd_state(struct dc_link *link); 1610 1611 /* Getter for cached link status from given link */ 1612 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1613 1614 /* enable/disable hardware HPD filter. 1615 * 1616 * @link - The link the HPD pin is associated with. 1617 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1618 * handler once after no HPD change has been detected within dc default HPD 1619 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1620 * pulses within default HPD interval, no HPD event will be received until HPD 1621 * toggles have stopped. Then HPD event will be queued to irq handler once after 1622 * dc default HPD filtering interval since last HPD event. 1623 * 1624 * @enable = false - disable hardware HPD filter. HPD event will be queued 1625 * immediately to irq handler after no HPD change has been detected within 1626 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1627 */ 1628 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1629 1630 /* submit i2c read/write payloads through ddc channel 1631 * @link_index - index to a link with ddc in i2c mode 1632 * @cmd - i2c command structure 1633 * return - true if success, false otherwise. 1634 */ 1635 bool dc_submit_i2c( 1636 struct dc *dc, 1637 uint32_t link_index, 1638 struct i2c_command *cmd); 1639 1640 /* submit i2c read/write payloads through oem channel 1641 * @link_index - index to a link with ddc in i2c mode 1642 * @cmd - i2c command structure 1643 * return - true if success, false otherwise. 1644 */ 1645 bool dc_submit_i2c_oem( 1646 struct dc *dc, 1647 struct i2c_command *cmd); 1648 1649 enum aux_return_code_type; 1650 /* Attempt to transfer the given aux payload. This function does not perform 1651 * retries or handle error states. The reply is returned in the payload->reply 1652 * and the result through operation_result. Returns the number of bytes 1653 * transferred,or -1 on a failure. 1654 */ 1655 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1656 struct aux_payload *payload, 1657 enum aux_return_code_type *operation_result); 1658 1659 bool dc_is_oem_i2c_device_present( 1660 struct dc *dc, 1661 size_t slave_address 1662 ); 1663 1664 /* return true if the connected receiver supports the hdcp version */ 1665 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1666 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1667 1668 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1669 * 1670 * TODO - When defer_handling is true the function will have a different purpose. 1671 * It no longer does complete hpd rx irq handling. We should create a separate 1672 * interface specifically for this case. 1673 * 1674 * Return: 1675 * true - Downstream port status changed. DM should call DC to do the 1676 * detection. 1677 * false - no change in Downstream port status. No further action required 1678 * from DM. 1679 */ 1680 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1681 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1682 bool defer_handling, bool *has_left_work); 1683 /* handle DP specs define test automation sequence*/ 1684 void dc_link_dp_handle_automated_test(struct dc_link *link); 1685 1686 /* handle DP Link loss sequence and try to recover RX link loss with best 1687 * effort 1688 */ 1689 void dc_link_dp_handle_link_loss(struct dc_link *link); 1690 1691 /* Determine if hpd rx irq should be handled or ignored 1692 * return true - hpd rx irq should be handled. 1693 * return false - it is safe to ignore hpd rx irq event 1694 */ 1695 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1696 1697 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1698 * @link - link the hpd irq data associated with 1699 * @hpd_irq_dpcd_data - input hpd irq data 1700 * return - true if hpd irq data indicates a link lost 1701 */ 1702 bool dc_link_check_link_loss_status(struct dc_link *link, 1703 union hpd_irq_data *hpd_irq_dpcd_data); 1704 1705 /* Read hpd rx irq data from a given link 1706 * @link - link where the hpd irq data should be read from 1707 * @irq_data - output hpd irq data 1708 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1709 * read has failed. 1710 */ 1711 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1712 struct dc_link *link, 1713 union hpd_irq_data *irq_data); 1714 1715 /* The function clears recorded DP RX states in the link. DM should call this 1716 * function when it is resuming from S3 power state to previously connected links. 1717 * 1718 * TODO - in the future we should consider to expand link resume interface to 1719 * support clearing previous rx states. So we don't have to rely on dm to call 1720 * this interface explicitly. 1721 */ 1722 void dc_link_clear_dprx_states(struct dc_link *link); 1723 1724 /* Destruct the mst topology of the link and reset the allocated payload table 1725 * 1726 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1727 * still wants to reset MST topology on an unplug event */ 1728 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1729 1730 /* The function calculates effective DP link bandwidth when a given link is 1731 * using the given link settings. 1732 * 1733 * return - total effective link bandwidth in kbps. 1734 */ 1735 uint32_t dc_link_bandwidth_kbps( 1736 const struct dc_link *link, 1737 const struct dc_link_settings *link_setting); 1738 1739 /* The function takes a snapshot of current link resource allocation state 1740 * @dc: pointer to dc of the dm calling this 1741 * @map: a dc link resource snapshot defined internally to dc. 1742 * 1743 * DM needs to capture a snapshot of current link resource allocation mapping 1744 * and store it in its persistent storage. 1745 * 1746 * Some of the link resource is using first come first serve policy. 1747 * The allocation mapping depends on original hotplug order. This information 1748 * is lost after driver is loaded next time. The snapshot is used in order to 1749 * restore link resource to its previous state so user will get consistent 1750 * link capability allocation across reboot. 1751 * 1752 */ 1753 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1754 1755 /* This function restores link resource allocation state from a snapshot 1756 * @dc: pointer to dc of the dm calling this 1757 * @map: a dc link resource snapshot defined internally to dc. 1758 * 1759 * DM needs to call this function after initial link detection on boot and 1760 * before first commit streams to restore link resource allocation state 1761 * from previous boot session. 1762 * 1763 * Some of the link resource is using first come first serve policy. 1764 * The allocation mapping depends on original hotplug order. This information 1765 * is lost after driver is loaded next time. The snapshot is used in order to 1766 * restore link resource to its previous state so user will get consistent 1767 * link capability allocation across reboot. 1768 * 1769 */ 1770 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1771 1772 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1773 * interface i.e stream_update->dsc_config 1774 */ 1775 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1776 1777 /* translate a raw link rate data to bandwidth in kbps */ 1778 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1779 1780 /* determine the optimal bandwidth given link and required bw. 1781 * @link - current detected link 1782 * @req_bw - requested bandwidth in kbps 1783 * @link_settings - returned most optimal link settings that can fit the 1784 * requested bandwidth 1785 * return - false if link can't support requested bandwidth, true if link 1786 * settings is found. 1787 */ 1788 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1789 struct dc_link_settings *link_settings, 1790 uint32_t req_bw); 1791 1792 /* return the max dp link settings can be driven by the link without considering 1793 * connected RX device and its capability 1794 */ 1795 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1796 struct dc_link_settings *max_link_enc_cap); 1797 1798 /* determine when the link is driving MST mode, what DP link channel coding 1799 * format will be used. The decision will remain unchanged until next HPD event. 1800 * 1801 * @link - a link with DP RX connection 1802 * return - if stream is committed to this link with MST signal type, type of 1803 * channel coding format dc will choose. 1804 */ 1805 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1806 const struct dc_link *link); 1807 1808 /* get max dp link settings the link can enable with all things considered. (i.e 1809 * TX/RX/Cable capabilities and dp override policies. 1810 * 1811 * @link - a link with DP RX connection 1812 * return - max dp link settings the link can enable. 1813 * 1814 */ 1815 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1816 1817 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1818 * to a link with dp connector signal type. 1819 * @link - a link with dp connector signal type 1820 * return - true if connected, false otherwise 1821 */ 1822 bool dc_link_is_dp_sink_present(struct dc_link *link); 1823 1824 /* Force DP lane settings update to main-link video signal and notify the change 1825 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1826 * tuning purpose. The interface assumes link has already been enabled with DP 1827 * signal. 1828 * 1829 * @lt_settings - a container structure with desired hw_lane_settings 1830 */ 1831 void dc_link_set_drive_settings(struct dc *dc, 1832 struct link_training_settings *lt_settings, 1833 struct dc_link *link); 1834 1835 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1836 * test or debugging purpose. The test pattern will remain until next un-plug. 1837 * 1838 * @link - active link with DP signal output enabled. 1839 * @test_pattern - desired test pattern to output. 1840 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1841 * @test_pattern_color_space - for video test pattern choose a desired color 1842 * space. 1843 * @p_link_settings - For PHY pattern choose a desired link settings 1844 * @p_custom_pattern - some test pattern will require a custom input to 1845 * customize some pattern details. Otherwise keep it to NULL. 1846 * @cust_pattern_size - size of the custom pattern input. 1847 * 1848 */ 1849 bool dc_link_dp_set_test_pattern( 1850 struct dc_link *link, 1851 enum dp_test_pattern test_pattern, 1852 enum dp_test_pattern_color_space test_pattern_color_space, 1853 const struct link_training_settings *p_link_settings, 1854 const unsigned char *p_custom_pattern, 1855 unsigned int cust_pattern_size); 1856 1857 /* Force DP link settings to always use a specific value until reboot to a 1858 * specific link. If link has already been enabled, the interface will also 1859 * switch to desired link settings immediately. This is a debug interface to 1860 * generic dp issue trouble shooting. 1861 */ 1862 void dc_link_set_preferred_link_settings(struct dc *dc, 1863 struct dc_link_settings *link_setting, 1864 struct dc_link *link); 1865 1866 /* Force DP link to customize a specific link training behavior by overriding to 1867 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1868 * display specific link training issues or apply some display specific 1869 * workaround in link training. 1870 * 1871 * @link_settings - if not NULL, force preferred link settings to the link. 1872 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1873 * will apply this particular override in future link training. If NULL is 1874 * passed in, dc resets previous overrides. 1875 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1876 * training settings. 1877 */ 1878 void dc_link_set_preferred_training_settings(struct dc *dc, 1879 struct dc_link_settings *link_setting, 1880 struct dc_link_training_overrides *lt_overrides, 1881 struct dc_link *link, 1882 bool skip_immediate_retrain); 1883 1884 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1885 bool dc_link_is_fec_supported(const struct dc_link *link); 1886 1887 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1888 * link enablement. 1889 * return - true if FEC should be enabled, false otherwise. 1890 */ 1891 bool dc_link_should_enable_fec(const struct dc_link *link); 1892 1893 /* determine lttpr mode the current link should be enabled with a specific link 1894 * settings. 1895 */ 1896 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1897 struct dc_link_settings *link_setting); 1898 1899 /* Force DP RX to update its power state. 1900 * NOTE: this interface doesn't update dp main-link. Calling this function will 1901 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1902 * RX power state back upon finish DM specific execution requiring DP RX in a 1903 * specific power state. 1904 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1905 * state. 1906 */ 1907 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1908 1909 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1910 * current value read from extended receiver cap from 02200h - 0220Fh. 1911 * Some DP RX has problems of providing accurate DP receiver caps from extended 1912 * field, this interface is a workaround to revert link back to use base caps. 1913 */ 1914 void dc_link_overwrite_extended_receiver_cap( 1915 struct dc_link *link); 1916 1917 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1918 bool wait_for_hpd); 1919 1920 /* Set backlight level of an embedded panel (eDP, LVDS). 1921 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1922 * and 16 bit fractional, where 1.0 is max backlight value. 1923 */ 1924 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1925 uint32_t backlight_pwm_u16_16, 1926 uint32_t frame_ramp); 1927 1928 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1929 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1930 bool isHDR, 1931 uint32_t backlight_millinits, 1932 uint32_t transition_time_in_ms); 1933 1934 bool dc_link_get_backlight_level_nits(struct dc_link *link, 1935 uint32_t *backlight_millinits, 1936 uint32_t *backlight_millinits_peak); 1937 1938 int dc_link_get_backlight_level(const struct dc_link *dc_link); 1939 1940 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 1941 1942 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 1943 bool wait, bool force_static, const unsigned int *power_opts); 1944 1945 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 1946 1947 bool dc_link_setup_psr(struct dc_link *dc_link, 1948 const struct dc_stream_state *stream, struct psr_config *psr_config, 1949 struct psr_context *psr_context); 1950 1951 /* On eDP links this function call will stall until T12 has elapsed. 1952 * If the panel is not in power off state, this function will return 1953 * immediately. 1954 */ 1955 bool dc_link_wait_for_t12(struct dc_link *link); 1956 1957 /* Determine if dp trace has been initialized to reflect upto date result * 1958 * return - true if trace is initialized and has valid data. False dp trace 1959 * doesn't have valid result. 1960 */ 1961 bool dc_dp_trace_is_initialized(struct dc_link *link); 1962 1963 /* Query a dp trace flag to indicate if the current dp trace data has been 1964 * logged before 1965 */ 1966 bool dc_dp_trace_is_logged(struct dc_link *link, 1967 bool in_detection); 1968 1969 /* Set dp trace flag to indicate whether DM has already logged the current dp 1970 * trace data. DM can set is_logged to true upon logging and check 1971 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 1972 */ 1973 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 1974 bool in_detection, 1975 bool is_logged); 1976 1977 /* Obtain driver time stamp for last dp link training end. The time stamp is 1978 * formatted based on dm_get_timestamp DM function. 1979 * @in_detection - true to get link training end time stamp of last link 1980 * training in detection sequence. false to get link training end time stamp 1981 * of last link training in commit (dpms) sequence 1982 */ 1983 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 1984 bool in_detection); 1985 1986 /* Get how many link training attempts dc has done with latest sequence. 1987 * @in_detection - true to get link training count of last link 1988 * training in detection sequence. false to get link training count of last link 1989 * training in commit (dpms) sequence 1990 */ 1991 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 1992 bool in_detection); 1993 1994 /* Get how many link loss has happened since last link training attempts */ 1995 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 1996 1997 /* 1998 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 1999 */ 2000 /* 2001 * Send a request from DP-Tx requesting to allocate BW remotely after 2002 * allocating it locally. This will get processed by CM and a CB function 2003 * will be called. 2004 * 2005 * @link: pointer to the dc_link struct instance 2006 * @req_bw: The requested bw in Kbyte to allocated 2007 * 2008 * return: none 2009 */ 2010 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2011 2012 /* 2013 * Handle function for when the status of the Request above is complete. 2014 * We will find out the result of allocating on CM and update structs. 2015 * 2016 * @link: pointer to the dc_link struct instance 2017 * @bw: Allocated or Estimated BW depending on the result 2018 * @result: Response type 2019 * 2020 * return: none 2021 */ 2022 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2023 uint8_t bw, uint8_t result); 2024 2025 /* 2026 * Handle the USB4 BW Allocation related functionality here: 2027 * Plug => Try to allocate max bw from timing parameters supported by the sink 2028 * Unplug => de-allocate bw 2029 * 2030 * @link: pointer to the dc_link struct instance 2031 * @peak_bw: Peak bw used by the link/sink 2032 * 2033 * return: allocated bw else return 0 2034 */ 2035 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2036 struct dc_link *link, int peak_bw); 2037 2038 /* 2039 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2040 * available BW for each host router 2041 * 2042 * @dc: pointer to dc struct 2043 * @stream: pointer to all possible streams 2044 * @num_streams: number of valid DPIA streams 2045 * 2046 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2047 */ 2048 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2049 const unsigned int count); 2050 2051 /* Sink Interfaces - A sink corresponds to a display output device */ 2052 2053 struct dc_container_id { 2054 // 128bit GUID in binary form 2055 unsigned char guid[16]; 2056 // 8 byte port ID -> ELD.PortID 2057 unsigned int portId[2]; 2058 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2059 unsigned short manufacturerName; 2060 // 2 byte product code -> ELD.ProductCode 2061 unsigned short productCode; 2062 }; 2063 2064 2065 struct dc_sink_dsc_caps { 2066 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2067 // 'false' if they are sink's DSC caps 2068 bool is_virtual_dpcd_dsc; 2069 #if defined(CONFIG_DRM_AMD_DC_FP) 2070 // 'true' if MST topology supports DSC passthrough for sink 2071 // 'false' if MST topology does not support DSC passthrough 2072 bool is_dsc_passthrough_supported; 2073 #endif 2074 struct dsc_dec_dpcd_caps dsc_dec_caps; 2075 }; 2076 2077 struct dc_sink_fec_caps { 2078 bool is_rx_fec_supported; 2079 bool is_topology_fec_supported; 2080 }; 2081 2082 struct scdc_caps { 2083 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2084 union hdmi_scdc_device_id_data device_id; 2085 }; 2086 2087 /* 2088 * The sink structure contains EDID and other display device properties 2089 */ 2090 struct dc_sink { 2091 enum signal_type sink_signal; 2092 struct dc_edid dc_edid; /* raw edid */ 2093 struct dc_edid_caps edid_caps; /* parse display caps */ 2094 struct dc_container_id *dc_container_id; 2095 uint32_t dongle_max_pix_clk; 2096 void *priv; 2097 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2098 bool converter_disable_audio; 2099 2100 struct scdc_caps scdc_caps; 2101 struct dc_sink_dsc_caps dsc_caps; 2102 struct dc_sink_fec_caps fec_caps; 2103 2104 bool is_vsc_sdp_colorimetry_supported; 2105 2106 /* private to DC core */ 2107 struct dc_link *link; 2108 struct dc_context *ctx; 2109 2110 uint32_t sink_id; 2111 2112 /* private to dc_sink.c */ 2113 // refcount must be the last member in dc_sink, since we want the 2114 // sink structure to be logically cloneable up to (but not including) 2115 // refcount 2116 struct kref refcount; 2117 }; 2118 2119 void dc_sink_retain(struct dc_sink *sink); 2120 void dc_sink_release(struct dc_sink *sink); 2121 2122 struct dc_sink_init_data { 2123 enum signal_type sink_signal; 2124 struct dc_link *link; 2125 uint32_t dongle_max_pix_clk; 2126 bool converter_disable_audio; 2127 }; 2128 2129 bool dc_extended_blank_supported(struct dc *dc); 2130 2131 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2132 2133 /* Newer interfaces */ 2134 struct dc_cursor { 2135 struct dc_plane_address address; 2136 struct dc_cursor_attributes attributes; 2137 }; 2138 2139 2140 /* Interrupt interfaces */ 2141 enum dc_irq_source dc_interrupt_to_irq_source( 2142 struct dc *dc, 2143 uint32_t src_id, 2144 uint32_t ext_id); 2145 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2146 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2147 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2148 struct dc *dc, uint32_t link_index); 2149 2150 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2151 2152 /* Power Interfaces */ 2153 2154 void dc_set_power_state( 2155 struct dc *dc, 2156 enum dc_acpi_cm_power_state power_state); 2157 void dc_resume(struct dc *dc); 2158 2159 void dc_power_down_on_boot(struct dc *dc); 2160 2161 /* 2162 * HDCP Interfaces 2163 */ 2164 enum hdcp_message_status dc_process_hdcp_msg( 2165 enum signal_type signal, 2166 struct dc_link *link, 2167 struct hdcp_protection_message *message_info); 2168 bool dc_is_dmcu_initialized(struct dc *dc); 2169 2170 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2171 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2172 2173 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2174 struct dc_cursor_attributes *cursor_attr); 2175 2176 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2177 2178 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2179 void dc_unlock_memory_clock_frequency(struct dc *dc); 2180 2181 /* set min memory clock to the min required for current mode, max to maxDPM */ 2182 void dc_lock_memory_clock_frequency(struct dc *dc); 2183 2184 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2185 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2186 2187 /* cleanup on driver unload */ 2188 void dc_hardware_release(struct dc *dc); 2189 2190 /* disables fw based mclk switch */ 2191 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2192 2193 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2194 void dc_z10_restore(const struct dc *dc); 2195 void dc_z10_save_init(struct dc *dc); 2196 2197 bool dc_is_dmub_outbox_supported(struct dc *dc); 2198 bool dc_enable_dmub_notifications(struct dc *dc); 2199 2200 void dc_enable_dmub_outbox(struct dc *dc); 2201 2202 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2203 uint32_t link_index, 2204 struct aux_payload *payload); 2205 2206 /* Get dc link index from dpia port index */ 2207 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2208 uint8_t dpia_port_index); 2209 2210 bool dc_process_dmub_set_config_async(struct dc *dc, 2211 uint32_t link_index, 2212 struct set_config_cmd_payload *payload, 2213 struct dmub_notification *notify); 2214 2215 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2216 uint32_t link_index, 2217 uint8_t mst_alloc_slots, 2218 uint8_t *mst_slots_in_use); 2219 2220 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2221 uint32_t hpd_int_enable); 2222 2223 /* DSC Interfaces */ 2224 #include "dc_dsc.h" 2225 2226 /* Disable acc mode Interfaces */ 2227 void dc_disable_accelerated_mode(struct dc *dc); 2228 2229 #endif /* DC_INTERFACE_H_ */ 2230