xref: /linux/drivers/gpu/drm/amd/display/dc/dc_hw_types.h (revision 44f57d78) 
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DC_HW_TYPES_H
27 #define DC_HW_TYPES_H
28 
29 #include "os_types.h"
30 #include "fixed31_32.h"
31 #include "signal_types.h"
32 
33 /******************************************************************************
34  * Data types for Virtual HW Layer of DAL3.
35  * (see DAL3 design documents for HW Layer definition)
36  *
37  * The intended uses are:
38  * 1. Generation pseudocode sequences for HW programming.
39  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
40  *
41  * Note: do *not* add any types which are *not* used for HW programming - this
42  * will ensure separation of Logic layer from HW layer.
43  ******************************************************************************/
44 
45 union large_integer {
46 	struct {
47 		uint32_t low_part;
48 		int32_t high_part;
49 	};
50 
51 	struct {
52 		uint32_t low_part;
53 		int32_t high_part;
54 	} u;
55 
56 	int64_t quad_part;
57 };
58 
59 #define PHYSICAL_ADDRESS_LOC union large_integer
60 
61 enum dc_plane_addr_type {
62 	PLN_ADDR_TYPE_GRAPHICS = 0,
63 	PLN_ADDR_TYPE_GRPH_STEREO,
64 	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
65 };
66 
67 struct dc_plane_address {
68 	enum dc_plane_addr_type type;
69 	bool tmz_surface;
70 	union {
71 		struct{
72 			PHYSICAL_ADDRESS_LOC addr;
73 			PHYSICAL_ADDRESS_LOC meta_addr;
74 			union large_integer dcc_const_color;
75 		} grph;
76 
77 		/*stereo*/
78 		struct {
79 			PHYSICAL_ADDRESS_LOC left_addr;
80 			PHYSICAL_ADDRESS_LOC left_meta_addr;
81 			union large_integer left_dcc_const_color;
82 
83 			PHYSICAL_ADDRESS_LOC right_addr;
84 			PHYSICAL_ADDRESS_LOC right_meta_addr;
85 			union large_integer right_dcc_const_color;
86 
87 		} grph_stereo;
88 
89 		/*video  progressive*/
90 		struct {
91 			PHYSICAL_ADDRESS_LOC luma_addr;
92 			PHYSICAL_ADDRESS_LOC luma_meta_addr;
93 			union large_integer luma_dcc_const_color;
94 
95 			PHYSICAL_ADDRESS_LOC chroma_addr;
96 			PHYSICAL_ADDRESS_LOC chroma_meta_addr;
97 			union large_integer chroma_dcc_const_color;
98 		} video_progressive;
99 	};
100 
101 	union large_integer page_table_base;
102 };
103 
104 struct dc_size {
105 	int width;
106 	int height;
107 };
108 
109 struct rect {
110 	int x;
111 	int y;
112 	int width;
113 	int height;
114 };
115 
116 union plane_size {
117 	/* Grph or Video will be selected
118 	 * based on format above:
119 	 * Use Video structure if
120 	 * format >= DalPixelFormat_VideoBegin
121 	 * else use Grph structure
122 	 */
123 	struct {
124 		struct rect surface_size;
125 		/* Graphic surface pitch in pixels.
126 		 * In LINEAR_GENERAL mode, pitch
127 		 * is 32 pixel aligned.
128 		 */
129 		int surface_pitch;
130 	} grph;
131 
132 	struct {
133 		struct rect luma_size;
134 		/* Graphic surface pitch in pixels.
135 		 * In LINEAR_GENERAL mode, pitch is
136 		 * 32 pixel aligned.
137 		 */
138 		int luma_pitch;
139 
140 		struct rect chroma_size;
141 		/* Graphic surface pitch in pixels.
142 		 * In LINEAR_GENERAL mode, pitch is
143 		 * 32 pixel aligned.
144 		 */
145 		int chroma_pitch;
146 	} video;
147 };
148 
149 struct dc_plane_dcc_param {
150 	bool enable;
151 
152 	union {
153 		struct {
154 			int meta_pitch;
155 			bool independent_64b_blks;
156 		} grph;
157 
158 		struct {
159 			int meta_pitch_l;
160 			bool independent_64b_blks_l;
161 
162 			int meta_pitch_c;
163 			bool independent_64b_blks_c;
164 		} video;
165 	};
166 };
167 
168 /*Displayable pixel format in fb*/
169 enum surface_pixel_format {
170 	SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
171 	/*TOBE REMOVED paletta 256 colors*/
172 	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
173 		SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
174 	/*16 bpp*/
175 	SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
176 	/*16 bpp*/
177 	SURFACE_PIXEL_FORMAT_GRPH_RGB565,
178 	/*32 bpp*/
179 	SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
180 	/*32 bpp swaped*/
181 	SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
182 
183 	SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
184 	/*swaped*/
185 	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
186 	/*TOBE REMOVED swaped, XR_BIAS has no differance
187 	 * for pixel layout than previous and we can
188 	 * delete this after discusion*/
189 	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
190 	/*64 bpp */
191 	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
192 	/*float*/
193 	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
194 	/*swaped & float*/
195 	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
196 	/*grow graphics here if necessary */
197 	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
198 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
199 		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
200 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
201 	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
202 	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
203 		SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
204 	SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
205 	SURFACE_PIXEL_FORMAT_INVALID
206 
207 	/*grow 444 video here if necessary */
208 };
209 
210 
211 
212 /* Pixel format */
213 enum pixel_format {
214 	/*graph*/
215 	PIXEL_FORMAT_UNINITIALIZED,
216 	PIXEL_FORMAT_INDEX8,
217 	PIXEL_FORMAT_RGB565,
218 	PIXEL_FORMAT_ARGB8888,
219 	PIXEL_FORMAT_ARGB2101010,
220 	PIXEL_FORMAT_ARGB2101010_XRBIAS,
221 	PIXEL_FORMAT_FP16,
222 	/*video*/
223 	PIXEL_FORMAT_420BPP8,
224 	PIXEL_FORMAT_420BPP10,
225 	/*end of pixel format definition*/
226 	PIXEL_FORMAT_INVALID,
227 
228 	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
229 	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
230 	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
231 	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
232 	PIXEL_FORMAT_UNKNOWN
233 };
234 
235 enum tile_split_values {
236 	DC_DISPLAY_MICRO_TILING = 0x0,
237 	DC_THIN_MICRO_TILING = 0x1,
238 	DC_DEPTH_MICRO_TILING = 0x2,
239 	DC_ROTATED_MICRO_TILING = 0x3,
240 };
241 
242 /* TODO: These values come from hardware spec. We need to readdress this
243  * if they ever change.
244  */
245 enum array_mode_values {
246 	DC_ARRAY_LINEAR_GENERAL = 0,
247 	DC_ARRAY_LINEAR_ALLIGNED,
248 	DC_ARRAY_1D_TILED_THIN1,
249 	DC_ARRAY_1D_TILED_THICK,
250 	DC_ARRAY_2D_TILED_THIN1,
251 	DC_ARRAY_PRT_TILED_THIN1,
252 	DC_ARRAY_PRT_2D_TILED_THIN1,
253 	DC_ARRAY_2D_TILED_THICK,
254 	DC_ARRAY_2D_TILED_X_THICK,
255 	DC_ARRAY_PRT_TILED_THICK,
256 	DC_ARRAY_PRT_2D_TILED_THICK,
257 	DC_ARRAY_PRT_3D_TILED_THIN1,
258 	DC_ARRAY_3D_TILED_THIN1,
259 	DC_ARRAY_3D_TILED_THICK,
260 	DC_ARRAY_3D_TILED_X_THICK,
261 	DC_ARRAY_PRT_3D_TILED_THICK,
262 };
263 
264 enum tile_mode_values {
265 	DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
266 	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
267 };
268 
269 enum swizzle_mode_values {
270 	DC_SW_LINEAR = 0,
271 	DC_SW_256B_S = 1,
272 	DC_SW_256_D = 2,
273 	DC_SW_256_R = 3,
274 	DC_SW_4KB_S = 5,
275 	DC_SW_4KB_D = 6,
276 	DC_SW_4KB_R = 7,
277 	DC_SW_64KB_S = 9,
278 	DC_SW_64KB_D = 10,
279 	DC_SW_64KB_R = 11,
280 	DC_SW_VAR_S = 13,
281 	DC_SW_VAR_D = 14,
282 	DC_SW_VAR_R = 15,
283 	DC_SW_64KB_S_T = 17,
284 	DC_SW_64KB_D_T = 18,
285 	DC_SW_4KB_S_X = 21,
286 	DC_SW_4KB_D_X = 22,
287 	DC_SW_4KB_R_X = 23,
288 	DC_SW_64KB_S_X = 25,
289 	DC_SW_64KB_D_X = 26,
290 	DC_SW_64KB_R_X = 27,
291 	DC_SW_VAR_S_X = 29,
292 	DC_SW_VAR_D_X = 30,
293 	DC_SW_VAR_R_X = 31,
294 	DC_SW_MAX = 32,
295 	DC_SW_UNKNOWN = DC_SW_MAX
296 };
297 
298 union dc_tiling_info {
299 
300 	struct {
301 		/* Specifies the number of memory banks for tiling
302 		 *	purposes.
303 		 * Only applies to 2D and 3D tiling modes.
304 		 *	POSSIBLE VALUES: 2,4,8,16
305 		 */
306 		unsigned int num_banks;
307 		/* Specifies the number of tiles in the x direction
308 		 *	to be incorporated into the same bank.
309 		 * Only applies to 2D and 3D tiling modes.
310 		 *	POSSIBLE VALUES: 1,2,4,8
311 		 */
312 		unsigned int bank_width;
313 		unsigned int bank_width_c;
314 		/* Specifies the number of tiles in the y direction to
315 		 *	be incorporated into the same bank.
316 		 * Only applies to 2D and 3D tiling modes.
317 		 *	POSSIBLE VALUES: 1,2,4,8
318 		 */
319 		unsigned int bank_height;
320 		unsigned int bank_height_c;
321 		/* Specifies the macro tile aspect ratio. Only applies
322 		 * to 2D and 3D tiling modes.
323 		 */
324 		unsigned int tile_aspect;
325 		unsigned int tile_aspect_c;
326 		/* Specifies the number of bytes that will be stored
327 		 *	contiguously for each tile.
328 		 * If the tile data requires more storage than this
329 		 *	amount, it is split into multiple slices.
330 		 * This field must not be larger than
331 		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
332 		 * Only applies to 2D and 3D tiling modes.
333 		 * For color render targets, TILE_SPLIT >= 256B.
334 		 */
335 		enum tile_split_values tile_split;
336 		enum tile_split_values tile_split_c;
337 		/* Specifies the addressing within a tile.
338 		 *	0x0 - DISPLAY_MICRO_TILING
339 		 *	0x1 - THIN_MICRO_TILING
340 		 *	0x2 - DEPTH_MICRO_TILING
341 		 *	0x3 - ROTATED_MICRO_TILING
342 		 */
343 		enum tile_mode_values tile_mode;
344 		enum tile_mode_values tile_mode_c;
345 		/* Specifies the number of pipes and how they are
346 		 *	interleaved in the surface.
347 		 * Refer to memory addressing document for complete
348 		 *	details and constraints.
349 		 */
350 		unsigned int pipe_config;
351 		/* Specifies the tiling mode of the surface.
352 		 * THIN tiles use an 8x8x1 tile size.
353 		 * THICK tiles use an 8x8x4 tile size.
354 		 * 2D tiling modes rotate banks for successive Z slices
355 		 * 3D tiling modes rotate pipes and banks for Z slices
356 		 * Refer to memory addressing document for complete
357 		 *	details and constraints.
358 		 */
359 		enum array_mode_values array_mode;
360 	} gfx8;
361 
362 	struct {
363 		enum swizzle_mode_values swizzle;
364 		unsigned int num_pipes;
365 		unsigned int max_compressed_frags;
366 		unsigned int pipe_interleave;
367 
368 		unsigned int num_banks;
369 		unsigned int num_shader_engines;
370 		unsigned int num_rb_per_se;
371 		bool shaderEnable;
372 
373 		bool meta_linear;
374 		bool rb_aligned;
375 		bool pipe_aligned;
376 	} gfx9;
377 };
378 
379 /* Rotation angle */
380 enum dc_rotation_angle {
381 	ROTATION_ANGLE_0 = 0,
382 	ROTATION_ANGLE_90,
383 	ROTATION_ANGLE_180,
384 	ROTATION_ANGLE_270,
385 	ROTATION_ANGLE_COUNT
386 };
387 
388 enum dc_scan_direction {
389 	SCAN_DIRECTION_UNKNOWN = 0,
390 	SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
391 	SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
392 };
393 
394 struct dc_cursor_position {
395 	uint32_t x;
396 	uint32_t y;
397 
398 	uint32_t x_hotspot;
399 	uint32_t y_hotspot;
400 
401 	/*
402 	 * This parameter indicates whether HW cursor should be enabled
403 	 */
404 	bool enable;
405 
406 };
407 
408 struct dc_cursor_mi_param {
409 	unsigned int pixel_clk_khz;
410 	unsigned int ref_clk_khz;
411 	struct rect viewport;
412 	struct fixed31_32 h_scale_ratio;
413 	struct fixed31_32 v_scale_ratio;
414 	enum dc_rotation_angle rotation;
415 	bool mirror;
416 };
417 
418 /* IPP related types */
419 
420 enum {
421 	GAMMA_RGB_256_ENTRIES = 256,
422 	GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
423 	GAMMA_CS_TFM_1D_ENTRIES = 4096,
424 	GAMMA_CUSTOM_ENTRIES = 4096,
425 	GAMMA_MAX_ENTRIES = 4096
426 };
427 
428 enum dc_gamma_type {
429 	GAMMA_RGB_256 = 1,
430 	GAMMA_RGB_FLOAT_1024 = 2,
431 	GAMMA_CS_TFM_1D = 3,
432 	GAMMA_CUSTOM = 4,
433 };
434 
435 struct dc_csc_transform {
436 	uint16_t matrix[12];
437 	bool enable_adjustment;
438 };
439 
440 struct dc_gamma {
441 	struct kref refcount;
442 	enum dc_gamma_type type;
443 	unsigned int num_entries;
444 
445 	struct dc_gamma_entries {
446 		struct fixed31_32 red[GAMMA_MAX_ENTRIES];
447 		struct fixed31_32 green[GAMMA_MAX_ENTRIES];
448 		struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
449 	} entries;
450 
451 	/* private to DC core */
452 	struct dc_context *ctx;
453 
454 	bool is_identity;
455 };
456 
457 /* Used by both ipp amd opp functions*/
458 /* TODO: to be consolidated with enum color_space */
459 
460 /*
461  * This enum is for programming CURSOR_MODE register field. What this register
462  * should be programmed to depends on OS requested cursor shape flags and what
463  * we stored in the cursor surface.
464  */
465 enum dc_cursor_color_format {
466 	CURSOR_MODE_MONO,
467 	CURSOR_MODE_COLOR_1BIT_AND,
468 	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
469 	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
470 };
471 
472 /*
473  * This is all the parameters required by DAL in order to update the cursor
474  * attributes, including the new cursor image surface address, size, hotspot
475  * location, color format, etc.
476  */
477 
478 union dc_cursor_attribute_flags {
479 	struct {
480 		uint32_t ENABLE_MAGNIFICATION:1;
481 		uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
482 		uint32_t HORIZONTAL_MIRROR:1;
483 		uint32_t VERTICAL_MIRROR:1;
484 		uint32_t INVERT_PIXEL_DATA:1;
485 		uint32_t ZERO_EXPANSION:1;
486 		uint32_t MIN_MAX_INVERT:1;
487 		uint32_t RESERVED:25;
488 	} bits;
489 	uint32_t value;
490 };
491 
492 struct dc_cursor_attributes {
493 	PHYSICAL_ADDRESS_LOC address;
494 	uint32_t pitch;
495 
496 	/* Width and height should correspond to cursor surface width x heigh */
497 	uint32_t width;
498 	uint32_t height;
499 
500 	enum dc_cursor_color_format color_format;
501 	uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
502 
503 	/* In case we support HW Cursor rotation in the future */
504 	enum dc_rotation_angle rotation_angle;
505 
506 	union dc_cursor_attribute_flags attribute_flags;
507 };
508 
509 struct dpp_cursor_attributes {
510 	int bias;
511 	int scale;
512 };
513 
514 /* OPP */
515 
516 enum dc_color_space {
517 	COLOR_SPACE_UNKNOWN,
518 	COLOR_SPACE_SRGB,
519 	COLOR_SPACE_XR_RGB,
520 	COLOR_SPACE_SRGB_LIMITED,
521 	COLOR_SPACE_MSREF_SCRGB,
522 	COLOR_SPACE_YCBCR601,
523 	COLOR_SPACE_YCBCR709,
524 	COLOR_SPACE_XV_YCC_709,
525 	COLOR_SPACE_XV_YCC_601,
526 	COLOR_SPACE_YCBCR601_LIMITED,
527 	COLOR_SPACE_YCBCR709_LIMITED,
528 	COLOR_SPACE_2020_RGB_FULLRANGE,
529 	COLOR_SPACE_2020_RGB_LIMITEDRANGE,
530 	COLOR_SPACE_2020_YCBCR,
531 	COLOR_SPACE_ADOBERGB,
532 	COLOR_SPACE_DCIP3,
533 	COLOR_SPACE_DISPLAYNATIVE,
534 	COLOR_SPACE_DOLBYVISION,
535 	COLOR_SPACE_APPCTRL,
536 	COLOR_SPACE_CUSTOMPOINTS,
537 };
538 
539 enum dc_dither_option {
540 	DITHER_OPTION_DEFAULT,
541 	DITHER_OPTION_DISABLE,
542 	DITHER_OPTION_FM6,
543 	DITHER_OPTION_FM8,
544 	DITHER_OPTION_FM10,
545 	DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
546 	DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
547 	DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
548 	DITHER_OPTION_SPATIAL6,
549 	DITHER_OPTION_SPATIAL8,
550 	DITHER_OPTION_SPATIAL10,
551 	DITHER_OPTION_TRUN6,
552 	DITHER_OPTION_TRUN8,
553 	DITHER_OPTION_TRUN10,
554 	DITHER_OPTION_TRUN10_SPATIAL8,
555 	DITHER_OPTION_TRUN10_SPATIAL6,
556 	DITHER_OPTION_TRUN10_FM8,
557 	DITHER_OPTION_TRUN10_FM6,
558 	DITHER_OPTION_TRUN10_SPATIAL8_FM6,
559 	DITHER_OPTION_SPATIAL10_FM8,
560 	DITHER_OPTION_SPATIAL10_FM6,
561 	DITHER_OPTION_TRUN8_SPATIAL6,
562 	DITHER_OPTION_TRUN8_FM6,
563 	DITHER_OPTION_SPATIAL8_FM6,
564 	DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
565 	DITHER_OPTION_INVALID
566 };
567 
568 enum dc_quantization_range {
569 	QUANTIZATION_RANGE_UNKNOWN,
570 	QUANTIZATION_RANGE_FULL,
571 	QUANTIZATION_RANGE_LIMITED
572 };
573 
574 /* XFM */
575 
576 /* used in  struct dc_plane_state */
577 struct scaling_taps {
578 	uint32_t v_taps;
579 	uint32_t h_taps;
580 	uint32_t v_taps_c;
581 	uint32_t h_taps_c;
582 };
583 
584 enum dc_timing_standard {
585 	DC_TIMING_STANDARD_UNDEFINED,
586 	DC_TIMING_STANDARD_DMT,
587 	DC_TIMING_STANDARD_GTF,
588 	DC_TIMING_STANDARD_CVT,
589 	DC_TIMING_STANDARD_CVT_RB,
590 	DC_TIMING_STANDARD_CEA770,
591 	DC_TIMING_STANDARD_CEA861,
592 	DC_TIMING_STANDARD_HDMI,
593 	DC_TIMING_STANDARD_TV_NTSC,
594 	DC_TIMING_STANDARD_TV_NTSC_J,
595 	DC_TIMING_STANDARD_TV_PAL,
596 	DC_TIMING_STANDARD_TV_PAL_M,
597 	DC_TIMING_STANDARD_TV_PAL_CN,
598 	DC_TIMING_STANDARD_TV_SECAM,
599 	DC_TIMING_STANDARD_EXPLICIT,
600 	/*!< For explicit timings from EDID, VBIOS, etc.*/
601 	DC_TIMING_STANDARD_USER_OVERRIDE,
602 	/*!< For mode timing override by user*/
603 	DC_TIMING_STANDARD_MAX
604 };
605 
606 enum dc_color_depth {
607 	COLOR_DEPTH_UNDEFINED,
608 	COLOR_DEPTH_666,
609 	COLOR_DEPTH_888,
610 	COLOR_DEPTH_101010,
611 	COLOR_DEPTH_121212,
612 	COLOR_DEPTH_141414,
613 	COLOR_DEPTH_161616,
614 	COLOR_DEPTH_COUNT
615 };
616 
617 enum dc_pixel_encoding {
618 	PIXEL_ENCODING_UNDEFINED,
619 	PIXEL_ENCODING_RGB,
620 	PIXEL_ENCODING_YCBCR422,
621 	PIXEL_ENCODING_YCBCR444,
622 	PIXEL_ENCODING_YCBCR420,
623 	PIXEL_ENCODING_COUNT
624 };
625 
626 enum dc_aspect_ratio {
627 	ASPECT_RATIO_NO_DATA,
628 	ASPECT_RATIO_4_3,
629 	ASPECT_RATIO_16_9,
630 	ASPECT_RATIO_64_27,
631 	ASPECT_RATIO_256_135,
632 	ASPECT_RATIO_FUTURE
633 };
634 
635 enum scanning_type {
636 	SCANNING_TYPE_NODATA = 0,
637 	SCANNING_TYPE_OVERSCAN,
638 	SCANNING_TYPE_UNDERSCAN,
639 	SCANNING_TYPE_FUTURE,
640 	SCANNING_TYPE_UNDEFINED
641 };
642 
643 struct dc_crtc_timing_flags {
644 	uint32_t INTERLACE :1;
645 	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
646 	 it is positive polarity --reversed with dal1 or video bios define*/
647 	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
648 	 it is positive polarity --reversed with dal1 or video bios define*/
649 
650 	uint32_t HORZ_COUNT_BY_TWO:1;
651 
652 	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
653 	 timing can be driven in 3D format only
654 	 and there is no corresponding 2D timing*/
655 	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
656 	 (right eye = '1', left eye = '0') */
657 	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
658 	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
659 	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
660 	 because corresponding 2D timing also present in the list*/
661 	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
662 	 and we want to match priority of corresponding 3D timing*/
663 	uint32_t Y_ONLY :1;
664 
665 	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
666 	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
667 
668 	uint32_t FORCE_HDR :1;
669 
670 	/* HDMI 2.0 - Support scrambling for TMDS character
671 	 * rates less than or equal to 340Mcsc */
672 	uint32_t LTE_340MCSC_SCRAMBLE:1;
673 
674 };
675 
676 enum dc_timing_3d_format {
677 	TIMING_3D_FORMAT_NONE,
678 	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
679 	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
680 	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
681 	/* for active DP-HDMI dongle*/
682 	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
683 	TIMING_3D_FORMAT_HW_FRAME_PACKING,
684 	TIMING_3D_FORMAT_SW_FRAME_PACKING,
685 	TIMING_3D_FORMAT_ROW_INTERLEAVE,
686 	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
687 	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
688 	TIMING_3D_FORMAT_SIDE_BY_SIDE,
689 	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
690 	TIMING_3D_FORMAT_SBS_SW_PACKED,
691 	/* Side-by-side, packed by application/driver into 2D frame*/
692 	TIMING_3D_FORMAT_TB_SW_PACKED,
693 	/* Top-and-bottom, packed by application/driver into 2D frame*/
694 
695 	TIMING_3D_FORMAT_MAX,
696 };
697 
698 enum trigger_delay {
699 	TRIGGER_DELAY_NEXT_PIXEL = 0,
700 	TRIGGER_DELAY_NEXT_LINE,
701 };
702 
703 enum crtc_event {
704 	CRTC_EVENT_VSYNC_RISING = 0,
705 	CRTC_EVENT_VSYNC_FALLING
706 };
707 
708 struct crtc_trigger_info {
709 	bool enabled;
710 	struct dc_stream_state *event_source;
711 	enum crtc_event event;
712 	enum trigger_delay delay;
713 };
714 
715 struct dc_crtc_timing_adjust {
716 	uint32_t v_total_min;
717 	uint32_t v_total_max;
718 };
719 
720 struct dc_crtc_timing {
721 	uint32_t h_total;
722 	uint32_t h_border_left;
723 	uint32_t h_addressable;
724 	uint32_t h_border_right;
725 	uint32_t h_front_porch;
726 	uint32_t h_sync_width;
727 
728 	uint32_t v_total;
729 	uint32_t v_border_top;
730 	uint32_t v_addressable;
731 	uint32_t v_border_bottom;
732 	uint32_t v_front_porch;
733 	uint32_t v_sync_width;
734 
735 	uint32_t pix_clk_100hz;
736 
737 	uint32_t vic;
738 	uint32_t hdmi_vic;
739 	enum dc_timing_3d_format timing_3d_format;
740 	enum dc_color_depth display_color_depth;
741 	enum dc_pixel_encoding pixel_encoding;
742 	enum dc_aspect_ratio aspect_ratio;
743 	enum scanning_type scan_type;
744 
745 	struct dc_crtc_timing_flags flags;
746 };
747 
748 #define MAX_TG_COLOR_VALUE 0x3FF
749 struct tg_color {
750 	/* Maximum 10 bits color value */
751 	uint16_t color_r_cr;
752 	uint16_t color_g_y;
753 	uint16_t color_b_cb;
754 };
755 
756 #endif /* DC_HW_TYPES_H */
757 
758