1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HW_TYPES_H 27 #define DC_HW_TYPES_H 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "signal_types.h" 32 33 /****************************************************************************** 34 * Data types for Virtual HW Layer of DAL3. 35 * (see DAL3 design documents for HW Layer definition) 36 * 37 * The intended uses are: 38 * 1. Generation pseudocode sequences for HW programming. 39 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 40 * 41 * Note: do *not* add any types which are *not* used for HW programming - this 42 * will ensure separation of Logic layer from HW layer. 43 ******************************************************************************/ 44 45 union large_integer { 46 struct { 47 uint32_t low_part; 48 int32_t high_part; 49 }; 50 51 struct { 52 uint32_t low_part; 53 int32_t high_part; 54 } u; 55 56 int64_t quad_part; 57 }; 58 59 #define PHYSICAL_ADDRESS_LOC union large_integer 60 61 enum dc_plane_addr_type { 62 PLN_ADDR_TYPE_GRAPHICS = 0, 63 PLN_ADDR_TYPE_GRPH_STEREO, 64 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 65 }; 66 67 struct dc_plane_address { 68 enum dc_plane_addr_type type; 69 bool tmz_surface; 70 union { 71 struct{ 72 PHYSICAL_ADDRESS_LOC addr; 73 PHYSICAL_ADDRESS_LOC meta_addr; 74 union large_integer dcc_const_color; 75 } grph; 76 77 /*stereo*/ 78 struct { 79 PHYSICAL_ADDRESS_LOC left_addr; 80 PHYSICAL_ADDRESS_LOC left_meta_addr; 81 union large_integer left_dcc_const_color; 82 83 PHYSICAL_ADDRESS_LOC right_addr; 84 PHYSICAL_ADDRESS_LOC right_meta_addr; 85 union large_integer right_dcc_const_color; 86 87 } grph_stereo; 88 89 /*video progressive*/ 90 struct { 91 PHYSICAL_ADDRESS_LOC luma_addr; 92 PHYSICAL_ADDRESS_LOC luma_meta_addr; 93 union large_integer luma_dcc_const_color; 94 95 PHYSICAL_ADDRESS_LOC chroma_addr; 96 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 97 union large_integer chroma_dcc_const_color; 98 } video_progressive; 99 }; 100 101 union large_integer page_table_base; 102 103 uint8_t vmid; 104 }; 105 106 struct dc_size { 107 int width; 108 int height; 109 }; 110 111 struct rect { 112 int x; 113 int y; 114 int width; 115 int height; 116 }; 117 118 struct plane_size { 119 /* Graphic surface pitch in pixels. 120 * In LINEAR_GENERAL mode, pitch 121 * is 32 pixel aligned. 122 */ 123 int surface_pitch; 124 int chroma_pitch; 125 struct rect surface_size; 126 struct rect chroma_size; 127 }; 128 129 struct dc_plane_dcc_param { 130 bool enable; 131 132 int meta_pitch; 133 bool independent_64b_blks; 134 135 int meta_pitch_c; 136 bool independent_64b_blks_c; 137 }; 138 139 /*Displayable pixel format in fb*/ 140 enum surface_pixel_format { 141 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 142 /*TOBE REMOVED paletta 256 colors*/ 143 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 144 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 145 /*16 bpp*/ 146 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 147 /*16 bpp*/ 148 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 149 /*32 bpp*/ 150 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 151 /*32 bpp swaped*/ 152 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 153 154 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 155 /*swaped*/ 156 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 157 /*TOBE REMOVED swaped, XR_BIAS has no differance 158 * for pixel layout than previous and we can 159 * delete this after discusion*/ 160 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 161 /*64 bpp */ 162 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 163 /*float*/ 164 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 165 /*swaped & float*/ 166 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 167 /*grow graphics here if necessary */ 168 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 169 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 170 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 171 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 172 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 173 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 174 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 175 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 176 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 177 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 178 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 179 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, 180 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 181 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 182 SURFACE_PIXEL_FORMAT_INVALID 183 184 /*grow 444 video here if necessary */ 185 }; 186 187 188 189 /* Pixel format */ 190 enum pixel_format { 191 /*graph*/ 192 PIXEL_FORMAT_UNINITIALIZED, 193 PIXEL_FORMAT_INDEX8, 194 PIXEL_FORMAT_RGB565, 195 PIXEL_FORMAT_ARGB8888, 196 PIXEL_FORMAT_ARGB2101010, 197 PIXEL_FORMAT_ARGB2101010_XRBIAS, 198 PIXEL_FORMAT_FP16, 199 /*video*/ 200 PIXEL_FORMAT_420BPP8, 201 PIXEL_FORMAT_420BPP10, 202 /*end of pixel format definition*/ 203 PIXEL_FORMAT_INVALID, 204 205 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 206 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 207 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 208 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 209 PIXEL_FORMAT_UNKNOWN 210 }; 211 212 enum tile_split_values { 213 DC_DISPLAY_MICRO_TILING = 0x0, 214 DC_THIN_MICRO_TILING = 0x1, 215 DC_DEPTH_MICRO_TILING = 0x2, 216 DC_ROTATED_MICRO_TILING = 0x3, 217 }; 218 219 enum tripleBuffer_enable { 220 DC_TRIPLEBUFFER_DISABLE = 0x0, 221 DC_TRIPLEBUFFER_ENABLE = 0x1, 222 }; 223 224 /* TODO: These values come from hardware spec. We need to readdress this 225 * if they ever change. 226 */ 227 enum array_mode_values { 228 DC_ARRAY_LINEAR_GENERAL = 0, 229 DC_ARRAY_LINEAR_ALLIGNED, 230 DC_ARRAY_1D_TILED_THIN1, 231 DC_ARRAY_1D_TILED_THICK, 232 DC_ARRAY_2D_TILED_THIN1, 233 DC_ARRAY_PRT_TILED_THIN1, 234 DC_ARRAY_PRT_2D_TILED_THIN1, 235 DC_ARRAY_2D_TILED_THICK, 236 DC_ARRAY_2D_TILED_X_THICK, 237 DC_ARRAY_PRT_TILED_THICK, 238 DC_ARRAY_PRT_2D_TILED_THICK, 239 DC_ARRAY_PRT_3D_TILED_THIN1, 240 DC_ARRAY_3D_TILED_THIN1, 241 DC_ARRAY_3D_TILED_THICK, 242 DC_ARRAY_3D_TILED_X_THICK, 243 DC_ARRAY_PRT_3D_TILED_THICK, 244 }; 245 246 enum tile_mode_values { 247 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 248 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 249 }; 250 251 enum swizzle_mode_values { 252 DC_SW_LINEAR = 0, 253 DC_SW_256B_S = 1, 254 DC_SW_256_D = 2, 255 DC_SW_256_R = 3, 256 DC_SW_4KB_S = 5, 257 DC_SW_4KB_D = 6, 258 DC_SW_4KB_R = 7, 259 DC_SW_64KB_S = 9, 260 DC_SW_64KB_D = 10, 261 DC_SW_64KB_R = 11, 262 DC_SW_VAR_S = 13, 263 DC_SW_VAR_D = 14, 264 DC_SW_VAR_R = 15, 265 DC_SW_64KB_S_T = 17, 266 DC_SW_64KB_D_T = 18, 267 DC_SW_4KB_S_X = 21, 268 DC_SW_4KB_D_X = 22, 269 DC_SW_4KB_R_X = 23, 270 DC_SW_64KB_S_X = 25, 271 DC_SW_64KB_D_X = 26, 272 DC_SW_64KB_R_X = 27, 273 DC_SW_VAR_S_X = 29, 274 DC_SW_VAR_D_X = 30, 275 DC_SW_VAR_R_X = 31, 276 DC_SW_MAX = 32, 277 DC_SW_UNKNOWN = DC_SW_MAX 278 }; 279 280 union dc_tiling_info { 281 282 struct { 283 /* Specifies the number of memory banks for tiling 284 * purposes. 285 * Only applies to 2D and 3D tiling modes. 286 * POSSIBLE VALUES: 2,4,8,16 287 */ 288 unsigned int num_banks; 289 /* Specifies the number of tiles in the x direction 290 * to be incorporated into the same bank. 291 * Only applies to 2D and 3D tiling modes. 292 * POSSIBLE VALUES: 1,2,4,8 293 */ 294 unsigned int bank_width; 295 unsigned int bank_width_c; 296 /* Specifies the number of tiles in the y direction to 297 * be incorporated into the same bank. 298 * Only applies to 2D and 3D tiling modes. 299 * POSSIBLE VALUES: 1,2,4,8 300 */ 301 unsigned int bank_height; 302 unsigned int bank_height_c; 303 /* Specifies the macro tile aspect ratio. Only applies 304 * to 2D and 3D tiling modes. 305 */ 306 unsigned int tile_aspect; 307 unsigned int tile_aspect_c; 308 /* Specifies the number of bytes that will be stored 309 * contiguously for each tile. 310 * If the tile data requires more storage than this 311 * amount, it is split into multiple slices. 312 * This field must not be larger than 313 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 314 * Only applies to 2D and 3D tiling modes. 315 * For color render targets, TILE_SPLIT >= 256B. 316 */ 317 enum tile_split_values tile_split; 318 enum tile_split_values tile_split_c; 319 /* Specifies the addressing within a tile. 320 * 0x0 - DISPLAY_MICRO_TILING 321 * 0x1 - THIN_MICRO_TILING 322 * 0x2 - DEPTH_MICRO_TILING 323 * 0x3 - ROTATED_MICRO_TILING 324 */ 325 enum tile_mode_values tile_mode; 326 enum tile_mode_values tile_mode_c; 327 /* Specifies the number of pipes and how they are 328 * interleaved in the surface. 329 * Refer to memory addressing document for complete 330 * details and constraints. 331 */ 332 unsigned int pipe_config; 333 /* Specifies the tiling mode of the surface. 334 * THIN tiles use an 8x8x1 tile size. 335 * THICK tiles use an 8x8x4 tile size. 336 * 2D tiling modes rotate banks for successive Z slices 337 * 3D tiling modes rotate pipes and banks for Z slices 338 * Refer to memory addressing document for complete 339 * details and constraints. 340 */ 341 enum array_mode_values array_mode; 342 } gfx8; 343 344 struct { 345 enum swizzle_mode_values swizzle; 346 unsigned int num_pipes; 347 unsigned int max_compressed_frags; 348 unsigned int pipe_interleave; 349 350 unsigned int num_banks; 351 unsigned int num_shader_engines; 352 unsigned int num_rb_per_se; 353 bool shaderEnable; 354 355 bool meta_linear; 356 bool rb_aligned; 357 bool pipe_aligned; 358 } gfx9; 359 }; 360 361 /* Rotation angle */ 362 enum dc_rotation_angle { 363 ROTATION_ANGLE_0 = 0, 364 ROTATION_ANGLE_90, 365 ROTATION_ANGLE_180, 366 ROTATION_ANGLE_270, 367 ROTATION_ANGLE_COUNT 368 }; 369 370 enum dc_scan_direction { 371 SCAN_DIRECTION_UNKNOWN = 0, 372 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 373 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 374 }; 375 376 struct dc_cursor_position { 377 uint32_t x; 378 uint32_t y; 379 380 uint32_t x_hotspot; 381 uint32_t y_hotspot; 382 383 /* 384 * This parameter indicates whether HW cursor should be enabled 385 */ 386 bool enable; 387 388 }; 389 390 struct dc_cursor_mi_param { 391 unsigned int pixel_clk_khz; 392 unsigned int ref_clk_khz; 393 struct rect viewport; 394 struct fixed31_32 h_scale_ratio; 395 struct fixed31_32 v_scale_ratio; 396 enum dc_rotation_angle rotation; 397 bool mirror; 398 }; 399 400 /* IPP related types */ 401 402 enum { 403 GAMMA_RGB_256_ENTRIES = 256, 404 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 405 GAMMA_CS_TFM_1D_ENTRIES = 4096, 406 GAMMA_CUSTOM_ENTRIES = 4096, 407 GAMMA_MAX_ENTRIES = 4096 408 }; 409 410 enum dc_gamma_type { 411 GAMMA_RGB_256 = 1, 412 GAMMA_RGB_FLOAT_1024 = 2, 413 GAMMA_CS_TFM_1D = 3, 414 GAMMA_CUSTOM = 4, 415 }; 416 417 struct dc_csc_transform { 418 uint16_t matrix[12]; 419 bool enable_adjustment; 420 }; 421 422 struct dc_rgb_fixed { 423 struct fixed31_32 red; 424 struct fixed31_32 green; 425 struct fixed31_32 blue; 426 }; 427 428 struct dc_gamma { 429 struct kref refcount; 430 enum dc_gamma_type type; 431 unsigned int num_entries; 432 433 struct dc_gamma_entries { 434 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 435 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 436 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 437 } entries; 438 439 /* private to DC core */ 440 struct dc_context *ctx; 441 442 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 443 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 444 */ 445 bool is_identity; 446 }; 447 448 /* Used by both ipp amd opp functions*/ 449 /* TODO: to be consolidated with enum color_space */ 450 451 /* 452 * This enum is for programming CURSOR_MODE register field. What this register 453 * should be programmed to depends on OS requested cursor shape flags and what 454 * we stored in the cursor surface. 455 */ 456 enum dc_cursor_color_format { 457 CURSOR_MODE_MONO, 458 CURSOR_MODE_COLOR_1BIT_AND, 459 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 460 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 461 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 462 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 463 }; 464 465 /* 466 * This is all the parameters required by DAL in order to update the cursor 467 * attributes, including the new cursor image surface address, size, hotspot 468 * location, color format, etc. 469 */ 470 471 union dc_cursor_attribute_flags { 472 struct { 473 uint32_t ENABLE_MAGNIFICATION:1; 474 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 475 uint32_t HORIZONTAL_MIRROR:1; 476 uint32_t VERTICAL_MIRROR:1; 477 uint32_t INVERT_PIXEL_DATA:1; 478 uint32_t ZERO_EXPANSION:1; 479 uint32_t MIN_MAX_INVERT:1; 480 uint32_t ENABLE_CURSOR_DEGAMMA:1; 481 uint32_t RESERVED:24; 482 } bits; 483 uint32_t value; 484 }; 485 486 struct dc_cursor_attributes { 487 PHYSICAL_ADDRESS_LOC address; 488 uint32_t pitch; 489 490 /* Width and height should correspond to cursor surface width x heigh */ 491 uint32_t width; 492 uint32_t height; 493 494 enum dc_cursor_color_format color_format; 495 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 496 497 /* In case we support HW Cursor rotation in the future */ 498 enum dc_rotation_angle rotation_angle; 499 500 union dc_cursor_attribute_flags attribute_flags; 501 }; 502 503 struct dpp_cursor_attributes { 504 int bias; 505 int scale; 506 }; 507 508 /* OPP */ 509 510 enum dc_color_space { 511 COLOR_SPACE_UNKNOWN, 512 COLOR_SPACE_SRGB, 513 COLOR_SPACE_XR_RGB, 514 COLOR_SPACE_SRGB_LIMITED, 515 COLOR_SPACE_MSREF_SCRGB, 516 COLOR_SPACE_YCBCR601, 517 COLOR_SPACE_YCBCR709, 518 COLOR_SPACE_XV_YCC_709, 519 COLOR_SPACE_XV_YCC_601, 520 COLOR_SPACE_YCBCR601_LIMITED, 521 COLOR_SPACE_YCBCR709_LIMITED, 522 COLOR_SPACE_2020_RGB_FULLRANGE, 523 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 524 COLOR_SPACE_2020_YCBCR, 525 COLOR_SPACE_ADOBERGB, 526 COLOR_SPACE_DCIP3, 527 COLOR_SPACE_DISPLAYNATIVE, 528 COLOR_SPACE_DOLBYVISION, 529 COLOR_SPACE_APPCTRL, 530 COLOR_SPACE_CUSTOMPOINTS, 531 COLOR_SPACE_YCBCR709_BLACK, 532 }; 533 534 enum dc_dither_option { 535 DITHER_OPTION_DEFAULT, 536 DITHER_OPTION_DISABLE, 537 DITHER_OPTION_FM6, 538 DITHER_OPTION_FM8, 539 DITHER_OPTION_FM10, 540 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 541 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 542 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 543 DITHER_OPTION_SPATIAL6, 544 DITHER_OPTION_SPATIAL8, 545 DITHER_OPTION_SPATIAL10, 546 DITHER_OPTION_TRUN6, 547 DITHER_OPTION_TRUN8, 548 DITHER_OPTION_TRUN10, 549 DITHER_OPTION_TRUN10_SPATIAL8, 550 DITHER_OPTION_TRUN10_SPATIAL6, 551 DITHER_OPTION_TRUN10_FM8, 552 DITHER_OPTION_TRUN10_FM6, 553 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 554 DITHER_OPTION_SPATIAL10_FM8, 555 DITHER_OPTION_SPATIAL10_FM6, 556 DITHER_OPTION_TRUN8_SPATIAL6, 557 DITHER_OPTION_TRUN8_FM6, 558 DITHER_OPTION_SPATIAL8_FM6, 559 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 560 DITHER_OPTION_INVALID 561 }; 562 563 enum dc_quantization_range { 564 QUANTIZATION_RANGE_UNKNOWN, 565 QUANTIZATION_RANGE_FULL, 566 QUANTIZATION_RANGE_LIMITED 567 }; 568 569 enum dc_dynamic_expansion { 570 DYN_EXPANSION_AUTO, 571 DYN_EXPANSION_DISABLE 572 }; 573 574 /* XFM */ 575 576 /* used in struct dc_plane_state */ 577 struct scaling_taps { 578 uint32_t v_taps; 579 uint32_t h_taps; 580 uint32_t v_taps_c; 581 uint32_t h_taps_c; 582 bool integer_scaling; 583 }; 584 585 enum dc_timing_standard { 586 DC_TIMING_STANDARD_UNDEFINED, 587 DC_TIMING_STANDARD_DMT, 588 DC_TIMING_STANDARD_GTF, 589 DC_TIMING_STANDARD_CVT, 590 DC_TIMING_STANDARD_CVT_RB, 591 DC_TIMING_STANDARD_CEA770, 592 DC_TIMING_STANDARD_CEA861, 593 DC_TIMING_STANDARD_HDMI, 594 DC_TIMING_STANDARD_TV_NTSC, 595 DC_TIMING_STANDARD_TV_NTSC_J, 596 DC_TIMING_STANDARD_TV_PAL, 597 DC_TIMING_STANDARD_TV_PAL_M, 598 DC_TIMING_STANDARD_TV_PAL_CN, 599 DC_TIMING_STANDARD_TV_SECAM, 600 DC_TIMING_STANDARD_EXPLICIT, 601 /*!< For explicit timings from EDID, VBIOS, etc.*/ 602 DC_TIMING_STANDARD_USER_OVERRIDE, 603 /*!< For mode timing override by user*/ 604 DC_TIMING_STANDARD_MAX 605 }; 606 607 enum dc_color_depth { 608 COLOR_DEPTH_UNDEFINED, 609 COLOR_DEPTH_666, 610 COLOR_DEPTH_888, 611 COLOR_DEPTH_101010, 612 COLOR_DEPTH_121212, 613 COLOR_DEPTH_141414, 614 COLOR_DEPTH_161616, 615 COLOR_DEPTH_999, 616 COLOR_DEPTH_111111, 617 COLOR_DEPTH_COUNT 618 }; 619 620 enum dc_pixel_encoding { 621 PIXEL_ENCODING_UNDEFINED, 622 PIXEL_ENCODING_RGB, 623 PIXEL_ENCODING_YCBCR422, 624 PIXEL_ENCODING_YCBCR444, 625 PIXEL_ENCODING_YCBCR420, 626 PIXEL_ENCODING_COUNT 627 }; 628 629 enum dc_aspect_ratio { 630 ASPECT_RATIO_NO_DATA, 631 ASPECT_RATIO_4_3, 632 ASPECT_RATIO_16_9, 633 ASPECT_RATIO_64_27, 634 ASPECT_RATIO_256_135, 635 ASPECT_RATIO_FUTURE 636 }; 637 638 enum scanning_type { 639 SCANNING_TYPE_NODATA = 0, 640 SCANNING_TYPE_OVERSCAN, 641 SCANNING_TYPE_UNDERSCAN, 642 SCANNING_TYPE_FUTURE, 643 SCANNING_TYPE_UNDEFINED 644 }; 645 646 struct dc_crtc_timing_flags { 647 uint32_t INTERLACE :1; 648 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 649 it is positive polarity --reversed with dal1 or video bios define*/ 650 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 651 it is positive polarity --reversed with dal1 or video bios define*/ 652 653 uint32_t HORZ_COUNT_BY_TWO:1; 654 655 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 656 timing can be driven in 3D format only 657 and there is no corresponding 2D timing*/ 658 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 659 (right eye = '1', left eye = '0') */ 660 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 661 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 662 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 663 because corresponding 2D timing also present in the list*/ 664 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 665 and we want to match priority of corresponding 3D timing*/ 666 uint32_t Y_ONLY :1; 667 668 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 669 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 670 671 uint32_t FORCE_HDR :1; 672 673 /* HDMI 2.0 - Support scrambling for TMDS character 674 * rates less than or equal to 340Mcsc */ 675 uint32_t LTE_340MCSC_SCRAMBLE:1; 676 677 uint32_t DSC : 1; /* Use DSC with this timing */ 678 }; 679 680 enum dc_timing_3d_format { 681 TIMING_3D_FORMAT_NONE, 682 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 683 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 684 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 685 /* for active DP-HDMI dongle*/ 686 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 687 TIMING_3D_FORMAT_HW_FRAME_PACKING, 688 TIMING_3D_FORMAT_SW_FRAME_PACKING, 689 TIMING_3D_FORMAT_ROW_INTERLEAVE, 690 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 691 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 692 TIMING_3D_FORMAT_SIDE_BY_SIDE, 693 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 694 TIMING_3D_FORMAT_SBS_SW_PACKED, 695 /* Side-by-side, packed by application/driver into 2D frame*/ 696 TIMING_3D_FORMAT_TB_SW_PACKED, 697 /* Top-and-bottom, packed by application/driver into 2D frame*/ 698 699 TIMING_3D_FORMAT_MAX, 700 }; 701 702 struct dc_dsc_config { 703 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 704 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 705 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 706 bool block_pred_enable; /* DSC block prediction enable */ 707 uint32_t linebuf_depth; /* DSC line buffer depth */ 708 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 709 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 710 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 711 }; 712 struct dc_crtc_timing { 713 uint32_t h_total; 714 uint32_t h_border_left; 715 uint32_t h_addressable; 716 uint32_t h_border_right; 717 uint32_t h_front_porch; 718 uint32_t h_sync_width; 719 720 uint32_t v_total; 721 uint32_t v_border_top; 722 uint32_t v_addressable; 723 uint32_t v_border_bottom; 724 uint32_t v_front_porch; 725 uint32_t v_sync_width; 726 727 uint32_t pix_clk_100hz; 728 729 uint32_t vic; 730 uint32_t hdmi_vic; 731 enum dc_timing_3d_format timing_3d_format; 732 enum dc_color_depth display_color_depth; 733 enum dc_pixel_encoding pixel_encoding; 734 enum dc_aspect_ratio aspect_ratio; 735 enum scanning_type scan_type; 736 737 struct dc_crtc_timing_flags flags; 738 struct dc_dsc_config dsc_cfg; 739 }; 740 741 enum trigger_delay { 742 TRIGGER_DELAY_NEXT_PIXEL = 0, 743 TRIGGER_DELAY_NEXT_LINE, 744 }; 745 746 enum crtc_event { 747 CRTC_EVENT_VSYNC_RISING = 0, 748 CRTC_EVENT_VSYNC_FALLING 749 }; 750 751 struct crtc_trigger_info { 752 bool enabled; 753 struct dc_stream_state *event_source; 754 enum crtc_event event; 755 enum trigger_delay delay; 756 }; 757 758 struct dc_crtc_timing_adjust { 759 uint32_t v_total_min; 760 uint32_t v_total_max; 761 uint32_t v_total_mid; 762 uint32_t v_total_mid_frame_num; 763 }; 764 765 766 /* Passed on init */ 767 enum vram_type { 768 VIDEO_MEMORY_TYPE_GDDR5 = 2, 769 VIDEO_MEMORY_TYPE_DDR3 = 3, 770 VIDEO_MEMORY_TYPE_DDR4 = 4, 771 VIDEO_MEMORY_TYPE_HBM = 5, 772 VIDEO_MEMORY_TYPE_GDDR6 = 6, 773 }; 774 775 enum dwb_cnv_out_bpc { 776 DWB_CNV_OUT_BPC_8BPC = 0, 777 DWB_CNV_OUT_BPC_10BPC = 1, 778 }; 779 780 enum dwb_output_depth { 781 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 782 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 783 }; 784 785 enum dwb_capture_rate { 786 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 787 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 788 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 789 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 790 }; 791 792 enum dwb_scaler_mode { 793 dwb_scaler_mode_bypass444 = 0, 794 dwb_scaler_mode_rgb444 = 1, 795 dwb_scaler_mode_yuv444 = 2, 796 dwb_scaler_mode_yuv420 = 3 797 }; 798 799 enum dwb_subsample_position { 800 DWB_INTERSTITIAL_SUBSAMPLING = 0, 801 DWB_COSITED_SUBSAMPLING = 1 802 }; 803 804 enum dwb_stereo_eye_select { 805 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 806 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 807 }; 808 809 enum dwb_stereo_type { 810 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 811 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 812 }; 813 814 #define MCIF_BUF_COUNT 4 815 816 struct mcif_buf_params { 817 unsigned long long luma_address[MCIF_BUF_COUNT]; 818 unsigned long long chroma_address[MCIF_BUF_COUNT]; 819 unsigned int luma_pitch; 820 unsigned int chroma_pitch; 821 unsigned int warmup_pitch; 822 unsigned int swlock; 823 }; 824 825 826 #define MAX_TG_COLOR_VALUE 0x3FF 827 struct tg_color { 828 /* Maximum 10 bits color value */ 829 uint16_t color_r_cr; 830 uint16_t color_g_y; 831 uint16_t color_b_cb; 832 }; 833 834 #endif /* DC_HW_TYPES_H */ 835 836