1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_dp_types.h" 36 #include "dc_hw_types.h" 37 #include "dal_types.h" 38 #include "grph_object_defs.h" 39 40 #ifdef CONFIG_DRM_AMD_DC_HDCP 41 #include "dm_cp_psp.h" 42 #endif 43 44 /* forward declarations */ 45 struct dc_plane_state; 46 struct dc_stream_state; 47 struct dc_link; 48 struct dc_sink; 49 struct dal; 50 struct dc_dmub_srv; 51 52 /******************************** 53 * Environment definitions 54 ********************************/ 55 enum dce_environment { 56 DCE_ENV_PRODUCTION_DRV = 0, 57 /* Emulation on FPGA, in "Maximus" System. 58 * This environment enforces that *only* DC registers accessed. 59 * (access to non-DC registers will hang FPGA) */ 60 DCE_ENV_FPGA_MAXIMUS, 61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 62 * requirements of Diagnostics team. */ 63 DCE_ENV_DIAG, 64 /* 65 * Guest VM system, DC HW may exist but is not virtualized and 66 * should not be used. SW support for VDI only. 67 */ 68 DCE_ENV_VIRTUAL_HW 69 }; 70 71 /* Note: use these macro definitions instead of direct comparison! */ 72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 73 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 74 75 #define IS_DIAG_DC(dce_environment) \ 76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 77 78 struct hw_asic_id { 79 uint32_t chip_id; 80 uint32_t chip_family; 81 uint32_t pci_revision_id; 82 uint32_t hw_internal_rev; 83 uint32_t vram_type; 84 uint32_t vram_width; 85 uint32_t feature_flags; 86 uint32_t fake_paths_num; 87 void *atombios_base_address; 88 }; 89 90 struct dc_perf_trace { 91 unsigned long read_count; 92 unsigned long write_count; 93 unsigned long last_entry_read; 94 unsigned long last_entry_write; 95 }; 96 97 struct dc_context { 98 struct dc *dc; 99 100 void *driver_context; /* e.g. amdgpu_device */ 101 struct dc_perf_trace *perf_trace; 102 void *cgs_device; 103 104 enum dce_environment dce_environment; 105 struct hw_asic_id asic_id; 106 107 /* todo: below should probably move to dc. to facilitate removal 108 * of AS we will store these here 109 */ 110 enum dce_version dce_version; 111 struct dc_bios *dc_bios; 112 bool created_bios; 113 struct gpio_service *gpio_service; 114 uint32_t dc_sink_id_count; 115 uint32_t dc_stream_id_count; 116 uint64_t fbc_gpu_addr; 117 struct dc_dmub_srv *dmub_srv; 118 119 #ifdef CONFIG_DRM_AMD_DC_HDCP 120 struct cp_psp cp_psp; 121 #endif 122 }; 123 124 125 #define DC_MAX_EDID_BUFFER_SIZE 1024 126 #define DC_EDID_BLOCK_SIZE 128 127 #define MAX_SURFACE_NUM 4 128 #define NUM_PIXEL_FORMATS 10 129 #define MAX_REPEATER_CNT 8 130 131 #include "dc_ddc_types.h" 132 133 enum tiling_mode { 134 TILING_MODE_INVALID, 135 TILING_MODE_LINEAR, 136 TILING_MODE_TILED, 137 TILING_MODE_COUNT 138 }; 139 140 enum view_3d_format { 141 VIEW_3D_FORMAT_NONE = 0, 142 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 143 VIEW_3D_FORMAT_SIDE_BY_SIDE, 144 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 145 VIEW_3D_FORMAT_COUNT, 146 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 147 }; 148 149 enum plane_stereo_format { 150 PLANE_STEREO_FORMAT_NONE = 0, 151 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 152 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 153 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 154 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 155 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 156 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 157 }; 158 159 /* TODO: Find way to calculate number of bits 160 * Please increase if pixel_format enum increases 161 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 162 */ 163 164 enum dc_edid_connector_type { 165 DC_EDID_CONNECTOR_UNKNOWN = 0, 166 DC_EDID_CONNECTOR_ANALOG = 1, 167 DC_EDID_CONNECTOR_DIGITAL = 10, 168 DC_EDID_CONNECTOR_DVI = 11, 169 DC_EDID_CONNECTOR_HDMIA = 12, 170 DC_EDID_CONNECTOR_MDDI = 14, 171 DC_EDID_CONNECTOR_DISPLAYPORT = 15 172 }; 173 174 enum dc_edid_status { 175 EDID_OK, 176 EDID_BAD_INPUT, 177 EDID_NO_RESPONSE, 178 EDID_BAD_CHECKSUM, 179 EDID_THE_SAME, 180 }; 181 182 enum act_return_status { 183 ACT_SUCCESS, 184 ACT_LINK_LOST, 185 ACT_FAILED 186 }; 187 188 /* audio capability from EDID*/ 189 struct dc_cea_audio_mode { 190 uint8_t format_code; /* ucData[0] [6:3]*/ 191 uint8_t channel_count; /* ucData[0] [2:0]*/ 192 uint8_t sample_rate; /* ucData[1]*/ 193 union { 194 uint8_t sample_size; /* for LPCM*/ 195 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 196 uint8_t max_bit_rate; 197 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 198 }; 199 }; 200 201 struct dc_edid { 202 uint32_t length; 203 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 204 }; 205 206 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 207 * is used. In this case we assume speaker location are: front left, front 208 * right and front center. */ 209 #define DEFAULT_SPEAKER_LOCATION 5 210 211 #define DC_MAX_AUDIO_DESC_COUNT 16 212 213 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 214 215 union display_content_support { 216 unsigned int raw; 217 struct { 218 unsigned int valid_content_type :1; 219 unsigned int game_content :1; 220 unsigned int cinema_content :1; 221 unsigned int photo_content :1; 222 unsigned int graphics_content :1; 223 unsigned int reserved :27; 224 } bits; 225 }; 226 227 struct dc_panel_patch { 228 unsigned int dppowerup_delay; 229 unsigned int extra_t12_ms; 230 unsigned int extra_delay_backlight_off; 231 unsigned int extra_t7_ms; 232 unsigned int manage_secondary_link; 233 }; 234 235 struct dc_edid_caps { 236 /* sink identification */ 237 uint16_t manufacturer_id; 238 uint16_t product_id; 239 uint32_t serial_number; 240 uint8_t manufacture_week; 241 uint8_t manufacture_year; 242 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 243 244 /* audio caps */ 245 uint8_t speaker_flags; 246 uint32_t audio_mode_count; 247 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 248 uint32_t audio_latency; 249 uint32_t video_latency; 250 251 union display_content_support content_support; 252 253 uint8_t qs_bit; 254 uint8_t qy_bit; 255 256 /*HDMI 2.0 caps*/ 257 bool lte_340mcsc_scramble; 258 259 bool edid_hdmi; 260 bool hdr_supported; 261 262 struct dc_panel_patch panel_patch; 263 }; 264 265 struct view { 266 uint32_t width; 267 uint32_t height; 268 }; 269 270 struct dc_mode_flags { 271 /* note: part of refresh rate flag*/ 272 uint32_t INTERLACE :1; 273 /* native display timing*/ 274 uint32_t NATIVE :1; 275 /* preferred is the recommended mode, one per display */ 276 uint32_t PREFERRED :1; 277 /* true if this mode should use reduced blanking timings 278 *_not_ related to the Reduced Blanking adjustment*/ 279 uint32_t REDUCED_BLANKING :1; 280 /* note: part of refreshrate flag*/ 281 uint32_t VIDEO_OPTIMIZED_RATE :1; 282 /* should be reported to upper layers as mode_flags*/ 283 uint32_t PACKED_PIXEL_FORMAT :1; 284 /*< preferred view*/ 285 uint32_t PREFERRED_VIEW :1; 286 /* this timing should be used only in tiled mode*/ 287 uint32_t TILED_MODE :1; 288 uint32_t DSE_MODE :1; 289 /* Refresh rate divider when Miracast sink is using a 290 different rate than the output display device 291 Must be zero for wired displays and non-zero for 292 Miracast displays*/ 293 uint32_t MIRACAST_REFRESH_DIVIDER; 294 }; 295 296 297 enum dc_timing_source { 298 TIMING_SOURCE_UNDEFINED, 299 300 /* explicitly specifed by user, most important*/ 301 TIMING_SOURCE_USER_FORCED, 302 TIMING_SOURCE_USER_OVERRIDE, 303 TIMING_SOURCE_CUSTOM, 304 TIMING_SOURCE_EXPLICIT, 305 306 /* explicitly specified by the display device, more important*/ 307 TIMING_SOURCE_EDID_CEA_SVD_3D, 308 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 309 TIMING_SOURCE_EDID_CEA_SVD_420, 310 TIMING_SOURCE_EDID_DETAILED, 311 TIMING_SOURCE_EDID_ESTABLISHED, 312 TIMING_SOURCE_EDID_STANDARD, 313 TIMING_SOURCE_EDID_CEA_SVD, 314 TIMING_SOURCE_EDID_CVT_3BYTE, 315 TIMING_SOURCE_EDID_4BYTE, 316 TIMING_SOURCE_VBIOS, 317 TIMING_SOURCE_CV, 318 TIMING_SOURCE_TV, 319 TIMING_SOURCE_HDMI_VIC, 320 321 /* implicitly specified by display device, still safe but less important*/ 322 TIMING_SOURCE_DEFAULT, 323 324 /* only used for custom base modes */ 325 TIMING_SOURCE_CUSTOM_BASE, 326 327 /* these timing might not work, least important*/ 328 TIMING_SOURCE_RANGELIMIT, 329 TIMING_SOURCE_OS_FORCED, 330 TIMING_SOURCE_IMPLICIT, 331 332 /* only used by default mode list*/ 333 TIMING_SOURCE_BASICMODE, 334 335 TIMING_SOURCE_COUNT 336 }; 337 338 339 struct stereo_3d_features { 340 bool supported ; 341 bool allTimings ; 342 bool cloneMode ; 343 bool scaling ; 344 bool singleFrameSWPacked; 345 }; 346 347 enum dc_timing_support_method { 348 TIMING_SUPPORT_METHOD_UNDEFINED, 349 TIMING_SUPPORT_METHOD_EXPLICIT, 350 TIMING_SUPPORT_METHOD_IMPLICIT, 351 TIMING_SUPPORT_METHOD_NATIVE 352 }; 353 354 struct dc_mode_info { 355 uint32_t pixel_width; 356 uint32_t pixel_height; 357 uint32_t field_rate; 358 /* Vertical refresh rate for progressive modes. 359 * Field rate for interlaced modes.*/ 360 361 enum dc_timing_standard timing_standard; 362 enum dc_timing_source timing_source; 363 struct dc_mode_flags flags; 364 }; 365 366 enum dc_power_state { 367 DC_POWER_STATE_ON = 1, 368 DC_POWER_STATE_STANDBY, 369 DC_POWER_STATE_SUSPEND, 370 DC_POWER_STATE_OFF 371 }; 372 373 /* DC PowerStates */ 374 enum dc_video_power_state { 375 DC_VIDEO_POWER_UNSPECIFIED = 0, 376 DC_VIDEO_POWER_ON = 1, 377 DC_VIDEO_POWER_STANDBY, 378 DC_VIDEO_POWER_SUSPEND, 379 DC_VIDEO_POWER_OFF, 380 DC_VIDEO_POWER_HIBERNATE, 381 DC_VIDEO_POWER_SHUTDOWN, 382 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 383 DC_VIDEO_POWER_AFTER_RESET, 384 DC_VIDEO_POWER_MAXIMUM 385 }; 386 387 enum dc_acpi_cm_power_state { 388 DC_ACPI_CM_POWER_STATE_D0 = 1, 389 DC_ACPI_CM_POWER_STATE_D1 = 2, 390 DC_ACPI_CM_POWER_STATE_D2 = 4, 391 DC_ACPI_CM_POWER_STATE_D3 = 8 392 }; 393 394 enum dc_connection_type { 395 dc_connection_none, 396 dc_connection_single, 397 dc_connection_mst_branch, 398 dc_connection_active_dongle 399 }; 400 401 struct dc_csc_adjustments { 402 struct fixed31_32 contrast; 403 struct fixed31_32 saturation; 404 struct fixed31_32 brightness; 405 struct fixed31_32 hue; 406 }; 407 408 enum dpcd_downstream_port_max_bpc { 409 DOWN_STREAM_MAX_8BPC = 0, 410 DOWN_STREAM_MAX_10BPC, 411 DOWN_STREAM_MAX_12BPC, 412 DOWN_STREAM_MAX_16BPC 413 }; 414 415 416 enum link_training_offset { 417 DPRX = 0, 418 LTTPR_PHY_REPEATER1 = 1, 419 LTTPR_PHY_REPEATER2 = 2, 420 LTTPR_PHY_REPEATER3 = 3, 421 LTTPR_PHY_REPEATER4 = 4, 422 LTTPR_PHY_REPEATER5 = 5, 423 LTTPR_PHY_REPEATER6 = 6, 424 LTTPR_PHY_REPEATER7 = 7, 425 LTTPR_PHY_REPEATER8 = 8 426 }; 427 428 struct dc_lttpr_caps { 429 union dpcd_rev revision; 430 uint8_t mode; 431 uint8_t max_lane_count; 432 uint8_t max_link_rate; 433 uint8_t phy_repeater_cnt; 434 uint8_t max_ext_timeout; 435 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 436 }; 437 438 struct dc_dongle_caps { 439 /* dongle type (DP converter, CV smart dongle) */ 440 enum display_dongle_type dongle_type; 441 bool extendedCapValid; 442 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 443 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 444 bool is_dp_hdmi_s3d_converter; 445 bool is_dp_hdmi_ycbcr422_pass_through; 446 bool is_dp_hdmi_ycbcr420_pass_through; 447 bool is_dp_hdmi_ycbcr422_converter; 448 bool is_dp_hdmi_ycbcr420_converter; 449 uint32_t dp_hdmi_max_bpc; 450 uint32_t dp_hdmi_max_pixel_clk_in_khz; 451 }; 452 /* Scaling format */ 453 enum scaling_transformation { 454 SCALING_TRANSFORMATION_UNINITIALIZED, 455 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 456 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 457 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 458 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 459 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 460 SCALING_TRANSFORMATION_INVALID = 0x80000000, 461 462 /* Flag the first and last */ 463 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 464 SCALING_TRANSFORMATION_END = 465 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 466 }; 467 468 enum display_content_type { 469 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 470 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 471 DISPLAY_CONTENT_TYPE_PHOTO = 2, 472 DISPLAY_CONTENT_TYPE_CINEMA = 4, 473 DISPLAY_CONTENT_TYPE_GAME = 8 474 }; 475 476 /* writeback */ 477 struct dwb_stereo_params { 478 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 479 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 480 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 481 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 482 }; 483 484 struct dc_dwb_cnv_params { 485 unsigned int src_width; /* input active width */ 486 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 487 unsigned int crop_width; /* cropped window width at cnv output */ 488 bool crop_en; /* window cropping enable in cnv */ 489 unsigned int crop_height; /* cropped window height at cnv output */ 490 unsigned int crop_x; /* cropped window start x value at cnv output */ 491 unsigned int crop_y; /* cropped window start y value at cnv output */ 492 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 493 }; 494 495 struct dc_dwb_params { 496 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 497 unsigned int dest_width; /* Destination width */ 498 unsigned int dest_height; /* Destination height */ 499 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 500 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 501 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 502 struct scaling_taps scaler_taps; /* Scaling taps */ 503 enum dwb_subsample_position subsample_position; 504 struct dc_transfer_func *out_transfer_func; 505 }; 506 507 /* audio*/ 508 509 union audio_sample_rates { 510 struct sample_rates { 511 uint8_t RATE_32:1; 512 uint8_t RATE_44_1:1; 513 uint8_t RATE_48:1; 514 uint8_t RATE_88_2:1; 515 uint8_t RATE_96:1; 516 uint8_t RATE_176_4:1; 517 uint8_t RATE_192:1; 518 } rate; 519 520 uint8_t all; 521 }; 522 523 struct audio_speaker_flags { 524 uint32_t FL_FR:1; 525 uint32_t LFE:1; 526 uint32_t FC:1; 527 uint32_t RL_RR:1; 528 uint32_t RC:1; 529 uint32_t FLC_FRC:1; 530 uint32_t RLC_RRC:1; 531 uint32_t SUPPORT_AI:1; 532 }; 533 534 struct audio_speaker_info { 535 uint32_t ALLSPEAKERS:7; 536 uint32_t SUPPORT_AI:1; 537 }; 538 539 540 struct audio_info_flags { 541 542 union { 543 544 struct audio_speaker_flags speaker_flags; 545 struct audio_speaker_info info; 546 547 uint8_t all; 548 }; 549 }; 550 551 enum audio_format_code { 552 AUDIO_FORMAT_CODE_FIRST = 1, 553 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 554 555 AUDIO_FORMAT_CODE_AC3, 556 /*Layers 1 & 2 */ 557 AUDIO_FORMAT_CODE_MPEG1, 558 /*MPEG1 Layer 3 */ 559 AUDIO_FORMAT_CODE_MP3, 560 /*multichannel */ 561 AUDIO_FORMAT_CODE_MPEG2, 562 AUDIO_FORMAT_CODE_AAC, 563 AUDIO_FORMAT_CODE_DTS, 564 AUDIO_FORMAT_CODE_ATRAC, 565 AUDIO_FORMAT_CODE_1BITAUDIO, 566 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 567 AUDIO_FORMAT_CODE_DTS_HD, 568 AUDIO_FORMAT_CODE_MAT_MLP, 569 AUDIO_FORMAT_CODE_DST, 570 AUDIO_FORMAT_CODE_WMAPRO, 571 AUDIO_FORMAT_CODE_LAST, 572 AUDIO_FORMAT_CODE_COUNT = 573 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 574 }; 575 576 struct audio_mode { 577 /* ucData[0] [6:3] */ 578 enum audio_format_code format_code; 579 /* ucData[0] [2:0] */ 580 uint8_t channel_count; 581 /* ucData[1] */ 582 union audio_sample_rates sample_rates; 583 union { 584 /* for LPCM */ 585 uint8_t sample_size; 586 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 587 uint8_t max_bit_rate; 588 /* for Audio Formats 9-15 */ 589 uint8_t vendor_specific; 590 }; 591 }; 592 593 struct audio_info { 594 struct audio_info_flags flags; 595 uint32_t video_latency; 596 uint32_t audio_latency; 597 uint32_t display_index; 598 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 599 uint32_t manufacture_id; 600 uint32_t product_id; 601 /* PortID used for ContainerID when defined */ 602 uint32_t port_id[2]; 603 uint32_t mode_count; 604 /* this field must be last in this struct */ 605 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 606 }; 607 struct audio_check { 608 unsigned int audio_packet_type; 609 unsigned int max_audiosample_rate; 610 unsigned int acat; 611 }; 612 enum dc_infoframe_type { 613 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 614 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 615 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 616 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 617 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 618 }; 619 620 struct dc_info_packet { 621 bool valid; 622 uint8_t hb0; 623 uint8_t hb1; 624 uint8_t hb2; 625 uint8_t hb3; 626 uint8_t sb[32]; 627 }; 628 629 struct dc_info_packet_128 { 630 bool valid; 631 uint8_t hb0; 632 uint8_t hb1; 633 uint8_t hb2; 634 uint8_t hb3; 635 uint8_t sb[128]; 636 }; 637 638 #define DC_PLANE_UPDATE_TIMES_MAX 10 639 640 struct dc_plane_flip_time { 641 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 642 unsigned int index; 643 unsigned int prev_update_time_in_us; 644 }; 645 646 struct psr_config { 647 unsigned char psr_version; 648 unsigned int psr_rfb_setup_time; 649 bool psr_exit_link_training_required; 650 bool psr_frame_capture_indication_req; 651 unsigned int psr_sdp_transmit_line_num_deadline; 652 bool allow_smu_optimizations; 653 }; 654 655 union dmcu_psr_level { 656 struct { 657 unsigned int SKIP_CRC:1; 658 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 659 unsigned int SKIP_PHY_POWER_DOWN:1; 660 unsigned int SKIP_AUX_ACK_CHECK:1; 661 unsigned int SKIP_CRTC_DISABLE:1; 662 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 663 unsigned int SKIP_SMU_NOTIFICATION:1; 664 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 665 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 666 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 667 unsigned int RESERVED:22; 668 } bits; 669 unsigned int u32all; 670 }; 671 672 enum physical_phy_id { 673 PHYLD_0, 674 PHYLD_1, 675 PHYLD_2, 676 PHYLD_3, 677 PHYLD_4, 678 PHYLD_5, 679 PHYLD_6, 680 PHYLD_7, 681 PHYLD_8, 682 PHYLD_9, 683 PHYLD_COUNT, 684 PHYLD_UNKNOWN = (-1L) 685 }; 686 687 enum phy_type { 688 PHY_TYPE_UNKNOWN = 1, 689 PHY_TYPE_PCIE_PHY = 2, 690 PHY_TYPE_UNIPHY = 3, 691 }; 692 693 struct psr_context { 694 /* ddc line */ 695 enum channel_id channel; 696 /* Transmitter id */ 697 enum transmitter transmitterId; 698 /* Engine Id is used for Dig Be source select */ 699 enum engine_id engineId; 700 /* Controller Id used for Dig Fe source select */ 701 enum controller_id controllerId; 702 /* Pcie or Uniphy */ 703 enum phy_type phyType; 704 /* Physical PHY Id used by SMU interpretation */ 705 enum physical_phy_id smuPhyId; 706 /* Vertical total pixels from crtc timing. 707 * This is used for static screen detection. 708 * ie. If we want to detect half a frame, 709 * we use this to determine the hyst lines. 710 */ 711 unsigned int crtcTimingVerticalTotal; 712 /* PSR supported from panel capabilities and 713 * current display configuration 714 */ 715 bool psrSupportedDisplayConfig; 716 /* Whether fast link training is supported by the panel */ 717 bool psrExitLinkTrainingRequired; 718 /* If RFB setup time is greater than the total VBLANK time, 719 * it is not possible for the sink to capture the video frame 720 * in the same frame the SDP is sent. In this case, 721 * the frame capture indication bit should be set and an extra 722 * static frame should be transmitted to the sink. 723 */ 724 bool psrFrameCaptureIndicationReq; 725 /* Set the last possible line SDP may be transmitted without violating 726 * the RFB setup time or entering the active video frame. 727 */ 728 unsigned int sdpTransmitLineNumDeadline; 729 /* The VSync rate in Hz used to calculate the 730 * step size for smooth brightness feature 731 */ 732 unsigned int vsync_rate_hz; 733 unsigned int skipPsrWaitForPllLock; 734 unsigned int numberOfControllers; 735 /* Unused, for future use. To indicate that first changed frame from 736 * state3 shouldn't result in psr_inactive, but rather to perform 737 * an automatic single frame rfb_update. 738 */ 739 bool rfb_update_auto_en; 740 /* Number of frame before entering static screen */ 741 unsigned int timehyst_frames; 742 /* Partial frames before entering static screen */ 743 unsigned int hyst_lines; 744 /* # of repeated AUX transaction attempts to make before 745 * indicating failure to the driver 746 */ 747 unsigned int aux_repeats; 748 /* Controls hw blocks to power down during PSR active state */ 749 union dmcu_psr_level psr_level; 750 /* Controls additional delay after remote frame capture before 751 * continuing powerd own 752 */ 753 unsigned int frame_delay; 754 bool allow_smu_optimizations; 755 }; 756 757 struct colorspace_transform { 758 struct fixed31_32 matrix[12]; 759 bool enable_remap; 760 }; 761 762 enum i2c_mot_mode { 763 I2C_MOT_UNDEF, 764 I2C_MOT_TRUE, 765 I2C_MOT_FALSE 766 }; 767 768 struct AsicStateEx { 769 unsigned int memoryClock; 770 unsigned int displayClock; 771 unsigned int engineClock; 772 unsigned int maxSupportedDppClock; 773 unsigned int dppClock; 774 unsigned int socClock; 775 unsigned int dcfClockDeepSleep; 776 unsigned int fClock; 777 unsigned int phyClock; 778 }; 779 780 781 enum dc_clock_type { 782 DC_CLOCK_TYPE_DISPCLK = 0, 783 DC_CLOCK_TYPE_DPPCLK = 1, 784 }; 785 786 struct dc_clock_config { 787 uint32_t max_clock_khz; 788 uint32_t min_clock_khz; 789 uint32_t bw_requirequired_clock_khz; 790 uint32_t current_clock_khz;/*current clock in use*/ 791 }; 792 793 /* DSC DPCD capabilities */ 794 union dsc_slice_caps1 { 795 struct { 796 uint8_t NUM_SLICES_1 : 1; 797 uint8_t NUM_SLICES_2 : 1; 798 uint8_t RESERVED : 1; 799 uint8_t NUM_SLICES_4 : 1; 800 uint8_t NUM_SLICES_6 : 1; 801 uint8_t NUM_SLICES_8 : 1; 802 uint8_t NUM_SLICES_10 : 1; 803 uint8_t NUM_SLICES_12 : 1; 804 } bits; 805 uint8_t raw; 806 }; 807 808 union dsc_slice_caps2 { 809 struct { 810 uint8_t NUM_SLICES_16 : 1; 811 uint8_t NUM_SLICES_20 : 1; 812 uint8_t NUM_SLICES_24 : 1; 813 uint8_t RESERVED : 5; 814 } bits; 815 uint8_t raw; 816 }; 817 818 union dsc_color_formats { 819 struct { 820 uint8_t RGB : 1; 821 uint8_t YCBCR_444 : 1; 822 uint8_t YCBCR_SIMPLE_422 : 1; 823 uint8_t YCBCR_NATIVE_422 : 1; 824 uint8_t YCBCR_NATIVE_420 : 1; 825 uint8_t RESERVED : 3; 826 } bits; 827 uint8_t raw; 828 }; 829 830 union dsc_color_depth { 831 struct { 832 uint8_t RESERVED1 : 1; 833 uint8_t COLOR_DEPTH_8_BPC : 1; 834 uint8_t COLOR_DEPTH_10_BPC : 1; 835 uint8_t COLOR_DEPTH_12_BPC : 1; 836 uint8_t RESERVED2 : 3; 837 } bits; 838 uint8_t raw; 839 }; 840 841 struct dsc_dec_dpcd_caps { 842 bool is_dsc_supported; 843 uint8_t dsc_version; 844 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 845 union dsc_slice_caps1 slice_caps1; 846 union dsc_slice_caps2 slice_caps2; 847 int32_t lb_bit_depth; 848 bool is_block_pred_supported; 849 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 850 union dsc_color_formats color_formats; 851 union dsc_color_depth color_depth; 852 int32_t throughput_mode_0_mps; /* In MPs */ 853 int32_t throughput_mode_1_mps; /* In MPs */ 854 int32_t max_slice_width; 855 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 856 857 /* Extended DSC caps */ 858 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 859 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 860 uint32_t branch_max_line_width; 861 }; 862 863 #endif /* DC_TYPES_H_ */ 864