1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed31_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define PSR_SET_WAITLOOP 0x31 52 #define MCP_INIT_DMCU 0x88 53 #define MCP_INIT_IRAM 0x89 54 #define MCP_SYNC_PHY_LOCK 0x90 55 #define MCP_SYNC_PHY_UNLOCK 0x91 56 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 57 #define CRC_WIN_NOTIFY 0x92 58 #define CRC_STOP_UPDATE 0x93 59 #define MCP_SEND_EDID_CEA 0xA0 60 #define EDID_CEA_CMD_ACK 1 61 #define EDID_CEA_CMD_NACK 2 62 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 63 64 // PSP FW version 65 #define mmMP0_SMN_C2PMSG_58 0x1607A 66 67 //Register access policy version 68 #define mmMP0_SMN_C2PMSG_91 0x1609B 69 70 static const uint32_t abm_gain_stepsize = 0x0060; 71 72 static bool dce_dmcu_init(struct dmcu *dmcu) 73 { 74 // Do nothing 75 return true; 76 } 77 78 static bool dce_dmcu_load_iram(struct dmcu *dmcu, 79 unsigned int start_offset, 80 const char *src, 81 unsigned int bytes) 82 { 83 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 84 unsigned int count = 0; 85 86 /* Enable write access to IRAM */ 87 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 88 IRAM_HOST_ACCESS_EN, 1, 89 IRAM_WR_ADDR_AUTO_INC, 1); 90 91 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 92 93 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 94 95 for (count = 0; count < bytes; count++) 96 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 97 98 /* Disable write access to IRAM to allow dynamic sleep state */ 99 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 100 IRAM_HOST_ACCESS_EN, 0, 101 IRAM_WR_ADDR_AUTO_INC, 0); 102 103 return true; 104 } 105 106 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 107 { 108 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 109 110 uint32_t psr_state_offset = 0xf0; 111 112 /* Enable write access to IRAM */ 113 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 114 115 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 116 117 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 118 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 119 120 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 121 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 122 123 /* Disable write access to IRAM after finished using IRAM 124 * in order to allow dynamic sleep state 125 */ 126 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 127 } 128 129 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 130 { 131 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 132 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 133 unsigned int dmcu_wait_reg_ready_interval = 100; 134 135 unsigned int retryCount; 136 enum dc_psr_state state = PSR_STATE0; 137 138 /* waitDMCUReadyForCmd */ 139 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 140 dmcu_wait_reg_ready_interval, 141 dmcu_max_retry_on_wait_reg_ready); 142 143 /* setDMCUParam_Cmd */ 144 if (enable) 145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 146 PSR_ENABLE); 147 else 148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 149 PSR_EXIT); 150 151 /* notifyDMCUMsg */ 152 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 153 if (wait == true) { 154 for (retryCount = 0; retryCount <= 100; retryCount++) { 155 dce_get_dmcu_psr_state(dmcu, &state); 156 if (enable) { 157 if (state != PSR_STATE0) 158 break; 159 } else { 160 if (state == PSR_STATE0) 161 break; 162 } 163 udelay(10); 164 } 165 } 166 } 167 168 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 169 struct dc_link *link, 170 struct psr_context *psr_context) 171 { 172 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 173 174 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 175 unsigned int dmcu_wait_reg_ready_interval = 100; 176 177 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 178 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 179 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 180 181 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 182 psr_context->psrExitLinkTrainingRequired); 183 184 /* Enable static screen interrupts for PSR supported display */ 185 /* Disable the interrupt coming from other displays. */ 186 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 187 STATIC_SCREEN1_INT_TO_UC_EN, 0, 188 STATIC_SCREEN2_INT_TO_UC_EN, 0, 189 STATIC_SCREEN3_INT_TO_UC_EN, 0, 190 STATIC_SCREEN4_INT_TO_UC_EN, 0); 191 192 switch (psr_context->controllerId) { 193 /* Driver uses case 1 for unconfigured */ 194 case 1: 195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 196 STATIC_SCREEN1_INT_TO_UC_EN, 1); 197 break; 198 case 2: 199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 200 STATIC_SCREEN2_INT_TO_UC_EN, 1); 201 break; 202 case 3: 203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 204 STATIC_SCREEN3_INT_TO_UC_EN, 1); 205 break; 206 case 4: 207 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 208 STATIC_SCREEN4_INT_TO_UC_EN, 1); 209 break; 210 case 5: 211 /* CZ/NL only has 4 CRTC!! 212 * really valid. 213 * There is no interrupt enable mask for these instances. 214 */ 215 break; 216 case 6: 217 /* CZ/NL only has 4 CRTC!! 218 * These are here because they are defined in HW regspec, 219 * but not really valid. There is no interrupt enable mask 220 * for these instances. 221 */ 222 break; 223 default: 224 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 225 STATIC_SCREEN1_INT_TO_UC_EN, 1); 226 break; 227 } 228 229 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 230 psr_context->sdpTransmitLineNumDeadline); 231 232 /* waitDMCUReadyForCmd */ 233 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 234 dmcu_wait_reg_ready_interval, 235 dmcu_max_retry_on_wait_reg_ready); 236 237 /* setDMCUParam_PSRHostConfigData */ 238 masterCmdData1.u32All = 0; 239 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 240 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 241 masterCmdData1.bits.rfb_update_auto_en = 242 psr_context->rfb_update_auto_en; 243 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 244 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 245 masterCmdData1.bits.phy_type = psr_context->phyType; 246 masterCmdData1.bits.frame_cap_ind = 247 psr_context->psrFrameCaptureIndicationReq; 248 masterCmdData1.bits.aux_chan = psr_context->channel; 249 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 250 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 251 masterCmdData1.u32All); 252 253 masterCmdData2.u32All = 0; 254 masterCmdData2.bits.dig_fe = psr_context->engineId; 255 masterCmdData2.bits.dig_be = psr_context->transmitterId; 256 masterCmdData2.bits.skip_wait_for_pll_lock = 257 psr_context->skipPsrWaitForPllLock; 258 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 259 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 260 masterCmdData2.bits.num_of_controllers = 261 psr_context->numberOfControllers; 262 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 263 masterCmdData2.u32All); 264 265 masterCmdData3.u32All = 0; 266 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 267 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 268 masterCmdData3.u32All); 269 270 /* setDMCUParam_Cmd */ 271 REG_UPDATE(MASTER_COMM_CMD_REG, 272 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 273 274 /* notifyDMCUMsg */ 275 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 276 277 return true; 278 } 279 280 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 281 { 282 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 283 unsigned int dmcu_uc_reset; 284 285 /* microcontroller is not running */ 286 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 287 288 /* DMCU is not running */ 289 if (dmcu_uc_reset) 290 return false; 291 292 return true; 293 } 294 295 static void dce_psr_wait_loop( 296 struct dmcu *dmcu, 297 unsigned int wait_loop_number) 298 { 299 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 300 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 301 302 if (dmcu->cached_wait_loop_number == wait_loop_number) 303 return; 304 305 /* DMCU is not running */ 306 if (!dce_is_dmcu_initialized(dmcu)) 307 return; 308 309 /* waitDMCUReadyForCmd */ 310 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 311 312 masterCmdData1.u32 = 0; 313 masterCmdData1.bits.wait_loop = wait_loop_number; 314 dmcu->cached_wait_loop_number = wait_loop_number; 315 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 316 317 /* setDMCUParam_Cmd */ 318 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 319 320 /* notifyDMCUMsg */ 321 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 322 } 323 324 static void dce_get_psr_wait_loop( 325 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 326 { 327 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 328 return; 329 } 330 331 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 332 { 333 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 334 uint32_t dmcu_version_offset = 0xf1; 335 336 /* Enable write access to IRAM */ 337 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 338 IRAM_HOST_ACCESS_EN, 1, 339 IRAM_RD_ADDR_AUTO_INC, 1); 340 341 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 342 343 /* Write address to IRAM_RD_ADDR and read from DATA register */ 344 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 345 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 346 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 347 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 348 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 349 REG_READ(DMCU_IRAM_RD_DATA)); 350 351 /* Disable write access to IRAM to allow dynamic sleep state */ 352 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 353 IRAM_HOST_ACCESS_EN, 0, 354 IRAM_RD_ADDR_AUTO_INC, 0); 355 } 356 357 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 358 uint32_t fractional_pwm) 359 { 360 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 361 362 /* Wait until microcontroller is ready to process interrupt */ 363 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 364 365 /* Set PWM fractional enable/disable */ 366 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 367 368 /* Set command to enable or disable fractional PWM microcontroller */ 369 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 370 MCP_BL_SET_PWM_FRAC); 371 372 /* Notify microcontroller of new command */ 373 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 374 375 /* Ensure command has been executed before continuing */ 376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 377 } 378 379 static bool dcn10_dmcu_init(struct dmcu *dmcu) 380 { 381 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 382 const struct dc_config *config = &dmcu->ctx->dc->config; 383 bool status = false; 384 struct dc_context *ctx = dmcu->ctx; 385 unsigned int i; 386 // 5 4 3 2 1 0 387 // F E D C B A - bit 0 is A, bit 5 is F 388 unsigned int tx_interrupt_mask = 0; 389 390 PERF_TRACE(); 391 /* Definition of DC_DMCU_SCRATCH 392 * 0 : firmare not loaded 393 * 1 : PSP load DMCU FW but not initialized 394 * 2 : Firmware already initialized 395 */ 396 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 397 398 for (i = 0; i < ctx->dc->link_count; i++) { 399 if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) { 400 if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A && 401 ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) { 402 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter; 403 } 404 } 405 } 406 407 switch (dmcu->dmcu_state) { 408 case DMCU_UNLOADED: 409 status = false; 410 break; 411 case DMCU_LOADED_UNINITIALIZED: 412 /* Wait until microcontroller is ready to process interrupt */ 413 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 414 415 /* Set initialized ramping boundary value */ 416 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 417 418 /* Set backlight ramping stepsize */ 419 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 420 421 REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask); 422 423 /* Set command to initialize microcontroller */ 424 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 425 MCP_INIT_DMCU); 426 427 /* Notify microcontroller of new command */ 428 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 429 430 /* Ensure command has been executed before continuing */ 431 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 432 433 // Check state is initialized 434 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 435 436 // If microcontroller is not in running state, fail 437 if (dmcu->dmcu_state == DMCU_RUNNING) { 438 /* Retrieve and cache the DMCU firmware version. */ 439 dcn10_get_dmcu_version(dmcu); 440 441 /* Initialize DMCU to use fractional PWM or not */ 442 dcn10_dmcu_enable_fractional_pwm(dmcu, 443 (config->disable_fractional_pwm == false) ? 1 : 0); 444 status = true; 445 } else { 446 status = false; 447 } 448 449 break; 450 case DMCU_RUNNING: 451 status = true; 452 break; 453 default: 454 status = false; 455 break; 456 } 457 458 PERF_TRACE(); 459 return status; 460 } 461 462 static bool dcn21_dmcu_init(struct dmcu *dmcu) 463 { 464 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 465 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 466 467 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 468 return false; 469 } 470 471 return dcn10_dmcu_init(dmcu); 472 } 473 474 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 475 unsigned int start_offset, 476 const char *src, 477 unsigned int bytes) 478 { 479 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 480 unsigned int count = 0; 481 482 /* If microcontroller is not running, do nothing */ 483 if (dmcu->dmcu_state != DMCU_RUNNING) 484 return false; 485 486 /* Enable write access to IRAM */ 487 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 488 IRAM_HOST_ACCESS_EN, 1, 489 IRAM_WR_ADDR_AUTO_INC, 1); 490 491 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 492 493 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 494 495 for (count = 0; count < bytes; count++) 496 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 497 498 /* Disable write access to IRAM to allow dynamic sleep state */ 499 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 500 IRAM_HOST_ACCESS_EN, 0, 501 IRAM_WR_ADDR_AUTO_INC, 0); 502 503 /* Wait until microcontroller is ready to process interrupt */ 504 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 505 506 /* Set command to signal IRAM is loaded and to initialize IRAM */ 507 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 508 MCP_INIT_IRAM); 509 510 /* Notify microcontroller of new command */ 511 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 512 513 /* Ensure command has been executed before continuing */ 514 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 515 516 return true; 517 } 518 519 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 520 { 521 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 522 523 uint32_t psr_state_offset = 0xf0; 524 525 /* If microcontroller is not running, do nothing */ 526 if (dmcu->dmcu_state != DMCU_RUNNING) 527 return; 528 529 /* Enable write access to IRAM */ 530 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 531 532 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 533 534 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 535 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 536 537 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 538 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 539 540 /* Disable write access to IRAM after finished using IRAM 541 * in order to allow dynamic sleep state 542 */ 543 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 544 } 545 546 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 547 { 548 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 549 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 550 unsigned int dmcu_wait_reg_ready_interval = 100; 551 552 unsigned int retryCount; 553 enum dc_psr_state state = PSR_STATE0; 554 555 /* If microcontroller is not running, do nothing */ 556 if (dmcu->dmcu_state != DMCU_RUNNING) 557 return; 558 559 /* waitDMCUReadyForCmd */ 560 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 561 dmcu_wait_reg_ready_interval, 562 dmcu_max_retry_on_wait_reg_ready); 563 564 /* setDMCUParam_Cmd */ 565 if (enable) 566 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 567 PSR_ENABLE); 568 else 569 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 570 PSR_EXIT); 571 572 /* notifyDMCUMsg */ 573 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 574 575 /* Below loops 1000 x 500us = 500 ms. 576 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 577 * least a few frames. Should never hit the max retry assert below. 578 */ 579 if (wait == true) { 580 for (retryCount = 0; retryCount <= 1000; retryCount++) { 581 dcn10_get_dmcu_psr_state(dmcu, &state); 582 if (enable) { 583 if (state != PSR_STATE0) 584 break; 585 } else { 586 if (state == PSR_STATE0) 587 break; 588 } 589 fsleep(500); 590 } 591 592 /* assert if max retry hit */ 593 if (retryCount >= 1000) 594 ASSERT(0); 595 } 596 } 597 598 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 599 struct dc_link *link, 600 struct psr_context *psr_context) 601 { 602 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 603 604 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 605 unsigned int dmcu_wait_reg_ready_interval = 100; 606 607 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 608 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 609 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 610 611 /* If microcontroller is not running, do nothing */ 612 if (dmcu->dmcu_state != DMCU_RUNNING) 613 return false; 614 615 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 616 psr_context->psrExitLinkTrainingRequired); 617 618 /* Enable static screen interrupts for PSR supported display */ 619 /* Disable the interrupt coming from other displays. */ 620 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 621 STATIC_SCREEN1_INT_TO_UC_EN, 0, 622 STATIC_SCREEN2_INT_TO_UC_EN, 0, 623 STATIC_SCREEN3_INT_TO_UC_EN, 0, 624 STATIC_SCREEN4_INT_TO_UC_EN, 0); 625 626 switch (psr_context->controllerId) { 627 /* Driver uses case 1 for unconfigured */ 628 case 1: 629 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 630 STATIC_SCREEN1_INT_TO_UC_EN, 1); 631 break; 632 case 2: 633 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 634 STATIC_SCREEN2_INT_TO_UC_EN, 1); 635 break; 636 case 3: 637 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 638 STATIC_SCREEN3_INT_TO_UC_EN, 1); 639 break; 640 case 4: 641 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 642 STATIC_SCREEN4_INT_TO_UC_EN, 1); 643 break; 644 case 5: 645 /* CZ/NL only has 4 CRTC!! 646 * really valid. 647 * There is no interrupt enable mask for these instances. 648 */ 649 break; 650 case 6: 651 /* CZ/NL only has 4 CRTC!! 652 * These are here because they are defined in HW regspec, 653 * but not really valid. There is no interrupt enable mask 654 * for these instances. 655 */ 656 break; 657 default: 658 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 659 STATIC_SCREEN1_INT_TO_UC_EN, 1); 660 break; 661 } 662 663 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 664 psr_context->sdpTransmitLineNumDeadline); 665 666 if (psr_context->allow_smu_optimizations) 667 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 668 669 /* waitDMCUReadyForCmd */ 670 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 671 dmcu_wait_reg_ready_interval, 672 dmcu_max_retry_on_wait_reg_ready); 673 674 /* setDMCUParam_PSRHostConfigData */ 675 masterCmdData1.u32All = 0; 676 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 677 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 678 masterCmdData1.bits.rfb_update_auto_en = 679 psr_context->rfb_update_auto_en; 680 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 681 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 682 masterCmdData1.bits.phy_type = psr_context->phyType; 683 masterCmdData1.bits.frame_cap_ind = 684 psr_context->psrFrameCaptureIndicationReq; 685 masterCmdData1.bits.aux_chan = psr_context->channel; 686 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 687 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 688 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 689 masterCmdData1.u32All); 690 691 masterCmdData2.u32All = 0; 692 masterCmdData2.bits.dig_fe = psr_context->engineId; 693 masterCmdData2.bits.dig_be = psr_context->transmitterId; 694 masterCmdData2.bits.skip_wait_for_pll_lock = 695 psr_context->skipPsrWaitForPllLock; 696 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 697 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 698 masterCmdData2.bits.num_of_controllers = 699 psr_context->numberOfControllers; 700 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 701 masterCmdData2.u32All); 702 703 masterCmdData3.u32All = 0; 704 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 705 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 706 masterCmdData3.u32All); 707 708 709 /* setDMCUParam_Cmd */ 710 REG_UPDATE(MASTER_COMM_CMD_REG, 711 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 712 713 /* notifyDMCUMsg */ 714 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 715 716 /* waitDMCUReadyForCmd */ 717 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 718 719 return true; 720 } 721 722 static void dcn10_psr_wait_loop( 723 struct dmcu *dmcu, 724 unsigned int wait_loop_number) 725 { 726 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 727 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 728 729 /* If microcontroller is not running, do nothing */ 730 if (dmcu->dmcu_state != DMCU_RUNNING) 731 return; 732 733 if (wait_loop_number != 0) { 734 /* waitDMCUReadyForCmd */ 735 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 736 737 masterCmdData1.u32 = 0; 738 masterCmdData1.bits.wait_loop = wait_loop_number; 739 dmcu->cached_wait_loop_number = wait_loop_number; 740 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 741 742 /* setDMCUParam_Cmd */ 743 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 744 745 /* notifyDMCUMsg */ 746 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 747 } 748 } 749 750 static void dcn10_get_psr_wait_loop( 751 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 752 { 753 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 754 return; 755 } 756 757 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 758 { 759 /* microcontroller is not running */ 760 if (dmcu->dmcu_state != DMCU_RUNNING) 761 return false; 762 return true; 763 } 764 765 766 767 static bool dcn20_lock_phy(struct dmcu *dmcu) 768 { 769 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 770 771 /* If microcontroller is not running, do nothing */ 772 if (dmcu->dmcu_state != DMCU_RUNNING) 773 return false; 774 775 /* waitDMCUReadyForCmd */ 776 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 777 778 /* setDMCUParam_Cmd */ 779 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 780 781 /* notifyDMCUMsg */ 782 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 783 784 /* waitDMCUReadyForCmd */ 785 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 786 787 return true; 788 } 789 790 static bool dcn20_unlock_phy(struct dmcu *dmcu) 791 { 792 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 793 794 /* If microcontroller is not running, do nothing */ 795 if (dmcu->dmcu_state != DMCU_RUNNING) 796 return false; 797 798 /* waitDMCUReadyForCmd */ 799 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 800 801 /* setDMCUParam_Cmd */ 802 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 803 804 /* notifyDMCUMsg */ 805 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 806 807 /* waitDMCUReadyForCmd */ 808 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 809 810 return true; 811 } 812 813 static bool dcn10_send_edid_cea(struct dmcu *dmcu, 814 int offset, 815 int total_length, 816 uint8_t *data, 817 int length) 818 { 819 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 820 uint32_t header, data1, data2; 821 822 /* If microcontroller is not running, do nothing */ 823 if (dmcu->dmcu_state != DMCU_RUNNING) 824 return false; 825 826 if (length > 8 || length <= 0) 827 return false; 828 829 header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF); 830 data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) | 831 (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]); 832 data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | 833 (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]); 834 835 /* waitDMCUReadyForCmd */ 836 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 837 838 /* setDMCUParam_Cmd */ 839 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA); 840 841 REG_WRITE(MASTER_COMM_DATA_REG1, header); 842 REG_WRITE(MASTER_COMM_DATA_REG2, data1); 843 REG_WRITE(MASTER_COMM_DATA_REG3, data2); 844 845 /* notifyDMCUMsg */ 846 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 847 848 /* waitDMCUReadyForCmd */ 849 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 850 851 return true; 852 } 853 854 static bool dcn10_get_scp_results(struct dmcu *dmcu, 855 uint32_t *cmd, 856 uint32_t *data1, 857 uint32_t *data2, 858 uint32_t *data3) 859 { 860 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 861 862 /* If microcontroller is not running, do nothing */ 863 if (dmcu->dmcu_state != DMCU_RUNNING) 864 return false; 865 866 *cmd = REG_READ(SLAVE_COMM_CMD_REG); 867 *data1 = REG_READ(SLAVE_COMM_DATA_REG1); 868 *data2 = REG_READ(SLAVE_COMM_DATA_REG2); 869 *data3 = REG_READ(SLAVE_COMM_DATA_REG3); 870 871 /* clear SCP interrupt */ 872 REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0); 873 874 return true; 875 } 876 877 static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu, 878 int *version, 879 int *min_frame_rate, 880 int *max_frame_rate) 881 { 882 uint32_t data[4]; 883 int cmd, ack, len; 884 885 if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3])) 886 return false; 887 888 cmd = data[0] & 0x3FF; 889 len = (data[0] >> 10) & 0x3F; 890 ack = data[1]; 891 892 if (cmd != MCP_SEND_EDID_CEA || ack != EDID_CEA_CMD_ACK || len != 12) 893 return false; 894 895 if ((data[2] & 0xFF)) { 896 *version = (data[2] >> 8) & 0xFF; 897 *min_frame_rate = (data[3] >> 16) & 0xFFFF; 898 *max_frame_rate = data[3] & 0xFFFF; 899 return true; 900 } 901 902 return false; 903 } 904 905 static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) 906 { 907 uint32_t data[4]; 908 int cmd, ack; 909 910 if (!dcn10_get_scp_results(dmcu, 911 &data[0], &data[1], &data[2], &data[3])) 912 return false; 913 914 cmd = data[0] & 0x3FF; 915 ack = data[1]; 916 917 if (cmd != MCP_SEND_EDID_CEA) 918 return false; 919 920 if (ack == EDID_CEA_CMD_ACK) 921 return true; 922 923 *offset = data[2]; /* nack */ 924 return false; 925 } 926 927 928 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 929 static void dcn10_forward_crc_window(struct dmcu *dmcu, 930 struct rect *rect, 931 struct otg_phy_mux *mux_mapping) 932 { 933 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 934 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 935 unsigned int dmcu_wait_reg_ready_interval = 100; 936 unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0; 937 int x_start, y_start, x_end, y_end; 938 939 /* If microcontroller is not running, do nothing */ 940 if (dmcu->dmcu_state != DMCU_RUNNING) 941 return; 942 943 if (!rect) 944 return; 945 946 /* waitDMCUReadyForCmd */ 947 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 948 dmcu_wait_reg_ready_interval, 949 dmcu_max_retry_on_wait_reg_ready); 950 951 x_start = rect->x; 952 y_start = rect->y; 953 x_end = x_start + rect->width; 954 y_end = y_start + rect->height; 955 956 /* build up nitification data */ 957 crc_start = (((unsigned int) x_start) << 16) | y_start; 958 crc_end = (((unsigned int) x_end) << 16) | y_end; 959 otg_phy_mux = 960 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 961 962 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 963 crc_start); 964 965 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 966 crc_end); 967 968 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 969 otg_phy_mux); 970 971 /* setDMCUParam_Cmd */ 972 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 973 CRC_WIN_NOTIFY); 974 975 /* notifyDMCUMsg */ 976 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 977 } 978 979 static void dcn10_stop_crc_win_update(struct dmcu *dmcu, 980 struct otg_phy_mux *mux_mapping) 981 { 982 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 983 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 984 unsigned int dmcu_wait_reg_ready_interval = 100; 985 unsigned int otg_phy_mux = 0; 986 987 /* If microcontroller is not running, do nothing */ 988 if (dmcu->dmcu_state != DMCU_RUNNING) 989 return; 990 991 /* waitDMCUReadyForCmd */ 992 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 993 dmcu_wait_reg_ready_interval, 994 dmcu_max_retry_on_wait_reg_ready); 995 996 /* build up nitification data */ 997 otg_phy_mux = 998 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 999 1000 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 1001 otg_phy_mux); 1002 1003 /* setDMCUParam_Cmd */ 1004 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 1005 CRC_STOP_UPDATE); 1006 1007 /* notifyDMCUMsg */ 1008 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 1009 } 1010 #endif 1011 1012 static const struct dmcu_funcs dce_funcs = { 1013 .dmcu_init = dce_dmcu_init, 1014 .load_iram = dce_dmcu_load_iram, 1015 .set_psr_enable = dce_dmcu_set_psr_enable, 1016 .setup_psr = dce_dmcu_setup_psr, 1017 .get_psr_state = dce_get_dmcu_psr_state, 1018 .set_psr_wait_loop = dce_psr_wait_loop, 1019 .get_psr_wait_loop = dce_get_psr_wait_loop, 1020 .is_dmcu_initialized = dce_is_dmcu_initialized 1021 }; 1022 1023 static const struct dmcu_funcs dcn10_funcs = { 1024 .dmcu_init = dcn10_dmcu_init, 1025 .load_iram = dcn10_dmcu_load_iram, 1026 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1027 .setup_psr = dcn10_dmcu_setup_psr, 1028 .get_psr_state = dcn10_get_dmcu_psr_state, 1029 .set_psr_wait_loop = dcn10_psr_wait_loop, 1030 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1031 .send_edid_cea = dcn10_send_edid_cea, 1032 .recv_amd_vsdb = dcn10_recv_amd_vsdb, 1033 .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, 1034 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1035 .forward_crc_window = dcn10_forward_crc_window, 1036 .stop_crc_win_update = dcn10_stop_crc_win_update, 1037 #endif 1038 .is_dmcu_initialized = dcn10_is_dmcu_initialized 1039 }; 1040 1041 static const struct dmcu_funcs dcn20_funcs = { 1042 .dmcu_init = dcn10_dmcu_init, 1043 .load_iram = dcn10_dmcu_load_iram, 1044 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1045 .setup_psr = dcn10_dmcu_setup_psr, 1046 .get_psr_state = dcn10_get_dmcu_psr_state, 1047 .set_psr_wait_loop = dcn10_psr_wait_loop, 1048 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1049 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1050 .lock_phy = dcn20_lock_phy, 1051 .unlock_phy = dcn20_unlock_phy 1052 }; 1053 1054 static const struct dmcu_funcs dcn21_funcs = { 1055 .dmcu_init = dcn21_dmcu_init, 1056 .load_iram = dcn10_dmcu_load_iram, 1057 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1058 .setup_psr = dcn10_dmcu_setup_psr, 1059 .get_psr_state = dcn10_get_dmcu_psr_state, 1060 .set_psr_wait_loop = dcn10_psr_wait_loop, 1061 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1062 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1063 .lock_phy = dcn20_lock_phy, 1064 .unlock_phy = dcn20_unlock_phy 1065 }; 1066 1067 static void dce_dmcu_construct( 1068 struct dce_dmcu *dmcu_dce, 1069 struct dc_context *ctx, 1070 const struct dce_dmcu_registers *regs, 1071 const struct dce_dmcu_shift *dmcu_shift, 1072 const struct dce_dmcu_mask *dmcu_mask) 1073 { 1074 struct dmcu *base = &dmcu_dce->base; 1075 1076 base->ctx = ctx; 1077 base->funcs = &dce_funcs; 1078 base->cached_wait_loop_number = 0; 1079 1080 dmcu_dce->regs = regs; 1081 dmcu_dce->dmcu_shift = dmcu_shift; 1082 dmcu_dce->dmcu_mask = dmcu_mask; 1083 } 1084 1085 static void dcn21_dmcu_construct( 1086 struct dce_dmcu *dmcu_dce, 1087 struct dc_context *ctx, 1088 const struct dce_dmcu_registers *regs, 1089 const struct dce_dmcu_shift *dmcu_shift, 1090 const struct dce_dmcu_mask *dmcu_mask) 1091 { 1092 uint32_t psp_version = 0; 1093 1094 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1095 1096 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 1097 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 1098 dmcu_dce->base.psp_version = psp_version; 1099 } 1100 1101 struct dmcu *dce_dmcu_create( 1102 struct dc_context *ctx, 1103 const struct dce_dmcu_registers *regs, 1104 const struct dce_dmcu_shift *dmcu_shift, 1105 const struct dce_dmcu_mask *dmcu_mask) 1106 { 1107 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 1108 1109 if (dmcu_dce == NULL) { 1110 BREAK_TO_DEBUGGER(); 1111 return NULL; 1112 } 1113 1114 dce_dmcu_construct( 1115 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1116 1117 dmcu_dce->base.funcs = &dce_funcs; 1118 1119 return &dmcu_dce->base; 1120 } 1121 1122 struct dmcu *dcn10_dmcu_create( 1123 struct dc_context *ctx, 1124 const struct dce_dmcu_registers *regs, 1125 const struct dce_dmcu_shift *dmcu_shift, 1126 const struct dce_dmcu_mask *dmcu_mask) 1127 { 1128 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1129 1130 if (dmcu_dce == NULL) { 1131 BREAK_TO_DEBUGGER(); 1132 return NULL; 1133 } 1134 1135 dce_dmcu_construct( 1136 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1137 1138 dmcu_dce->base.funcs = &dcn10_funcs; 1139 1140 return &dmcu_dce->base; 1141 } 1142 1143 struct dmcu *dcn20_dmcu_create( 1144 struct dc_context *ctx, 1145 const struct dce_dmcu_registers *regs, 1146 const struct dce_dmcu_shift *dmcu_shift, 1147 const struct dce_dmcu_mask *dmcu_mask) 1148 { 1149 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1150 1151 if (dmcu_dce == NULL) { 1152 BREAK_TO_DEBUGGER(); 1153 return NULL; 1154 } 1155 1156 dce_dmcu_construct( 1157 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1158 1159 dmcu_dce->base.funcs = &dcn20_funcs; 1160 1161 return &dmcu_dce->base; 1162 } 1163 1164 struct dmcu *dcn21_dmcu_create( 1165 struct dc_context *ctx, 1166 const struct dce_dmcu_registers *regs, 1167 const struct dce_dmcu_shift *dmcu_shift, 1168 const struct dce_dmcu_mask *dmcu_mask) 1169 { 1170 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1171 1172 if (dmcu_dce == NULL) { 1173 BREAK_TO_DEBUGGER(); 1174 return NULL; 1175 } 1176 1177 dcn21_dmcu_construct( 1178 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1179 1180 dmcu_dce->base.funcs = &dcn21_funcs; 1181 1182 return &dmcu_dce->base; 1183 } 1184 1185 void dce_dmcu_destroy(struct dmcu **dmcu) 1186 { 1187 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 1188 1189 kfree(dmcu_dce); 1190 *dmcu = NULL; 1191 } 1192