15e7773a2SAnthony Koo /* 25e7773a2SAnthony Koo * Copyright 2012-16 Advanced Micro Devices, Inc. 35e7773a2SAnthony Koo * 45e7773a2SAnthony Koo * Permission is hereby granted, free of charge, to any person obtaining a 55e7773a2SAnthony Koo * copy of this software and associated documentation files (the "Software"), 65e7773a2SAnthony Koo * to deal in the Software without restriction, including without limitation 75e7773a2SAnthony Koo * the rights to use, copy, modify, merge, publish, distribute, sublicense, 85e7773a2SAnthony Koo * and/or sell copies of the Software, and to permit persons to whom the 95e7773a2SAnthony Koo * Software is furnished to do so, subject to the following conditions: 105e7773a2SAnthony Koo * 115e7773a2SAnthony Koo * The above copyright notice and this permission notice shall be included in 125e7773a2SAnthony Koo * all copies or substantial portions of the Software. 135e7773a2SAnthony Koo * 145e7773a2SAnthony Koo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 155e7773a2SAnthony Koo * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 165e7773a2SAnthony Koo * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 175e7773a2SAnthony Koo * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 185e7773a2SAnthony Koo * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 195e7773a2SAnthony Koo * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 205e7773a2SAnthony Koo * OTHER DEALINGS IN THE SOFTWARE. 215e7773a2SAnthony Koo * 225e7773a2SAnthony Koo * Authors: AMD 235e7773a2SAnthony Koo * 245e7773a2SAnthony Koo */ 255e7773a2SAnthony Koo 265e7773a2SAnthony Koo 275e7773a2SAnthony Koo #ifndef _DCE_DMCU_H_ 285e7773a2SAnthony Koo #define _DCE_DMCU_H_ 295e7773a2SAnthony Koo 305e7773a2SAnthony Koo #include "dmcu.h" 315e7773a2SAnthony Koo 325e7773a2SAnthony Koo #define DMCU_COMMON_REG_LIST_DCE_BASE() \ 3390b9d7faSAnthony Koo SR(DMCU_CTRL), \ 344952d4c5SAnthony Koo SR(DMCU_STATUS), \ 355e7773a2SAnthony Koo SR(DMCU_RAM_ACCESS_CTRL), \ 365e7773a2SAnthony Koo SR(DMCU_IRAM_WR_CTRL), \ 373548f073SAmy Zhang SR(DMCU_IRAM_WR_DATA), \ 383548f073SAmy Zhang SR(MASTER_COMM_DATA_REG1), \ 393548f073SAmy Zhang SR(MASTER_COMM_DATA_REG2), \ 403548f073SAmy Zhang SR(MASTER_COMM_DATA_REG3), \ 413548f073SAmy Zhang SR(MASTER_COMM_CMD_REG), \ 423548f073SAmy Zhang SR(MASTER_COMM_CNTL_REG), \ 43*a0c898f2SStylon Wang SR(SLAVE_COMM_DATA_REG1), \ 44*a0c898f2SStylon Wang SR(SLAVE_COMM_DATA_REG2), \ 45*a0c898f2SStylon Wang SR(SLAVE_COMM_DATA_REG3), \ 46*a0c898f2SStylon Wang SR(SLAVE_COMM_CMD_REG), \ 473548f073SAmy Zhang SR(DMCU_IRAM_RD_CTRL), \ 483548f073SAmy Zhang SR(DMCU_IRAM_RD_DATA), \ 493548f073SAmy Zhang SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 504952d4c5SAnthony Koo SR(SMU_INTERRUPT_CONTROL), \ 514952d4c5SAnthony Koo SR(DC_DMCU_SCRATCH) 525e7773a2SAnthony Koo 53eab5a799SMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 54eab5a799SMauro Rossi #define DMCU_DCE60_REG_LIST() \ 55eab5a799SMauro Rossi SR(DMCU_CTRL), \ 56eab5a799SMauro Rossi SR(DMCU_STATUS), \ 57eab5a799SMauro Rossi SR(DMCU_RAM_ACCESS_CTRL), \ 58eab5a799SMauro Rossi SR(DMCU_IRAM_WR_CTRL), \ 59eab5a799SMauro Rossi SR(DMCU_IRAM_WR_DATA), \ 60eab5a799SMauro Rossi SR(MASTER_COMM_DATA_REG1), \ 61eab5a799SMauro Rossi SR(MASTER_COMM_DATA_REG2), \ 62eab5a799SMauro Rossi SR(MASTER_COMM_DATA_REG3), \ 63eab5a799SMauro Rossi SR(MASTER_COMM_CMD_REG), \ 64eab5a799SMauro Rossi SR(MASTER_COMM_CNTL_REG), \ 65eab5a799SMauro Rossi SR(DMCU_IRAM_RD_CTRL), \ 66eab5a799SMauro Rossi SR(DMCU_IRAM_RD_DATA), \ 67eab5a799SMauro Rossi SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 68eab5a799SMauro Rossi SR(DC_DMCU_SCRATCH) 69eab5a799SMauro Rossi #endif 70eab5a799SMauro Rossi 71d54ee946SMikita Lipski #define DMCU_DCE80_REG_LIST() \ 72d54ee946SMikita Lipski SR(DMCU_CTRL), \ 73d54ee946SMikita Lipski SR(DMCU_STATUS), \ 74d54ee946SMikita Lipski SR(DMCU_RAM_ACCESS_CTRL), \ 75d54ee946SMikita Lipski SR(DMCU_IRAM_WR_CTRL), \ 76d54ee946SMikita Lipski SR(DMCU_IRAM_WR_DATA), \ 77d54ee946SMikita Lipski SR(MASTER_COMM_DATA_REG1), \ 78d54ee946SMikita Lipski SR(MASTER_COMM_DATA_REG2), \ 79d54ee946SMikita Lipski SR(MASTER_COMM_DATA_REG3), \ 80d54ee946SMikita Lipski SR(MASTER_COMM_CMD_REG), \ 81d54ee946SMikita Lipski SR(MASTER_COMM_CNTL_REG), \ 82d54ee946SMikita Lipski SR(DMCU_IRAM_RD_CTRL), \ 83d54ee946SMikita Lipski SR(DMCU_IRAM_RD_DATA), \ 84d54ee946SMikita Lipski SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 85d54ee946SMikita Lipski SR(SMU_INTERRUPT_CONTROL), \ 86d54ee946SMikita Lipski SR(DC_DMCU_SCRATCH) 87d54ee946SMikita Lipski 885e7773a2SAnthony Koo #define DMCU_DCE110_COMMON_REG_LIST() \ 895e7773a2SAnthony Koo DMCU_COMMON_REG_LIST_DCE_BASE(), \ 905e7773a2SAnthony Koo SR(DCI_MEM_PWR_STATUS) 915e7773a2SAnthony Koo 92ff5ef992SAlex Deucher #define DMCU_DCN10_REG_LIST()\ 93ff5ef992SAlex Deucher DMCU_COMMON_REG_LIST_DCE_BASE(), \ 94ff5ef992SAlex Deucher SR(DMU_MEM_PWR_CNTL) 95ff5ef992SAlex Deucher 96a7e3658eSYongqiang Sun #define DMCU_DCN20_REG_LIST()\ 97a7e3658eSYongqiang Sun DMCU_DCN10_REG_LIST(), \ 98a7e3658eSYongqiang Sun SR(DMCUB_SCRATCH15) 99a7e3658eSYongqiang Sun 1005e7773a2SAnthony Koo #define DMCU_SF(reg_name, field_name, post_fix)\ 1015e7773a2SAnthony Koo .field_name = reg_name ## __ ## field_name ## post_fix 1025e7773a2SAnthony Koo 1035e7773a2SAnthony Koo #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 10490b9d7faSAnthony Koo DMCU_SF(DMCU_CTRL, \ 10590b9d7faSAnthony Koo DMCU_ENABLE, mask_sh), \ 1064952d4c5SAnthony Koo DMCU_SF(DMCU_STATUS, \ 1074952d4c5SAnthony Koo UC_IN_STOP_MODE, mask_sh), \ 10823bfb331SAnthony Koo DMCU_SF(DMCU_STATUS, \ 10923bfb331SAnthony Koo UC_IN_RESET, mask_sh), \ 1105e7773a2SAnthony Koo DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 1115e7773a2SAnthony Koo IRAM_HOST_ACCESS_EN, mask_sh), \ 1125e7773a2SAnthony Koo DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 1133548f073SAmy Zhang IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 1144952d4c5SAnthony Koo DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 1154952d4c5SAnthony Koo IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 1163548f073SAmy Zhang DMCU_SF(MASTER_COMM_CMD_REG, \ 1173548f073SAmy Zhang MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 1183548f073SAmy Zhang DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 119*a0c898f2SStylon Wang DMCU_SF(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, mask_sh), \ 1203548f073SAmy Zhang DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 1213548f073SAmy Zhang STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \ 1223548f073SAmy Zhang DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 1233548f073SAmy Zhang STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \ 1243548f073SAmy Zhang DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 1253548f073SAmy Zhang STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \ 1263548f073SAmy Zhang DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 1273548f073SAmy Zhang STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \ 1283548f073SAmy Zhang DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 1295e7773a2SAnthony Koo 130eab5a799SMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 131eab5a799SMauro Rossi #define DMCU_MASK_SH_LIST_DCE60(mask_sh) \ 132eab5a799SMauro Rossi DMCU_SF(DMCU_CTRL, \ 133eab5a799SMauro Rossi DMCU_ENABLE, mask_sh), \ 134eab5a799SMauro Rossi DMCU_SF(DMCU_STATUS, \ 135eab5a799SMauro Rossi UC_IN_STOP_MODE, mask_sh), \ 136eab5a799SMauro Rossi DMCU_SF(DMCU_STATUS, \ 137eab5a799SMauro Rossi UC_IN_RESET, mask_sh), \ 138eab5a799SMauro Rossi DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 139eab5a799SMauro Rossi IRAM_HOST_ACCESS_EN, mask_sh), \ 140eab5a799SMauro Rossi DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 141eab5a799SMauro Rossi IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 142eab5a799SMauro Rossi DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 143eab5a799SMauro Rossi IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 144eab5a799SMauro Rossi DMCU_SF(MASTER_COMM_CMD_REG, \ 145eab5a799SMauro Rossi MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 146eab5a799SMauro Rossi DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) 147eab5a799SMauro Rossi #endif 148eab5a799SMauro Rossi 149d54ee946SMikita Lipski #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \ 150d54ee946SMikita Lipski DMCU_SF(DMCU_CTRL, \ 151d54ee946SMikita Lipski DMCU_ENABLE, mask_sh), \ 152d54ee946SMikita Lipski DMCU_SF(DMCU_STATUS, \ 153d54ee946SMikita Lipski UC_IN_STOP_MODE, mask_sh), \ 154d54ee946SMikita Lipski DMCU_SF(DMCU_STATUS, \ 155d54ee946SMikita Lipski UC_IN_RESET, mask_sh), \ 156d54ee946SMikita Lipski DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 157d54ee946SMikita Lipski IRAM_HOST_ACCESS_EN, mask_sh), \ 158d54ee946SMikita Lipski DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 159d54ee946SMikita Lipski IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 160d54ee946SMikita Lipski DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 161d54ee946SMikita Lipski IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 162d54ee946SMikita Lipski DMCU_SF(MASTER_COMM_CMD_REG, \ 163d54ee946SMikita Lipski MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 164d54ee946SMikita Lipski DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 165d54ee946SMikita Lipski DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 166d54ee946SMikita Lipski 1675e7773a2SAnthony Koo #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \ 1685e7773a2SAnthony Koo DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 1695e7773a2SAnthony Koo DMCU_SF(DCI_MEM_PWR_STATUS, \ 1705e7773a2SAnthony Koo DMCU_IRAM_MEM_PWR_STATE, mask_sh) 1715e7773a2SAnthony Koo 172ff5ef992SAlex Deucher #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ 173ff5ef992SAlex Deucher DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 174ff5ef992SAlex Deucher DMCU_SF(DMU_MEM_PWR_CNTL, \ 175ff5ef992SAlex Deucher DMCU_IRAM_MEM_PWR_STATE, mask_sh) 176ff5ef992SAlex Deucher 1775e7773a2SAnthony Koo #define DMCU_REG_FIELD_LIST(type) \ 1785e7773a2SAnthony Koo type DMCU_IRAM_MEM_PWR_STATE; \ 1795e7773a2SAnthony Koo type IRAM_HOST_ACCESS_EN; \ 18090b9d7faSAnthony Koo type IRAM_WR_ADDR_AUTO_INC; \ 1814952d4c5SAnthony Koo type IRAM_RD_ADDR_AUTO_INC; \ 1823548f073SAmy Zhang type DMCU_ENABLE; \ 1834952d4c5SAnthony Koo type UC_IN_STOP_MODE; \ 18423bfb331SAnthony Koo type UC_IN_RESET; \ 1853548f073SAmy Zhang type MASTER_COMM_CMD_REG_BYTE0; \ 1863548f073SAmy Zhang type MASTER_COMM_INTERRUPT; \ 187*a0c898f2SStylon Wang type SLAVE_COMM_INTERRUPT; \ 1883548f073SAmy Zhang type DPHY_RX_FAST_TRAINING_CAPABLE; \ 1893548f073SAmy Zhang type DPHY_LOAD_BS_COUNT; \ 1903548f073SAmy Zhang type STATIC_SCREEN1_INT_TO_UC_EN; \ 1913548f073SAmy Zhang type STATIC_SCREEN2_INT_TO_UC_EN; \ 1923548f073SAmy Zhang type STATIC_SCREEN3_INT_TO_UC_EN; \ 1933548f073SAmy Zhang type STATIC_SCREEN4_INT_TO_UC_EN; \ 1943548f073SAmy Zhang type DP_SEC_GSP0_LINE_NUM; \ 1953548f073SAmy Zhang type DP_SEC_GSP0_PRIORITY; \ 1963548f073SAmy Zhang type DC_SMU_INT_ENABLE 1975e7773a2SAnthony Koo 1985e7773a2SAnthony Koo struct dce_dmcu_shift { 1995e7773a2SAnthony Koo DMCU_REG_FIELD_LIST(uint8_t); 2005e7773a2SAnthony Koo }; 2015e7773a2SAnthony Koo 2025e7773a2SAnthony Koo struct dce_dmcu_mask { 2035e7773a2SAnthony Koo DMCU_REG_FIELD_LIST(uint32_t); 2045e7773a2SAnthony Koo }; 2055e7773a2SAnthony Koo 2065e7773a2SAnthony Koo struct dce_dmcu_registers { 20790b9d7faSAnthony Koo uint32_t DMCU_CTRL; 2084952d4c5SAnthony Koo uint32_t DMCU_STATUS; 2095e7773a2SAnthony Koo uint32_t DMCU_RAM_ACCESS_CTRL; 2105e7773a2SAnthony Koo uint32_t DCI_MEM_PWR_STATUS; 2115e7773a2SAnthony Koo uint32_t DMU_MEM_PWR_CNTL; 2125e7773a2SAnthony Koo uint32_t DMCU_IRAM_WR_CTRL; 2135e7773a2SAnthony Koo uint32_t DMCU_IRAM_WR_DATA; 2143548f073SAmy Zhang 2153548f073SAmy Zhang uint32_t MASTER_COMM_DATA_REG1; 2163548f073SAmy Zhang uint32_t MASTER_COMM_DATA_REG2; 2173548f073SAmy Zhang uint32_t MASTER_COMM_DATA_REG3; 2183548f073SAmy Zhang uint32_t MASTER_COMM_CMD_REG; 2193548f073SAmy Zhang uint32_t MASTER_COMM_CNTL_REG; 220*a0c898f2SStylon Wang uint32_t SLAVE_COMM_DATA_REG1; 221*a0c898f2SStylon Wang uint32_t SLAVE_COMM_DATA_REG2; 222*a0c898f2SStylon Wang uint32_t SLAVE_COMM_DATA_REG3; 223*a0c898f2SStylon Wang uint32_t SLAVE_COMM_CMD_REG; 224*a0c898f2SStylon Wang uint32_t SLAVE_COMM_CNTL_REG; 2253548f073SAmy Zhang uint32_t DMCU_IRAM_RD_CTRL; 2263548f073SAmy Zhang uint32_t DMCU_IRAM_RD_DATA; 2273548f073SAmy Zhang uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 2283548f073SAmy Zhang uint32_t SMU_INTERRUPT_CONTROL; 2294952d4c5SAnthony Koo uint32_t DC_DMCU_SCRATCH; 230a7e3658eSYongqiang Sun uint32_t DMCUB_SCRATCH15; 2315e7773a2SAnthony Koo }; 2325e7773a2SAnthony Koo 2335e7773a2SAnthony Koo struct dce_dmcu { 2345e7773a2SAnthony Koo struct dmcu base; 2355e7773a2SAnthony Koo const struct dce_dmcu_registers *regs; 2365e7773a2SAnthony Koo const struct dce_dmcu_shift *dmcu_shift; 2375e7773a2SAnthony Koo const struct dce_dmcu_mask *dmcu_mask; 2385e7773a2SAnthony Koo }; 2395e7773a2SAnthony Koo 2403548f073SAmy Zhang /******************************************************************* 2413548f073SAmy Zhang * MASTER_COMM_DATA_REG1 Bit position Data 2423548f073SAmy Zhang * 7:0 hyst_frames[7:0] 2433548f073SAmy Zhang * 14:8 hyst_lines[6:0] 2443548f073SAmy Zhang * 15 RFB_UPDATE_AUTO_EN 2453548f073SAmy Zhang * 18:16 phy_num[2:0] 2463548f073SAmy Zhang * 21:19 dcp_sel[2:0] 2473548f073SAmy Zhang * 22 phy_type 2483548f073SAmy Zhang * 23 frame_cap_ind 2493548f073SAmy Zhang * 26:24 aux_chan[2:0] 2503548f073SAmy Zhang * 30:27 aux_repeat[3:0] 2513548f073SAmy Zhang * 31:31 reserved[31:31] 2523548f073SAmy Zhang ******************************************************************/ 2533548f073SAmy Zhang union dce_dmcu_psr_config_data_reg1 { 2543548f073SAmy Zhang struct { 2553548f073SAmy Zhang unsigned int timehyst_frames:8; /*[7:0]*/ 2563548f073SAmy Zhang unsigned int hyst_lines:7; /*[14:8]*/ 2573548f073SAmy Zhang unsigned int rfb_update_auto_en:1; /*[15:15]*/ 2583548f073SAmy Zhang unsigned int dp_port_num:3; /*[18:16]*/ 2593548f073SAmy Zhang unsigned int dcp_sel:3; /*[21:19]*/ 2603548f073SAmy Zhang unsigned int phy_type:1; /*[22:22]*/ 2613548f073SAmy Zhang unsigned int frame_cap_ind:1; /*[23:23]*/ 2623548f073SAmy Zhang unsigned int aux_chan:3; /*[26:24]*/ 2633548f073SAmy Zhang unsigned int aux_repeat:4; /*[30:27]*/ 2645d87a3fdSSivapiriyanKumarasamy unsigned int allow_smu_optimizations:1; /*[31:31]*/ 2653548f073SAmy Zhang } bits; 2663548f073SAmy Zhang unsigned int u32All; 2673548f073SAmy Zhang }; 2683548f073SAmy Zhang 2693548f073SAmy Zhang /******************************************************************* 2703548f073SAmy Zhang * MASTER_COMM_DATA_REG2 2713548f073SAmy Zhang *******************************************************************/ 2723548f073SAmy Zhang union dce_dmcu_psr_config_data_reg2 { 2733548f073SAmy Zhang struct { 2743548f073SAmy Zhang unsigned int dig_fe:3; /*[2:0]*/ 2753548f073SAmy Zhang unsigned int dig_be:3; /*[5:3]*/ 2763548f073SAmy Zhang unsigned int skip_wait_for_pll_lock:1; /*[6:6]*/ 2773548f073SAmy Zhang unsigned int reserved:9; /*[15:7]*/ 2783548f073SAmy Zhang unsigned int frame_delay:8; /*[23:16]*/ 2793548f073SAmy Zhang unsigned int smu_phy_id:4; /*[27:24]*/ 2803548f073SAmy Zhang unsigned int num_of_controllers:4; /*[31:28]*/ 2813548f073SAmy Zhang } bits; 2823548f073SAmy Zhang unsigned int u32All; 2833548f073SAmy Zhang }; 2843548f073SAmy Zhang 2853548f073SAmy Zhang /******************************************************************* 2863548f073SAmy Zhang * MASTER_COMM_DATA_REG3 2873548f073SAmy Zhang *******************************************************************/ 2883548f073SAmy Zhang union dce_dmcu_psr_config_data_reg3 { 2893548f073SAmy Zhang struct { 2903548f073SAmy Zhang unsigned int psr_level:16; /*[15:0]*/ 2913548f073SAmy Zhang unsigned int link_rate:4; /*[19:16]*/ 2923548f073SAmy Zhang unsigned int reserved:12; /*[31:20]*/ 2933548f073SAmy Zhang } bits; 2943548f073SAmy Zhang unsigned int u32All; 2953548f073SAmy Zhang }; 2963548f073SAmy Zhang 2979f72f51dSAmy Zhang union dce_dmcu_psr_config_data_wait_loop_reg1 { 2989f72f51dSAmy Zhang struct { 2999f72f51dSAmy Zhang unsigned int wait_loop:16; /* [15:0] */ 3009f72f51dSAmy Zhang unsigned int reserved:16; /* [31:16] */ 3019f72f51dSAmy Zhang } bits; 3029f72f51dSAmy Zhang unsigned int u32; 3039f72f51dSAmy Zhang }; 3049f72f51dSAmy Zhang 3055e7773a2SAnthony Koo struct dmcu *dce_dmcu_create( 3065e7773a2SAnthony Koo struct dc_context *ctx, 3075e7773a2SAnthony Koo const struct dce_dmcu_registers *regs, 3085e7773a2SAnthony Koo const struct dce_dmcu_shift *dmcu_shift, 3095e7773a2SAnthony Koo const struct dce_dmcu_mask *dmcu_mask); 3105e7773a2SAnthony Koo 311ff5ef992SAlex Deucher struct dmcu *dcn10_dmcu_create( 312ff5ef992SAlex Deucher struct dc_context *ctx, 313ff5ef992SAlex Deucher const struct dce_dmcu_registers *regs, 314ff5ef992SAlex Deucher const struct dce_dmcu_shift *dmcu_shift, 315ff5ef992SAlex Deucher const struct dce_dmcu_mask *dmcu_mask); 316ff5ef992SAlex Deucher 3177ed4e635SHarry Wentland struct dmcu *dcn20_dmcu_create( 3187ed4e635SHarry Wentland struct dc_context *ctx, 3197ed4e635SHarry Wentland const struct dce_dmcu_registers *regs, 3207ed4e635SHarry Wentland const struct dce_dmcu_shift *dmcu_shift, 3217ed4e635SHarry Wentland const struct dce_dmcu_mask *dmcu_mask); 3227ed4e635SHarry Wentland 323a7e3658eSYongqiang Sun struct dmcu *dcn21_dmcu_create( 324a7e3658eSYongqiang Sun struct dc_context *ctx, 325a7e3658eSYongqiang Sun const struct dce_dmcu_registers *regs, 326a7e3658eSYongqiang Sun const struct dce_dmcu_shift *dmcu_shift, 327a7e3658eSYongqiang Sun const struct dce_dmcu_mask *dmcu_mask); 328a7e3658eSYongqiang Sun 3295e7773a2SAnthony Koo void dce_dmcu_destroy(struct dmcu **dmcu); 3305e7773a2SAnthony Koo 3315e7773a2SAnthony Koo #endif /* _DCE_ABM_H_ */ 332