1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "resource.h" 29 #include "dce_i2c.h" 30 #include "dce_i2c_hw.h" 31 #include "reg_helper.h" 32 #include "include/gpio_service_interface.h" 33 34 #define CTX \ 35 dce_i2c_hw->ctx 36 #define REG(reg)\ 37 dce_i2c_hw->regs->reg 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name 42 43 static void execute_transaction( 44 struct dce_i2c_hw *dce_i2c_hw) 45 { 46 REG_UPDATE_N(SETUP, 5, 47 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0, 48 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0, 49 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0, 50 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0, 51 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0); 52 53 54 REG_UPDATE_5(DC_I2C_CONTROL, 55 DC_I2C_SOFT_RESET, 0, 56 DC_I2C_SW_STATUS_RESET, 0, 57 DC_I2C_SEND_RESET, 0, 58 DC_I2C_GO, 0, 59 DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1); 60 61 /* start I2C transfer */ 62 REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1); 63 64 /* all transactions were executed and HW buffer became empty 65 * (even though it actually happens when status becomes DONE) 66 */ 67 dce_i2c_hw->transaction_count = 0; 68 dce_i2c_hw->buffer_used_bytes = 0; 69 } 70 71 static enum i2c_channel_operation_result get_channel_status( 72 struct dce_i2c_hw *dce_i2c_hw, 73 uint8_t *returned_bytes) 74 { 75 uint32_t i2c_sw_status = 0; 76 uint32_t value = 77 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 78 if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW) 79 return I2C_CHANNEL_OPERATION_ENGINE_BUSY; 80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) 81 return I2C_CHANNEL_OPERATION_NO_RESPONSE; 82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) 83 return I2C_CHANNEL_OPERATION_TIMEOUT; 84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) 85 return I2C_CHANNEL_OPERATION_FAILED; 86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) 87 return I2C_CHANNEL_OPERATION_SUCCEEDED; 88 89 /* 90 * this is the case when HW used for communication, I2C_SW_STATUS 91 * could be zero 92 */ 93 return I2C_CHANNEL_OPERATION_SUCCEEDED; 94 } 95 96 static uint32_t get_hw_buffer_available_size( 97 const struct dce_i2c_hw *dce_i2c_hw) 98 { 99 return dce_i2c_hw->buffer_size - 100 dce_i2c_hw->buffer_used_bytes; 101 } 102 103 static void process_channel_reply( 104 struct dce_i2c_hw *dce_i2c_hw, 105 struct i2c_payload *reply) 106 { 107 uint32_t length = reply->length; 108 uint8_t *buffer = reply->data; 109 110 REG_SET_3(DC_I2C_DATA, 0, 111 DC_I2C_INDEX, dce_i2c_hw->buffer_used_write, 112 DC_I2C_DATA_RW, 1, 113 DC_I2C_INDEX_WRITE, 1); 114 115 while (length) { 116 /* after reading the status, 117 * if the I2C operation executed successfully 118 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller 119 * should read data bytes from I2C circular data buffer 120 */ 121 122 uint32_t i2c_data; 123 124 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); 125 *buffer++ = i2c_data; 126 127 --length; 128 } 129 } 130 131 static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw) 132 { 133 unsigned int arbitrate; 134 unsigned int i2c_hw_status; 135 136 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); 137 if (i2c_hw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW) 138 return false; 139 140 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); 141 if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY) 142 return false; 143 144 return true; 145 } 146 147 static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw) 148 { 149 uint32_t i2c_sw_status = 0; 150 151 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 152 if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE) 153 return false; 154 155 if (is_engine_available(dce_i2c_hw)) 156 return false; 157 158 return true; 159 } 160 161 static bool process_transaction( 162 struct dce_i2c_hw *dce_i2c_hw, 163 struct i2c_request_transaction_data *request) 164 { 165 uint32_t length = request->length; 166 uint8_t *buffer = request->data; 167 168 bool last_transaction = false; 169 uint32_t value = 0; 170 171 if (is_hw_busy(dce_i2c_hw)) { 172 request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY; 173 return false; 174 } 175 176 last_transaction = ((dce_i2c_hw->transaction_count == 3) || 177 (request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) || 178 (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)); 179 180 181 switch (dce_i2c_hw->transaction_count) { 182 case 0: 183 REG_UPDATE_5(DC_I2C_TRANSACTION0, 184 DC_I2C_STOP_ON_NACK0, 1, 185 DC_I2C_START0, 1, 186 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ), 187 DC_I2C_COUNT0, length, 188 DC_I2C_STOP0, last_transaction ? 1 : 0); 189 break; 190 case 1: 191 REG_UPDATE_5(DC_I2C_TRANSACTION1, 192 DC_I2C_STOP_ON_NACK0, 1, 193 DC_I2C_START0, 1, 194 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ), 195 DC_I2C_COUNT0, length, 196 DC_I2C_STOP0, last_transaction ? 1 : 0); 197 break; 198 case 2: 199 REG_UPDATE_5(DC_I2C_TRANSACTION2, 200 DC_I2C_STOP_ON_NACK0, 1, 201 DC_I2C_START0, 1, 202 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ), 203 DC_I2C_COUNT0, length, 204 DC_I2C_STOP0, last_transaction ? 1 : 0); 205 break; 206 case 3: 207 REG_UPDATE_5(DC_I2C_TRANSACTION3, 208 DC_I2C_STOP_ON_NACK0, 1, 209 DC_I2C_START0, 1, 210 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ), 211 DC_I2C_COUNT0, length, 212 DC_I2C_STOP0, last_transaction ? 1 : 0); 213 break; 214 default: 215 /* TODO Warning ? */ 216 break; 217 } 218 219 /* Write the I2C address and I2C data 220 * into the hardware circular buffer, one byte per entry. 221 * As an example, the 7-bit I2C slave address for CRT monitor 222 * for reading DDC/EDID information is 0b1010001. 223 * For an I2C send operation, the LSB must be programmed to 0; 224 * for I2C receive operation, the LSB must be programmed to 1. 225 */ 226 if (dce_i2c_hw->transaction_count == 0) { 227 value = REG_SET_4(DC_I2C_DATA, 0, 228 DC_I2C_DATA_RW, false, 229 DC_I2C_DATA, request->address, 230 DC_I2C_INDEX, 0, 231 DC_I2C_INDEX_WRITE, 1); 232 dce_i2c_hw->buffer_used_write = 0; 233 } else 234 value = REG_SET_2(DC_I2C_DATA, 0, 235 DC_I2C_DATA_RW, false, 236 DC_I2C_DATA, request->address); 237 238 dce_i2c_hw->buffer_used_write++; 239 240 if (!(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)) { 241 while (length) { 242 REG_SET_2(DC_I2C_DATA, value, 243 DC_I2C_INDEX_WRITE, 0, 244 DC_I2C_DATA, *buffer++); 245 dce_i2c_hw->buffer_used_write++; 246 --length; 247 } 248 } 249 250 ++dce_i2c_hw->transaction_count; 251 dce_i2c_hw->buffer_used_bytes += length + 1; 252 253 return last_transaction; 254 } 255 256 static inline void reset_hw_engine(struct dce_i2c_hw *dce_i2c_hw) 257 { 258 REG_UPDATE_2(DC_I2C_CONTROL, 259 DC_I2C_SW_STATUS_RESET, 1, 260 DC_I2C_SW_STATUS_RESET, 1); 261 } 262 263 static void set_speed( 264 struct dce_i2c_hw *dce_i2c_hw, 265 uint32_t speed) 266 { 267 uint32_t xtal_ref_div = 0; 268 uint32_t prescale = 0; 269 270 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); 271 272 if (xtal_ref_div == 0) 273 xtal_ref_div = 2; 274 275 prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) / speed; 276 277 if (speed) { 278 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) 279 REG_UPDATE_N(SPEED, 3, 280 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale, 281 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2, 282 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1); 283 else 284 REG_UPDATE_N(SPEED, 2, 285 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale, 286 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2); 287 } 288 } 289 290 static bool setup_engine( 291 struct dce_i2c_hw *dce_i2c_hw) 292 { 293 uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE; 294 uint32_t reset_length = 0; 295 /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ 296 REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); 297 298 /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ 299 REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); 300 301 if (dce_i2c_hw->setup_limit != 0) 302 i2c_setup_limit = dce_i2c_hw->setup_limit; 303 /* Program pin select */ 304 REG_UPDATE_6(DC_I2C_CONTROL, 305 DC_I2C_GO, 0, 306 DC_I2C_SOFT_RESET, 0, 307 DC_I2C_SEND_RESET, 0, 308 DC_I2C_SW_STATUS_RESET, 1, 309 DC_I2C_TRANSACTION_COUNT, 0, 310 DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id); 311 312 /* Program time limit */ 313 if (dce_i2c_hw->send_reset_length == 0) { 314 /*pre-dcn*/ 315 REG_UPDATE_N(SETUP, 2, 316 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, 317 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); 318 } else { 319 reset_length = dce_i2c_hw->send_reset_length; 320 REG_UPDATE_N(SETUP, 3, 321 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, 322 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length, 323 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); 324 } 325 /* Program HW priority 326 * set to High - interrupt software I2C at any time 327 * Enable restart of SW I2C that was interrupted by HW 328 * disable queuing of software while I2C is in use by HW 329 */ 330 REG_UPDATE(DC_I2C_ARBITRATION, 331 DC_I2C_NO_QUEUED_SW_GO, 0); 332 333 return true; 334 } 335 336 static void release_engine( 337 struct dce_i2c_hw *dce_i2c_hw) 338 { 339 bool safe_to_reset; 340 341 /* Restore original HW engine speed */ 342 set_speed(dce_i2c_hw, dce_i2c_hw->default_speed); 343 344 /* Reset HW engine */ 345 { 346 uint32_t i2c_sw_status = 0; 347 348 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 349 /* if used by SW, safe to reset */ 350 safe_to_reset = (i2c_sw_status == 1); 351 } 352 353 if (safe_to_reset) 354 REG_UPDATE_2(DC_I2C_CONTROL, 355 DC_I2C_SOFT_RESET, 1, 356 DC_I2C_SW_STATUS_RESET, 1); 357 else 358 REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1); 359 /* HW I2c engine - clock gating feature */ 360 if (!dce_i2c_hw->engine_keep_power_up_count) 361 REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0); 362 /* Release I2C after reset, so HW or DMCU could use it */ 363 REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1, 364 DC_I2C_SW_USE_I2C_REG_REQ, 0); 365 366 } 367 368 struct dce_i2c_hw *acquire_i2c_hw_engine( 369 struct resource_pool *pool, 370 struct ddc *ddc) 371 { 372 uint32_t counter = 0; 373 enum gpio_result result; 374 struct dce_i2c_hw *dce_i2c_hw = NULL; 375 376 if (!ddc) 377 return NULL; 378 379 if (ddc->hw_info.hw_supported) { 380 enum gpio_ddc_line line = dal_ddc_get_line(ddc); 381 382 if (line < pool->res_cap->num_ddc) 383 dce_i2c_hw = pool->hw_i2cs[line]; 384 } 385 386 if (!dce_i2c_hw) 387 return NULL; 388 389 if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw)) 390 return NULL; 391 392 do { 393 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, 394 GPIO_DDC_CONFIG_TYPE_MODE_I2C); 395 396 if (result == GPIO_RESULT_OK) 397 break; 398 399 /* i2c_engine is busy by VBios, lets wait and retry */ 400 401 udelay(10); 402 403 ++counter; 404 } while (counter < 2); 405 406 if (result != GPIO_RESULT_OK) 407 return NULL; 408 409 dce_i2c_hw->ddc = ddc; 410 411 if (!setup_engine(dce_i2c_hw)) { 412 release_engine(dce_i2c_hw); 413 return NULL; 414 } 415 416 pool->i2c_hw_buffer_in_use = true; 417 return dce_i2c_hw; 418 } 419 420 enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result( 421 struct dce_i2c_hw *dce_i2c_hw, 422 uint32_t timeout, 423 enum i2c_channel_operation_result expected_result) 424 { 425 enum i2c_channel_operation_result result; 426 uint32_t i = 0; 427 428 if (!timeout) 429 return I2C_CHANNEL_OPERATION_SUCCEEDED; 430 431 do { 432 433 result = get_channel_status( 434 dce_i2c_hw, NULL); 435 436 if (result != expected_result) 437 break; 438 439 udelay(1); 440 441 ++i; 442 } while (i < timeout); 443 return result; 444 } 445 446 static void submit_channel_request_hw( 447 struct dce_i2c_hw *dce_i2c_hw, 448 struct i2c_request_transaction_data *request) 449 { 450 request->status = I2C_CHANNEL_OPERATION_SUCCEEDED; 451 452 if (!process_transaction(dce_i2c_hw, request)) 453 return; 454 455 if (is_hw_busy(dce_i2c_hw)) { 456 request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY; 457 return; 458 } 459 reset_hw_engine(dce_i2c_hw); 460 461 execute_transaction(dce_i2c_hw); 462 463 464 } 465 466 static uint32_t get_transaction_timeout_hw( 467 const struct dce_i2c_hw *dce_i2c_hw, 468 uint32_t length, 469 uint32_t speed) 470 { 471 uint32_t period_timeout; 472 uint32_t num_of_clock_stretches; 473 474 if (!speed) 475 return 0; 476 477 period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed; 478 479 num_of_clock_stretches = 1 + (length << 3) + 1; 480 num_of_clock_stretches += 481 (dce_i2c_hw->buffer_used_bytes << 3) + 482 (dce_i2c_hw->transaction_count << 1); 483 484 return period_timeout * num_of_clock_stretches; 485 } 486 487 bool dce_i2c_hw_engine_submit_payload( 488 struct dce_i2c_hw *dce_i2c_hw, 489 struct i2c_payload *payload, 490 bool middle_of_transaction, 491 uint32_t speed) 492 { 493 494 struct i2c_request_transaction_data request; 495 496 uint32_t transaction_timeout; 497 498 enum i2c_channel_operation_result operation_result; 499 500 bool result = false; 501 502 /* We need following: 503 * transaction length will not exceed 504 * the number of free bytes in HW buffer (minus one for address) 505 */ 506 507 if (payload->length >= 508 get_hw_buffer_available_size(dce_i2c_hw)) { 509 return false; 510 } 511 512 if (!payload->write) 513 request.action = middle_of_transaction ? 514 DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT : 515 DCE_I2C_TRANSACTION_ACTION_I2C_READ; 516 else 517 request.action = middle_of_transaction ? 518 DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT : 519 DCE_I2C_TRANSACTION_ACTION_I2C_WRITE; 520 521 522 request.address = (uint8_t) ((payload->address << 1) | !payload->write); 523 request.length = payload->length; 524 request.data = payload->data; 525 526 /* obtain timeout value before submitting request */ 527 528 transaction_timeout = get_transaction_timeout_hw( 529 dce_i2c_hw, payload->length + 1, speed); 530 531 submit_channel_request_hw( 532 dce_i2c_hw, &request); 533 534 if ((request.status == I2C_CHANNEL_OPERATION_FAILED) || 535 (request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY)) 536 return false; 537 538 /* wait until transaction proceed */ 539 540 operation_result = dce_i2c_hw_engine_wait_on_operation_result( 541 dce_i2c_hw, 542 transaction_timeout, 543 I2C_CHANNEL_OPERATION_ENGINE_BUSY); 544 545 /* update transaction status */ 546 547 if (operation_result == I2C_CHANNEL_OPERATION_SUCCEEDED) 548 result = true; 549 550 if (result && (!payload->write)) 551 process_channel_reply(dce_i2c_hw, payload); 552 553 return result; 554 } 555 556 bool dce_i2c_submit_command_hw( 557 struct resource_pool *pool, 558 struct ddc *ddc, 559 struct i2c_command *cmd, 560 struct dce_i2c_hw *dce_i2c_hw) 561 { 562 uint8_t index_of_payload = 0; 563 bool result; 564 565 set_speed(dce_i2c_hw, cmd->speed); 566 567 result = true; 568 569 while (index_of_payload < cmd->number_of_payloads) { 570 bool mot = (index_of_payload != cmd->number_of_payloads - 1); 571 572 struct i2c_payload *payload = cmd->payloads + index_of_payload; 573 574 if (!dce_i2c_hw_engine_submit_payload( 575 dce_i2c_hw, payload, mot, cmd->speed)) { 576 result = false; 577 break; 578 } 579 580 ++index_of_payload; 581 } 582 583 pool->i2c_hw_buffer_in_use = false; 584 585 release_engine(dce_i2c_hw); 586 dal_ddc_close(dce_i2c_hw->ddc); 587 588 dce_i2c_hw->ddc = NULL; 589 590 return result; 591 } 592 593 void dce_i2c_hw_construct( 594 struct dce_i2c_hw *dce_i2c_hw, 595 struct dc_context *ctx, 596 uint32_t engine_id, 597 const struct dce_i2c_registers *regs, 598 const struct dce_i2c_shift *shifts, 599 const struct dce_i2c_mask *masks) 600 { 601 dce_i2c_hw->ctx = ctx; 602 dce_i2c_hw->engine_id = engine_id; 603 dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1; 604 dce_i2c_hw->regs = regs; 605 dce_i2c_hw->shifts = shifts; 606 dce_i2c_hw->masks = masks; 607 dce_i2c_hw->buffer_used_bytes = 0; 608 dce_i2c_hw->transaction_count = 0; 609 dce_i2c_hw->engine_keep_power_up_count = 1; 610 dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED; 611 dce_i2c_hw->send_reset_length = 0; 612 dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCE; 613 dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE; 614 } 615 616 void dce100_i2c_hw_construct( 617 struct dce_i2c_hw *dce_i2c_hw, 618 struct dc_context *ctx, 619 uint32_t engine_id, 620 const struct dce_i2c_registers *regs, 621 const struct dce_i2c_shift *shifts, 622 const struct dce_i2c_mask *masks) 623 { 624 dce_i2c_hw_construct(dce_i2c_hw, 625 ctx, 626 engine_id, 627 regs, 628 shifts, 629 masks); 630 dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE100; 631 } 632 633 void dce112_i2c_hw_construct( 634 struct dce_i2c_hw *dce_i2c_hw, 635 struct dc_context *ctx, 636 uint32_t engine_id, 637 const struct dce_i2c_registers *regs, 638 const struct dce_i2c_shift *shifts, 639 const struct dce_i2c_mask *masks) 640 { 641 dce100_i2c_hw_construct(dce_i2c_hw, 642 ctx, 643 engine_id, 644 regs, 645 shifts, 646 masks); 647 dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED_100KHZ; 648 } 649 650 void dcn1_i2c_hw_construct( 651 struct dce_i2c_hw *dce_i2c_hw, 652 struct dc_context *ctx, 653 uint32_t engine_id, 654 const struct dce_i2c_registers *regs, 655 const struct dce_i2c_shift *shifts, 656 const struct dce_i2c_mask *masks) 657 { 658 dce112_i2c_hw_construct(dce_i2c_hw, 659 ctx, 660 engine_id, 661 regs, 662 shifts, 663 masks); 664 dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN; 665 } 666 667 void dcn2_i2c_hw_construct( 668 struct dce_i2c_hw *dce_i2c_hw, 669 struct dc_context *ctx, 670 uint32_t engine_id, 671 const struct dce_i2c_registers *regs, 672 const struct dce_i2c_shift *shifts, 673 const struct dce_i2c_mask *masks) 674 { 675 dcn1_i2c_hw_construct(dce_i2c_hw, 676 ctx, 677 engine_id, 678 regs, 679 shifts, 680 masks); 681 dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9; 682 if (ctx->dc->debug.scl_reset_length10) 683 dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10; 684 } 685