14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef __DC_LINK_ENCODER__DCE110_H__ 274562236bSHarry Wentland #define __DC_LINK_ENCODER__DCE110_H__ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "link_encoder.h" 304562236bSHarry Wentland 314562236bSHarry Wentland #define TO_DCE110_LINK_ENC(link_encoder)\ 324562236bSHarry Wentland container_of(link_encoder, struct dce110_link_encoder, base) 334562236bSHarry Wentland 342c8ad2d5SAlex Deucher /* Not found regs in dce120 spec 352c8ad2d5SAlex Deucher * BIOS_SCRATCH_2 362c8ad2d5SAlex Deucher * DP_DPHY_INTERNAL_CTRL 372c8ad2d5SAlex Deucher */ 382c8ad2d5SAlex Deucher 394562236bSHarry Wentland #define AUX_REG_LIST(id)\ 404562236bSHarry Wentland SRI(AUX_CONTROL, DP_AUX, id), \ 416224220dSIgor Kravchenko SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \ 426224220dSIgor Kravchenko SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id) 434562236bSHarry Wentland 444562236bSHarry Wentland #define HPD_REG_LIST(id)\ 454562236bSHarry Wentland SRI(DC_HPD_CONTROL, HPD, id) 464562236bSHarry Wentland 474562236bSHarry Wentland #define LE_COMMON_REG_LIST_BASE(id) \ 484562236bSHarry Wentland SR(DMCU_RAM_ACCESS_CTRL), \ 494562236bSHarry Wentland SR(DMCU_IRAM_RD_CTRL), \ 504562236bSHarry Wentland SR(DMCU_IRAM_RD_DATA), \ 514562236bSHarry Wentland SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 524562236bSHarry Wentland SRI(DIG_BE_CNTL, DIG, id), \ 534562236bSHarry Wentland SRI(DIG_BE_EN_CNTL, DIG, id), \ 544562236bSHarry Wentland SRI(DP_CONFIG, DP, id), \ 554562236bSHarry Wentland SRI(DP_DPHY_CNTL, DP, id), \ 564562236bSHarry Wentland SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 574562236bSHarry Wentland SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 584562236bSHarry Wentland SRI(DP_DPHY_SYM0, DP, id), \ 594562236bSHarry Wentland SRI(DP_DPHY_SYM1, DP, id), \ 604562236bSHarry Wentland SRI(DP_DPHY_SYM2, DP, id), \ 614562236bSHarry Wentland SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 624562236bSHarry Wentland SRI(DP_LINK_CNTL, DP, id), \ 634562236bSHarry Wentland SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 644562236bSHarry Wentland SRI(DP_MSE_SAT0, DP, id), \ 654562236bSHarry Wentland SRI(DP_MSE_SAT1, DP, id), \ 664562236bSHarry Wentland SRI(DP_MSE_SAT2, DP, id), \ 674562236bSHarry Wentland SRI(DP_MSE_SAT_UPDATE, DP, id), \ 684562236bSHarry Wentland SRI(DP_SEC_CNTL, DP, id), \ 694562236bSHarry Wentland SRI(DP_VID_STREAM_CNTL, DP, id), \ 704562236bSHarry Wentland SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 714562236bSHarry Wentland SRI(DP_SEC_CNTL1, DP, id) 724562236bSHarry Wentland 734562236bSHarry Wentland #define LE_COMMON_REG_LIST(id)\ 744562236bSHarry Wentland LE_COMMON_REG_LIST_BASE(id), \ 754562236bSHarry Wentland SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 764562236bSHarry Wentland SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 774562236bSHarry Wentland SR(DCI_MEM_PWR_STATUS) 784562236bSHarry Wentland 79c1a64ebdSMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 80c1a64ebdSMauro Rossi #define LE_DCE60_REG_LIST(id)\ 81c1a64ebdSMauro Rossi SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 82c1a64ebdSMauro Rossi SR(DMCU_RAM_ACCESS_CTRL), \ 83c1a64ebdSMauro Rossi SR(DMCU_IRAM_RD_CTRL), \ 84c1a64ebdSMauro Rossi SR(DMCU_IRAM_RD_DATA), \ 85c1a64ebdSMauro Rossi SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 86c1a64ebdSMauro Rossi SRI(DIG_BE_CNTL, DIG, id), \ 87c1a64ebdSMauro Rossi SRI(DIG_BE_EN_CNTL, DIG, id), \ 88c1a64ebdSMauro Rossi SRI(DP_CONFIG, DP, id), \ 89c1a64ebdSMauro Rossi SRI(DP_DPHY_CNTL, DP, id), \ 90c1a64ebdSMauro Rossi SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 91c1a64ebdSMauro Rossi SRI(DP_DPHY_SYM0, DP, id), \ 92c1a64ebdSMauro Rossi SRI(DP_DPHY_SYM1, DP, id), \ 93c1a64ebdSMauro Rossi SRI(DP_DPHY_SYM2, DP, id), \ 94c1a64ebdSMauro Rossi SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 95c1a64ebdSMauro Rossi SRI(DP_LINK_CNTL, DP, id), \ 96c1a64ebdSMauro Rossi SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 97c1a64ebdSMauro Rossi SRI(DP_MSE_SAT0, DP, id), \ 98c1a64ebdSMauro Rossi SRI(DP_MSE_SAT1, DP, id), \ 99c1a64ebdSMauro Rossi SRI(DP_MSE_SAT2, DP, id), \ 100c1a64ebdSMauro Rossi SRI(DP_MSE_SAT_UPDATE, DP, id), \ 101c1a64ebdSMauro Rossi SRI(DP_SEC_CNTL, DP, id), \ 102c1a64ebdSMauro Rossi SRI(DP_VID_STREAM_CNTL, DP, id), \ 103c1a64ebdSMauro Rossi SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 104c1a64ebdSMauro Rossi SRI(DP_SEC_CNTL1, DP, id) 105c1a64ebdSMauro Rossi #endif 106c1a64ebdSMauro Rossi 107ff5ef992SAlex Deucher #define LE_DCE80_REG_LIST(id)\ 108ff5ef992SAlex Deucher SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 1095eefbc40SYue Hin Lau LE_COMMON_REG_LIST_BASE(id) 110ff5ef992SAlex Deucher 1113f8a9440STony Cheng #define LE_DCE100_REG_LIST(id)\ 1123f8a9440STony Cheng LE_COMMON_REG_LIST_BASE(id), \ 1133f8a9440STony Cheng SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 1143f8a9440STony Cheng SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 1155eefbc40SYue Hin Lau SR(DCI_MEM_PWR_STATUS) 1163f8a9440STony Cheng 1174562236bSHarry Wentland #define LE_DCE110_REG_LIST(id)\ 1184562236bSHarry Wentland LE_COMMON_REG_LIST_BASE(id), \ 1194562236bSHarry Wentland SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 1204562236bSHarry Wentland SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 1213f8a9440STony Cheng SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ 1225eefbc40SYue Hin Lau SR(DCI_MEM_PWR_STATUS) 1234562236bSHarry Wentland 1242c8ad2d5SAlex Deucher #define LE_DCE120_REG_LIST(id)\ 1252c8ad2d5SAlex Deucher LE_COMMON_REG_LIST_BASE(id), \ 1262c8ad2d5SAlex Deucher SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 1273f8a9440STony Cheng SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ 1285eefbc40SYue Hin Lau SR(DCI_MEM_PWR_STATUS) 1292c8ad2d5SAlex Deucher 130ff5ef992SAlex Deucher #define LE_DCN10_REG_LIST(id)\ 131ff5ef992SAlex Deucher LE_COMMON_REG_LIST_BASE(id), \ 132ff5ef992SAlex Deucher SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 1334562236bSHarry Wentland SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 1345eefbc40SYue Hin Lau SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) 1354562236bSHarry Wentland 1364562236bSHarry Wentland struct dce110_link_enc_aux_registers { 1374562236bSHarry Wentland uint32_t AUX_CONTROL; 1384562236bSHarry Wentland uint32_t AUX_DPHY_RX_CONTROL0; 1396224220dSIgor Kravchenko uint32_t AUX_DPHY_RX_CONTROL1; 1404562236bSHarry Wentland }; 1414562236bSHarry Wentland 1424562236bSHarry Wentland struct dce110_link_enc_hpd_registers { 1434562236bSHarry Wentland uint32_t DC_HPD_CONTROL; 1444562236bSHarry Wentland }; 1454562236bSHarry Wentland 1464562236bSHarry Wentland struct dce110_link_enc_registers { 1474562236bSHarry Wentland /* DMCU registers */ 1484562236bSHarry Wentland uint32_t MASTER_COMM_DATA_REG1; 1494562236bSHarry Wentland uint32_t MASTER_COMM_DATA_REG2; 1504562236bSHarry Wentland uint32_t MASTER_COMM_DATA_REG3; 1514562236bSHarry Wentland uint32_t MASTER_COMM_CMD_REG; 1524562236bSHarry Wentland uint32_t MASTER_COMM_CNTL_REG; 1534562236bSHarry Wentland uint32_t DMCU_RAM_ACCESS_CTRL; 1544562236bSHarry Wentland uint32_t DCI_MEM_PWR_STATUS; 1554562236bSHarry Wentland uint32_t DMU_MEM_PWR_CNTL; 1564562236bSHarry Wentland uint32_t DMCU_IRAM_RD_CTRL; 1574562236bSHarry Wentland uint32_t DMCU_IRAM_RD_DATA; 1584562236bSHarry Wentland uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 1594562236bSHarry Wentland 1604562236bSHarry Wentland /* Common DP registers */ 1614562236bSHarry Wentland uint32_t DIG_BE_CNTL; 1624562236bSHarry Wentland uint32_t DIG_BE_EN_CNTL; 1634562236bSHarry Wentland uint32_t DP_CONFIG; 1644562236bSHarry Wentland uint32_t DP_DPHY_CNTL; 1654562236bSHarry Wentland uint32_t DP_DPHY_INTERNAL_CTRL; 1664562236bSHarry Wentland uint32_t DP_DPHY_PRBS_CNTL; 1674562236bSHarry Wentland uint32_t DP_DPHY_SCRAM_CNTL; 1684562236bSHarry Wentland uint32_t DP_DPHY_SYM0; 1694562236bSHarry Wentland uint32_t DP_DPHY_SYM1; 1704562236bSHarry Wentland uint32_t DP_DPHY_SYM2; 1714562236bSHarry Wentland uint32_t DP_DPHY_TRAINING_PATTERN_SEL; 1724562236bSHarry Wentland uint32_t DP_LINK_CNTL; 1734562236bSHarry Wentland uint32_t DP_LINK_FRAMING_CNTL; 1744562236bSHarry Wentland uint32_t DP_MSE_SAT0; 1754562236bSHarry Wentland uint32_t DP_MSE_SAT1; 1764562236bSHarry Wentland uint32_t DP_MSE_SAT2; 1774562236bSHarry Wentland uint32_t DP_MSE_SAT_UPDATE; 1784562236bSHarry Wentland uint32_t DP_SEC_CNTL; 1794562236bSHarry Wentland uint32_t DP_VID_STREAM_CNTL; 1804562236bSHarry Wentland uint32_t DP_DPHY_FAST_TRAINING; 1814562236bSHarry Wentland uint32_t DP_DPHY_BS_SR_SWAP_CNTL; 1823f8a9440STony Cheng uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; 1834562236bSHarry Wentland uint32_t DP_SEC_CNTL1; 1844562236bSHarry Wentland }; 1854562236bSHarry Wentland 1864562236bSHarry Wentland struct dce110_link_encoder { 1874562236bSHarry Wentland struct link_encoder base; 1884562236bSHarry Wentland const struct dce110_link_enc_registers *link_regs; 1894562236bSHarry Wentland const struct dce110_link_enc_aux_registers *aux_regs; 1904562236bSHarry Wentland const struct dce110_link_enc_hpd_registers *hpd_regs; 1914562236bSHarry Wentland }; 1924562236bSHarry Wentland 1934562236bSHarry Wentland 194c60ae112SDave Airlie void dce110_link_encoder_construct( 1954562236bSHarry Wentland struct dce110_link_encoder *enc110, 1964562236bSHarry Wentland const struct encoder_init_data *init_data, 1977fc698a0STony Cheng const struct encoder_feature_support *enc_features, 1984562236bSHarry Wentland const struct dce110_link_enc_registers *link_regs, 1994562236bSHarry Wentland const struct dce110_link_enc_aux_registers *aux_regs, 2004562236bSHarry Wentland const struct dce110_link_enc_hpd_registers *hpd_regs); 2014562236bSHarry Wentland 202c1a64ebdSMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 203c1a64ebdSMauro Rossi void dce60_link_encoder_construct( 204c1a64ebdSMauro Rossi struct dce110_link_encoder *enc110, 205c1a64ebdSMauro Rossi const struct encoder_init_data *init_data, 206c1a64ebdSMauro Rossi const struct encoder_feature_support *enc_features, 207c1a64ebdSMauro Rossi const struct dce110_link_enc_registers *link_regs, 208c1a64ebdSMauro Rossi const struct dce110_link_enc_aux_registers *aux_regs, 209c1a64ebdSMauro Rossi const struct dce110_link_enc_hpd_registers *hpd_regs); 210c1a64ebdSMauro Rossi #endif 211c1a64ebdSMauro Rossi 2124562236bSHarry Wentland bool dce110_link_encoder_validate_dvi_output( 2134562236bSHarry Wentland const struct dce110_link_encoder *enc110, 2144562236bSHarry Wentland enum signal_type connector_signal, 2154562236bSHarry Wentland enum signal_type signal, 2164562236bSHarry Wentland const struct dc_crtc_timing *crtc_timing); 2174562236bSHarry Wentland 2184562236bSHarry Wentland bool dce110_link_encoder_validate_rgb_output( 2194562236bSHarry Wentland const struct dce110_link_encoder *enc110, 2204562236bSHarry Wentland const struct dc_crtc_timing *crtc_timing); 2214562236bSHarry Wentland 2224562236bSHarry Wentland bool dce110_link_encoder_validate_dp_output( 2234562236bSHarry Wentland const struct dce110_link_encoder *enc110, 2244562236bSHarry Wentland const struct dc_crtc_timing *crtc_timing); 2254562236bSHarry Wentland 2264562236bSHarry Wentland bool dce110_link_encoder_validate_wireless_output( 2274562236bSHarry Wentland const struct dce110_link_encoder *enc110, 2284562236bSHarry Wentland const struct dc_crtc_timing *crtc_timing); 2294562236bSHarry Wentland 2304562236bSHarry Wentland bool dce110_link_encoder_validate_output_with_stream( 2314562236bSHarry Wentland struct link_encoder *enc, 2320971c40eSHarry Wentland const struct dc_stream_state *stream); 2334562236bSHarry Wentland 2344562236bSHarry Wentland /****************** HW programming ************************/ 2354562236bSHarry Wentland 2364562236bSHarry Wentland /* initialize HW */ /* why do we initialze aux in here? */ 2374562236bSHarry Wentland void dce110_link_encoder_hw_init(struct link_encoder *enc); 2384562236bSHarry Wentland 2394562236bSHarry Wentland void dce110_link_encoder_destroy(struct link_encoder **enc); 2404562236bSHarry Wentland 2414562236bSHarry Wentland /* program DIG_MODE in DIG_BE */ 2424562236bSHarry Wentland /* TODO can this be combined with enable_output? */ 2434562236bSHarry Wentland void dce110_link_encoder_setup( 2444562236bSHarry Wentland struct link_encoder *enc, 2454562236bSHarry Wentland enum signal_type signal); 2464562236bSHarry Wentland 2474562236bSHarry Wentland /* enables TMDS PHY output */ 2484562236bSHarry Wentland /* TODO: still need depth or just pass in adjusted pixel clock? */ 2494562236bSHarry Wentland void dce110_link_encoder_enable_tmds_output( 2504562236bSHarry Wentland struct link_encoder *enc, 2514562236bSHarry Wentland enum clock_source_id clock_source, 2524562236bSHarry Wentland enum dc_color_depth color_depth, 2533d5bae9eSHarry Wentland enum signal_type signal, 2544562236bSHarry Wentland uint32_t pixel_clock); 2554562236bSHarry Wentland 2564562236bSHarry Wentland /* enables DP PHY output */ 2574562236bSHarry Wentland void dce110_link_encoder_enable_dp_output( 2584562236bSHarry Wentland struct link_encoder *enc, 2594562236bSHarry Wentland const struct dc_link_settings *link_settings, 2604562236bSHarry Wentland enum clock_source_id clock_source); 2614562236bSHarry Wentland 2624562236bSHarry Wentland /* enables DP PHY output in MST mode */ 2634562236bSHarry Wentland void dce110_link_encoder_enable_dp_mst_output( 2644562236bSHarry Wentland struct link_encoder *enc, 2654562236bSHarry Wentland const struct dc_link_settings *link_settings, 2664562236bSHarry Wentland enum clock_source_id clock_source); 2674562236bSHarry Wentland 26811c3ee48SAlex Deucher /* enables LVDS PHY output */ 26911c3ee48SAlex Deucher void dce110_link_encoder_enable_lvds_output( 27011c3ee48SAlex Deucher struct link_encoder *enc, 27111c3ee48SAlex Deucher enum clock_source_id clock_source, 27211c3ee48SAlex Deucher uint32_t pixel_clock); 27311c3ee48SAlex Deucher 2744562236bSHarry Wentland /* disable PHY output */ 2754562236bSHarry Wentland void dce110_link_encoder_disable_output( 276069d418fSAndrew Jiang struct link_encoder *enc, 277069d418fSAndrew Jiang enum signal_type signal); 2784562236bSHarry Wentland 2794562236bSHarry Wentland /* set DP lane settings */ 2804562236bSHarry Wentland void dce110_link_encoder_dp_set_lane_settings( 2814562236bSHarry Wentland struct link_encoder *enc, 2828788e066SWenjing Liu const struct dc_link_settings *link_settings, 2838788e066SWenjing Liu const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 2844562236bSHarry Wentland 2854562236bSHarry Wentland void dce110_link_encoder_dp_set_phy_pattern( 2864562236bSHarry Wentland struct link_encoder *enc, 2874562236bSHarry Wentland const struct encoder_set_dp_phy_pattern_param *param); 2884562236bSHarry Wentland 2894562236bSHarry Wentland /* programs DP MST VC payload allocation */ 2904562236bSHarry Wentland void dce110_link_encoder_update_mst_stream_allocation_table( 2914562236bSHarry Wentland struct link_encoder *enc, 2924562236bSHarry Wentland const struct link_mst_stream_allocation_table *table); 2934562236bSHarry Wentland 2944562236bSHarry Wentland void dce110_link_encoder_connect_dig_be_to_fe( 2954562236bSHarry Wentland struct link_encoder *enc, 2964562236bSHarry Wentland enum engine_id engine, 2974562236bSHarry Wentland bool connect); 2984562236bSHarry Wentland 2996bdeff12SRodrigo Siqueira unsigned int dce110_get_dig_frontend(struct link_encoder *enc); 3006bdeff12SRodrigo Siqueira 3014562236bSHarry Wentland void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 3024562236bSHarry Wentland struct link_encoder *enc, 3034562236bSHarry Wentland uint32_t index); 3044562236bSHarry Wentland 3054562236bSHarry Wentland void dce110_link_encoder_enable_hpd(struct link_encoder *enc); 3064562236bSHarry Wentland 3074562236bSHarry Wentland void dce110_link_encoder_disable_hpd(struct link_encoder *enc); 3084562236bSHarry Wentland 3093548f073SAmy Zhang void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 3103548f073SAmy Zhang bool exit_link_training_required); 3113548f073SAmy Zhang 3123548f073SAmy Zhang void dce110_psr_program_secondary_packet(struct link_encoder *enc, 3133548f073SAmy Zhang unsigned int sdp_transmit_line_num_deadline); 3143548f073SAmy Zhang 315f0c0761bSYongqiang Sun bool dce110_is_dig_enabled(struct link_encoder *enc); 316f0c0761bSYongqiang Sun 3178ccf0e20SWenjing Liu void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, 3188ccf0e20SWenjing Liu struct dc_link_settings *link_settings); 3198ccf0e20SWenjing Liu 3204562236bSHarry Wentland #endif /* __DC_LINK_ENCODER__DCE110_H__ */ 321