1 /* Copyright 2012-17 Advanced Micro Devices, Inc.
2  *
3  * Permission is hereby granted, free of charge, to any person obtaining a
4  * copy of this software and associated documentation files (the "Software"),
5  * to deal in the Software without restriction, including without limitation
6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7  * and/or sell copies of the Software, and to permit persons to whom the
8  * Software is furnished to do so, subject to the following conditions:
9  *
10  * The above copyright notice and this permission notice shall be included in
11  * all copies or substantial portions of the Software.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19  * OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * Authors: AMD
22  *
23  */
24 #ifndef __DC_DWBC_DCN10_H__
25 #define __DC_DWBC_DCN10_H__
26 
27 #if defined(CONFIG_DRM_AMD_DC_DCN)
28 
29 /* DCN */
30 #define BASE_INNER(seg) \
31 	DCE_BASE__INST0_SEG ## seg
32 
33 #define BASE(seg) \
34 	BASE_INNER(seg)
35 
36 #define SR(reg_name)\
37 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
38 					mm ## reg_name
39 
40 #define SRI(reg_name, block, id)\
41 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
42 					mm ## block ## id ## _ ## reg_name
43 
44 
45 #define SRII(reg_name, block, id)\
46 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
47 					mm ## block ## id ## _ ## reg_name
48 
49 #define SF(reg_name, field_name, post_fix)\
50 	.field_name = reg_name ## __ ## field_name ## post_fix
51 
52 
53 #define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
54 	SRI(WB_ENABLE, CNV, inst),\
55 	SRI(WB_EC_CONFIG, CNV, inst),\
56 	SRI(CNV_MODE, CNV, inst),\
57 	SRI(WB_SOFT_RESET, CNV, inst),\
58 	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
59 	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
60 	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
61 	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
62 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
63 	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
64 	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
65 	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
66 	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
67 	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
68 	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
69 	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
70 	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
71 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
72 	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
73 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
74 	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
75 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
76 	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
77 	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
78 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
79 	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
80 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
81 	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
82 	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
83 	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
84 	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
85 
86 #define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
87 	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
88 	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
89 	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
90 	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
91 	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
92 	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
93 	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
94 	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
95 	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
96 	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
97 	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
98 	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
99 	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
100 	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
101 	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
102 	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
103 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
104 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
105 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
106 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
107 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
108 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
109 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
110 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
111 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
112 	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
113 	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
114 	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
115 	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
116 	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
117 	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
118 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
119 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
120 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
121 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
122 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
123 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
124 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
125 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
126 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
127 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
128 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
129 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
130 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
131 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
132 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
133 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
134 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
135 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
136 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
137 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
138 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
139 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
140 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
141 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
142 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
143 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
144 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
145 	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
146 	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
147 	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
148 	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)
149 
150 #define DWBC_REG_FIELD_LIST(type) \
151 	type WB_ENABLE;\
152 	type DISPCLK_R_WB_GATE_DIS;\
153 	type DISPCLK_G_WB_GATE_DIS;\
154 	type DISPCLK_G_WBSCL_GATE_DIS;\
155 	type WB_LB_LS_DIS;\
156 	type WB_LB_SD_DIS;\
157 	type WB_LUT_LS_DIS;\
158 	type CNV_WINDOW_CROP_EN;\
159 	type CNV_STEREO_TYPE;\
160 	type CNV_INTERLACED_MODE;\
161 	type CNV_EYE_SELECTION;\
162 	type CNV_STEREO_POLARITY;\
163 	type CNV_INTERLACED_FIELD_ORDER;\
164 	type CNV_STEREO_SPLIT;\
165 	type CNV_NEW_CONTENT;\
166 	type CNV_FRAME_CAPTURE_EN;\
167 	type WB_SOFT_RESET;\
168 	type MCIF_WB_BUFMGR_ENABLE;\
169 	type MCIF_WB_BUF_DUALSIZE_REQ;\
170 	type MCIF_WB_BUFMGR_SW_INT_EN;\
171 	type MCIF_WB_BUFMGR_SW_INT_ACK;\
172 	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
173 	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
174 	type MCIF_WB_BUFMGR_SW_LOCK;\
175 	type MCIF_WB_P_VMID;\
176 	type MCIF_WB_BUF_ADDR_FENCE_EN;\
177 	type MCIF_WB_BUF_LUMA_PITCH;\
178 	type MCIF_WB_BUF_CHROMA_PITCH;\
179 	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
180 	type MCIF_WB_TIME_PER_PIXEL;\
181 	type WM_CHANGE_ACK_FORCE_ON;\
182 	type MCIF_WB_CLI_WATERMARK_MASK;\
183 	type MCIF_WB_BUF_1_ADDR_Y;\
184 	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
185 	type MCIF_WB_BUF_1_ADDR_C;\
186 	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
187 	type MCIF_WB_BUF_2_ADDR_Y;\
188 	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
189 	type MCIF_WB_BUF_2_ADDR_C;\
190 	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
191 	type MCIF_WB_BUF_3_ADDR_Y;\
192 	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
193 	type MCIF_WB_BUF_3_ADDR_C;\
194 	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
195 	type MCIF_WB_BUF_4_ADDR_Y;\
196 	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
197 	type MCIF_WB_BUF_4_ADDR_C;\
198 	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
199 	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
200 	type MCIF_WB_BUFMGR_VCE_INT_EN;\
201 	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
202 	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
203 	type MCIF_WB_BUFMGR_VCE_LOCK;\
204 	type MCIF_WB_BUFMGR_SLICE_SIZE;\
205 	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
206 	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
207 	type NB_PSTATE_CHANGE_FORCE_ON;\
208 	type NB_PSTATE_ALLOW_FOR_URGENT;\
209 	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
210 	type MCIF_WB_CLI_WATERMARK;\
211 	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
212 	type MCIF_WB_PITCH_SIZE_WARMUP;\
213 	type MCIF_WB_BUF_LUMA_SIZE;\
214 	type MCIF_WB_BUF_CHROMA_SIZE;\
215 
216 struct dcn10_dwbc_registers {
217 	uint32_t WB_ENABLE;
218 	uint32_t WB_EC_CONFIG;
219 	uint32_t CNV_MODE;
220 	uint32_t WB_SOFT_RESET;
221 	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
222 	uint32_t MCIF_WB_BUF_PITCH;
223 	uint32_t MCIF_WB_ARBITRATION_CONTROL;
224 	uint32_t MCIF_WB_SCLK_CHANGE;
225 	uint32_t MCIF_WB_BUF_1_ADDR_Y;
226 	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
227 	uint32_t MCIF_WB_BUF_1_ADDR_C;
228 	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
229 	uint32_t MCIF_WB_BUF_2_ADDR_Y;
230 	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
231 	uint32_t MCIF_WB_BUF_2_ADDR_C;
232 	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
233 	uint32_t MCIF_WB_BUF_3_ADDR_Y;
234 	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
235 	uint32_t MCIF_WB_BUF_3_ADDR_C;
236 	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
237 	uint32_t MCIF_WB_BUF_4_ADDR_Y;
238 	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
239 	uint32_t MCIF_WB_BUF_4_ADDR_C;
240 	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
241 	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
242 	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
243 	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
244 	uint32_t MCIF_WB_WATERMARK;
245 	uint32_t MCIF_WB_WARM_UP_CNTL;
246 	uint32_t MCIF_WB_BUF_LUMA_SIZE;
247 	uint32_t MCIF_WB_BUF_CHROMA_SIZE;
248 };
249 struct dcn10_dwbc_mask {
250 	DWBC_REG_FIELD_LIST(uint32_t)
251 };
252 struct dcn10_dwbc_shift {
253 	DWBC_REG_FIELD_LIST(uint8_t)
254 };
255 struct dcn10_dwbc {
256 	struct dwbc base;
257 	const struct dcn10_dwbc_registers *dwbc_regs;
258 	const struct dcn10_dwbc_shift *dwbc_shift;
259 	const struct dcn10_dwbc_mask *dwbc_mask;
260 };
261 
262 void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
263 		struct dc_context *ctx,
264 		const struct dcn10_dwbc_registers *dwbc_regs,
265 		const struct dcn10_dwbc_shift *dwbc_shift,
266 		const struct dcn10_dwbc_mask *dwbc_mask,
267 		int inst);
268 
269 #endif
270 
271 #endif
272