1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HUBBUB_DCN10_H__ 27 #define __DC_HUBBUB_DCN10_H__ 28 29 #include "core_types.h" 30 #include "dchubbub.h" 31 32 #define TO_DCN10_HUBBUB(hubbub)\ 33 container_of(hubbub, struct dcn10_hubbub, base) 34 35 #define HUBBUB_REG_LIST_DCN_COMMON()\ 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 37 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ 38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ 40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ 42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ 44 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 45 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 46 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 47 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 48 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 49 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 50 SR(DCHUBBUB_TEST_DEBUG_DATA),\ 51 SR(DCHUBBUB_SOFT_RESET) 52 53 #define HUBBUB_VM_REG_LIST() \ 54 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ 55 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ 56 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ 57 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D) 58 59 #define HUBBUB_SR_WATERMARK_REG_LIST()\ 60 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ 61 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ 62 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ 63 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ 64 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ 65 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ 66 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ 67 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) 68 69 #define HUBBUB_REG_LIST_DCN10(id)\ 70 HUBBUB_REG_LIST_DCN_COMMON(), \ 71 HUBBUB_VM_REG_LIST(), \ 72 HUBBUB_SR_WATERMARK_REG_LIST(), \ 73 SR(DCHUBBUB_SDPIF_FB_TOP),\ 74 SR(DCHUBBUB_SDPIF_FB_BASE),\ 75 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 76 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 77 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 78 SR(DCHUBBUB_SDPIF_AGP_TOP) 79 80 struct dcn_hubbub_registers { 81 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; 82 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; 83 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; 84 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; 85 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; 86 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; 87 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; 88 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; 89 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; 90 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; 91 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; 92 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; 93 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; 94 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; 95 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; 96 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; 97 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; 98 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; 99 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; 100 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; 101 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; 102 uint32_t DCHUBBUB_ARB_SAT_LEVEL; 103 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; 104 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 105 uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; 106 uint32_t DCHUBBUB_TEST_DEBUG_INDEX; 107 uint32_t DCHUBBUB_TEST_DEBUG_DATA; 108 uint32_t DCHUBBUB_SDPIF_FB_TOP; 109 uint32_t DCHUBBUB_SDPIF_FB_BASE; 110 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 111 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 112 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 113 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 114 uint32_t DCHUBBUB_CRC_CTRL; 115 uint32_t DCHUBBUB_SOFT_RESET; 116 uint32_t DCN_VM_FB_LOCATION_BASE; 117 uint32_t DCN_VM_FB_LOCATION_TOP; 118 uint32_t DCN_VM_FB_OFFSET; 119 uint32_t DCN_VM_AGP_BOT; 120 uint32_t DCN_VM_AGP_TOP; 121 uint32_t DCN_VM_AGP_BASE; 122 uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; 123 uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; 124 uint32_t DCN_VM_FAULT_ADDR_MSB; 125 uint32_t DCN_VM_FAULT_ADDR_LSB; 126 uint32_t DCN_VM_FAULT_CNTL; 127 uint32_t DCN_VM_FAULT_STATUS; 128 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; 129 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; 130 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; 131 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; 132 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; 133 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; 134 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; 135 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; 136 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; 137 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; 138 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; 139 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; 140 uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; 141 uint32_t DCHVM_CTRL0; 142 uint32_t DCHVM_MEM_CTRL; 143 uint32_t DCHVM_CLK_CTRL; 144 uint32_t DCHVM_RIOMMU_CTRL0; 145 uint32_t DCHVM_RIOMMU_STAT0; 146 uint32_t DCHUBBUB_DET0_CTRL; 147 uint32_t DCHUBBUB_DET1_CTRL; 148 uint32_t DCHUBBUB_DET2_CTRL; 149 uint32_t DCHUBBUB_DET3_CTRL; 150 uint32_t DCHUBBUB_COMPBUF_CTRL; 151 uint32_t COMPBUF_RESERVED_SPACE; 152 uint32_t DCHUBBUB_DEBUG_CTRL_0; 153 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A; 154 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A; 155 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B; 156 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B; 157 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C; 158 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C; 159 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D; 160 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D; 161 uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL; 162 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A; 163 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B; 164 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C; 165 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D; 166 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A; 167 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B; 168 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C; 169 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D; 170 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A; 171 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B; 172 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C; 173 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D; 174 uint32_t DCHUBBUB_ARB_MALL_CNTL; 175 uint32_t SDPIF_REQUEST_RATE_LIMIT; 176 uint32_t DCHUBBUB_SDPIF_CFG0; 177 uint32_t DCHUBBUB_SDPIF_CFG1; 178 uint32_t DCHUBBUB_CLOCK_CNTL; 179 uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL; 180 uint32_t DCHUBBUB_ARB_QOS_FORCE; 181 }; 182 183 #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ 184 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\ 185 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\ 186 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\ 187 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\ 188 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\ 189 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\ 190 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\ 191 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\ 192 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\ 193 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;\ 194 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;\ 195 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;\ 196 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\ 197 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\ 198 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\ 199 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;\ 200 type MALL_PREFETCH_COMPLETE;\ 201 type MALL_IN_USE 202 203 #define HUBBUB_REG_FIELD_LIST_DCN35(type) \ 204 type DCHUBBUB_FGCG_REP_DIS;\ 205 type DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE 206 207 /* set field name */ 208 #define HUBBUB_SF(reg_name, field_name, post_fix)\ 209 .field_name = reg_name ## __ ## field_name ## post_fix 210 211 #define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\ 212 HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 213 HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ 214 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ 215 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ 216 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ 217 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ 218 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ 219 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ 220 HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ 221 HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ 222 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ 223 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ 224 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ 225 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ 226 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ 227 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ 228 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ 229 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh) 230 231 #define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \ 232 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ 233 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ 234 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ 235 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ 236 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ 237 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ 238 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ 239 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh) 240 241 #define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\ 242 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ 243 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ 244 HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ 245 HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 246 HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 247 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 248 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 249 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh) 250 251 #define DCN_HUBBUB_REG_FIELD_LIST(type) \ 252 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 253 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ 254 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ 255 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ 256 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ 257 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\ 258 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\ 259 type DCHUBBUB_ARB_SAT_LEVEL;\ 260 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ 261 type DCHUBBUB_GLOBAL_TIMER_REFDIV;\ 262 type DCHUBBUB_GLOBAL_SOFT_RESET; \ 263 type SDPIF_FB_TOP;\ 264 type SDPIF_FB_BASE;\ 265 type SDPIF_FB_OFFSET;\ 266 type SDPIF_AGP_BASE;\ 267 type SDPIF_AGP_BOT;\ 268 type SDPIF_AGP_TOP;\ 269 type FB_BASE;\ 270 type FB_TOP;\ 271 type FB_OFFSET;\ 272 type AGP_BOT;\ 273 type AGP_TOP;\ 274 type AGP_BASE;\ 275 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\ 276 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\ 277 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\ 278 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\ 279 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ 280 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ 281 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ 282 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ 283 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ 284 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ 285 type DCN_VM_FAULT_ADDR_MSB;\ 286 type DCN_VM_FAULT_ADDR_LSB;\ 287 type DCN_VM_ERROR_STATUS_CLEAR;\ 288 type DCN_VM_ERROR_STATUS_MODE;\ 289 type DCN_VM_ERROR_INTERRUPT_ENABLE;\ 290 type DCN_VM_RANGE_FAULT_DISABLE;\ 291 type DCN_VM_PRQ_FAULT_DISABLE;\ 292 type DCN_VM_ERROR_STATUS;\ 293 type DCN_VM_ERROR_VMID;\ 294 type DCN_VM_ERROR_TABLE_LEVEL;\ 295 type DCN_VM_ERROR_PIPE;\ 296 type DCN_VM_ERROR_INTERRUPT_STATUS 297 298 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ 299 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ 300 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\ 301 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\ 302 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\ 303 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\ 304 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\ 305 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ 306 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 307 308 #define HUBBUB_HVM_REG_FIELD_LIST(type) \ 309 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ 310 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ 311 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\ 312 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\ 313 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\ 314 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\ 315 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\ 316 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\ 317 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\ 318 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\ 319 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\ 320 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\ 321 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\ 322 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ 323 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ 324 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ 325 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ 326 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\ 327 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\ 328 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\ 329 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\ 330 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\ 331 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\ 332 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\ 333 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\ 334 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\ 335 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\ 336 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\ 337 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\ 338 type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\ 339 type HOSTVM_INIT_REQ; \ 340 type HVM_GPUVMRET_PWR_REQ_DIS; \ 341 type HVM_GPUVMRET_FORCE_REQ; \ 342 type HVM_GPUVMRET_POWER_STATUS; \ 343 type HVM_DISPCLK_R_GATE_DIS; \ 344 type HVM_DISPCLK_G_GATE_DIS; \ 345 type HVM_DCFCLK_R_GATE_DIS; \ 346 type HVM_DCFCLK_G_GATE_DIS; \ 347 type TR_REQ_REQCLKREQ_MODE; \ 348 type TW_RSP_COMPCLKREQ_MODE; \ 349 type HOSTVM_PREFETCH_REQ; \ 350 type HOSTVM_POWERSTATUS; \ 351 type RIOMMU_ACTIVE; \ 352 type HOSTVM_PREFETCH_DONE 353 354 #define HUBBUB_RET_REG_FIELD_LIST(type) \ 355 type DET_DEPTH;\ 356 type DET0_SIZE;\ 357 type DET1_SIZE;\ 358 type DET2_SIZE;\ 359 type DET3_SIZE;\ 360 type DET0_SIZE_CURRENT;\ 361 type DET1_SIZE_CURRENT;\ 362 type DET2_SIZE_CURRENT;\ 363 type DET3_SIZE_CURRENT;\ 364 type COMPBUF_SIZE;\ 365 type COMPBUF_SIZE_CURRENT;\ 366 type CONFIG_ERROR;\ 367 type COMPBUF_RESERVED_SPACE_64B;\ 368 type COMPBUF_RESERVED_SPACE_ZS;\ 369 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\ 370 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\ 371 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\ 372 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\ 373 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\ 374 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\ 375 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\ 376 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;\ 377 type SDPIF_REQUEST_RATE_LIMIT;\ 378 type DISPCLK_R_DCHUBBUB_GATE_DIS;\ 379 type DCFCLK_R_DCHUBBUB_GATE_DIS;\ 380 type SDPIF_MAX_NUM_OUTSTANDING;\ 381 type DCHUBBUB_ARB_MAX_REQ_OUTSTAND;\ 382 type SDPIF_PORT_CONTROL;\ 383 type DET_MEM_PWR_LS_MODE 384 385 386 struct dcn_hubbub_shift { 387 DCN_HUBBUB_REG_FIELD_LIST(uint8_t); 388 HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); 389 HUBBUB_HVM_REG_FIELD_LIST(uint8_t); 390 HUBBUB_RET_REG_FIELD_LIST(uint8_t); 391 HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); 392 HUBBUB_REG_FIELD_LIST_DCN35(uint8_t); 393 }; 394 395 struct dcn_hubbub_mask { 396 DCN_HUBBUB_REG_FIELD_LIST(uint32_t); 397 HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); 398 HUBBUB_HVM_REG_FIELD_LIST(uint32_t); 399 HUBBUB_RET_REG_FIELD_LIST(uint32_t); 400 HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); 401 HUBBUB_REG_FIELD_LIST_DCN35(uint32_t); 402 }; 403 404 struct dc; 405 406 struct dcn10_hubbub { 407 struct hubbub base; 408 const struct dcn_hubbub_registers *regs; 409 const struct dcn_hubbub_shift *shifts; 410 const struct dcn_hubbub_mask *masks; 411 unsigned int debug_test_index_pstate; 412 struct dcn_watermark_set watermarks; 413 }; 414 415 void hubbub1_update_dchub( 416 struct hubbub *hubbub, 417 struct dchub_init_data *dh_data); 418 419 bool hubbub1_verify_allow_pstate_change_high( 420 struct hubbub *hubbub); 421 422 void hubbub1_wm_change_req_wa(struct hubbub *hubbub); 423 424 bool hubbub1_program_watermarks( 425 struct hubbub *hubbub, 426 struct dcn_watermark_set *watermarks, 427 unsigned int refclk_mhz, 428 bool safe_to_lower); 429 430 void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); 431 432 bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); 433 434 void hubbub1_toggle_watermark_change_req( 435 struct hubbub *hubbub); 436 437 void hubbub1_wm_read_state(struct hubbub *hubbub, 438 struct dcn_hubbub_wm *wm); 439 440 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset); 441 void hubbub1_construct(struct hubbub *hubbub, 442 struct dc_context *ctx, 443 const struct dcn_hubbub_registers *hubbub_regs, 444 const struct dcn_hubbub_shift *hubbub_shift, 445 const struct dcn_hubbub_mask *hubbub_mask); 446 447 bool hubbub1_program_urgent_watermarks( 448 struct hubbub *hubbub, 449 struct dcn_watermark_set *watermarks, 450 unsigned int refclk_mhz, 451 bool safe_to_lower); 452 bool hubbub1_program_stutter_watermarks( 453 struct hubbub *hubbub, 454 struct dcn_watermark_set *watermarks, 455 unsigned int refclk_mhz, 456 bool safe_to_lower); 457 bool hubbub1_program_pstate_watermarks( 458 struct hubbub *hubbub, 459 struct dcn_watermark_set *watermarks, 460 unsigned int refclk_mhz, 461 bool safe_to_lower); 462 463 #endif 464