1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dc_bios_types.h" 29 #include "dcn10_stream_encoder.h" 30 #include "reg_helper.h" 31 #include "hw_shared.h" 32 33 #define DC_LOGGER \ 34 enc1->base.ctx->logger 35 36 37 #define REG(reg)\ 38 (enc1->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 enc1->se_shift->field_name, enc1->se_mask->field_name 43 44 #define VBI_LINE_0 0 45 #define DP_BLANK_MAX_RETRY 20 46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 47 48 49 enum { 50 DP_MST_UPDATE_MAX_RETRY = 50 51 }; 52 53 #define CTX \ 54 enc1->base.ctx 55 56 void enc1_update_generic_info_packet( 57 struct dcn10_stream_encoder *enc1, 58 uint32_t packet_index, 59 const struct dc_info_packet *info_packet) 60 { 61 uint32_t regval; 62 /* TODOFPGA Figure out a proper number for max_retries polling for lock 63 * use 50 for now. 64 */ 65 uint32_t max_retries = 50; 66 67 /*we need turn on clock before programming AFMT block*/ 68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 69 70 if (packet_index >= 8) 71 ASSERT(0); 72 73 /* poll dig_update_lock is not locked -> asic internal signal 74 * assume otg master lock will unlock it 75 */ 76 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 77 0, 10, max_retries);*/ 78 79 /* check if HW reading GSP memory */ 80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 81 0, 10, max_retries); 82 83 /* HW does is not reading GSP memory not reading too long -> 84 * something wrong. clear GPS memory access and notify? 85 * hw SW is writing to GSP memory 86 */ 87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 88 89 /* choose which generic packet to use */ 90 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 91 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 92 AFMT_GENERIC_INDEX, packet_index); 93 94 /* write generic packet header 95 * (4th byte is for GENERIC0 only) 96 */ 97 REG_SET_4(AFMT_GENERIC_HDR, 0, 98 AFMT_GENERIC_HB0, info_packet->hb0, 99 AFMT_GENERIC_HB1, info_packet->hb1, 100 AFMT_GENERIC_HB2, info_packet->hb2, 101 AFMT_GENERIC_HB3, info_packet->hb3); 102 103 /* write generic packet contents 104 * (we never use last 4 bytes) 105 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 106 */ 107 { 108 const uint32_t *content = 109 (const uint32_t *) &info_packet->sb[0]; 110 111 REG_WRITE(AFMT_GENERIC_0, *content++); 112 REG_WRITE(AFMT_GENERIC_1, *content++); 113 REG_WRITE(AFMT_GENERIC_2, *content++); 114 REG_WRITE(AFMT_GENERIC_3, *content++); 115 REG_WRITE(AFMT_GENERIC_4, *content++); 116 REG_WRITE(AFMT_GENERIC_5, *content++); 117 REG_WRITE(AFMT_GENERIC_6, *content++); 118 REG_WRITE(AFMT_GENERIC_7, *content); 119 } 120 121 switch (packet_index) { 122 case 0: 123 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 124 AFMT_GENERIC0_FRAME_UPDATE, 1); 125 break; 126 case 1: 127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 128 AFMT_GENERIC1_FRAME_UPDATE, 1); 129 break; 130 case 2: 131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 132 AFMT_GENERIC2_FRAME_UPDATE, 1); 133 break; 134 case 3: 135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 136 AFMT_GENERIC3_FRAME_UPDATE, 1); 137 break; 138 case 4: 139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 140 AFMT_GENERIC4_FRAME_UPDATE, 1); 141 break; 142 case 5: 143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 144 AFMT_GENERIC5_FRAME_UPDATE, 1); 145 break; 146 case 6: 147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 148 AFMT_GENERIC6_FRAME_UPDATE, 1); 149 break; 150 case 7: 151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 152 AFMT_GENERIC7_FRAME_UPDATE, 1); 153 break; 154 default: 155 break; 156 } 157 } 158 159 static void enc1_update_hdmi_info_packet( 160 struct dcn10_stream_encoder *enc1, 161 uint32_t packet_index, 162 const struct dc_info_packet *info_packet) 163 { 164 uint32_t cont, send, line; 165 166 if (info_packet->valid) { 167 enc1_update_generic_info_packet( 168 enc1, 169 packet_index, 170 info_packet); 171 172 /* enable transmission of packet(s) - 173 * packet transmission begins on the next frame 174 */ 175 cont = 1; 176 /* send packet(s) every frame */ 177 send = 1; 178 /* select line number to send packets on */ 179 line = 2; 180 } else { 181 cont = 0; 182 send = 0; 183 line = 0; 184 } 185 186 /* choose which generic packet control to use */ 187 switch (packet_index) { 188 case 0: 189 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 190 HDMI_GENERIC0_CONT, cont, 191 HDMI_GENERIC0_SEND, send, 192 HDMI_GENERIC0_LINE, line); 193 break; 194 case 1: 195 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 196 HDMI_GENERIC1_CONT, cont, 197 HDMI_GENERIC1_SEND, send, 198 HDMI_GENERIC1_LINE, line); 199 break; 200 case 2: 201 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 202 HDMI_GENERIC0_CONT, cont, 203 HDMI_GENERIC0_SEND, send, 204 HDMI_GENERIC0_LINE, line); 205 break; 206 case 3: 207 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 208 HDMI_GENERIC1_CONT, cont, 209 HDMI_GENERIC1_SEND, send, 210 HDMI_GENERIC1_LINE, line); 211 break; 212 case 4: 213 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 214 HDMI_GENERIC0_CONT, cont, 215 HDMI_GENERIC0_SEND, send, 216 HDMI_GENERIC0_LINE, line); 217 break; 218 case 5: 219 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 220 HDMI_GENERIC1_CONT, cont, 221 HDMI_GENERIC1_SEND, send, 222 HDMI_GENERIC1_LINE, line); 223 break; 224 case 6: 225 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 226 HDMI_GENERIC0_CONT, cont, 227 HDMI_GENERIC0_SEND, send, 228 HDMI_GENERIC0_LINE, line); 229 break; 230 case 7: 231 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 232 HDMI_GENERIC1_CONT, cont, 233 HDMI_GENERIC1_SEND, send, 234 HDMI_GENERIC1_LINE, line); 235 break; 236 default: 237 /* invalid HW packet index */ 238 DC_LOG_WARNING( 239 "Invalid HW packet index: %s()\n", 240 __func__); 241 return; 242 } 243 } 244 245 /* setup stream encoder in dp mode */ 246 void enc1_stream_encoder_dp_set_stream_attribute( 247 struct stream_encoder *enc, 248 struct dc_crtc_timing *crtc_timing, 249 enum dc_color_space output_color_space, 250 uint32_t enable_sdp_splitting) 251 { 252 uint32_t h_active_start; 253 uint32_t v_active_start; 254 uint32_t misc0 = 0; 255 uint32_t misc1 = 0; 256 uint32_t h_blank; 257 uint32_t h_back_porch; 258 uint8_t synchronous_clock = 0; /* asynchronous mode */ 259 uint8_t colorimetry_bpc; 260 uint8_t dynamic_range_rgb = 0; /*full range*/ 261 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 262 uint8_t dp_pixel_encoding = 0; 263 uint8_t dp_component_depth = 0; 264 265 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 266 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 267 268 if (hw_crtc_timing.flags.INTERLACE) { 269 /*the input timing is in VESA spec format with Interlace flag =1*/ 270 hw_crtc_timing.v_total /= 2; 271 hw_crtc_timing.v_border_top /= 2; 272 hw_crtc_timing.v_addressable /= 2; 273 hw_crtc_timing.v_border_bottom /= 2; 274 hw_crtc_timing.v_front_porch /= 2; 275 hw_crtc_timing.v_sync_width /= 2; 276 } 277 278 279 /* set pixel encoding */ 280 switch (hw_crtc_timing.pixel_encoding) { 281 case PIXEL_ENCODING_YCBCR422: 282 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; 283 break; 284 case PIXEL_ENCODING_YCBCR444: 285 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; 286 287 if (hw_crtc_timing.flags.Y_ONLY) 288 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 289 /* HW testing only, no use case yet. 290 * Color depth of Y-only could be 291 * 8, 10, 12, 16 bits 292 */ 293 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; 294 295 /* Note: DP_MSA_MISC1 bit 7 is the indicator 296 * of Y-only mode. 297 * This bit is set in HW if register 298 * DP_PIXEL_ENCODING is programmed to 0x4 299 */ 300 break; 301 case PIXEL_ENCODING_YCBCR420: 302 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; 303 break; 304 default: 305 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; 306 break; 307 } 308 309 misc1 = REG_READ(DP_MSA_MISC); 310 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. 311 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the 312 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, 313 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). 314 */ 315 if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) || 316 (output_color_space == COLOR_SPACE_2020_YCBCR) || 317 (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) || 318 (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)) 319 misc1 = misc1 | 0x40; 320 else 321 misc1 = misc1 & ~0x40; 322 323 /* set color depth */ 324 switch (hw_crtc_timing.display_color_depth) { 325 case COLOR_DEPTH_666: 326 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 327 break; 328 case COLOR_DEPTH_888: 329 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; 330 break; 331 case COLOR_DEPTH_101010: 332 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; 333 break; 334 case COLOR_DEPTH_121212: 335 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; 336 break; 337 case COLOR_DEPTH_161616: 338 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; 339 break; 340 default: 341 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 342 break; 343 } 344 345 /* Set DP pixel encoding and component depth */ 346 REG_UPDATE_2(DP_PIXEL_FORMAT, 347 DP_PIXEL_ENCODING, dp_pixel_encoding, 348 DP_COMPONENT_DEPTH, dp_component_depth); 349 350 /* set dynamic range and YCbCr range */ 351 352 switch (hw_crtc_timing.display_color_depth) { 353 case COLOR_DEPTH_666: 354 colorimetry_bpc = 0; 355 break; 356 case COLOR_DEPTH_888: 357 colorimetry_bpc = 1; 358 break; 359 case COLOR_DEPTH_101010: 360 colorimetry_bpc = 2; 361 break; 362 case COLOR_DEPTH_121212: 363 colorimetry_bpc = 3; 364 break; 365 default: 366 colorimetry_bpc = 0; 367 break; 368 } 369 370 misc0 = misc0 | synchronous_clock; 371 misc0 = colorimetry_bpc << 5; 372 373 switch (output_color_space) { 374 case COLOR_SPACE_SRGB: 375 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 376 dynamic_range_rgb = 0; /*full range*/ 377 break; 378 case COLOR_SPACE_SRGB_LIMITED: 379 misc0 = misc0 | 0x8; /* bit3=1 */ 380 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 381 dynamic_range_rgb = 1; /*limited range*/ 382 break; 383 case COLOR_SPACE_YCBCR601: 384 case COLOR_SPACE_YCBCR601_LIMITED: 385 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 386 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 387 dynamic_range_ycbcr = 0; /*bt601*/ 388 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 389 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 390 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 391 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 392 break; 393 case COLOR_SPACE_YCBCR709: 394 case COLOR_SPACE_YCBCR709_LIMITED: 395 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 396 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 397 dynamic_range_ycbcr = 1; /*bt709*/ 398 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 399 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 400 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 401 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 402 break; 403 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 404 dynamic_range_rgb = 1; /*limited range*/ 405 break; 406 case COLOR_SPACE_2020_RGB_FULLRANGE: 407 case COLOR_SPACE_2020_YCBCR: 408 case COLOR_SPACE_XR_RGB: 409 case COLOR_SPACE_MSREF_SCRGB: 410 case COLOR_SPACE_ADOBERGB: 411 case COLOR_SPACE_DCIP3: 412 case COLOR_SPACE_XV_YCC_709: 413 case COLOR_SPACE_XV_YCC_601: 414 case COLOR_SPACE_DISPLAYNATIVE: 415 case COLOR_SPACE_DOLBYVISION: 416 case COLOR_SPACE_APPCTRL: 417 case COLOR_SPACE_CUSTOMPOINTS: 418 case COLOR_SPACE_UNKNOWN: 419 case COLOR_SPACE_YCBCR709_BLACK: 420 /* do nothing */ 421 break; 422 } 423 424 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 425 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 426 427 /* dcn new register 428 * dc_crtc_timing is vesa dmt struct. data from edid 429 */ 430 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 431 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 432 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 433 434 /* calculate from vesa timing parameters 435 * h_active_start related to leading edge of sync 436 */ 437 438 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 439 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 440 441 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 442 hw_crtc_timing.h_sync_width; 443 444 /* start at beginning of left border */ 445 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 446 447 448 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 449 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 450 hw_crtc_timing.v_front_porch; 451 452 453 /* start at beginning of left border */ 454 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 455 DP_MSA_HSTART, h_active_start, 456 DP_MSA_VSTART, v_active_start); 457 458 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 459 DP_MSA_HSYNCWIDTH, 460 hw_crtc_timing.h_sync_width, 461 DP_MSA_HSYNCPOLARITY, 462 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 463 DP_MSA_VSYNCWIDTH, 464 hw_crtc_timing.v_sync_width, 465 DP_MSA_VSYNCPOLARITY, 466 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 467 468 /* HWDITH include border or overscan */ 469 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 470 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 471 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 472 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 473 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 474 } 475 476 void enc1_stream_encoder_set_stream_attribute_helper( 477 struct dcn10_stream_encoder *enc1, 478 struct dc_crtc_timing *crtc_timing) 479 { 480 switch (crtc_timing->pixel_encoding) { 481 case PIXEL_ENCODING_YCBCR422: 482 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 483 break; 484 default: 485 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 486 break; 487 } 488 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 489 } 490 491 /* setup stream encoder in hdmi mode */ 492 void enc1_stream_encoder_hdmi_set_stream_attribute( 493 struct stream_encoder *enc, 494 struct dc_crtc_timing *crtc_timing, 495 int actual_pix_clk_khz, 496 bool enable_audio) 497 { 498 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 499 struct bp_encoder_control cntl = {0}; 500 501 cntl.action = ENCODER_CONTROL_SETUP; 502 cntl.engine_id = enc1->base.id; 503 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 504 cntl.enable_dp_audio = enable_audio; 505 cntl.pixel_clock = actual_pix_clk_khz; 506 cntl.lanes_number = LANE_COUNT_FOUR; 507 508 if (enc1->base.bp->funcs->encoder_control( 509 enc1->base.bp, &cntl) != BP_RESULT_OK) 510 return; 511 512 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 513 514 /* setup HDMI engine */ 515 REG_UPDATE_6(HDMI_CONTROL, 516 HDMI_PACKET_GEN_VERSION, 1, 517 HDMI_KEEPOUT_MODE, 1, 518 HDMI_DEEP_COLOR_ENABLE, 0, 519 HDMI_DATA_SCRAMBLE_EN, 0, 520 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 521 HDMI_CLOCK_CHANNEL_RATE, 0); 522 523 524 switch (crtc_timing->display_color_depth) { 525 case COLOR_DEPTH_888: 526 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 527 break; 528 case COLOR_DEPTH_101010: 529 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 530 REG_UPDATE_2(HDMI_CONTROL, 531 HDMI_DEEP_COLOR_DEPTH, 1, 532 HDMI_DEEP_COLOR_ENABLE, 0); 533 } else { 534 REG_UPDATE_2(HDMI_CONTROL, 535 HDMI_DEEP_COLOR_DEPTH, 1, 536 HDMI_DEEP_COLOR_ENABLE, 1); 537 } 538 break; 539 case COLOR_DEPTH_121212: 540 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 541 REG_UPDATE_2(HDMI_CONTROL, 542 HDMI_DEEP_COLOR_DEPTH, 2, 543 HDMI_DEEP_COLOR_ENABLE, 0); 544 } else { 545 REG_UPDATE_2(HDMI_CONTROL, 546 HDMI_DEEP_COLOR_DEPTH, 2, 547 HDMI_DEEP_COLOR_ENABLE, 1); 548 } 549 break; 550 case COLOR_DEPTH_161616: 551 REG_UPDATE_2(HDMI_CONTROL, 552 HDMI_DEEP_COLOR_DEPTH, 3, 553 HDMI_DEEP_COLOR_ENABLE, 1); 554 break; 555 default: 556 break; 557 } 558 559 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 560 /* enable HDMI data scrambler 561 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 562 * Clock channel frequency is 1/4 of character rate. 563 */ 564 REG_UPDATE_2(HDMI_CONTROL, 565 HDMI_DATA_SCRAMBLE_EN, 1, 566 HDMI_CLOCK_CHANNEL_RATE, 1); 567 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 568 569 /* TODO: New feature for DCE11, still need to implement */ 570 571 /* enable HDMI data scrambler 572 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 573 * Clock channel frequency is the same 574 * as character rate 575 */ 576 REG_UPDATE_2(HDMI_CONTROL, 577 HDMI_DATA_SCRAMBLE_EN, 1, 578 HDMI_CLOCK_CHANNEL_RATE, 0); 579 } 580 581 582 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 583 HDMI_GC_CONT, 1, 584 HDMI_GC_SEND, 1, 585 HDMI_NULL_SEND, 1); 586 587 /* following belongs to audio */ 588 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 589 590 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 591 592 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 593 VBI_LINE_0 + 2); 594 595 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 596 } 597 598 /* setup stream encoder in dvi mode */ 599 void enc1_stream_encoder_dvi_set_stream_attribute( 600 struct stream_encoder *enc, 601 struct dc_crtc_timing *crtc_timing, 602 bool is_dual_link) 603 { 604 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 605 struct bp_encoder_control cntl = {0}; 606 607 cntl.action = ENCODER_CONTROL_SETUP; 608 cntl.engine_id = enc1->base.id; 609 cntl.signal = is_dual_link ? 610 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 611 cntl.enable_dp_audio = false; 612 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 613 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 614 615 if (enc1->base.bp->funcs->encoder_control( 616 enc1->base.bp, &cntl) != BP_RESULT_OK) 617 return; 618 619 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 620 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 621 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 622 } 623 624 void enc1_stream_encoder_set_mst_bandwidth( 625 struct stream_encoder *enc, 626 struct fixed31_32 avg_time_slots_per_mtp) 627 { 628 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 629 uint32_t x = dc_fixpt_floor( 630 avg_time_slots_per_mtp); 631 uint32_t y = dc_fixpt_ceil( 632 dc_fixpt_shl( 633 dc_fixpt_sub_int( 634 avg_time_slots_per_mtp, 635 x), 636 26)); 637 638 REG_SET_2(DP_MSE_RATE_CNTL, 0, 639 DP_MSE_RATE_X, x, 640 DP_MSE_RATE_Y, y); 641 642 /* wait for update to be completed on the link */ 643 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 644 /* is reset to 0 (not pending) */ 645 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 646 0, 647 10, DP_MST_UPDATE_MAX_RETRY); 648 } 649 650 static void enc1_stream_encoder_update_hdmi_info_packets( 651 struct stream_encoder *enc, 652 const struct encoder_info_frame *info_frame) 653 { 654 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 655 656 /* for bring up, disable dp double TODO */ 657 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 658 659 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 660 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 661 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 662 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 663 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 664 } 665 666 static void enc1_stream_encoder_stop_hdmi_info_packets( 667 struct stream_encoder *enc) 668 { 669 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 670 671 /* stop generic packets 0 & 1 on HDMI */ 672 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 673 HDMI_GENERIC1_CONT, 0, 674 HDMI_GENERIC1_LINE, 0, 675 HDMI_GENERIC1_SEND, 0, 676 HDMI_GENERIC0_CONT, 0, 677 HDMI_GENERIC0_LINE, 0, 678 HDMI_GENERIC0_SEND, 0); 679 680 /* stop generic packets 2 & 3 on HDMI */ 681 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 682 HDMI_GENERIC0_CONT, 0, 683 HDMI_GENERIC0_LINE, 0, 684 HDMI_GENERIC0_SEND, 0, 685 HDMI_GENERIC1_CONT, 0, 686 HDMI_GENERIC1_LINE, 0, 687 HDMI_GENERIC1_SEND, 0); 688 689 /* stop generic packets 2 & 3 on HDMI */ 690 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 691 HDMI_GENERIC0_CONT, 0, 692 HDMI_GENERIC0_LINE, 0, 693 HDMI_GENERIC0_SEND, 0, 694 HDMI_GENERIC1_CONT, 0, 695 HDMI_GENERIC1_LINE, 0, 696 HDMI_GENERIC1_SEND, 0); 697 698 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 699 HDMI_GENERIC0_CONT, 0, 700 HDMI_GENERIC0_LINE, 0, 701 HDMI_GENERIC0_SEND, 0, 702 HDMI_GENERIC1_CONT, 0, 703 HDMI_GENERIC1_LINE, 0, 704 HDMI_GENERIC1_SEND, 0); 705 } 706 707 void enc1_stream_encoder_update_dp_info_packets( 708 struct stream_encoder *enc, 709 const struct encoder_info_frame *info_frame) 710 { 711 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 712 uint32_t value = 0; 713 714 if (info_frame->vsc.valid) 715 enc1_update_generic_info_packet( 716 enc1, 717 0, /* packetIndex */ 718 &info_frame->vsc); 719 720 if (info_frame->spd.valid) 721 enc1_update_generic_info_packet( 722 enc1, 723 2, /* packetIndex */ 724 &info_frame->spd); 725 726 if (info_frame->hdrsmd.valid) 727 enc1_update_generic_info_packet( 728 enc1, 729 3, /* packetIndex */ 730 &info_frame->hdrsmd); 731 732 /* packetIndex 4 is used for send immediate sdp message, and please 733 * use other packetIndex (such as 5,6) for other info packet 734 */ 735 736 /* enable/disable transmission of packet(s). 737 * If enabled, packet transmission begins on the next frame 738 */ 739 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 740 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 741 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 742 743 744 /* This bit is the master enable bit. 745 * When enabling secondary stream engine, 746 * this master bit must also be set. 747 * This register shared with audio info frame. 748 * Therefore we need to enable master bit 749 * if at least on of the fields is not 0 750 */ 751 value = REG_READ(DP_SEC_CNTL); 752 if (value) 753 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 754 } 755 756 void enc1_stream_encoder_send_immediate_sdp_message( 757 struct stream_encoder *enc, 758 const uint8_t *custom_sdp_message, 759 unsigned int sdp_message_size) 760 { 761 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 762 uint32_t value = 0; 763 764 /* TODOFPGA Figure out a proper number for max_retries polling for lock 765 * use 50 for now. 766 */ 767 uint32_t max_retries = 50; 768 769 /* check if GSP4 is transmitted */ 770 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, 771 0, 10, max_retries); 772 773 /* disable GSP4 transmitting */ 774 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); 775 776 /* transmit GSP4 at the earliest time in a frame */ 777 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); 778 779 /*we need turn on clock before programming AFMT block*/ 780 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 781 782 /* check if HW reading GSP memory */ 783 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 784 0, 10, max_retries); 785 786 /* HW does is not reading GSP memory not reading too long -> 787 * something wrong. clear GPS memory access and notify? 788 * hw SW is writing to GSP memory 789 */ 790 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 791 792 /* use generic packet 4 for immediate sdp message */ 793 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 794 AFMT_GENERIC_INDEX, 4); 795 796 /* write generic packet header 797 * (4th byte is for GENERIC0 only) 798 */ 799 REG_SET_4(AFMT_GENERIC_HDR, 0, 800 AFMT_GENERIC_HB0, custom_sdp_message[0], 801 AFMT_GENERIC_HB1, custom_sdp_message[1], 802 AFMT_GENERIC_HB2, custom_sdp_message[2], 803 AFMT_GENERIC_HB3, custom_sdp_message[3]); 804 805 /* write generic packet contents 806 * (we never use last 4 bytes) 807 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 808 */ 809 { 810 const uint32_t *content = 811 (const uint32_t *) &custom_sdp_message[4]; 812 813 REG_WRITE(AFMT_GENERIC_0, *content++); 814 REG_WRITE(AFMT_GENERIC_1, *content++); 815 REG_WRITE(AFMT_GENERIC_2, *content++); 816 REG_WRITE(AFMT_GENERIC_3, *content++); 817 REG_WRITE(AFMT_GENERIC_4, *content++); 818 REG_WRITE(AFMT_GENERIC_5, *content++); 819 REG_WRITE(AFMT_GENERIC_6, *content++); 820 REG_WRITE(AFMT_GENERIC_7, *content); 821 } 822 823 /* check whether GENERIC4 registers double buffer update in immediate mode 824 * is pending 825 */ 826 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, 827 0, 10, max_retries); 828 829 /* atomically update double-buffered GENERIC4 registers in immediate mode 830 * (update immediately) 831 */ 832 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 833 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); 834 835 /* enable GSP4 transmitting */ 836 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); 837 838 /* This bit is the master enable bit. 839 * When enabling secondary stream engine, 840 * this master bit must also be set. 841 * This register shared with audio info frame. 842 * Therefore we need to enable master bit 843 * if at least on of the fields is not 0 844 */ 845 value = REG_READ(DP_SEC_CNTL); 846 if (value) 847 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 848 } 849 850 void enc1_stream_encoder_stop_dp_info_packets( 851 struct stream_encoder *enc) 852 { 853 /* stop generic packets on DP */ 854 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 855 uint32_t value = 0; 856 857 REG_SET_10(DP_SEC_CNTL, 0, 858 DP_SEC_GSP0_ENABLE, 0, 859 DP_SEC_GSP1_ENABLE, 0, 860 DP_SEC_GSP2_ENABLE, 0, 861 DP_SEC_GSP3_ENABLE, 0, 862 DP_SEC_GSP4_ENABLE, 0, 863 DP_SEC_GSP5_ENABLE, 0, 864 DP_SEC_GSP6_ENABLE, 0, 865 DP_SEC_GSP7_ENABLE, 0, 866 DP_SEC_MPG_ENABLE, 0, 867 DP_SEC_STREAM_ENABLE, 0); 868 869 /* this register shared with audio info frame. 870 * therefore we need to keep master enabled 871 * if at least one of the fields is not 0 */ 872 value = REG_READ(DP_SEC_CNTL); 873 if (value) 874 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 875 876 } 877 878 void enc1_stream_encoder_dp_blank( 879 struct stream_encoder *enc) 880 { 881 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 882 uint32_t reg1 = 0; 883 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 884 885 /* Note: For CZ, we are changing driver default to disable 886 * stream deferred to next VBLANK. If results are positive, we 887 * will make the same change to all DCE versions. There are a 888 * handful of panels that cannot handle disable stream at 889 * HBLANK and will result in a white line flash across the 890 * screen on stream disable. 891 */ 892 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 893 if ((reg1 & 0x1) == 0) 894 /*stream not enabled*/ 895 return; 896 /* Specify the video stream disable point 897 * (2 = start of the next vertical blank) 898 */ 899 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 900 /* Larger delay to wait until VBLANK - use max retry of 901 * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode + 902 * a little more because we may not trust delay accuracy. 903 */ 904 max_retries = DP_BLANK_MAX_RETRY * 250; 905 906 /* disable DP stream */ 907 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 908 909 /* the encoder stops sending the video stream 910 * at the start of the vertical blanking. 911 * Poll for DP_VID_STREAM_STATUS == 0 912 */ 913 914 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 915 0, 916 10, max_retries); 917 918 /* Tell the DP encoder to ignore timing from CRTC, must be done after 919 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 920 * complete, stream status will be stuck in video stream enabled state, 921 * i.e. DP_VID_STREAM_STATUS stuck at 1. 922 */ 923 924 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 925 } 926 927 /* output video stream to link encoder */ 928 void enc1_stream_encoder_dp_unblank( 929 struct stream_encoder *enc, 930 const struct encoder_unblank_param *param) 931 { 932 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 933 934 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 935 uint32_t n_vid = 0x8000; 936 uint32_t m_vid; 937 uint32_t n_multiply = 0; 938 uint64_t m_vid_l = n_vid; 939 940 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ 941 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 942 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ 943 n_multiply = 1; 944 } 945 /* M / N = Fstream / Flink 946 * m_vid / n_vid = pixel rate / link rate 947 */ 948 949 m_vid_l *= param->timing.pix_clk_100hz / 10; 950 m_vid_l = div_u64(m_vid_l, 951 param->link_settings.link_rate 952 * LINK_RATE_REF_FREQ_IN_KHZ); 953 954 m_vid = (uint32_t) m_vid_l; 955 956 /* enable auto measurement */ 957 958 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 959 960 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 961 * therefore program initial value for Mvid and Nvid 962 */ 963 964 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 965 966 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 967 968 REG_UPDATE_2(DP_VID_TIMING, 969 DP_VID_M_N_GEN_EN, 1, 970 DP_VID_N_MUL, n_multiply); 971 } 972 973 /* set DIG_START to 0x1 to resync FIFO */ 974 975 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 976 977 /* switch DP encoder to CRTC data */ 978 979 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 980 981 /* wait 100us for DIG/DP logic to prime 982 * (i.e. a few video lines) 983 */ 984 udelay(100); 985 986 /* the hardware would start sending video at the start of the next DP 987 * frame (i.e. rising edge of the vblank). 988 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 989 * register has no effect on enable transition! HW always guarantees 990 * VID_STREAM enable at start of next frame, and this is not 991 * programmable 992 */ 993 994 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 995 } 996 997 void enc1_stream_encoder_set_avmute( 998 struct stream_encoder *enc, 999 bool enable) 1000 { 1001 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1002 unsigned int value = enable ? 1 : 0; 1003 1004 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1005 } 1006 1007 void enc1_reset_hdmi_stream_attribute( 1008 struct stream_encoder *enc) 1009 { 1010 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1011 1012 REG_UPDATE_5(HDMI_CONTROL, 1013 HDMI_PACKET_GEN_VERSION, 1, 1014 HDMI_KEEPOUT_MODE, 1, 1015 HDMI_DEEP_COLOR_ENABLE, 0, 1016 HDMI_DATA_SCRAMBLE_EN, 0, 1017 HDMI_CLOCK_CHANNEL_RATE, 0); 1018 } 1019 1020 1021 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1022 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1023 1024 #include "include/audio_types.h" 1025 1026 /** 1027 * speakersToChannels 1028 * 1029 * @brief 1030 * translate speakers to channels 1031 * 1032 * FL - Front Left 1033 * FR - Front Right 1034 * RL - Rear Left 1035 * RR - Rear Right 1036 * RC - Rear Center 1037 * FC - Front Center 1038 * FLC - Front Left Center 1039 * FRC - Front Right Center 1040 * RLC - Rear Left Center 1041 * RRC - Rear Right Center 1042 * LFE - Low Freq Effect 1043 * 1044 * FC 1045 * FLC FRC 1046 * FL FR 1047 * 1048 * LFE 1049 * () 1050 * 1051 * 1052 * RL RR 1053 * RLC RRC 1054 * RC 1055 * 1056 * ch 8 7 6 5 4 3 2 1 1057 * 0b00000011 - - - - - - FR FL 1058 * 0b00000111 - - - - - LFE FR FL 1059 * 0b00001011 - - - - FC - FR FL 1060 * 0b00001111 - - - - FC LFE FR FL 1061 * 0b00010011 - - - RC - - FR FL 1062 * 0b00010111 - - - RC - LFE FR FL 1063 * 0b00011011 - - - RC FC - FR FL 1064 * 0b00011111 - - - RC FC LFE FR FL 1065 * 0b00110011 - - RR RL - - FR FL 1066 * 0b00110111 - - RR RL - LFE FR FL 1067 * 0b00111011 - - RR RL FC - FR FL 1068 * 0b00111111 - - RR RL FC LFE FR FL 1069 * 0b01110011 - RC RR RL - - FR FL 1070 * 0b01110111 - RC RR RL - LFE FR FL 1071 * 0b01111011 - RC RR RL FC - FR FL 1072 * 0b01111111 - RC RR RL FC LFE FR FL 1073 * 0b11110011 RRC RLC RR RL - - FR FL 1074 * 0b11110111 RRC RLC RR RL - LFE FR FL 1075 * 0b11111011 RRC RLC RR RL FC - FR FL 1076 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1077 * 0b11000011 FRC FLC - - - - FR FL 1078 * 0b11000111 FRC FLC - - - LFE FR FL 1079 * 0b11001011 FRC FLC - - FC - FR FL 1080 * 0b11001111 FRC FLC - - FC LFE FR FL 1081 * 0b11010011 FRC FLC - RC - - FR FL 1082 * 0b11010111 FRC FLC - RC - LFE FR FL 1083 * 0b11011011 FRC FLC - RC FC - FR FL 1084 * 0b11011111 FRC FLC - RC FC LFE FR FL 1085 * 0b11110011 FRC FLC RR RL - - FR FL 1086 * 0b11110111 FRC FLC RR RL - LFE FR FL 1087 * 0b11111011 FRC FLC RR RL FC - FR FL 1088 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1089 * 1090 * @param 1091 * speakers - speaker information as it comes from CEA audio block 1092 */ 1093 /* translate speakers to channels */ 1094 1095 union audio_cea_channels { 1096 uint8_t all; 1097 struct audio_cea_channels_bits { 1098 uint32_t FL:1; 1099 uint32_t FR:1; 1100 uint32_t LFE:1; 1101 uint32_t FC:1; 1102 uint32_t RL_RC:1; 1103 uint32_t RR:1; 1104 uint32_t RC_RLC_FLC:1; 1105 uint32_t RRC_FRC:1; 1106 } channels; 1107 }; 1108 1109 /* 25.2MHz/1.001*/ 1110 /* 25.2MHz/1.001*/ 1111 /* 25.2MHz*/ 1112 /* 27MHz */ 1113 /* 27MHz*1.001*/ 1114 /* 27MHz*1.001*/ 1115 /* 54MHz*/ 1116 /* 54MHz*1.001*/ 1117 /* 74.25MHz/1.001*/ 1118 /* 74.25MHz*/ 1119 /* 148.5MHz/1.001*/ 1120 /* 148.5MHz*/ 1121 1122 static const struct audio_clock_info audio_clock_info_table[16] = { 1123 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1124 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1125 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1126 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1127 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1128 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1129 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1130 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1131 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1132 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1133 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1134 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1135 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1136 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1137 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1138 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1139 }; 1140 1141 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1142 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1143 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1144 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1145 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1146 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1147 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1148 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1149 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1150 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1151 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1152 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1153 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1154 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1155 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1156 }; 1157 1158 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1159 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1160 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1161 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1162 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1163 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1164 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1165 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1166 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1167 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1168 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1169 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1170 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1171 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1172 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1173 1174 1175 }; 1176 1177 static union audio_cea_channels speakers_to_channels( 1178 struct audio_speaker_flags speaker_flags) 1179 { 1180 union audio_cea_channels cea_channels = {0}; 1181 1182 /* these are one to one */ 1183 cea_channels.channels.FL = speaker_flags.FL_FR; 1184 cea_channels.channels.FR = speaker_flags.FL_FR; 1185 cea_channels.channels.LFE = speaker_flags.LFE; 1186 cea_channels.channels.FC = speaker_flags.FC; 1187 1188 /* if Rear Left and Right exist move RC speaker to channel 7 1189 * otherwise to channel 5 1190 */ 1191 if (speaker_flags.RL_RR) { 1192 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1193 cea_channels.channels.RR = speaker_flags.RL_RR; 1194 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1195 } else { 1196 cea_channels.channels.RL_RC = speaker_flags.RC; 1197 } 1198 1199 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1200 if (speaker_flags.FLC_FRC) { 1201 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1202 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1203 } else { 1204 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1205 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1206 } 1207 1208 return cea_channels; 1209 } 1210 1211 void get_audio_clock_info( 1212 enum dc_color_depth color_depth, 1213 uint32_t crtc_pixel_clock_100Hz, 1214 uint32_t actual_pixel_clock_100Hz, 1215 struct audio_clock_info *audio_clock_info) 1216 { 1217 const struct audio_clock_info *clock_info; 1218 uint32_t index; 1219 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1220 uint32_t audio_array_size; 1221 1222 switch (color_depth) { 1223 case COLOR_DEPTH_161616: 1224 clock_info = audio_clock_info_table_48bpc; 1225 audio_array_size = ARRAY_SIZE( 1226 audio_clock_info_table_48bpc); 1227 break; 1228 case COLOR_DEPTH_121212: 1229 clock_info = audio_clock_info_table_36bpc; 1230 audio_array_size = ARRAY_SIZE( 1231 audio_clock_info_table_36bpc); 1232 break; 1233 default: 1234 clock_info = audio_clock_info_table; 1235 audio_array_size = ARRAY_SIZE( 1236 audio_clock_info_table); 1237 break; 1238 } 1239 1240 if (clock_info != NULL) { 1241 /* search for exact pixel clock in table */ 1242 for (index = 0; index < audio_array_size; index++) { 1243 if (clock_info[index].pixel_clock_in_10khz > 1244 crtc_pixel_clock_in_10khz) 1245 break; /* not match */ 1246 else if (clock_info[index].pixel_clock_in_10khz == 1247 crtc_pixel_clock_in_10khz) { 1248 /* match found */ 1249 *audio_clock_info = clock_info[index]; 1250 return; 1251 } 1252 } 1253 } 1254 1255 /* not found */ 1256 if (actual_pixel_clock_100Hz == 0) 1257 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1258 1259 /* See HDMI spec the table entry under 1260 * pixel clock of "Other". */ 1261 audio_clock_info->pixel_clock_in_10khz = 1262 actual_pixel_clock_100Hz / 100; 1263 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1264 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1265 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1266 1267 audio_clock_info->n_32khz = 4096; 1268 audio_clock_info->n_44khz = 6272; 1269 audio_clock_info->n_48khz = 6144; 1270 } 1271 1272 static void enc1_se_audio_setup( 1273 struct stream_encoder *enc, 1274 unsigned int az_inst, 1275 struct audio_info *audio_info) 1276 { 1277 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1278 1279 uint32_t speakers = 0; 1280 uint32_t channels = 0; 1281 1282 ASSERT(audio_info); 1283 if (audio_info == NULL) 1284 /* This should not happen.it does so we don't get BSOD*/ 1285 return; 1286 1287 speakers = audio_info->flags.info.ALLSPEAKERS; 1288 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1289 1290 /* setup the audio stream source select (audio -> dig mapping) */ 1291 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1292 1293 /* Channel allocation */ 1294 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1295 } 1296 1297 static void enc1_se_setup_hdmi_audio( 1298 struct stream_encoder *enc, 1299 const struct audio_crtc_info *crtc_info) 1300 { 1301 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1302 1303 struct audio_clock_info audio_clock_info = {0}; 1304 1305 /* HDMI_AUDIO_PACKET_CONTROL */ 1306 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 1307 HDMI_AUDIO_DELAY_EN, 1); 1308 1309 /* AFMT_AUDIO_PACKET_CONTROL */ 1310 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1311 1312 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1313 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1314 AFMT_AUDIO_LAYOUT_OVRD, 0, 1315 AFMT_60958_OSF_OVRD, 0); 1316 1317 /* HDMI_ACR_PACKET_CONTROL */ 1318 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1319 HDMI_ACR_AUTO_SEND, 1, 1320 HDMI_ACR_SOURCE, 0, 1321 HDMI_ACR_AUDIO_PRIORITY, 0); 1322 1323 /* Program audio clock sample/regeneration parameters */ 1324 get_audio_clock_info(crtc_info->color_depth, 1325 crtc_info->requested_pixel_clock_100Hz, 1326 crtc_info->calculated_pixel_clock_100Hz, 1327 &audio_clock_info); 1328 DC_LOG_HW_AUDIO( 1329 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1330 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1331 crtc_info->requested_pixel_clock_100Hz, \ 1332 crtc_info->calculated_pixel_clock_100Hz); 1333 1334 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1335 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1336 1337 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1338 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1339 1340 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1341 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1342 1343 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1344 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1345 1346 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1347 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1348 1349 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1350 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1351 1352 /* Video driver cannot know in advance which sample rate will 1353 * be used by HD Audio driver 1354 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1355 * programmed below in interruppt callback 1356 */ 1357 1358 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1359 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 1360 */ 1361 REG_UPDATE_2(AFMT_60958_0, 1362 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1363 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1364 1365 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1366 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1367 1368 /* AFMT_60958_2 now keep this settings until 1369 * Programming guide comes out 1370 */ 1371 REG_UPDATE_6(AFMT_60958_2, 1372 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1373 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1374 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1375 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1376 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1377 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1378 } 1379 1380 static void enc1_se_setup_dp_audio( 1381 struct stream_encoder *enc) 1382 { 1383 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1384 1385 /* --- DP Audio packet configurations --- */ 1386 1387 /* ATP Configuration */ 1388 REG_SET(DP_SEC_AUD_N, 0, 1389 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1390 1391 /* Async/auto-calc timestamp mode */ 1392 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1393 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1394 1395 /* --- The following are the registers 1396 * copied from the SetupHDMI --- 1397 */ 1398 1399 /* AFMT_AUDIO_PACKET_CONTROL */ 1400 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1401 1402 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1403 /* Program the ATP and AIP next */ 1404 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1405 AFMT_AUDIO_LAYOUT_OVRD, 0, 1406 AFMT_60958_OSF_OVRD, 0); 1407 1408 /* AFMT_INFOFRAME_CONTROL0 */ 1409 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1410 1411 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1412 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1413 } 1414 1415 void enc1_se_enable_audio_clock( 1416 struct stream_encoder *enc, 1417 bool enable) 1418 { 1419 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1420 1421 if (REG(AFMT_CNTL) == 0) 1422 return; /* DCE8/10 does not have this register */ 1423 1424 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1425 1426 /* wait for AFMT clock to turn on, 1427 * expectation: this should complete in 1-2 reads 1428 * 1429 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1430 * 1431 * TODO: wait for clock_on does not work well. May need HW 1432 * program sequence. But audio seems work normally even without wait 1433 * for clock_on status change 1434 */ 1435 } 1436 1437 void enc1_se_enable_dp_audio( 1438 struct stream_encoder *enc) 1439 { 1440 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1441 1442 /* Enable Audio packets */ 1443 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1444 1445 /* Program the ATP and AIP next */ 1446 REG_UPDATE_2(DP_SEC_CNTL, 1447 DP_SEC_ATP_ENABLE, 1, 1448 DP_SEC_AIP_ENABLE, 1); 1449 1450 /* Program STREAM_ENABLE after all the other enables. */ 1451 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1452 } 1453 1454 static void enc1_se_disable_dp_audio( 1455 struct stream_encoder *enc) 1456 { 1457 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1458 uint32_t value = 0; 1459 1460 /* Disable Audio packets */ 1461 REG_UPDATE_5(DP_SEC_CNTL, 1462 DP_SEC_ASP_ENABLE, 0, 1463 DP_SEC_ATP_ENABLE, 0, 1464 DP_SEC_AIP_ENABLE, 0, 1465 DP_SEC_ACM_ENABLE, 0, 1466 DP_SEC_STREAM_ENABLE, 0); 1467 1468 /* This register shared with encoder info frame. Therefore we need to 1469 * keep master enabled if at least on of the fields is not 0 1470 */ 1471 value = REG_READ(DP_SEC_CNTL); 1472 if (value != 0) 1473 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1474 1475 } 1476 1477 void enc1_se_audio_mute_control( 1478 struct stream_encoder *enc, 1479 bool mute) 1480 { 1481 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1482 1483 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1484 } 1485 1486 void enc1_se_dp_audio_setup( 1487 struct stream_encoder *enc, 1488 unsigned int az_inst, 1489 struct audio_info *info) 1490 { 1491 enc1_se_audio_setup(enc, az_inst, info); 1492 } 1493 1494 void enc1_se_dp_audio_enable( 1495 struct stream_encoder *enc) 1496 { 1497 enc1_se_enable_audio_clock(enc, true); 1498 enc1_se_setup_dp_audio(enc); 1499 enc1_se_enable_dp_audio(enc); 1500 } 1501 1502 void enc1_se_dp_audio_disable( 1503 struct stream_encoder *enc) 1504 { 1505 enc1_se_disable_dp_audio(enc); 1506 enc1_se_enable_audio_clock(enc, false); 1507 } 1508 1509 void enc1_se_hdmi_audio_setup( 1510 struct stream_encoder *enc, 1511 unsigned int az_inst, 1512 struct audio_info *info, 1513 struct audio_crtc_info *audio_crtc_info) 1514 { 1515 enc1_se_enable_audio_clock(enc, true); 1516 enc1_se_setup_hdmi_audio(enc, audio_crtc_info); 1517 enc1_se_audio_setup(enc, az_inst, info); 1518 } 1519 1520 void enc1_se_hdmi_audio_disable( 1521 struct stream_encoder *enc) 1522 { 1523 enc1_se_enable_audio_clock(enc, false); 1524 } 1525 1526 1527 void enc1_setup_stereo_sync( 1528 struct stream_encoder *enc, 1529 int tg_inst, bool enable) 1530 { 1531 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1532 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1533 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1534 } 1535 1536 void enc1_dig_connect_to_otg( 1537 struct stream_encoder *enc, 1538 int tg_inst) 1539 { 1540 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1541 1542 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1543 } 1544 1545 unsigned int enc1_dig_source_otg( 1546 struct stream_encoder *enc) 1547 { 1548 uint32_t tg_inst = 0; 1549 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1550 1551 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1552 1553 return tg_inst; 1554 } 1555 1556 static const struct stream_encoder_funcs dcn10_str_enc_funcs = { 1557 .dp_set_stream_attribute = 1558 enc1_stream_encoder_dp_set_stream_attribute, 1559 .hdmi_set_stream_attribute = 1560 enc1_stream_encoder_hdmi_set_stream_attribute, 1561 .dvi_set_stream_attribute = 1562 enc1_stream_encoder_dvi_set_stream_attribute, 1563 .set_mst_bandwidth = 1564 enc1_stream_encoder_set_mst_bandwidth, 1565 .update_hdmi_info_packets = 1566 enc1_stream_encoder_update_hdmi_info_packets, 1567 .stop_hdmi_info_packets = 1568 enc1_stream_encoder_stop_hdmi_info_packets, 1569 .update_dp_info_packets = 1570 enc1_stream_encoder_update_dp_info_packets, 1571 .send_immediate_sdp_message = 1572 enc1_stream_encoder_send_immediate_sdp_message, 1573 .stop_dp_info_packets = 1574 enc1_stream_encoder_stop_dp_info_packets, 1575 .dp_blank = 1576 enc1_stream_encoder_dp_blank, 1577 .dp_unblank = 1578 enc1_stream_encoder_dp_unblank, 1579 .audio_mute_control = enc1_se_audio_mute_control, 1580 1581 .dp_audio_setup = enc1_se_dp_audio_setup, 1582 .dp_audio_enable = enc1_se_dp_audio_enable, 1583 .dp_audio_disable = enc1_se_dp_audio_disable, 1584 1585 .hdmi_audio_setup = enc1_se_hdmi_audio_setup, 1586 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 1587 .setup_stereo_sync = enc1_setup_stereo_sync, 1588 .set_avmute = enc1_stream_encoder_set_avmute, 1589 .dig_connect_to_otg = enc1_dig_connect_to_otg, 1590 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 1591 .dig_source_otg = enc1_dig_source_otg, 1592 }; 1593 1594 void dcn10_stream_encoder_construct( 1595 struct dcn10_stream_encoder *enc1, 1596 struct dc_context *ctx, 1597 struct dc_bios *bp, 1598 enum engine_id eng_id, 1599 const struct dcn10_stream_enc_registers *regs, 1600 const struct dcn10_stream_encoder_shift *se_shift, 1601 const struct dcn10_stream_encoder_mask *se_mask) 1602 { 1603 enc1->base.funcs = &dcn10_str_enc_funcs; 1604 enc1->base.ctx = ctx; 1605 enc1->base.id = eng_id; 1606 enc1->base.bp = bp; 1607 enc1->regs = regs; 1608 enc1->se_shift = se_shift; 1609 enc1->se_mask = se_mask; 1610 } 1611 1612