1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 28 #include "core_types.h" 29 #include "link_encoder.h" 30 #include "dcn30_dio_link_encoder.h" 31 #include "stream_encoder.h" 32 #include "i2caux_interface.h" 33 #include "dc_bios_types.h" 34 /* #include "dcn3ag/dcn3ag_phy_fw.h" */ 35 36 #include "gpio_service_interface.h" 37 38 #define CTX \ 39 enc10->base.ctx 40 #define DC_LOGGER \ 41 enc10->base.ctx->logger 42 43 #define REG(reg)\ 44 (enc10->link_regs->reg) 45 46 #undef FN 47 #define FN(reg_name, field_name) \ 48 enc10->link_shift->field_name, enc10->link_mask->field_name 49 50 #define IND_REG(index) \ 51 (enc10->link_regs->index) 52 53 54 bool dcn30_link_encoder_validate_output_with_stream( 55 struct link_encoder *enc, 56 const struct dc_stream_state *stream) 57 { 58 return dcn10_link_encoder_validate_output_with_stream(enc, stream); 59 } 60 61 static const struct link_encoder_funcs dcn30_link_enc_funcs = { 62 .read_state = link_enc2_read_state, 63 .validate_output_with_stream = 64 dcn30_link_encoder_validate_output_with_stream, 65 .hw_init = enc3_hw_init, 66 .setup = dcn10_link_encoder_setup, 67 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 68 .enable_dp_output = dcn20_link_encoder_enable_dp_output, 69 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, 70 .disable_output = dcn10_link_encoder_disable_output, 71 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 72 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 73 .update_mst_stream_allocation_table = 74 dcn10_link_encoder_update_mst_stream_allocation_table, 75 .psr_program_dp_dphy_fast_training = 76 dcn10_psr_program_dp_dphy_fast_training, 77 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 78 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 79 .enable_hpd = dcn10_link_encoder_enable_hpd, 80 .disable_hpd = dcn10_link_encoder_disable_hpd, 81 .is_dig_enabled = dcn10_is_dig_enabled, 82 .destroy = dcn10_link_encoder_destroy, 83 .fec_set_enable = enc2_fec_set_enable, 84 .fec_set_ready = enc2_fec_set_ready, 85 .fec_is_active = enc2_fec_is_active, 86 .get_dig_frontend = dcn10_get_dig_frontend, 87 .get_dig_mode = dcn10_get_dig_mode, 88 .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, 89 .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, 90 }; 91 92 void dcn30_link_encoder_construct( 93 struct dcn20_link_encoder *enc20, 94 const struct encoder_init_data *init_data, 95 const struct encoder_feature_support *enc_features, 96 const struct dcn10_link_enc_registers *link_regs, 97 const struct dcn10_link_enc_aux_registers *aux_regs, 98 const struct dcn10_link_enc_hpd_registers *hpd_regs, 99 const struct dcn10_link_enc_shift *link_shift, 100 const struct dcn10_link_enc_mask *link_mask) 101 { 102 struct bp_encoder_cap_info bp_cap_info = {0}; 103 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 104 enum bp_result result = BP_RESULT_OK; 105 struct dcn10_link_encoder *enc10 = &enc20->enc10; 106 107 enc10->base.funcs = &dcn30_link_enc_funcs; 108 enc10->base.ctx = init_data->ctx; 109 enc10->base.id = init_data->encoder; 110 111 enc10->base.hpd_source = init_data->hpd_source; 112 enc10->base.connector = init_data->connector; 113 114 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 115 116 enc10->base.features = *enc_features; 117 118 enc10->base.transmitter = init_data->transmitter; 119 120 /* set the flag to indicate whether driver poll the I2C data pin 121 * while doing the DP sink detect 122 */ 123 124 /* if (dal_adapter_service_is_feature_supported(as, 125 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 126 enc10->base.features.flags.bits. 127 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 128 129 enc10->base.output_signals = 130 SIGNAL_TYPE_DVI_SINGLE_LINK | 131 SIGNAL_TYPE_DVI_DUAL_LINK | 132 SIGNAL_TYPE_LVDS | 133 SIGNAL_TYPE_DISPLAY_PORT | 134 SIGNAL_TYPE_DISPLAY_PORT_MST | 135 SIGNAL_TYPE_EDP | 136 SIGNAL_TYPE_HDMI_TYPE_A; 137 138 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 139 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 140 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 141 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 142 * Prefer DIG assignment is decided by board design. 143 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 144 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 145 * By this, adding DIGG should not hurt DCE 8.0. 146 * This will let DCE 8.1 share DCE 8.0 as much as possible 147 */ 148 149 enc10->link_regs = link_regs; 150 enc10->aux_regs = aux_regs; 151 enc10->hpd_regs = hpd_regs; 152 enc10->link_shift = link_shift; 153 enc10->link_mask = link_mask; 154 155 switch (enc10->base.transmitter) { 156 case TRANSMITTER_UNIPHY_A: 157 enc10->base.preferred_engine = ENGINE_ID_DIGA; 158 break; 159 case TRANSMITTER_UNIPHY_B: 160 enc10->base.preferred_engine = ENGINE_ID_DIGB; 161 break; 162 case TRANSMITTER_UNIPHY_C: 163 enc10->base.preferred_engine = ENGINE_ID_DIGC; 164 break; 165 case TRANSMITTER_UNIPHY_D: 166 enc10->base.preferred_engine = ENGINE_ID_DIGD; 167 break; 168 case TRANSMITTER_UNIPHY_E: 169 enc10->base.preferred_engine = ENGINE_ID_DIGE; 170 break; 171 case TRANSMITTER_UNIPHY_F: 172 enc10->base.preferred_engine = ENGINE_ID_DIGF; 173 break; 174 case TRANSMITTER_UNIPHY_G: 175 enc10->base.preferred_engine = ENGINE_ID_DIGG; 176 break; 177 default: 178 ASSERT_CRITICAL(false); 179 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 180 } 181 182 /* default to one to mirror Windows behavior */ 183 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 184 185 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, 186 enc10->base.id, &bp_cap_info); 187 188 /* Override features with DCE-specific values */ 189 if (result == BP_RESULT_OK) { 190 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 191 bp_cap_info.DP_HBR2_EN; 192 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 193 bp_cap_info.DP_HBR3_EN; 194 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 195 enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE; 196 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; 197 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; 198 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; 199 enc10->base.features.flags.bits.DP_IS_USB_C = 200 bp_cap_info.DP_IS_USB_C; 201 } else { 202 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 203 __func__, 204 result); 205 } 206 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 207 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 208 } 209 } 210 211 #define AUX_REG(reg)\ 212 (enc10->aux_regs->reg) 213 214 #define AUX_REG_READ(reg_name) \ 215 dm_read_reg(CTX, AUX_REG(reg_name)) 216 217 #define AUX_REG_WRITE(reg_name, val) \ 218 dm_write_reg(CTX, AUX_REG(reg_name), val) 219 void enc3_hw_init(struct link_encoder *enc) 220 { 221 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 222 223 /* 224 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 225 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 226 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 227 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 228 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 229 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 230 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 231 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 232 */ 233 234 /* 235 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, 236 AUX_RX_START_WINDOW = 1 [6:4] 237 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] 238 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 239 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 240 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 241 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 242 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 243 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 244 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 245 */ 246 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 247 248 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); 249 250 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; 251 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk 252 // 27MHz -> 0xd 253 // 100MHz -> 0x32 254 // 48MHz -> 0x18 255 256 // Set TMDS_CTL0 to 1. This is a legacy setting. 257 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); 258 259 dcn10_aux_initialize(enc10); 260 } 261