1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_ENCODER__DCN301_H__ 27 #define __DC_LINK_ENCODER__DCN301_H__ 28 29 #include "dcn20/dcn20_link_encoder.h" 30 31 32 #define LE_DCN301_REG_LIST(id)\ 33 SRI(DIG_BE_CNTL, DIG, id), \ 34 SRI(DIG_BE_EN_CNTL, DIG, id), \ 35 SRI(TMDS_CTL_BITS, DIG, id), \ 36 SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \ 37 SRI(DP_CONFIG, DP, id), \ 38 SRI(DP_DPHY_CNTL, DP, id), \ 39 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 40 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 41 SRI(DP_DPHY_SYM0, DP, id), \ 42 SRI(DP_DPHY_SYM1, DP, id), \ 43 SRI(DP_DPHY_SYM2, DP, id), \ 44 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 45 SRI(DP_LINK_CNTL, DP, id), \ 46 SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 47 SRI(DP_MSE_SAT0, DP, id), \ 48 SRI(DP_MSE_SAT1, DP, id), \ 49 SRI(DP_MSE_SAT2, DP, id), \ 50 SRI(DP_MSE_SAT_UPDATE, DP, id), \ 51 SRI(DP_SEC_CNTL, DP, id), \ 52 SRI(DP_VID_STREAM_CNTL, DP, id), \ 53 SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 54 SRI(DP_SEC_CNTL1, DP, id), \ 55 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 56 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) 57 58 #define LINK_ENCODER_MASK_SH_LIST_DCN301(mask_sh) \ 59 LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\ 60 LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh) 61 62 #define DPCS_DCN301_MASK_SH_LIST(mask_sh)\ 63 DPCS_DCN2_MASK_SH_LIST(mask_sh),\ 64 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_HDMI_FRL_MODE, mask_sh),\ 65 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP_10_BIT, mask_sh),\ 66 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\ 67 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\ 68 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh) 69 70 void dcn301_link_encoder_construct( 71 struct dcn20_link_encoder *enc20, 72 const struct encoder_init_data *init_data, 73 const struct encoder_feature_support *enc_features, 74 const struct dcn10_link_enc_registers *link_regs, 75 const struct dcn10_link_enc_aux_registers *aux_regs, 76 const struct dcn10_link_enc_hpd_registers *hpd_regs, 77 const struct dcn10_link_enc_shift *link_shift, 78 const struct dcn10_link_enc_mask *link_mask); 79 80 void enc3_hw_init(struct link_encoder *enc); 81 82 #endif /* __DC_LINK_ENCODER__DCN301_H__ */ 83