1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 #include "dc_bios_types.h" 29 #include "dcn30/dcn30_dio_stream_encoder.h" 30 #include "dcn314_dio_stream_encoder.h" 31 #include "reg_helper.h" 32 #include "hw_shared.h" 33 #include "inc/link_dpcd.h" 34 #include "dpcd_defs.h" 35 36 #define DC_LOGGER \ 37 enc1->base.ctx->logger 38 39 #define REG(reg)\ 40 (enc1->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 enc1->se_shift->field_name, enc1->se_mask->field_name 45 46 #define VBI_LINE_0 0 47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 48 49 #define CTX \ 50 enc1->base.ctx 51 52 53 static void enc314_enable_fifo(struct stream_encoder *enc) 54 { 55 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 56 57 /* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */ 58 REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); 59 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); 60 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); 61 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); 62 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0); 63 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); 64 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); 65 } 66 67 static void enc314_disable_fifo(struct stream_encoder *enc) 68 { 69 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 70 71 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); 72 } 73 74 static void enc314_dp_set_odm_combine( 75 struct stream_encoder *enc, 76 bool odm_combine) 77 { 78 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 79 80 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine); 81 } 82 83 /* setup stream encoder in dvi mode */ 84 static void enc314_stream_encoder_dvi_set_stream_attribute( 85 struct stream_encoder *enc, 86 struct dc_crtc_timing *crtc_timing, 87 bool is_dual_link) 88 { 89 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 90 91 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 92 struct bp_encoder_control cntl = {0}; 93 94 cntl.action = ENCODER_CONTROL_SETUP; 95 cntl.engine_id = enc1->base.id; 96 cntl.signal = is_dual_link ? 97 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 98 cntl.enable_dp_audio = false; 99 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 100 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 101 102 if (enc1->base.bp->funcs->encoder_control( 103 enc1->base.bp, &cntl) != BP_RESULT_OK) 104 return; 105 106 } else { 107 108 //Set pattern for clock channel, default vlue 0x63 does not work 109 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 110 111 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup 112 113 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 114 115 enc314_enable_fifo(enc); 116 } 117 118 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 119 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 120 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 121 } 122 123 /* setup stream encoder in hdmi mode */ 124 static void enc314_stream_encoder_hdmi_set_stream_attribute( 125 struct stream_encoder *enc, 126 struct dc_crtc_timing *crtc_timing, 127 int actual_pix_clk_khz, 128 bool enable_audio) 129 { 130 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 131 132 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 133 struct bp_encoder_control cntl = {0}; 134 135 cntl.action = ENCODER_CONTROL_SETUP; 136 cntl.engine_id = enc1->base.id; 137 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 138 cntl.enable_dp_audio = enable_audio; 139 cntl.pixel_clock = actual_pix_clk_khz; 140 cntl.lanes_number = LANE_COUNT_FOUR; 141 142 if (enc1->base.bp->funcs->encoder_control( 143 enc1->base.bp, &cntl) != BP_RESULT_OK) 144 return; 145 146 } else { 147 148 //Set pattern for clock channel, default vlue 0x63 does not work 149 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 150 151 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup 152 153 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 154 155 enc314_enable_fifo(enc); 156 } 157 158 /* Configure pixel encoding */ 159 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 160 161 /* setup HDMI engine */ 162 REG_UPDATE_6(HDMI_CONTROL, 163 HDMI_PACKET_GEN_VERSION, 1, 164 HDMI_KEEPOUT_MODE, 1, 165 HDMI_DEEP_COLOR_ENABLE, 0, 166 HDMI_DATA_SCRAMBLE_EN, 0, 167 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 168 HDMI_CLOCK_CHANNEL_RATE, 0); 169 170 /* Configure color depth */ 171 switch (crtc_timing->display_color_depth) { 172 case COLOR_DEPTH_888: 173 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 174 break; 175 case COLOR_DEPTH_101010: 176 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 177 REG_UPDATE_2(HDMI_CONTROL, 178 HDMI_DEEP_COLOR_DEPTH, 1, 179 HDMI_DEEP_COLOR_ENABLE, 0); 180 } else { 181 REG_UPDATE_2(HDMI_CONTROL, 182 HDMI_DEEP_COLOR_DEPTH, 1, 183 HDMI_DEEP_COLOR_ENABLE, 1); 184 } 185 break; 186 case COLOR_DEPTH_121212: 187 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 188 REG_UPDATE_2(HDMI_CONTROL, 189 HDMI_DEEP_COLOR_DEPTH, 2, 190 HDMI_DEEP_COLOR_ENABLE, 0); 191 } else { 192 REG_UPDATE_2(HDMI_CONTROL, 193 HDMI_DEEP_COLOR_DEPTH, 2, 194 HDMI_DEEP_COLOR_ENABLE, 1); 195 } 196 break; 197 case COLOR_DEPTH_161616: 198 REG_UPDATE_2(HDMI_CONTROL, 199 HDMI_DEEP_COLOR_DEPTH, 3, 200 HDMI_DEEP_COLOR_ENABLE, 1); 201 break; 202 default: 203 break; 204 } 205 206 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 207 /* enable HDMI data scrambler 208 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 209 * Clock channel frequency is 1/4 of character rate. 210 */ 211 REG_UPDATE_2(HDMI_CONTROL, 212 HDMI_DATA_SCRAMBLE_EN, 1, 213 HDMI_CLOCK_CHANNEL_RATE, 1); 214 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 215 216 /* TODO: New feature for DCE11, still need to implement */ 217 218 /* enable HDMI data scrambler 219 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 220 * Clock channel frequency is the same 221 * as character rate 222 */ 223 REG_UPDATE_2(HDMI_CONTROL, 224 HDMI_DATA_SCRAMBLE_EN, 1, 225 HDMI_CLOCK_CHANNEL_RATE, 0); 226 } 227 228 229 /* Enable transmission of General Control packet on every frame */ 230 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 231 HDMI_GC_CONT, 1, 232 HDMI_GC_SEND, 1, 233 HDMI_NULL_SEND, 1); 234 235 /* Disable Audio Content Protection packet transmission */ 236 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); 237 238 /* following belongs to audio */ 239 /* Enable Audio InfoFrame packet transmission. */ 240 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 241 242 /* update double-buffered AUDIO_INFO registers immediately */ 243 ASSERT(enc->afmt); 244 enc->afmt->funcs->audio_info_immediate_update(enc->afmt); 245 246 /* Select line number on which to send Audio InfoFrame packets */ 247 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 248 VBI_LINE_0 + 2); 249 250 /* set HDMI GC AVMUTE */ 251 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 252 } 253 254 255 256 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 257 { 258 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 259 260 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 261 && !timing->dsc_cfg.ycbcr422_simple); 262 return two_pix; 263 } 264 265 static void enc314_stream_encoder_dp_blank( 266 struct dc_link *link, 267 struct stream_encoder *enc) 268 { 269 /* New to DCN314 - disable the FIFO before VID stream disable. */ 270 enc314_disable_fifo(enc); 271 272 enc1_stream_encoder_dp_blank(link, enc); 273 } 274 275 static void enc314_stream_encoder_dp_unblank( 276 struct dc_link *link, 277 struct stream_encoder *enc, 278 const struct encoder_unblank_param *param) 279 { 280 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 281 282 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 283 uint32_t n_vid = 0x8000; 284 uint32_t m_vid; 285 uint32_t n_multiply = 0; 286 uint64_t m_vid_l = n_vid; 287 288 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ 289 if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { 290 /*this logic should be the same in get_pixel_clock_parameters() */ 291 n_multiply = 1; 292 } 293 /* M / N = Fstream / Flink 294 * m_vid / n_vid = pixel rate / link rate 295 */ 296 297 m_vid_l *= param->timing.pix_clk_100hz / 10; 298 m_vid_l = div_u64(m_vid_l, 299 param->link_settings.link_rate 300 * LINK_RATE_REF_FREQ_IN_KHZ); 301 302 m_vid = (uint32_t) m_vid_l; 303 304 /* enable auto measurement */ 305 306 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 307 308 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 309 * therefore program initial value for Mvid and Nvid 310 */ 311 312 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 313 314 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 315 316 REG_UPDATE_2(DP_VID_TIMING, 317 DP_VID_M_N_GEN_EN, 1, 318 DP_VID_N_MUL, n_multiply); 319 } 320 321 /* make sure stream is disabled before resetting steer fifo */ 322 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); 323 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); 324 325 /* DIG_START is removed from the register spec */ 326 327 /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen 328 * that it overflows during mode transition, and sometimes doesn't recover. 329 */ 330 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); 331 udelay(10); 332 333 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 334 335 /* wait 100us for DIG/DP logic to prime 336 * (i.e. a few video lines) 337 */ 338 udelay(100); 339 340 /* the hardware would start sending video at the start of the next DP 341 * frame (i.e. rising edge of the vblank). 342 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 343 * register has no effect on enable transition! HW always guarantees 344 * VID_STREAM enable at start of next frame, and this is not 345 * programmable 346 */ 347 348 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 349 350 /* 351 * DIG Resync FIFO now needs to be explicitly enabled. 352 * This should come after DP_VID_STREAM_ENABLE per HW docs. 353 */ 354 enc314_enable_fifo(enc); 355 356 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); 357 } 358 359 /* Set DSC-related configuration. 360 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 361 * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 362 * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32 363 */ 364 static void enc314_dp_set_dsc_config(struct stream_encoder *enc, 365 enum optc_dsc_mode dsc_mode, 366 uint32_t dsc_bytes_per_pixel, 367 uint32_t dsc_slice_width) 368 { 369 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 370 371 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); 372 } 373 374 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 375 * into a dcn_dsc_state struct. 376 */ 377 static void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) 378 { 379 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 380 381 //if dsc is enabled, continue to read 382 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); 383 if (s->dsc_mode) { 384 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); 385 386 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); 387 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); 388 389 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); 390 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); 391 } 392 } 393 394 static void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) 395 { 396 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 397 398 // The naming of this field is confusing, what it means is the output mode of otg, which 399 // is the input mode of the dig 400 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); 401 } 402 403 404 static const struct stream_encoder_funcs dcn314_str_enc_funcs = { 405 .dp_set_odm_combine = 406 enc314_dp_set_odm_combine, 407 .dp_set_stream_attribute = 408 enc2_stream_encoder_dp_set_stream_attribute, 409 .hdmi_set_stream_attribute = 410 enc314_stream_encoder_hdmi_set_stream_attribute, 411 .dvi_set_stream_attribute = 412 enc314_stream_encoder_dvi_set_stream_attribute, 413 .set_throttled_vcp_size = 414 enc1_stream_encoder_set_throttled_vcp_size, 415 .update_hdmi_info_packets = 416 enc3_stream_encoder_update_hdmi_info_packets, 417 .stop_hdmi_info_packets = 418 enc3_stream_encoder_stop_hdmi_info_packets, 419 .update_dp_info_packets = 420 enc3_stream_encoder_update_dp_info_packets, 421 .stop_dp_info_packets = 422 enc1_stream_encoder_stop_dp_info_packets, 423 .dp_blank = 424 enc314_stream_encoder_dp_blank, 425 .dp_unblank = 426 enc314_stream_encoder_dp_unblank, 427 .audio_mute_control = enc3_audio_mute_control, 428 429 .dp_audio_setup = enc3_se_dp_audio_setup, 430 .dp_audio_enable = enc3_se_dp_audio_enable, 431 .dp_audio_disable = enc1_se_dp_audio_disable, 432 433 .hdmi_audio_setup = enc3_se_hdmi_audio_setup, 434 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 435 .setup_stereo_sync = enc1_setup_stereo_sync, 436 .set_avmute = enc1_stream_encoder_set_avmute, 437 .dig_connect_to_otg = enc1_dig_connect_to_otg, 438 .dig_source_otg = enc1_dig_source_otg, 439 440 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 441 442 .enc_read_state = enc314_read_state, 443 .dp_set_dsc_config = enc314_dp_set_dsc_config, 444 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, 445 .set_dynamic_metadata = enc2_set_dynamic_metadata, 446 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 447 448 .enable_fifo = enc314_enable_fifo, 449 .disable_fifo = enc314_disable_fifo, 450 .set_input_mode = enc314_set_dig_input_mode, 451 }; 452 453 void dcn314_dio_stream_encoder_construct( 454 struct dcn10_stream_encoder *enc1, 455 struct dc_context *ctx, 456 struct dc_bios *bp, 457 enum engine_id eng_id, 458 struct vpg *vpg, 459 struct afmt *afmt, 460 const struct dcn10_stream_enc_registers *regs, 461 const struct dcn10_stream_encoder_shift *se_shift, 462 const struct dcn10_stream_encoder_mask *se_mask) 463 { 464 enc1->base.funcs = &dcn314_str_enc_funcs; 465 enc1->base.ctx = ctx; 466 enc1->base.id = eng_id; 467 enc1->base.bp = bp; 468 enc1->base.vpg = vpg; 469 enc1->base.afmt = afmt; 470 enc1->regs = regs; 471 enc1->se_shift = se_shift; 472 enc1->se_mask = se_mask; 473 enc1->base.stream_enc_inst = vpg->inst; 474 } 475 476