1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dcn31/dcn31_dio_link_encoder.h" 32 #include "dcn32_dio_link_encoder.h" 33 #include "stream_encoder.h" 34 #include "i2caux_interface.h" 35 #include "dc_bios_types.h" 36 #include "link_enc_cfg.h" 37 38 #include "gpio_service_interface.h" 39 40 #ifndef MIN 41 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 42 #endif 43 44 #define CTX \ 45 enc10->base.ctx 46 #define DC_LOGGER \ 47 enc10->base.ctx->logger 48 49 #define REG(reg)\ 50 (enc10->link_regs->reg) 51 52 #undef FN 53 #define FN(reg_name, field_name) \ 54 enc10->link_shift->field_name, enc10->link_mask->field_name 55 56 #define AUX_REG(reg)\ 57 (enc10->aux_regs->reg) 58 59 #define AUX_REG_READ(reg_name) \ 60 dm_read_reg(CTX, AUX_REG(reg_name)) 61 62 #define AUX_REG_WRITE(reg_name, val) \ 63 dm_write_reg(CTX, AUX_REG(reg_name), val) 64 65 66 void enc32_hw_init(struct link_encoder *enc) 67 { 68 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 69 70 /* 71 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 72 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 73 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 74 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 75 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 76 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 77 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 78 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 79 */ 80 81 /* 82 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, 83 AUX_RX_START_WINDOW = 1 [6:4] 84 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] 85 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 86 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 87 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 88 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 89 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 90 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 91 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 92 */ 93 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 94 95 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); 96 97 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; 98 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk 99 // 27MHz -> 0xd 100 // 100MHz -> 0x32 101 // 48MHz -> 0x18 102 103 // Set TMDS_CTL0 to 1. This is a legacy setting. 104 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); 105 106 dcn10_aux_initialize(enc10); 107 } 108 109 110 void dcn32_link_encoder_enable_dp_output( 111 struct link_encoder *enc, 112 const struct dc_link_settings *link_settings, 113 enum clock_source_id clock_source) 114 { 115 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 116 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); 117 return; 118 } 119 } 120 121 static bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc) 122 { 123 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 124 uint32_t dp_alt_mode_disable = 0; 125 bool is_usb_c_alt_mode = false; 126 127 if (enc->features.flags.bits.DP_IS_USB_C) { 128 /* if value == 1 alt mode is disabled, otherwise it is enabled */ 129 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); 130 is_usb_c_alt_mode = (dp_alt_mode_disable == 0); 131 } 132 133 return is_usb_c_alt_mode; 134 } 135 136 static void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, 137 struct dc_link_settings *link_settings) 138 { 139 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 140 uint32_t is_in_usb_c_dp4_mode = 0; 141 142 dcn10_link_encoder_get_max_link_cap(enc, link_settings); 143 144 /* in usb c dp2 mode, max lane count is 2 */ 145 if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { 146 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); 147 if (!is_in_usb_c_dp4_mode) 148 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); 149 } 150 151 } 152 153 static const struct link_encoder_funcs dcn32_link_enc_funcs = { 154 .read_state = link_enc2_read_state, 155 .validate_output_with_stream = 156 dcn30_link_encoder_validate_output_with_stream, 157 .hw_init = enc32_hw_init, 158 .setup = dcn10_link_encoder_setup, 159 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 160 .enable_dp_output = dcn32_link_encoder_enable_dp_output, 161 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, 162 .disable_output = dcn10_link_encoder_disable_output, 163 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 164 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 165 .update_mst_stream_allocation_table = 166 dcn10_link_encoder_update_mst_stream_allocation_table, 167 .psr_program_dp_dphy_fast_training = 168 dcn10_psr_program_dp_dphy_fast_training, 169 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 170 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 171 .enable_hpd = dcn10_link_encoder_enable_hpd, 172 .disable_hpd = dcn10_link_encoder_disable_hpd, 173 .is_dig_enabled = dcn10_is_dig_enabled, 174 .destroy = dcn10_link_encoder_destroy, 175 .fec_set_enable = enc2_fec_set_enable, 176 .fec_set_ready = enc2_fec_set_ready, 177 .fec_is_active = enc2_fec_is_active, 178 .get_dig_frontend = dcn10_get_dig_frontend, 179 .get_dig_mode = dcn10_get_dig_mode, 180 .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, 181 .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, 182 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, 183 }; 184 185 void dcn32_link_encoder_construct( 186 struct dcn20_link_encoder *enc20, 187 const struct encoder_init_data *init_data, 188 const struct encoder_feature_support *enc_features, 189 const struct dcn10_link_enc_registers *link_regs, 190 const struct dcn10_link_enc_aux_registers *aux_regs, 191 const struct dcn10_link_enc_hpd_registers *hpd_regs, 192 const struct dcn10_link_enc_shift *link_shift, 193 const struct dcn10_link_enc_mask *link_mask) 194 { 195 struct bp_connector_speed_cap_info bp_cap_info = {0}; 196 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 197 enum bp_result result = BP_RESULT_OK; 198 struct dcn10_link_encoder *enc10 = &enc20->enc10; 199 200 enc10->base.funcs = &dcn32_link_enc_funcs; 201 enc10->base.ctx = init_data->ctx; 202 enc10->base.id = init_data->encoder; 203 204 enc10->base.hpd_source = init_data->hpd_source; 205 enc10->base.connector = init_data->connector; 206 207 if (enc10->base.connector.id == CONNECTOR_ID_USBC) 208 enc10->base.features.flags.bits.DP_IS_USB_C = 1; 209 210 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 211 212 enc10->base.features = *enc_features; 213 214 enc10->base.transmitter = init_data->transmitter; 215 216 /* set the flag to indicate whether driver poll the I2C data pin 217 * while doing the DP sink detect 218 */ 219 220 /* if (dal_adapter_service_is_feature_supported(as, 221 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 222 enc10->base.features.flags.bits. 223 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 224 225 enc10->base.output_signals = 226 SIGNAL_TYPE_DVI_SINGLE_LINK | 227 SIGNAL_TYPE_DVI_DUAL_LINK | 228 SIGNAL_TYPE_LVDS | 229 SIGNAL_TYPE_DISPLAY_PORT | 230 SIGNAL_TYPE_DISPLAY_PORT_MST | 231 SIGNAL_TYPE_EDP | 232 SIGNAL_TYPE_HDMI_TYPE_A; 233 234 enc10->link_regs = link_regs; 235 enc10->aux_regs = aux_regs; 236 enc10->hpd_regs = hpd_regs; 237 enc10->link_shift = link_shift; 238 enc10->link_mask = link_mask; 239 240 switch (enc10->base.transmitter) { 241 case TRANSMITTER_UNIPHY_A: 242 enc10->base.preferred_engine = ENGINE_ID_DIGA; 243 break; 244 case TRANSMITTER_UNIPHY_B: 245 enc10->base.preferred_engine = ENGINE_ID_DIGB; 246 break; 247 case TRANSMITTER_UNIPHY_C: 248 enc10->base.preferred_engine = ENGINE_ID_DIGC; 249 break; 250 case TRANSMITTER_UNIPHY_D: 251 enc10->base.preferred_engine = ENGINE_ID_DIGD; 252 break; 253 case TRANSMITTER_UNIPHY_E: 254 enc10->base.preferred_engine = ENGINE_ID_DIGE; 255 break; 256 default: 257 ASSERT_CRITICAL(false); 258 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 259 } 260 261 /* default to one to mirror Windows behavior */ 262 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 263 264 if (bp_funcs->get_connector_speed_cap_info) 265 result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, 266 enc10->base.connector, &bp_cap_info); 267 268 /* Override features with DCE-specific values */ 269 if (result == BP_RESULT_OK) { 270 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 271 bp_cap_info.DP_HBR2_EN; 272 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 273 bp_cap_info.DP_HBR3_EN; 274 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 275 enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; 276 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; 277 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; 278 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; 279 } else { 280 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 281 __func__, 282 result); 283 } 284 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 285 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 286 } 287 } 288