1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 // header file of functions being implemented 27 #include "dcn32_resource.h" 28 #include "dcn20/dcn20_resource.h" 29 #include "dml/dcn32/display_mode_vba_util_32.h" 30 31 static bool is_dual_plane(enum surface_pixel_format format) 32 { 33 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 34 } 35 36 /** 37 * ******************************************************************************************** 38 * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed for SubVP 39 * 40 * This function first checks the bytes required per pixel on the SubVP pipe, then calculates 41 * the total number of pixels required in the SubVP MALL region. These are used to calculate 42 * the number of cache lines used (then number of ways required) for SubVP MCLK switching. 43 * 44 * @param [in] dc: current dc state 45 * @param [in] context: new dc state 46 * 47 * @return: number of ways required for SubVP 48 * 49 * ******************************************************************************************** 50 */ 51 uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_state *context) 52 { 53 uint32_t num_ways = 0; 54 uint32_t bytes_per_pixel = 0; 55 uint32_t cache_lines_used = 0; 56 uint32_t lines_per_way = 0; 57 uint32_t total_cache_lines = 0; 58 uint32_t bytes_in_mall = 0; 59 uint32_t num_mblks = 0; 60 uint32_t cache_lines_per_plane = 0; 61 uint32_t i = 0, j = 0; 62 uint16_t mblk_width = 0; 63 uint16_t mblk_height = 0; 64 uint32_t full_vp_width_blk_aligned = 0; 65 uint32_t full_vp_height_blk_aligned = 0; 66 uint32_t mall_alloc_width_blk_aligned = 0; 67 uint32_t mall_alloc_height_blk_aligned = 0; 68 uint16_t full_vp_height = 0; 69 bool subvp_in_use = false; 70 71 for (i = 0; i < dc->res_pool->pipe_count; i++) { 72 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 73 74 /* Find the phantom pipes. 75 * - For pipe split case we need to loop through the bottom and next ODM 76 * pipes or only half the viewport size is counted 77 */ 78 if (pipe->stream && pipe->plane_state && 79 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 80 struct pipe_ctx *main_pipe = NULL; 81 82 subvp_in_use = true; 83 /* Get full viewport height from main pipe (required for MBLK calculation) */ 84 for (j = 0; j < dc->res_pool->pipe_count; j++) { 85 main_pipe = &context->res_ctx.pipe_ctx[j]; 86 if (main_pipe->stream == pipe->stream->mall_stream_config.paired_stream) { 87 full_vp_height = main_pipe->plane_res.scl_data.viewport.height; 88 break; 89 } 90 } 91 92 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 93 mblk_width = DCN3_2_MBLK_WIDTH; 94 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 95 96 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 97 * FLOOR(vp_x_start, blk_width) 98 */ 99 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 100 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + 101 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 102 103 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 104 * FLOOR(vp_y_start, blk_height) 105 */ 106 full_vp_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 107 full_vp_height + mblk_height - 1) / mblk_height * mblk_height) + 108 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 109 110 /* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */ 111 mall_alloc_width_blk_aligned = full_vp_width_blk_aligned; 112 113 /* mall_alloc_height_blk_aligned_l/c = CEILING(sub_vp_height_l/c - 1, blk_height_l/c) + blk_height_l/c */ 114 mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) / 115 mblk_height * mblk_height + mblk_height; 116 117 /* full_mblk_width_ub_l/c = mall_alloc_width_blk_aligned_l/c; 118 * full_mblk_height_ub_l/c = mall_alloc_height_blk_aligned_l/c; 119 * num_mblk_l/c = (full_mblk_width_ub_l/c / mblk_width_l/c) * (full_mblk_height_ub_l/c / mblk_height_l/c); 120 * (Should be divisible, but round up if not) 121 */ 122 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 123 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 124 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 125 // cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 126 // (MALL is 64-byte aligned) 127 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 128 129 /* For DCC divide by 256 */ 130 if (pipe->plane_state->dcc.enable) 131 cache_lines_per_plane = cache_lines_per_plane + (cache_lines_per_plane / 256) + 1; 132 cache_lines_used += cache_lines_per_plane; 133 } 134 } 135 136 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 137 lines_per_way = total_cache_lines / dc->caps.cache_num_ways; 138 num_ways = cache_lines_used / lines_per_way; 139 if (cache_lines_used % lines_per_way > 0) 140 num_ways++; 141 142 if (subvp_in_use && dc->debug.force_subvp_num_ways > 0) 143 num_ways = dc->debug.force_subvp_num_ways; 144 145 return num_ways; 146 } 147 148 void dcn32_merge_pipes_for_subvp(struct dc *dc, 149 struct dc_state *context) 150 { 151 uint32_t i; 152 153 /* merge pipes if necessary */ 154 for (i = 0; i < dc->res_pool->pipe_count; i++) { 155 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 156 157 // For now merge all pipes for SubVP since pipe split case isn't supported yet 158 159 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 160 if (pipe->prev_odm_pipe) { 161 /*split off odm pipe*/ 162 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 163 if (pipe->next_odm_pipe) 164 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 165 166 pipe->bottom_pipe = NULL; 167 pipe->next_odm_pipe = NULL; 168 pipe->plane_state = NULL; 169 pipe->stream = NULL; 170 pipe->top_pipe = NULL; 171 pipe->prev_odm_pipe = NULL; 172 if (pipe->stream_res.dsc) 173 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 174 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 175 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 176 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 177 struct pipe_ctx *top_pipe = pipe->top_pipe; 178 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 179 180 top_pipe->bottom_pipe = bottom_pipe; 181 if (bottom_pipe) 182 bottom_pipe->top_pipe = top_pipe; 183 184 pipe->top_pipe = NULL; 185 pipe->bottom_pipe = NULL; 186 pipe->plane_state = NULL; 187 pipe->stream = NULL; 188 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 189 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 190 } 191 } 192 } 193 194 bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, 195 struct dc_state *context) 196 { 197 uint32_t i; 198 199 for (i = 0; i < dc->res_pool->pipe_count; i++) { 200 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 201 202 if (!pipe->stream) 203 continue; 204 205 if (!pipe->plane_state) 206 return false; 207 } 208 return true; 209 } 210 211 bool dcn32_subvp_in_use(struct dc *dc, 212 struct dc_state *context) 213 { 214 uint32_t i; 215 216 for (i = 0; i < dc->res_pool->pipe_count; i++) { 217 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 218 219 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) 220 return true; 221 } 222 return false; 223 } 224 225 bool dcn32_mpo_in_use(struct dc_state *context) 226 { 227 uint32_t i; 228 229 for (i = 0; i < context->stream_count; i++) { 230 if (context->stream_status[i].plane_count > 1) 231 return true; 232 } 233 return false; 234 } 235 236 237 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context) 238 { 239 uint32_t i; 240 241 for (i = 0; i < dc->res_pool->pipe_count; i++) { 242 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 243 244 if (!pipe->stream) 245 continue; 246 247 if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0) 248 return true; 249 } 250 return false; 251 } 252 253 /** 254 * ******************************************************************************************* 255 * dcn32_determine_det_override: Determine DET allocation for each pipe 256 * 257 * This function determines how much DET to allocate for each pipe. The total number of 258 * DET segments will be split equally among each of the streams, and after that the DET 259 * segments per stream will be split equally among the planes for the given stream. 260 * 261 * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the 262 * number of DET for that given plane will be split among the pipes driving that plane. 263 * 264 * 265 * High level algorithm: 266 * 1. Split total DET among number of streams 267 * 2. For each stream, split DET among the planes 268 * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation 269 * among those pipes. 270 * 4. Assign the DET override to the DML pipes. 271 * 272 * @param [in]: dc: Current DC state 273 * @param [in]: context: New DC state to be programmed 274 * @param [in]: pipes: Array of DML pipes 275 * 276 * @return: void 277 * 278 * ******************************************************************************************* 279 */ 280 void dcn32_determine_det_override(struct dc *dc, 281 struct dc_state *context, 282 display_e2e_pipe_params_st *pipes) 283 { 284 uint32_t i, j, k; 285 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0}; 286 uint8_t pipe_counted[MAX_PIPES] = {0}; 287 uint8_t pipe_cnt = 0; 288 struct dc_plane_state *current_plane = NULL; 289 uint8_t stream_count = 0; 290 291 for (i = 0; i < context->stream_count; i++) { 292 /* Don't count SubVP streams for DET allocation */ 293 if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { 294 stream_count++; 295 } 296 } 297 298 if (stream_count > 0) { 299 stream_segments = 18 / stream_count; 300 for (i = 0; i < context->stream_count; i++) { 301 if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM) 302 continue; 303 if (context->stream_status[i].plane_count > 0) 304 plane_segments = stream_segments / context->stream_status[i].plane_count; 305 else 306 plane_segments = stream_segments; 307 for (j = 0; j < dc->res_pool->pipe_count; j++) { 308 pipe_plane_count = 0; 309 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] && 310 pipe_counted[j] != 1) { 311 /* Note: pipe_plane_count indicates the number of pipes to be used for a 312 * given plane. e.g. pipe_plane_count = 1 means single pipe (i.e. not split), 313 * pipe_plane_count = 2 means 2:1 split, etc. 314 */ 315 pipe_plane_count++; 316 pipe_counted[j] = 1; 317 current_plane = context->res_ctx.pipe_ctx[j].plane_state; 318 for (k = 0; k < dc->res_pool->pipe_count; k++) { 319 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && 320 context->res_ctx.pipe_ctx[k].plane_state == current_plane) { 321 pipe_plane_count++; 322 pipe_counted[k] = 1; 323 } 324 } 325 326 pipe_segments[j] = plane_segments / pipe_plane_count; 327 for (k = 0; k < dc->res_pool->pipe_count; k++) { 328 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && 329 context->res_ctx.pipe_ctx[k].plane_state == current_plane) { 330 pipe_segments[k] = plane_segments / pipe_plane_count; 331 } 332 } 333 } 334 } 335 } 336 337 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 338 if (!context->res_ctx.pipe_ctx[i].stream) 339 continue; 340 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; 341 pipe_cnt++; 342 } 343 } else { 344 for (i = 0; i < dc->res_pool->pipe_count; i++) 345 pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE 346 } 347 } 348 349 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, 350 display_e2e_pipe_params_st *pipes) 351 { 352 int i, pipe_cnt; 353 struct resource_context *res_ctx = &context->res_ctx; 354 struct pipe_ctx *pipe; 355 356 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 357 358 if (!res_ctx->pipe_ctx[i].stream) 359 continue; 360 361 pipe = &res_ctx->pipe_ctx[i]; 362 pipe_cnt++; 363 } 364 365 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 366 * the DET available for each pipe). Use the DET override input to maintain our driver 367 * policy. 368 */ 369 if (pipe_cnt == 1) { 370 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; 371 if (pipe->plane_state && !dc->debug.disable_z9_mpc && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { 372 if (!is_dual_plane(pipe->plane_state->format)) { 373 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; 374 pipes[0].pipe.src.unbounded_req_mode = true; 375 if (pipe->plane_state->src_rect.width >= 5120 && 376 pipe->plane_state->src_rect.height >= 2880) 377 pipes[0].pipe.src.det_size_override = 320; // 5K or higher 378 } 379 } 380 } else 381 dcn32_determine_det_override(dc, context, pipes); 382 } 383 384 /** 385 * ******************************************************************************************* 386 * dcn32_save_mall_state: Save MALL (SubVP) state for fast validation cases 387 * 388 * This function saves the MALL (SubVP) case for fast validation cases. For fast validation, 389 * there are situations where a shallow copy of the dc->current_state is created for the 390 * validation. In this case we want to save and restore the mall config because we always 391 * teardown subvp at the beginning of validation (and don't attempt to add it back if it's 392 * fast validation). If we don't restore the subvp config in cases of fast validation + 393 * shallow copy of the dc->current_state, the dc->current_state will have a partially 394 * removed subvp state when we did not intend to remove it. 395 * 396 * NOTE: This function ONLY works if the streams are not moved to a different pipe in the 397 * validation. We don't expect this to happen in fast_validation=1 cases. 398 * 399 * @param [in]: dc: Current DC state 400 * @param [in]: context: New DC state to be programmed 401 * @param [out]: temp_config: struct used to cache the existing MALL state 402 * 403 * @return: void 404 * 405 * ******************************************************************************************* 406 */ 407 void dcn32_save_mall_state(struct dc *dc, 408 struct dc_state *context, 409 struct mall_temp_config *temp_config) 410 { 411 uint32_t i; 412 413 for (i = 0; i < dc->res_pool->pipe_count; i++) { 414 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 415 416 if (pipe->stream) 417 temp_config->mall_stream_config[i] = pipe->stream->mall_stream_config; 418 419 if (pipe->plane_state) 420 temp_config->is_phantom_plane[i] = pipe->plane_state->is_phantom; 421 } 422 } 423 424 /** 425 * ******************************************************************************************* 426 * dcn32_restore_mall_state: Restore MALL (SubVP) state for fast validation cases 427 * 428 * Restore the MALL state based on the previously saved state from dcn32_save_mall_state 429 * 430 * @param [in]: dc: Current DC state 431 * @param [in/out]: context: New DC state to be programmed, restore MALL state into here 432 * @param [in]: temp_config: struct that has the cached MALL state 433 * 434 * @return: void 435 * 436 * ******************************************************************************************* 437 */ 438 void dcn32_restore_mall_state(struct dc *dc, 439 struct dc_state *context, 440 struct mall_temp_config *temp_config) 441 { 442 uint32_t i; 443 444 for (i = 0; i < dc->res_pool->pipe_count; i++) { 445 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 446 447 if (pipe->stream) 448 pipe->stream->mall_stream_config = temp_config->mall_stream_config[i]; 449 450 if (pipe->plane_state) 451 pipe->plane_state->is_phantom = temp_config->is_phantom_plane[i]; 452 } 453 } 454