1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dcn35_hubp.h" 28 #include "reg_helper.h" 29 30 #define REG(reg)\ 31 hubp2->hubp_regs->reg 32 33 #define CTX \ 34 hubp2->base.ctx 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 ((const struct dcn35_hubp2_shift *)hubp2->hubp_shift)->field_name, \ 39 ((const struct dcn35_hubp2_mask *)hubp2->hubp_mask)->field_name 40 41 void hubp35_set_fgcg(struct hubp *hubp, bool enable) 42 { 43 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 44 45 REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable); 46 } 47 48 static void hubp35_init(struct hubp *hubp) 49 { 50 hubp3_init(hubp); 51 52 hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub); 53 54 /*do nothing for now for dcn3.5 or later*/ 55 } 56 57 void hubp35_program_pixel_format( 58 struct hubp *hubp, 59 enum surface_pixel_format format) 60 { 61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 62 uint32_t green_bar = 1; 63 uint32_t red_bar = 3; 64 uint32_t blue_bar = 2; 65 66 /* swap for ABGR format */ 67 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 68 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 69 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 70 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 71 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 72 red_bar = 2; 73 blue_bar = 3; 74 } 75 76 REG_UPDATE_3(HUBPRET_CONTROL, 77 CROSSBAR_SRC_Y_G, green_bar, 78 CROSSBAR_SRC_CB_B, blue_bar, 79 CROSSBAR_SRC_CR_R, red_bar); 80 81 /* Mapping is same as ipp programming (cnvc) */ 82 83 switch (format) { 84 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 85 REG_UPDATE(DCSURF_SURFACE_CONFIG, 86 SURFACE_PIXEL_FORMAT, 1); 87 break; 88 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 89 REG_UPDATE(DCSURF_SURFACE_CONFIG, 90 SURFACE_PIXEL_FORMAT, 3); 91 break; 92 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 93 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 94 REG_UPDATE(DCSURF_SURFACE_CONFIG, 95 SURFACE_PIXEL_FORMAT, 8); 96 break; 97 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 98 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 99 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 100 REG_UPDATE(DCSURF_SURFACE_CONFIG, 101 SURFACE_PIXEL_FORMAT, 10); 102 break; 103 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 104 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */ 105 REG_UPDATE(DCSURF_SURFACE_CONFIG, 106 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 107 break; 108 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 109 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 110 REG_UPDATE(DCSURF_SURFACE_CONFIG, 111 SURFACE_PIXEL_FORMAT, 24); 112 break; 113 114 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 115 REG_UPDATE(DCSURF_SURFACE_CONFIG, 116 SURFACE_PIXEL_FORMAT, 65); 117 break; 118 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 119 REG_UPDATE(DCSURF_SURFACE_CONFIG, 120 SURFACE_PIXEL_FORMAT, 64); 121 break; 122 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 123 REG_UPDATE(DCSURF_SURFACE_CONFIG, 124 SURFACE_PIXEL_FORMAT, 67); 125 break; 126 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 127 REG_UPDATE(DCSURF_SURFACE_CONFIG, 128 SURFACE_PIXEL_FORMAT, 66); 129 break; 130 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 131 REG_UPDATE(DCSURF_SURFACE_CONFIG, 132 SURFACE_PIXEL_FORMAT, 12); 133 break; 134 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 135 REG_UPDATE(DCSURF_SURFACE_CONFIG, 136 SURFACE_PIXEL_FORMAT, 112); 137 break; 138 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 139 REG_UPDATE(DCSURF_SURFACE_CONFIG, 140 SURFACE_PIXEL_FORMAT, 113); 141 break; 142 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 143 REG_UPDATE(DCSURF_SURFACE_CONFIG, 144 SURFACE_PIXEL_FORMAT, 114); 145 break; 146 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 147 REG_UPDATE(DCSURF_SURFACE_CONFIG, 148 SURFACE_PIXEL_FORMAT, 118); 149 break; 150 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 151 REG_UPDATE(DCSURF_SURFACE_CONFIG, 152 SURFACE_PIXEL_FORMAT, 119); 153 break; 154 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 155 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 156 SURFACE_PIXEL_FORMAT, 116, 157 ALPHA_PLANE_EN, 0); 158 break; 159 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 160 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 161 SURFACE_PIXEL_FORMAT, 116, 162 ALPHA_PLANE_EN, 1); 163 break; 164 default: 165 BREAK_TO_DEBUGGER(); 166 break; 167 } 168 169 /* don't see the need of program the xbar in DCN 1.0 */ 170 } 171 172 void hubp35_program_surface_config( 173 struct hubp *hubp, 174 enum surface_pixel_format format, 175 union dc_tiling_info *tiling_info, 176 struct plane_size *plane_size, 177 enum dc_rotation_angle rotation, 178 struct dc_plane_dcc_param *dcc, 179 bool horizontal_mirror, 180 unsigned int compat_level) 181 { 182 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 183 184 hubp3_dcc_control_sienna_cichlid(hubp, dcc); 185 hubp3_program_tiling(hubp2, tiling_info, format); 186 hubp2_program_size(hubp, format, plane_size, dcc); 187 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 188 hubp35_program_pixel_format(hubp, format); 189 } 190 191 struct hubp_funcs dcn35_hubp_funcs = { 192 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 193 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 194 .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, 195 .hubp_program_surface_config = hubp35_program_surface_config, 196 .hubp_is_flip_pending = hubp2_is_flip_pending, 197 .hubp_setup = hubp3_setup, 198 .hubp_setup_interdependent = hubp2_setup_interdependent, 199 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, 200 .set_blank = hubp2_set_blank, 201 .dcc_control = hubp3_dcc_control, 202 .mem_program_viewport = min_set_viewport, 203 .set_cursor_attributes = hubp2_cursor_set_attributes, 204 .set_cursor_position = hubp2_cursor_set_position, 205 .hubp_clk_cntl = hubp2_clk_cntl, 206 .hubp_vtg_sel = hubp2_vtg_sel, 207 .dmdata_set_attributes = hubp3_dmdata_set_attributes, 208 .dmdata_load = hubp2_dmdata_load, 209 .dmdata_status_done = hubp2_dmdata_status_done, 210 .hubp_read_state = hubp3_read_state, 211 .hubp_clear_underflow = hubp2_clear_underflow, 212 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 213 .hubp_init = hubp35_init, 214 .set_unbounded_requesting = hubp31_set_unbounded_requesting, 215 .hubp_soft_reset = hubp31_soft_reset, 216 .hubp_set_flip_int = hubp1_set_flip_int, 217 .hubp_in_blank = hubp1_in_blank, 218 .program_extended_blank = hubp31_program_extended_blank_value, 219 }; 220 221 bool hubp35_construct( 222 struct dcn20_hubp *hubp2, 223 struct dc_context *ctx, 224 uint32_t inst, 225 const struct dcn_hubp2_registers *hubp_regs, 226 const struct dcn35_hubp2_shift *hubp_shift, 227 const struct dcn35_hubp2_mask *hubp_mask) 228 { 229 hubp2->base.funcs = &dcn35_hubp_funcs; 230 hubp2->base.ctx = ctx; 231 hubp2->hubp_regs = hubp_regs; 232 hubp2->hubp_shift = (const struct dcn_hubp2_shift *)hubp_shift; 233 hubp2->hubp_mask = (const struct dcn_hubp2_mask *)hubp_mask; 234 hubp2->base.inst = inst; 235 hubp2->base.opp_id = OPP_ID_INVALID; 236 hubp2->base.mpcc_id = 0xf; 237 238 return true; 239 } 240 241 242