1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../display_mode_lib.h" 27 #include "../display_mode_vba.h" 28 #include "display_rq_dlg_calc_20.h" 29 30 // Function: dml20_rq_dlg_get_rq_params 31 // Calculate requestor related parameters that register definition agnostic 32 // (i.e. this layer does try to separate real values from register definition) 33 // Input: 34 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) 35 // Output: 36 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.) 37 // 38 static void dml20_rq_dlg_get_rq_params( 39 struct display_mode_lib *mode_lib, 40 display_rq_params_st * rq_param, 41 const display_pipe_source_params_st pipe_src_param); 42 43 // Function: dml20_rq_dlg_get_dlg_params 44 // Calculate deadline related parameters 45 // 46 static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 47 const display_e2e_pipe_params_st *e2e_pipe_param, 48 const unsigned int num_pipes, 49 const unsigned int pipe_idx, 50 display_dlg_regs_st *disp_dlg_regs, 51 display_ttu_regs_st *disp_ttu_regs, 52 const display_rq_dlg_params_st rq_dlg_param, 53 const display_dlg_sys_params_st dlg_sys_param, 54 const bool cstate_en, 55 const bool pstate_en); 56 /* 57 * NOTE: 58 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 59 * 60 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 61 * ways. Unless there is something clearly wrong with it the code should 62 * remain as-is as it provides us with a guarantee from HW that it is correct. 63 */ 64 65 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 66 double *refcyc_per_req_delivery_pre_cur, 67 double *refcyc_per_req_delivery_cur, 68 double refclk_freq_in_mhz, 69 double ref_freq_to_pix_freq, 70 double hscale_pixel_rate_l, 71 double hscl_ratio, 72 double vratio_pre_l, 73 double vratio_l, 74 unsigned int cur_width, 75 enum cursor_bpp cur_bpp); 76 77 #include "../dml_inline_defs.h" 78 79 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 80 { 81 unsigned int ret_val = 0; 82 83 if (source_format == dm_444_16) { 84 if (!is_chroma) 85 ret_val = 2; 86 } else if (source_format == dm_444_32) { 87 if (!is_chroma) 88 ret_val = 4; 89 } else if (source_format == dm_444_64) { 90 if (!is_chroma) 91 ret_val = 8; 92 } else if (source_format == dm_420_8) { 93 if (is_chroma) 94 ret_val = 2; 95 else 96 ret_val = 1; 97 } else if (source_format == dm_420_10) { 98 if (is_chroma) 99 ret_val = 4; 100 else 101 ret_val = 2; 102 } else if (source_format == dm_444_8) { 103 ret_val = 1; 104 } 105 return ret_val; 106 } 107 108 static bool is_dual_plane(enum source_format_class source_format) 109 { 110 bool ret_val = false; 111 112 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 113 ret_val = true; 114 115 return ret_val; 116 } 117 118 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, 119 double refclk_freq_in_mhz, 120 double pclk_freq_in_mhz, 121 bool odm_combine, 122 unsigned int recout_width, 123 unsigned int hactive, 124 double vratio, 125 double hscale_pixel_rate, 126 unsigned int delivery_width, 127 unsigned int req_per_swath_ub) 128 { 129 double refcyc_per_delivery = 0.0; 130 131 if (vratio <= 1.0) { 132 if (odm_combine) 133 refcyc_per_delivery = (double) refclk_freq_in_mhz 134 * dml_min((double) recout_width, (double) hactive / 2.0) 135 / pclk_freq_in_mhz / (double) req_per_swath_ub; 136 else 137 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 138 / pclk_freq_in_mhz / (double) req_per_swath_ub; 139 } else { 140 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 141 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 142 } 143 144 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 145 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 146 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 147 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 148 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 149 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 150 151 return refcyc_per_delivery; 152 153 } 154 155 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 156 { 157 if (tile_size == dm_256k_tile) 158 return (256 * 1024); 159 else if (tile_size == dm_64k_tile) 160 return (64 * 1024); 161 else 162 return (4 * 1024); 163 } 164 165 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 166 display_data_rq_regs_st *rq_regs, 167 const display_data_rq_sizing_params_st rq_sizing) 168 { 169 dml_print("DML_DLG: %s: rq_sizing param\n", __func__); 170 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 171 172 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; 173 174 if (rq_sizing.min_chunk_bytes == 0) 175 rq_regs->min_chunk_size = 0; 176 else 177 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; 178 179 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; 180 if (rq_sizing.min_meta_chunk_bytes == 0) 181 rq_regs->min_meta_chunk_size = 0; 182 else 183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; 184 185 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; 186 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; 187 } 188 189 static void extract_rq_regs(struct display_mode_lib *mode_lib, 190 display_rq_regs_st *rq_regs, 191 const display_rq_params_st rq_param) 192 { 193 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 194 unsigned int detile_buf_plane1_addr = 0; 195 196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); 197 198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 199 1) - 3; 200 201 if (rq_param.yuv420) { 202 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); 203 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 204 1) - 3; 205 } 206 207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 208 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 209 210 // TODO: take the max between luma, chroma chunk size? 211 // okay for now, as we are setting chunk_bytes to 8kb anyways 212 if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 213 rq_regs->drq_expansion_mode = 0; 214 } else { 215 rq_regs->drq_expansion_mode = 2; 216 } 217 rq_regs->prq_expansion_mode = 1; 218 rq_regs->mrq_expansion_mode = 1; 219 rq_regs->crq_expansion_mode = 1; 220 221 if (rq_param.yuv420) { 222 if ((double) rq_param.misc.rq_l.stored_swath_bytes 223 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 224 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 225 } else { 226 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 227 256, 228 0) / 64.0; // 2/3 to chroma 229 } 230 } 231 rq_regs->plane1_base_address = detile_buf_plane1_addr; 232 } 233 234 static void handle_det_buf_split(struct display_mode_lib *mode_lib, 235 display_rq_params_st *rq_param, 236 const display_pipe_source_params_st pipe_src_param) 237 { 238 unsigned int total_swath_bytes = 0; 239 unsigned int swath_bytes_l = 0; 240 unsigned int swath_bytes_c = 0; 241 unsigned int full_swath_bytes_packed_l = 0; 242 unsigned int full_swath_bytes_packed_c = 0; 243 bool req128_l = false; 244 bool req128_c = false; 245 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 246 bool surf_vert = (pipe_src_param.source_scan == dm_vert); 247 unsigned int log2_swath_height_l = 0; 248 unsigned int log2_swath_height_c = 0; 249 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 250 251 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 252 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 253 254 if (rq_param->yuv420_10bpc) { 255 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 256 256, 257 1) + 256; 258 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 259 256, 260 1) + 256; 261 } 262 263 if (rq_param->yuv420) { 264 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 265 266 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 267 req128_l = false; 268 req128_c = false; 269 swath_bytes_l = full_swath_bytes_packed_l; 270 swath_bytes_c = full_swath_bytes_packed_c; 271 } else { //128b request (for luma only for yuv420 8bpc) 272 req128_l = true; 273 req128_c = false; 274 swath_bytes_l = full_swath_bytes_packed_l / 2; 275 swath_bytes_c = full_swath_bytes_packed_c; 276 } 277 // Note: assumption, the config that pass in will fit into 278 // the detiled buffer. 279 } else { 280 total_swath_bytes = 2 * full_swath_bytes_packed_l; 281 282 if (total_swath_bytes <= detile_buf_size_in_bytes) 283 req128_l = false; 284 else 285 req128_l = true; 286 287 swath_bytes_l = total_swath_bytes; 288 swath_bytes_c = 0; 289 } 290 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 291 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 292 293 if (surf_linear) { 294 log2_swath_height_l = 0; 295 log2_swath_height_c = 0; 296 } else if (!surf_vert) { 297 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l; 298 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c; 299 } else { 300 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l; 301 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c; 302 } 303 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 304 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 305 306 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 307 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 308 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", 309 __func__, 310 full_swath_bytes_packed_l); 311 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", 312 __func__, 313 full_swath_bytes_packed_c); 314 } 315 316 static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, 317 display_data_rq_dlg_params_st *rq_dlg_param, 318 display_data_rq_misc_params_st *rq_misc_param, 319 display_data_rq_sizing_params_st *rq_sizing_param, 320 unsigned int vp_width, 321 unsigned int vp_height, 322 unsigned int data_pitch, 323 unsigned int meta_pitch, 324 unsigned int source_format, 325 unsigned int tiling, 326 unsigned int macro_tile_size, 327 unsigned int source_scan, 328 unsigned int is_chroma) 329 { 330 bool surf_linear = (tiling == dm_sw_linear); 331 bool surf_vert = (source_scan == dm_vert); 332 333 unsigned int bytes_per_element; 334 unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format), 335 false); 336 unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format), 337 true); 338 339 unsigned int blk256_width = 0; 340 unsigned int blk256_height = 0; 341 342 unsigned int blk256_width_y = 0; 343 unsigned int blk256_height_y = 0; 344 unsigned int blk256_width_c = 0; 345 unsigned int blk256_height_c = 0; 346 unsigned int log2_bytes_per_element; 347 unsigned int log2_blk256_width; 348 unsigned int log2_blk256_height; 349 unsigned int blk_bytes; 350 unsigned int log2_blk_bytes; 351 unsigned int log2_blk_height; 352 unsigned int log2_blk_width; 353 unsigned int log2_meta_req_bytes; 354 unsigned int log2_meta_req_height; 355 unsigned int log2_meta_req_width; 356 unsigned int meta_req_width; 357 unsigned int meta_req_height; 358 unsigned int log2_meta_row_height; 359 unsigned int meta_row_width_ub; 360 unsigned int log2_meta_chunk_bytes; 361 unsigned int log2_meta_chunk_height; 362 363 //full sized meta chunk width in unit of data elements 364 unsigned int log2_meta_chunk_width; 365 unsigned int log2_min_meta_chunk_bytes; 366 unsigned int min_meta_chunk_width; 367 unsigned int meta_chunk_width; 368 unsigned int meta_chunk_per_row_int; 369 unsigned int meta_row_remainder; 370 unsigned int meta_chunk_threshold; 371 unsigned int meta_blk_bytes; 372 unsigned int meta_blk_height; 373 unsigned int meta_blk_width; 374 unsigned int meta_surface_bytes; 375 unsigned int vmpg_bytes; 376 unsigned int meta_pte_req_per_frame_ub; 377 unsigned int meta_pte_bytes_per_frame_ub; 378 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 379 const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 380 const unsigned int pde_proc_buffer_size_64k_reqs = 381 mode_lib->ip.pde_proc_buffer_size_64k_reqs; 382 383 unsigned int log2_vmpg_height = 0; 384 unsigned int log2_vmpg_width = 0; 385 unsigned int log2_dpte_req_height_ptes = 0; 386 unsigned int log2_dpte_req_height = 0; 387 unsigned int log2_dpte_req_width = 0; 388 unsigned int log2_dpte_row_height_linear = 0; 389 unsigned int log2_dpte_row_height = 0; 390 unsigned int log2_dpte_group_width = 0; 391 unsigned int dpte_row_width_ub = 0; 392 unsigned int dpte_req_height = 0; 393 unsigned int dpte_req_width = 0; 394 unsigned int dpte_group_width = 0; 395 unsigned int log2_dpte_group_bytes = 0; 396 unsigned int log2_dpte_group_length = 0; 397 unsigned int pde_buf_entries; 398 bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); 399 400 Calculate256BBlockSizes((enum source_format_class)(source_format), 401 (enum dm_swizzle_mode)(tiling), 402 bytes_per_element_y, 403 bytes_per_element_c, 404 &blk256_height_y, 405 &blk256_height_c, 406 &blk256_width_y, 407 &blk256_width_c); 408 409 if (!is_chroma) { 410 blk256_width = blk256_width_y; 411 blk256_height = blk256_height_y; 412 bytes_per_element = bytes_per_element_y; 413 } else { 414 blk256_width = blk256_width_c; 415 blk256_height = blk256_height_c; 416 bytes_per_element = bytes_per_element_c; 417 } 418 419 log2_bytes_per_element = dml_log2(bytes_per_element); 420 421 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 422 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 423 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 424 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 425 426 log2_blk256_width = dml_log2((double) blk256_width); 427 log2_blk256_height = dml_log2((double) blk256_height); 428 blk_bytes = surf_linear ? 429 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 430 log2_blk_bytes = dml_log2((double) blk_bytes); 431 log2_blk_height = 0; 432 log2_blk_width = 0; 433 434 // remember log rule 435 // "+" in log is multiply 436 // "-" in log is divide 437 // "/2" is like square root 438 // blk is vertical biased 439 if (tiling != dm_sw_linear) 440 log2_blk_height = log2_blk256_height 441 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 442 else 443 log2_blk_height = 0; // blk height of 1 444 445 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 446 447 if (!surf_vert) { 448 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 449 + blk256_width; 450 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 451 } else { 452 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) 453 + blk256_height; 454 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 455 } 456 457 if (!surf_vert) 458 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 459 * bytes_per_element; 460 else 461 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 462 * bytes_per_element; 463 464 rq_misc_param->blk256_height = blk256_height; 465 rq_misc_param->blk256_width = blk256_width; 466 467 // ------- 468 // meta 469 // ------- 470 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 471 472 // each 64b meta request for dcn is 8x8 meta elements and 473 // a meta element covers one 256b block of the the data surface. 474 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 475 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 476 - log2_meta_req_height; 477 meta_req_width = 1 << log2_meta_req_width; 478 meta_req_height = 1 << log2_meta_req_height; 479 log2_meta_row_height = 0; 480 meta_row_width_ub = 0; 481 482 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 483 // calculate upper bound of the meta_row_width 484 if (!surf_vert) { 485 log2_meta_row_height = log2_meta_req_height; 486 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 487 + meta_req_width; 488 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 489 } else { 490 log2_meta_row_height = log2_meta_req_width; 491 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 492 + meta_req_height; 493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 494 } 495 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 496 497 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 498 499 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 500 log2_meta_chunk_height = log2_meta_row_height; 501 502 //full sized meta chunk width in unit of data elements 503 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 504 - log2_meta_chunk_height; 505 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 506 min_meta_chunk_width = 1 507 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 508 - log2_meta_chunk_height); 509 meta_chunk_width = 1 << log2_meta_chunk_width; 510 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 511 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 512 meta_chunk_threshold = 0; 513 meta_blk_bytes = 4096; 514 meta_blk_height = blk256_height * 64; 515 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 516 meta_surface_bytes = meta_pitch 517 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) 518 * bytes_per_element / 256; 519 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 520 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 521 8 * vmpg_bytes, 522 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 523 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 524 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 525 526 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 527 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); 528 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 529 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", 530 __func__, 531 meta_pte_req_per_frame_ub); 532 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", 533 __func__, 534 meta_pte_bytes_per_frame_ub); 535 536 if (!surf_vert) 537 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 538 else 539 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 540 541 if (meta_row_remainder <= meta_chunk_threshold) 542 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 543 else 544 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 545 546 // ------ 547 // dpte 548 // ------ 549 if (surf_linear) { 550 log2_vmpg_height = 0; // one line high 551 } else { 552 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 553 } 554 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 555 556 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 557 if (surf_linear) { //one 64B PTE request returns 8 PTEs 558 log2_dpte_req_height_ptes = 0; 559 log2_dpte_req_width = log2_vmpg_width + 3; 560 log2_dpte_req_height = 0; 561 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 562 //one 64B req gives 8x1 PTEs for 4KB tile 563 log2_dpte_req_height_ptes = 0; 564 log2_dpte_req_width = log2_blk_width + 3; 565 log2_dpte_req_height = log2_blk_height + 0; 566 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 567 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 568 log2_dpte_req_height_ptes = 4; 569 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 570 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 571 } else { //64KB page size and must 64KB tile block 572 //one 64B req gives 8x1 PTEs for 64KB tile 573 log2_dpte_req_height_ptes = 0; 574 log2_dpte_req_width = log2_blk_width + 3; 575 log2_dpte_req_height = log2_blk_height + 0; 576 } 577 578 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 579 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 580 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 581 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 582 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 583 dpte_req_height = 1 << log2_dpte_req_height; 584 dpte_req_width = 1 << log2_dpte_req_width; 585 586 // calculate pitch dpte row buffer can hold 587 // round the result down to a power of two. 588 pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; 589 if (surf_linear) { 590 unsigned int dpte_row_height; 591 592 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries 593 / bytes_per_element, 594 dpte_buf_in_pte_reqs 595 * dpte_req_width) 596 / data_pitch), 597 1); 598 599 ASSERT(log2_dpte_row_height_linear >= 3); 600 601 if (log2_dpte_row_height_linear > 7) 602 log2_dpte_row_height_linear = 7; 603 604 log2_dpte_row_height = log2_dpte_row_height_linear; 605 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 606 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 607 dpte_row_height = 1 << log2_dpte_row_height; 608 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, 609 dpte_req_width, 610 1) + dpte_req_width; 611 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 612 } else { 613 // the upper bound of the dpte_row_width without dependency on viewport position follows. 614 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 615 if (!surf_vert) { 616 log2_dpte_row_height = log2_dpte_req_height; 617 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 618 + dpte_req_width; 619 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 620 } else { 621 log2_dpte_row_height = 622 (log2_blk_width < log2_dpte_req_width) ? 623 log2_blk_width : log2_dpte_req_width; 624 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 625 + dpte_req_height; 626 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 627 } 628 } 629 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 630 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 631 else 632 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 633 634 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 635 636 // the dpte_group_bytes is reduced for the specific case of vertical 637 // access of a tile surface that has dpte request of 8x1 ptes. 638 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group 639 rq_sizing_param->dpte_group_bytes = 512; 640 else 641 //full size 642 rq_sizing_param->dpte_group_bytes = 2048; 643 644 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 645 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 646 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 647 648 // full sized data pte group width in elements 649 if (!surf_vert) 650 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 651 else 652 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 653 654 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 655 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 656 log2_dpte_group_width = log2_dpte_group_width - 1; 657 658 dpte_group_width = 1 << log2_dpte_group_width; 659 660 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 661 // the upper bound for the dpte groups per row is as follows. 662 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 663 1); 664 } 665 666 static void get_surf_rq_param(struct display_mode_lib *mode_lib, 667 display_data_rq_sizing_params_st *rq_sizing_param, 668 display_data_rq_dlg_params_st *rq_dlg_param, 669 display_data_rq_misc_params_st *rq_misc_param, 670 const display_pipe_source_params_st pipe_src_param, 671 bool is_chroma) 672 { 673 bool mode_422 = false; 674 unsigned int vp_width = 0; 675 unsigned int vp_height = 0; 676 unsigned int data_pitch = 0; 677 unsigned int meta_pitch = 0; 678 unsigned int ppe = mode_422 ? 2 : 1; 679 680 // TODO check if ppe apply for both luma and chroma in 422 case 681 if (is_chroma) { 682 vp_width = pipe_src_param.viewport_width_c / ppe; 683 vp_height = pipe_src_param.viewport_height_c; 684 data_pitch = pipe_src_param.data_pitch_c; 685 meta_pitch = pipe_src_param.meta_pitch_c; 686 } else { 687 vp_width = pipe_src_param.viewport_width / ppe; 688 vp_height = pipe_src_param.viewport_height; 689 data_pitch = pipe_src_param.data_pitch; 690 meta_pitch = pipe_src_param.meta_pitch; 691 } 692 693 rq_sizing_param->chunk_bytes = 8192; 694 695 if (rq_sizing_param->chunk_bytes == 64 * 1024) 696 rq_sizing_param->min_chunk_bytes = 0; 697 else 698 rq_sizing_param->min_chunk_bytes = 1024; 699 700 rq_sizing_param->meta_chunk_bytes = 2048; 701 rq_sizing_param->min_meta_chunk_bytes = 256; 702 703 rq_sizing_param->mpte_group_bytes = 2048; 704 705 get_meta_and_pte_attr(mode_lib, 706 rq_dlg_param, 707 rq_misc_param, 708 rq_sizing_param, 709 vp_width, 710 vp_height, 711 data_pitch, 712 meta_pitch, 713 pipe_src_param.source_format, 714 pipe_src_param.sw_mode, 715 pipe_src_param.macro_tile_size, 716 pipe_src_param.source_scan, 717 is_chroma); 718 } 719 720 static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 721 display_rq_params_st *rq_param, 722 const display_pipe_source_params_st pipe_src_param) 723 { 724 // get param for luma surface 725 rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 726 || pipe_src_param.source_format == dm_420_10; 727 rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; 728 729 get_surf_rq_param(mode_lib, 730 &(rq_param->sizing.rq_l), 731 &(rq_param->dlg.rq_l), 732 &(rq_param->misc.rq_l), 733 pipe_src_param, 734 0); 735 736 if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) { 737 // get param for chroma surface 738 get_surf_rq_param(mode_lib, 739 &(rq_param->sizing.rq_c), 740 &(rq_param->dlg.rq_c), 741 &(rq_param->misc.rq_c), 742 pipe_src_param, 743 1); 744 } 745 746 // calculate how to split the det buffer space between luma and chroma 747 handle_det_buf_split(mode_lib, rq_param, pipe_src_param); 748 print__rq_params_st(mode_lib, *rq_param); 749 } 750 751 void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 752 display_rq_regs_st *rq_regs, 753 const display_pipe_params_st pipe_param) 754 { 755 display_rq_params_st rq_param = {0}; 756 757 memset(rq_regs, 0, sizeof(*rq_regs)); 758 dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src); 759 extract_rq_regs(mode_lib, rq_regs, rq_param); 760 761 print__rq_regs_st(mode_lib, *rq_regs); 762 } 763 764 // Note: currently taken in as is. 765 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 766 static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 767 const display_e2e_pipe_params_st *e2e_pipe_param, 768 const unsigned int num_pipes, 769 const unsigned int pipe_idx, 770 display_dlg_regs_st *disp_dlg_regs, 771 display_ttu_regs_st *disp_ttu_regs, 772 const display_rq_dlg_params_st rq_dlg_param, 773 const display_dlg_sys_params_st dlg_sys_param, 774 const bool cstate_en, 775 const bool pstate_en) 776 { 777 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 778 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 779 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 780 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 781 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 782 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 783 784 // ------------------------- 785 // Section 1.15.2.1: OTG dependent Params 786 // ------------------------- 787 // Timing 788 unsigned int htotal = dst->htotal; 789 // unsigned int hblank_start = dst.hblank_start; // TODO: Remove 790 unsigned int hblank_end = dst->hblank_end; 791 unsigned int vblank_start = dst->vblank_start; 792 unsigned int vblank_end = dst->vblank_end; 793 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 794 795 double dppclk_freq_in_mhz = clks->dppclk_mhz; 796 double dispclk_freq_in_mhz = clks->dispclk_mhz; 797 double refclk_freq_in_mhz = clks->refclk_mhz; 798 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 799 bool interlaced = dst->interlaced; 800 801 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 802 803 double min_dcfclk_mhz; 804 double t_calc_us; 805 double min_ttu_vblank; 806 807 double min_dst_y_ttu_vblank; 808 unsigned int dlg_vblank_start; 809 bool dual_plane; 810 bool mode_422; 811 unsigned int access_dir; 812 unsigned int vp_height_l; 813 unsigned int vp_width_l; 814 unsigned int vp_height_c; 815 unsigned int vp_width_c; 816 817 // Scaling 818 unsigned int htaps_l; 819 unsigned int htaps_c; 820 double hratio_l; 821 double hratio_c; 822 double vratio_l; 823 double vratio_c; 824 bool scl_enable; 825 826 double line_time_in_us; 827 // double vinit_l; 828 // double vinit_c; 829 // double vinit_bot_l; 830 // double vinit_bot_c; 831 832 // unsigned int swath_height_l; 833 unsigned int swath_width_ub_l; 834 // unsigned int dpte_bytes_per_row_ub_l; 835 unsigned int dpte_groups_per_row_ub_l; 836 // unsigned int meta_pte_bytes_per_frame_ub_l; 837 // unsigned int meta_bytes_per_row_ub_l; 838 839 // unsigned int swath_height_c; 840 unsigned int swath_width_ub_c; 841 // unsigned int dpte_bytes_per_row_ub_c; 842 unsigned int dpte_groups_per_row_ub_c; 843 844 unsigned int meta_chunks_per_row_ub_l; 845 unsigned int meta_chunks_per_row_ub_c; 846 unsigned int vupdate_offset; 847 unsigned int vupdate_width; 848 unsigned int vready_offset; 849 850 unsigned int dppclk_delay_subtotal; 851 unsigned int dispclk_delay_subtotal; 852 unsigned int pixel_rate_delay_subtotal; 853 854 unsigned int vstartup_start; 855 unsigned int dst_x_after_scaler; 856 unsigned int dst_y_after_scaler; 857 double line_wait; 858 double dst_y_prefetch; 859 double dst_y_per_vm_vblank; 860 double dst_y_per_row_vblank; 861 double dst_y_per_vm_flip; 862 double dst_y_per_row_flip; 863 double min_dst_y_per_vm_vblank; 864 double min_dst_y_per_row_vblank; 865 double lsw; 866 double vratio_pre_l; 867 double vratio_pre_c; 868 unsigned int req_per_swath_ub_l; 869 unsigned int req_per_swath_ub_c; 870 unsigned int meta_row_height_l; 871 unsigned int meta_row_height_c; 872 unsigned int swath_width_pixels_ub_l; 873 unsigned int swath_width_pixels_ub_c; 874 unsigned int scaler_rec_in_width_l; 875 unsigned int scaler_rec_in_width_c; 876 unsigned int dpte_row_height_l; 877 unsigned int dpte_row_height_c; 878 double hscale_pixel_rate_l; 879 double hscale_pixel_rate_c; 880 double min_hratio_fact_l; 881 double min_hratio_fact_c; 882 double refcyc_per_line_delivery_pre_l; 883 double refcyc_per_line_delivery_pre_c; 884 double refcyc_per_line_delivery_l; 885 double refcyc_per_line_delivery_c; 886 887 double refcyc_per_req_delivery_pre_l; 888 double refcyc_per_req_delivery_pre_c; 889 double refcyc_per_req_delivery_l; 890 double refcyc_per_req_delivery_c; 891 892 unsigned int full_recout_width; 893 double xfc_transfer_delay; 894 double xfc_precharge_delay; 895 double xfc_remote_surface_flip_latency; 896 double xfc_dst_y_delta_drq_limit; 897 double xfc_prefetch_margin; 898 double refcyc_per_req_delivery_pre_cur0; 899 double refcyc_per_req_delivery_cur0; 900 double refcyc_per_req_delivery_pre_cur1; 901 double refcyc_per_req_delivery_cur1; 902 903 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 904 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 905 906 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 907 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 908 909 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 910 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); 911 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 912 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 913 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 914 ASSERT(ref_freq_to_pix_freq < 4.0); 915 916 disp_dlg_regs->ref_freq_to_pix_freq = 917 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 918 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 919 * dml_pow(2, 8)); 920 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 921 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 922 * (double) ref_freq_to_pix_freq); 923 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 924 925 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 926 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 927 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 928 929 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 930 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 931 932 disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2)); 933 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 934 935 dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", 936 __func__, 937 min_dcfclk_mhz); 938 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n", 939 __func__, 940 min_ttu_vblank); 941 dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", 942 __func__, 943 min_dst_y_ttu_vblank); 944 dml_print("DML_DLG: %s: t_calc_us = %3.2f\n", 945 __func__, 946 t_calc_us); 947 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", 948 __func__, 949 disp_dlg_regs->min_dst_y_next_start); 950 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", 951 __func__, 952 ref_freq_to_pix_freq); 953 954 // ------------------------- 955 // Section 1.15.2.2: Prefetch, Active and TTU 956 // ------------------------- 957 // Prefetch Calc 958 // Source 959 // dcc_en = src.dcc; 960 dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); 961 mode_422 = false; // TODO 962 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 963 // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); 964 // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); 965 vp_height_l = src->viewport_height; 966 vp_width_l = src->viewport_width; 967 vp_height_c = src->viewport_height_c; 968 vp_width_c = src->viewport_width_c; 969 970 // Scaling 971 htaps_l = taps->htaps; 972 htaps_c = taps->htaps_c; 973 hratio_l = scl->hscl_ratio; 974 hratio_c = scl->hscl_ratio_c; 975 vratio_l = scl->vscl_ratio; 976 vratio_c = scl->vscl_ratio_c; 977 scl_enable = scl->scl_enable; 978 979 line_time_in_us = (htotal / pclk_freq_in_mhz); 980 // vinit_l = scl.vinit; 981 // vinit_c = scl.vinit_c; 982 // vinit_bot_l = scl.vinit_bot; 983 // vinit_bot_c = scl.vinit_bot_c; 984 985 // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height; 986 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 987 // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; 988 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 989 // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; 990 // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; 991 992 // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height; 993 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 994 // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; 995 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 996 997 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 998 meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 999 vupdate_offset = dst->vupdate_offset; 1000 vupdate_width = dst->vupdate_width; 1001 vready_offset = dst->vready_offset; 1002 1003 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1004 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1005 1006 if (scl_enable) 1007 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; 1008 else 1009 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; 1010 1011 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter 1012 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; 1013 1014 if (dout->dsc_enable) { 1015 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1016 1017 dispclk_delay_subtotal += dsc_delay; 1018 } 1019 1020 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1021 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1022 1023 vstartup_start = dst->vstartup_start; 1024 if (interlaced) { 1025 if (vstartup_start / 2.0 1026 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1027 <= vblank_end / 2.0) 1028 disp_dlg_regs->vready_after_vcount0 = 1; 1029 else 1030 disp_dlg_regs->vready_after_vcount0 = 0; 1031 } else { 1032 if (vstartup_start 1033 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1034 <= vblank_end) 1035 disp_dlg_regs->vready_after_vcount0 = 1; 1036 else 1037 disp_dlg_regs->vready_after_vcount0 = 0; 1038 } 1039 1040 // TODO: Where is this coming from? 1041 if (interlaced) 1042 vstartup_start = vstartup_start / 2; 1043 1044 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? 1045 if (vstartup_start >= min_vblank) { 1046 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", 1047 __func__, 1048 vblank_start, 1049 vblank_end); 1050 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1051 __func__, 1052 vstartup_start, 1053 min_vblank); 1054 min_vblank = vstartup_start + 1; 1055 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1056 __func__, 1057 vstartup_start, 1058 min_vblank); 1059 } 1060 1061 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1062 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1063 1064 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1065 dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", 1066 __func__, 1067 pixel_rate_delay_subtotal); 1068 dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n", 1069 __func__, 1070 dst_x_after_scaler); 1071 dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n", 1072 __func__, 1073 dst_y_after_scaler); 1074 1075 // Lwait 1076 line_wait = mode_lib->soc.urgent_latency_us; 1077 if (cstate_en) 1078 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1079 if (pstate_en) 1080 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us 1081 + mode_lib->soc.urgent_latency_us, 1082 line_wait); 1083 line_wait = line_wait / line_time_in_us; 1084 1085 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1086 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1087 1088 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, 1089 e2e_pipe_param, 1090 num_pipes, 1091 pipe_idx); 1092 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, 1093 e2e_pipe_param, 1094 num_pipes, 1095 pipe_idx); 1096 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1097 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1098 1099 min_dst_y_per_vm_vblank = 8.0; 1100 min_dst_y_per_row_vblank = 16.0; 1101 1102 // magic! 1103 if (htotal <= 75) { 1104 min_vblank = 300; 1105 min_dst_y_per_vm_vblank = 100.0; 1106 min_dst_y_per_row_vblank = 100.0; 1107 } 1108 1109 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1110 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1111 1112 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); 1113 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); 1114 1115 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1116 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1117 1118 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); 1119 1120 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1121 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1122 1123 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); 1124 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1125 1126 // Active 1127 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1128 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1129 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1130 meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1131 swath_width_pixels_ub_l = 0; 1132 swath_width_pixels_ub_c = 0; 1133 scaler_rec_in_width_l = 0; 1134 scaler_rec_in_width_c = 0; 1135 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1136 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1137 1138 if (mode_422) { 1139 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element 1140 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1141 } else { 1142 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1143 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1144 } 1145 1146 hscale_pixel_rate_l = 0.; 1147 hscale_pixel_rate_c = 0.; 1148 min_hratio_fact_l = 1.0; 1149 min_hratio_fact_c = 1.0; 1150 1151 if (htaps_l <= 1) 1152 min_hratio_fact_l = 2.0; 1153 else if (htaps_l <= 6) { 1154 if ((hratio_l * 2.0) > 4.0) 1155 min_hratio_fact_l = 4.0; 1156 else 1157 min_hratio_fact_l = hratio_l * 2.0; 1158 } else { 1159 if (hratio_l > 4.0) 1160 min_hratio_fact_l = 4.0; 1161 else 1162 min_hratio_fact_l = hratio_l; 1163 } 1164 1165 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1166 1167 if (htaps_c <= 1) 1168 min_hratio_fact_c = 2.0; 1169 else if (htaps_c <= 6) { 1170 if ((hratio_c * 2.0) > 4.0) 1171 min_hratio_fact_c = 4.0; 1172 else 1173 min_hratio_fact_c = hratio_c * 2.0; 1174 } else { 1175 if (hratio_c > 4.0) 1176 min_hratio_fact_c = 4.0; 1177 else 1178 min_hratio_fact_c = hratio_c; 1179 } 1180 1181 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1182 1183 refcyc_per_line_delivery_pre_l = 0.; 1184 refcyc_per_line_delivery_pre_c = 0.; 1185 refcyc_per_line_delivery_l = 0.; 1186 refcyc_per_line_delivery_c = 0.; 1187 1188 refcyc_per_req_delivery_pre_l = 0.; 1189 refcyc_per_req_delivery_pre_c = 0.; 1190 refcyc_per_req_delivery_l = 0.; 1191 refcyc_per_req_delivery_c = 0.; 1192 1193 full_recout_width = 0; 1194 // In ODM 1195 if (src->is_hsplit) { 1196 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1197 // combine, you MUST specify the full_recout_width...according to Oswin 1198 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1199 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", 1200 __func__); 1201 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1202 } else 1203 full_recout_width = dst->full_recout_width; 1204 } else 1205 full_recout_width = dst->recout_width; 1206 1207 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1208 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1209 refclk_freq_in_mhz, 1210 pclk_freq_in_mhz, 1211 dst->odm_combine, 1212 full_recout_width, 1213 dst->hactive, 1214 vratio_pre_l, 1215 hscale_pixel_rate_l, 1216 swath_width_pixels_ub_l, 1217 1); // per line 1218 1219 refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, 1220 refclk_freq_in_mhz, 1221 pclk_freq_in_mhz, 1222 dst->odm_combine, 1223 full_recout_width, 1224 dst->hactive, 1225 vratio_l, 1226 hscale_pixel_rate_l, 1227 swath_width_pixels_ub_l, 1228 1); // per line 1229 1230 dml_print("DML_DLG: %s: full_recout_width = %d\n", 1231 __func__, 1232 full_recout_width); 1233 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", 1234 __func__, 1235 hscale_pixel_rate_l); 1236 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1237 __func__, 1238 refcyc_per_line_delivery_pre_l); 1239 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", 1240 __func__, 1241 refcyc_per_line_delivery_l); 1242 1243 if (dual_plane) { 1244 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1245 refclk_freq_in_mhz, 1246 pclk_freq_in_mhz, 1247 dst->odm_combine, 1248 full_recout_width, 1249 dst->hactive, 1250 vratio_pre_c, 1251 hscale_pixel_rate_c, 1252 swath_width_pixels_ub_c, 1253 1); // per line 1254 1255 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, 1256 refclk_freq_in_mhz, 1257 pclk_freq_in_mhz, 1258 dst->odm_combine, 1259 full_recout_width, 1260 dst->hactive, 1261 vratio_c, 1262 hscale_pixel_rate_c, 1263 swath_width_pixels_ub_c, 1264 1); // per line 1265 1266 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 1267 __func__, 1268 refcyc_per_line_delivery_pre_c); 1269 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 1270 __func__, 1271 refcyc_per_line_delivery_c); 1272 } 1273 1274 // TTU - Luma / Chroma 1275 if (access_dir) { // vertical access 1276 scaler_rec_in_width_l = vp_height_l; 1277 scaler_rec_in_width_c = vp_height_c; 1278 } else { 1279 scaler_rec_in_width_l = vp_width_l; 1280 scaler_rec_in_width_c = vp_width_c; 1281 } 1282 1283 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1284 refclk_freq_in_mhz, 1285 pclk_freq_in_mhz, 1286 dst->odm_combine, 1287 full_recout_width, 1288 dst->hactive, 1289 vratio_pre_l, 1290 hscale_pixel_rate_l, 1291 scaler_rec_in_width_l, 1292 req_per_swath_ub_l); // per req 1293 refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, 1294 refclk_freq_in_mhz, 1295 pclk_freq_in_mhz, 1296 dst->odm_combine, 1297 full_recout_width, 1298 dst->hactive, 1299 vratio_l, 1300 hscale_pixel_rate_l, 1301 scaler_rec_in_width_l, 1302 req_per_swath_ub_l); // per req 1303 1304 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", 1305 __func__, 1306 refcyc_per_req_delivery_pre_l); 1307 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", 1308 __func__, 1309 refcyc_per_req_delivery_l); 1310 1311 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1312 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1313 1314 if (dual_plane) { 1315 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1316 refclk_freq_in_mhz, 1317 pclk_freq_in_mhz, 1318 dst->odm_combine, 1319 full_recout_width, 1320 dst->hactive, 1321 vratio_pre_c, 1322 hscale_pixel_rate_c, 1323 scaler_rec_in_width_c, 1324 req_per_swath_ub_c); // per req 1325 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, 1326 refclk_freq_in_mhz, 1327 pclk_freq_in_mhz, 1328 dst->odm_combine, 1329 full_recout_width, 1330 dst->hactive, 1331 vratio_c, 1332 hscale_pixel_rate_c, 1333 scaler_rec_in_width_c, 1334 req_per_swath_ub_c); // per req 1335 1336 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 1337 __func__, 1338 refcyc_per_req_delivery_pre_c); 1339 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", 1340 __func__, 1341 refcyc_per_req_delivery_c); 1342 1343 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1344 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1345 } 1346 1347 // XFC 1348 xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1349 xfc_precharge_delay = get_xfc_precharge_delay(mode_lib, 1350 e2e_pipe_param, 1351 num_pipes, 1352 pipe_idx); 1353 xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib, 1354 e2e_pipe_param, 1355 num_pipes, 1356 pipe_idx); 1357 xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency; 1358 xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib, 1359 e2e_pipe_param, 1360 num_pipes, 1361 pipe_idx); 1362 1363 // TTU - Cursor 1364 refcyc_per_req_delivery_pre_cur0 = 0.0; 1365 refcyc_per_req_delivery_cur0 = 0.0; 1366 if (src->num_cursors > 0) { 1367 calculate_ttu_cursor(mode_lib, 1368 &refcyc_per_req_delivery_pre_cur0, 1369 &refcyc_per_req_delivery_cur0, 1370 refclk_freq_in_mhz, 1371 ref_freq_to_pix_freq, 1372 hscale_pixel_rate_l, 1373 scl->hscl_ratio, 1374 vratio_pre_l, 1375 vratio_l, 1376 src->cur0_src_width, 1377 (enum cursor_bpp)(src->cur0_bpp)); 1378 } 1379 1380 refcyc_per_req_delivery_pre_cur1 = 0.0; 1381 refcyc_per_req_delivery_cur1 = 0.0; 1382 if (src->num_cursors > 1) { 1383 calculate_ttu_cursor(mode_lib, 1384 &refcyc_per_req_delivery_pre_cur1, 1385 &refcyc_per_req_delivery_cur1, 1386 refclk_freq_in_mhz, 1387 ref_freq_to_pix_freq, 1388 hscale_pixel_rate_l, 1389 scl->hscl_ratio, 1390 vratio_pre_l, 1391 vratio_l, 1392 src->cur1_src_width, 1393 (enum cursor_bpp)(src->cur1_bpp)); 1394 } 1395 1396 // TTU - Misc 1397 // all hard-coded 1398 1399 // Assignment to register structures 1400 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1401 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1402 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1403 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1404 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1405 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1406 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 1407 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 1408 1409 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1410 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1411 1412 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1413 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1414 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1415 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); 1416 1417 if (dual_plane) { 1418 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank 1419 * (double) htotal * ref_freq_to_pix_freq 1420 / (double) dpte_groups_per_row_ub_c); 1421 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c 1422 < (unsigned int) dml_pow(2, 13)); 1423 } 1424 1425 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1426 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1427 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1428 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); 1429 1430 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1431 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1432 1433 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1434 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1435 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1436 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1437 1438 if (dual_plane) { 1439 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip 1440 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1441 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip 1442 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1443 } 1444 1445 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1446 / (double) vratio_l * dml_pow(2, 2)); 1447 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); 1448 1449 if (dual_plane) { 1450 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1451 / (double) vratio_c * dml_pow(2, 2)); 1452 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 1453 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1454 __func__, 1455 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1456 (unsigned int) dml_pow(2, 17) - 1); 1457 } 1458 } 1459 1460 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1461 / (double) vratio_l * dml_pow(2, 2)); 1462 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); 1463 1464 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1465 1466 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1467 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1468 / (double) dpte_groups_per_row_ub_l); 1469 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1470 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1471 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1472 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1473 / (double) meta_chunks_per_row_ub_l); 1474 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1475 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1476 1477 if (dual_plane) { 1478 disp_dlg_regs->refcyc_per_pte_group_nom_c = 1479 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c 1480 * (double) htotal * ref_freq_to_pix_freq 1481 / (double) dpte_groups_per_row_ub_c); 1482 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1483 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1484 1485 // TODO: Is this the right calculation? Does htotal need to be halved? 1486 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = 1487 (unsigned int) ((double) meta_row_height_c / (double) vratio_c 1488 * (double) htotal * ref_freq_to_pix_freq 1489 / (double) meta_chunks_per_row_ub_c); 1490 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 1491 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1492 } 1493 1494 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1495 1); 1496 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1497 1); 1498 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); 1499 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); 1500 1501 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1502 1); 1503 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1504 1); 1505 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); 1506 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); 1507 1508 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1509 disp_dlg_regs->dst_y_offset_cur0 = 0; 1510 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1511 disp_dlg_regs->dst_y_offset_cur1 = 0; 1512 1513 disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; 1514 disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; 1515 disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; 1516 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz, 1517 1); 1518 1519 // slave has to have this value also set to off 1520 if (src->xfc_enable && !src->xfc_slave) 1521 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); 1522 else 1523 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1524 1525 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1526 * dml_pow(2, 10)); 1527 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1528 * dml_pow(2, 10)); 1529 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c 1530 * dml_pow(2, 10)); 1531 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1532 * dml_pow(2, 10)); 1533 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1534 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1535 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 1536 * dml_pow(2, 10)); 1537 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = 1538 (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1539 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 1540 * dml_pow(2, 10)); 1541 disp_ttu_regs->qos_level_low_wm = 0; 1542 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1543 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1544 * ref_freq_to_pix_freq); 1545 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/ 1546 1547 disp_ttu_regs->qos_level_flip = 14; 1548 disp_ttu_regs->qos_level_fixed_l = 8; 1549 disp_ttu_regs->qos_level_fixed_c = 8; 1550 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1551 disp_ttu_regs->qos_ramp_disable_l = 0; 1552 disp_ttu_regs->qos_ramp_disable_c = 0; 1553 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1554 1555 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1556 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1557 1558 print__ttu_regs_st(mode_lib, *disp_ttu_regs); 1559 print__dlg_regs_st(mode_lib, *disp_dlg_regs); 1560 } 1561 1562 void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 1563 display_dlg_regs_st *dlg_regs, 1564 display_ttu_regs_st *ttu_regs, 1565 display_e2e_pipe_params_st *e2e_pipe_param, 1566 const unsigned int num_pipes, 1567 const unsigned int pipe_idx, 1568 const bool cstate_en, 1569 const bool pstate_en, 1570 const bool vm_en, 1571 const bool ignore_viewport_pos, 1572 const bool immediate_flip_support) 1573 { 1574 display_rq_params_st rq_param = {0}; 1575 display_dlg_sys_params_st dlg_sys_param = {0}; 1576 1577 // Get watermark and Tex. 1578 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1579 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, 1580 e2e_pipe_param, 1581 num_pipes); 1582 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1583 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1584 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1585 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1586 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, 1587 e2e_pipe_param, 1588 num_pipes); 1589 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, 1590 e2e_pipe_param, 1591 num_pipes); 1592 dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency 1593 / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated 1594 1595 print__dlg_sys_params_st(mode_lib, dlg_sys_param); 1596 1597 // system parameter calculation done 1598 1599 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1600 dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); 1601 dml20_rq_dlg_get_dlg_params(mode_lib, 1602 e2e_pipe_param, 1603 num_pipes, 1604 pipe_idx, 1605 dlg_regs, 1606 ttu_regs, 1607 rq_param.dlg, 1608 dlg_sys_param, 1609 cstate_en, 1610 pstate_en); 1611 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1612 } 1613 1614 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 1615 double *refcyc_per_req_delivery_pre_cur, 1616 double *refcyc_per_req_delivery_cur, 1617 double refclk_freq_in_mhz, 1618 double ref_freq_to_pix_freq, 1619 double hscale_pixel_rate_l, 1620 double hscl_ratio, 1621 double vratio_pre_l, 1622 double vratio_l, 1623 unsigned int cur_width, 1624 enum cursor_bpp cur_bpp) 1625 { 1626 unsigned int cur_src_width = cur_width; 1627 unsigned int cur_req_size = 0; 1628 unsigned int cur_req_width = 0; 1629 double cur_width_ub = 0.0; 1630 double cur_req_per_width = 0.0; 1631 double hactive_cur = 0.0; 1632 1633 ASSERT(cur_src_width <= 256); 1634 1635 *refcyc_per_req_delivery_pre_cur = 0.0; 1636 *refcyc_per_req_delivery_cur = 0.0; 1637 if (cur_src_width > 0) { 1638 unsigned int cur_bit_per_pixel = 0; 1639 1640 if (cur_bpp == dm_cur_2bit) { 1641 cur_req_size = 64; // byte 1642 cur_bit_per_pixel = 2; 1643 } else { // 32bit 1644 cur_bit_per_pixel = 32; 1645 if (cur_src_width >= 1 && cur_src_width <= 16) 1646 cur_req_size = 64; 1647 else if (cur_src_width >= 17 && cur_src_width <= 31) 1648 cur_req_size = 128; 1649 else 1650 cur_req_size = 256; 1651 } 1652 1653 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); 1654 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) 1655 * (double) cur_req_width; 1656 cur_req_per_width = cur_width_ub / (double) cur_req_width; 1657 hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor 1658 1659 if (vratio_pre_l <= 1.0) { 1660 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq 1661 / (double) cur_req_per_width; 1662 } else { 1663 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz 1664 * (double) cur_src_width / hscale_pixel_rate_l 1665 / (double) cur_req_per_width; 1666 } 1667 1668 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 1669 1670 if (vratio_l <= 1.0) { 1671 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq 1672 / (double) cur_req_per_width; 1673 } else { 1674 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz 1675 * (double) cur_src_width / hscale_pixel_rate_l 1676 / (double) cur_req_per_width; 1677 } 1678 1679 dml_print("DML_DLG: %s: cur_req_width = %d\n", 1680 __func__, 1681 cur_req_width); 1682 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", 1683 __func__, 1684 cur_width_ub); 1685 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", 1686 __func__, 1687 cur_req_per_width); 1688 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", 1689 __func__, 1690 hactive_cur); 1691 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", 1692 __func__, 1693 *refcyc_per_req_delivery_pre_cur); 1694 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", 1695 __func__, 1696 *refcyc_per_req_delivery_cur); 1697 1698 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1699 } 1700 } 1701