1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 27 28 #include "../display_mode_lib.h" 29 #include "../display_mode_vba.h" 30 #include "../dml_inline_defs.h" 31 #include "display_rq_dlg_calc_21.h" 32 33 /* 34 * NOTE: 35 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 36 * 37 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 38 * ways. Unless there is something clearly wrong with it the code should 39 * remain as-is as it provides us with a guarantee from HW that it is correct. 40 */ 41 42 static void calculate_ttu_cursor( 43 struct display_mode_lib *mode_lib, 44 double *refcyc_per_req_delivery_pre_cur, 45 double *refcyc_per_req_delivery_cur, 46 double refclk_freq_in_mhz, 47 double ref_freq_to_pix_freq, 48 double hscale_pixel_rate_l, 49 double hscl_ratio, 50 double vratio_pre_l, 51 double vratio_l, 52 unsigned int cur_width, 53 enum cursor_bpp cur_bpp); 54 55 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 56 { 57 unsigned int ret_val = 0; 58 59 if (source_format == dm_444_16) { 60 if (!is_chroma) 61 ret_val = 2; 62 } else if (source_format == dm_444_32) { 63 if (!is_chroma) 64 ret_val = 4; 65 } else if (source_format == dm_444_64) { 66 if (!is_chroma) 67 ret_val = 8; 68 } else if (source_format == dm_420_8) { 69 if (is_chroma) 70 ret_val = 2; 71 else 72 ret_val = 1; 73 } else if (source_format == dm_420_10) { 74 if (is_chroma) 75 ret_val = 4; 76 else 77 ret_val = 2; 78 } else if (source_format == dm_444_8) { 79 ret_val = 1; 80 } 81 return ret_val; 82 } 83 84 static bool is_dual_plane(enum source_format_class source_format) 85 { 86 bool ret_val = 0; 87 88 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 89 ret_val = 1; 90 91 return ret_val; 92 } 93 94 static double get_refcyc_per_delivery( 95 struct display_mode_lib *mode_lib, 96 double refclk_freq_in_mhz, 97 double pclk_freq_in_mhz, 98 bool odm_combine, 99 unsigned int recout_width, 100 unsigned int hactive, 101 double vratio, 102 double hscale_pixel_rate, 103 unsigned int delivery_width, 104 unsigned int req_per_swath_ub) 105 { 106 double refcyc_per_delivery = 0.0; 107 108 if (vratio <= 1.0) { 109 if (odm_combine) 110 refcyc_per_delivery = (double) refclk_freq_in_mhz 111 * dml_min((double) recout_width, (double) hactive / 2.0) 112 / pclk_freq_in_mhz / (double) req_per_swath_ub; 113 else 114 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 115 / pclk_freq_in_mhz / (double) req_per_swath_ub; 116 } else { 117 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 118 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 119 } 120 121 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 122 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 123 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 124 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 125 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 126 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 127 128 return refcyc_per_delivery; 129 130 } 131 132 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 133 { 134 if (tile_size == dm_256k_tile) 135 return (256 * 1024); 136 else if (tile_size == dm_64k_tile) 137 return (64 * 1024); 138 else 139 return (4 * 1024); 140 } 141 142 static void extract_rq_sizing_regs( 143 struct display_mode_lib *mode_lib, 144 display_data_rq_regs_st *rq_regs, 145 const display_data_rq_sizing_params_st rq_sizing) 146 { 147 dml_print("DML_DLG: %s: rq_sizing param\n", __func__); 148 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 149 150 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; 151 152 if (rq_sizing.min_chunk_bytes == 0) 153 rq_regs->min_chunk_size = 0; 154 else 155 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; 156 157 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; 158 if (rq_sizing.min_meta_chunk_bytes == 0) 159 rq_regs->min_meta_chunk_size = 0; 160 else 161 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; 162 163 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; 164 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; 165 } 166 167 static void extract_rq_regs( 168 struct display_mode_lib *mode_lib, 169 display_rq_regs_st *rq_regs, 170 const display_rq_params_st rq_param) 171 { 172 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 173 unsigned int detile_buf_plane1_addr = 0; 174 175 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); 176 177 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( 178 dml_log2(rq_param.dlg.rq_l.dpte_row_height), 179 1) - 3; 180 181 if (rq_param.yuv420) { 182 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); 183 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( 184 dml_log2(rq_param.dlg.rq_c.dpte_row_height), 185 1) - 3; 186 } 187 188 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 189 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 190 191 // FIXME: take the max between luma, chroma chunk size? 192 // okay for now, as we are setting chunk_bytes to 8kb anyways 193 if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 194 rq_regs->drq_expansion_mode = 0; 195 } else { 196 rq_regs->drq_expansion_mode = 2; 197 } 198 rq_regs->prq_expansion_mode = 1; 199 rq_regs->mrq_expansion_mode = 1; 200 rq_regs->crq_expansion_mode = 1; 201 202 if (rq_param.yuv420) { 203 if ((double) rq_param.misc.rq_l.stored_swath_bytes 204 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 205 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 206 } else { 207 detile_buf_plane1_addr = dml_round_to_multiple( 208 (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 209 256, 210 0) / 64.0; // 2/3 to chroma 211 } 212 } 213 rq_regs->plane1_base_address = detile_buf_plane1_addr; 214 } 215 216 static void handle_det_buf_split( 217 struct display_mode_lib *mode_lib, 218 display_rq_params_st *rq_param, 219 const display_pipe_source_params_st pipe_src_param) 220 { 221 unsigned int total_swath_bytes = 0; 222 unsigned int swath_bytes_l = 0; 223 unsigned int swath_bytes_c = 0; 224 unsigned int full_swath_bytes_packed_l = 0; 225 unsigned int full_swath_bytes_packed_c = 0; 226 bool req128_l = 0; 227 bool req128_c = 0; 228 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 229 bool surf_vert = (pipe_src_param.source_scan == dm_vert); 230 unsigned int log2_swath_height_l = 0; 231 unsigned int log2_swath_height_c = 0; 232 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 233 234 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 235 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 236 237 if (rq_param->yuv420_10bpc) { 238 full_swath_bytes_packed_l = dml_round_to_multiple( 239 rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 240 256, 241 1) + 256; 242 full_swath_bytes_packed_c = dml_round_to_multiple( 243 rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 244 256, 245 1) + 256; 246 } 247 248 if (rq_param->yuv420) { 249 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 250 251 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 252 req128_l = 0; 253 req128_c = 0; 254 swath_bytes_l = full_swath_bytes_packed_l; 255 swath_bytes_c = full_swath_bytes_packed_c; 256 } else { //128b request (for luma only for yuv420 8bpc) 257 req128_l = 1; 258 req128_c = 0; 259 swath_bytes_l = full_swath_bytes_packed_l / 2; 260 swath_bytes_c = full_swath_bytes_packed_c; 261 } 262 // Note: assumption, the config that pass in will fit into 263 // the detiled buffer. 264 } else { 265 total_swath_bytes = 2 * full_swath_bytes_packed_l; 266 267 if (total_swath_bytes <= detile_buf_size_in_bytes) 268 req128_l = 0; 269 else 270 req128_l = 1; 271 272 swath_bytes_l = total_swath_bytes; 273 swath_bytes_c = 0; 274 } 275 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 276 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 277 278 if (surf_linear) { 279 log2_swath_height_l = 0; 280 log2_swath_height_c = 0; 281 } else if (!surf_vert) { 282 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l; 283 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c; 284 } else { 285 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l; 286 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c; 287 } 288 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 289 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 290 291 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 292 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 293 dml_print( 294 "DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", 295 __func__, 296 full_swath_bytes_packed_l); 297 dml_print( 298 "DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", 299 __func__, 300 full_swath_bytes_packed_c); 301 } 302 303 static void get_meta_and_pte_attr( 304 struct display_mode_lib *mode_lib, 305 display_data_rq_dlg_params_st *rq_dlg_param, 306 display_data_rq_misc_params_st *rq_misc_param, 307 display_data_rq_sizing_params_st *rq_sizing_param, 308 unsigned int vp_width, 309 unsigned int vp_height, 310 unsigned int data_pitch, 311 unsigned int meta_pitch, 312 unsigned int source_format, 313 unsigned int tiling, 314 unsigned int macro_tile_size, 315 unsigned int source_scan, 316 unsigned int hostvm_enable, 317 unsigned int is_chroma) 318 { 319 bool surf_linear = (tiling == dm_sw_linear); 320 bool surf_vert = (source_scan == dm_vert); 321 322 unsigned int bytes_per_element; 323 unsigned int bytes_per_element_y = get_bytes_per_element( 324 (enum source_format_class) (source_format), 325 false); 326 unsigned int bytes_per_element_c = get_bytes_per_element( 327 (enum source_format_class) (source_format), 328 true); 329 330 unsigned int blk256_width = 0; 331 unsigned int blk256_height = 0; 332 333 unsigned int blk256_width_y = 0; 334 unsigned int blk256_height_y = 0; 335 unsigned int blk256_width_c = 0; 336 unsigned int blk256_height_c = 0; 337 unsigned int log2_bytes_per_element; 338 unsigned int log2_blk256_width; 339 unsigned int log2_blk256_height; 340 unsigned int blk_bytes; 341 unsigned int log2_blk_bytes; 342 unsigned int log2_blk_height; 343 unsigned int log2_blk_width; 344 unsigned int log2_meta_req_bytes; 345 unsigned int log2_meta_req_height; 346 unsigned int log2_meta_req_width; 347 unsigned int meta_req_width; 348 unsigned int meta_req_height; 349 unsigned int log2_meta_row_height; 350 unsigned int meta_row_width_ub; 351 unsigned int log2_meta_chunk_bytes; 352 unsigned int log2_meta_chunk_height; 353 354 //full sized meta chunk width in unit of data elements 355 unsigned int log2_meta_chunk_width; 356 unsigned int log2_min_meta_chunk_bytes; 357 unsigned int min_meta_chunk_width; 358 unsigned int meta_chunk_width; 359 unsigned int meta_chunk_per_row_int; 360 unsigned int meta_row_remainder; 361 unsigned int meta_chunk_threshold; 362 unsigned int meta_blk_bytes; 363 unsigned int meta_blk_height; 364 unsigned int meta_blk_width; 365 unsigned int meta_surface_bytes; 366 unsigned int vmpg_bytes; 367 unsigned int meta_pte_req_per_frame_ub; 368 unsigned int meta_pte_bytes_per_frame_ub; 369 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 370 const unsigned int dpte_buf_in_pte_reqs = 371 mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma; 372 const unsigned int pde_proc_buffer_size_64k_reqs = 373 mode_lib->ip.pde_proc_buffer_size_64k_reqs; 374 375 unsigned int log2_vmpg_height = 0; 376 unsigned int log2_vmpg_width = 0; 377 unsigned int log2_dpte_req_height_ptes = 0; 378 unsigned int log2_dpte_req_height = 0; 379 unsigned int log2_dpte_req_width = 0; 380 unsigned int log2_dpte_row_height_linear = 0; 381 unsigned int log2_dpte_row_height = 0; 382 unsigned int log2_dpte_group_width = 0; 383 unsigned int dpte_row_width_ub = 0; 384 unsigned int dpte_req_height = 0; 385 unsigned int dpte_req_width = 0; 386 unsigned int dpte_group_width = 0; 387 unsigned int log2_dpte_group_bytes = 0; 388 unsigned int log2_dpte_group_length = 0; 389 unsigned int pde_buf_entries; 390 bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); 391 392 Calculate256BBlockSizes( 393 (enum source_format_class) (source_format), 394 (enum dm_swizzle_mode) (tiling), 395 bytes_per_element_y, 396 bytes_per_element_c, 397 &blk256_height_y, 398 &blk256_height_c, 399 &blk256_width_y, 400 &blk256_width_c); 401 402 if (!is_chroma) { 403 blk256_width = blk256_width_y; 404 blk256_height = blk256_height_y; 405 bytes_per_element = bytes_per_element_y; 406 } else { 407 blk256_width = blk256_width_c; 408 blk256_height = blk256_height_c; 409 bytes_per_element = bytes_per_element_c; 410 } 411 412 log2_bytes_per_element = dml_log2(bytes_per_element); 413 414 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 415 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 416 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 417 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 418 419 log2_blk256_width = dml_log2((double) blk256_width); 420 log2_blk256_height = dml_log2((double) blk256_height); 421 blk_bytes = surf_linear ? 422 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 423 log2_blk_bytes = dml_log2((double) blk_bytes); 424 log2_blk_height = 0; 425 log2_blk_width = 0; 426 427 // remember log rule 428 // "+" in log is multiply 429 // "-" in log is divide 430 // "/2" is like square root 431 // blk is vertical biased 432 if (tiling != dm_sw_linear) 433 log2_blk_height = log2_blk256_height 434 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 435 else 436 log2_blk_height = 0; // blk height of 1 437 438 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 439 440 if (!surf_vert) { 441 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 442 + blk256_width; 443 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 444 } else { 445 rq_dlg_param->swath_width_ub = dml_round_to_multiple( 446 vp_height - 1, 447 blk256_height, 448 1) + blk256_height; 449 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 450 } 451 452 if (!surf_vert) 453 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 454 * bytes_per_element; 455 else 456 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 457 * bytes_per_element; 458 459 rq_misc_param->blk256_height = blk256_height; 460 rq_misc_param->blk256_width = blk256_width; 461 462 // ------- 463 // meta 464 // ------- 465 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 466 467 // each 64b meta request for dcn is 8x8 meta elements and 468 // a meta element covers one 256b block of the the data surface. 469 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 470 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 471 - log2_meta_req_height; 472 meta_req_width = 1 << log2_meta_req_width; 473 meta_req_height = 1 << log2_meta_req_height; 474 log2_meta_row_height = 0; 475 meta_row_width_ub = 0; 476 477 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 478 // calculate upper bound of the meta_row_width 479 if (!surf_vert) { 480 log2_meta_row_height = log2_meta_req_height; 481 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 482 + meta_req_width; 483 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 484 } else { 485 log2_meta_row_height = log2_meta_req_width; 486 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 487 + meta_req_height; 488 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 489 } 490 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 491 492 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 493 494 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 495 log2_meta_chunk_height = log2_meta_row_height; 496 497 //full sized meta chunk width in unit of data elements 498 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 499 - log2_meta_chunk_height; 500 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 501 min_meta_chunk_width = 1 502 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 503 - log2_meta_chunk_height); 504 meta_chunk_width = 1 << log2_meta_chunk_width; 505 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 506 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 507 meta_chunk_threshold = 0; 508 meta_blk_bytes = 4096; 509 meta_blk_height = blk256_height * 64; 510 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 511 meta_surface_bytes = meta_pitch 512 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) 513 + meta_blk_height) * bytes_per_element / 256; 514 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 515 meta_pte_req_per_frame_ub = (dml_round_to_multiple( 516 meta_surface_bytes - vmpg_bytes, 517 8 * vmpg_bytes, 518 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 519 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 520 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 521 522 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 523 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); 524 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 525 dml_print( 526 "DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", 527 __func__, 528 meta_pte_req_per_frame_ub); 529 dml_print( 530 "DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", 531 __func__, 532 meta_pte_bytes_per_frame_ub); 533 534 if (!surf_vert) 535 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 536 else 537 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 538 539 if (meta_row_remainder <= meta_chunk_threshold) 540 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 541 else 542 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 543 544 // ------ 545 // dpte 546 // ------ 547 if (surf_linear) { 548 log2_vmpg_height = 0; // one line high 549 } else { 550 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 551 } 552 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 553 554 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 555 if (surf_linear) { //one 64B PTE request returns 8 PTEs 556 log2_dpte_req_height_ptes = 0; 557 log2_dpte_req_width = log2_vmpg_width + 3; 558 log2_dpte_req_height = 0; 559 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 560 //one 64B req gives 8x1 PTEs for 4KB tile 561 log2_dpte_req_height_ptes = 0; 562 log2_dpte_req_width = log2_blk_width + 3; 563 log2_dpte_req_height = log2_blk_height + 0; 564 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 565 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 566 log2_dpte_req_height_ptes = 4; 567 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 568 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 569 } else { //64KB page size and must 64KB tile block 570 //one 64B req gives 8x1 PTEs for 64KB tile 571 log2_dpte_req_height_ptes = 0; 572 log2_dpte_req_width = log2_blk_width + 3; 573 log2_dpte_req_height = log2_blk_height + 0; 574 } 575 576 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 577 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 578 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 579 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 580 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 581 dpte_req_height = 1 << log2_dpte_req_height; 582 dpte_req_width = 1 << log2_dpte_req_width; 583 584 // calculate pitch dpte row buffer can hold 585 // round the result down to a power of two. 586 pde_buf_entries = 587 yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; 588 if (surf_linear) { 589 unsigned int dpte_row_height; 590 591 log2_dpte_row_height_linear = dml_floor( 592 dml_log2( 593 dml_min( 594 64 * 1024 * pde_buf_entries 595 / bytes_per_element, 596 dpte_buf_in_pte_reqs 597 * dpte_req_width) 598 / data_pitch), 599 1); 600 601 ASSERT(log2_dpte_row_height_linear >= 3); 602 603 if (log2_dpte_row_height_linear > 7) 604 log2_dpte_row_height_linear = 7; 605 606 log2_dpte_row_height = log2_dpte_row_height_linear; 607 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 608 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 609 dpte_row_height = 1 << log2_dpte_row_height; 610 dpte_row_width_ub = dml_round_to_multiple( 611 data_pitch * dpte_row_height - 1, 612 dpte_req_width, 613 1) + dpte_req_width; 614 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 615 } else { 616 // the upper bound of the dpte_row_width without dependency on viewport position follows. 617 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 618 if (!surf_vert) { 619 log2_dpte_row_height = log2_dpte_req_height; 620 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 621 + dpte_req_width; 622 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 623 } else { 624 log2_dpte_row_height = 625 (log2_blk_width < log2_dpte_req_width) ? 626 log2_blk_width : log2_dpte_req_width; 627 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 628 + dpte_req_height; 629 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 630 } 631 } 632 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 633 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 634 else 635 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 636 637 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 638 639 // the dpte_group_bytes is reduced for the specific case of vertical 640 // access of a tile surface that has dpte request of 8x1 ptes. 641 642 if (hostvm_enable) 643 rq_sizing_param->dpte_group_bytes = 512; 644 else { 645 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group 646 rq_sizing_param->dpte_group_bytes = 512; 647 else 648 //full size 649 rq_sizing_param->dpte_group_bytes = 2048; 650 } 651 652 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 653 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 654 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 655 656 // full sized data pte group width in elements 657 if (!surf_vert) 658 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 659 else 660 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 661 662 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 663 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 664 log2_dpte_group_width = log2_dpte_group_width - 1; 665 666 dpte_group_width = 1 << log2_dpte_group_width; 667 668 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 669 // the upper bound for the dpte groups per row is as follows. 670 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( 671 (double) dpte_row_width_ub / dpte_group_width, 672 1); 673 } 674 675 static void get_surf_rq_param( 676 struct display_mode_lib *mode_lib, 677 display_data_rq_sizing_params_st *rq_sizing_param, 678 display_data_rq_dlg_params_st *rq_dlg_param, 679 display_data_rq_misc_params_st *rq_misc_param, 680 const display_pipe_params_st pipe_param, 681 bool is_chroma) 682 { 683 bool mode_422 = 0; 684 unsigned int vp_width = 0; 685 unsigned int vp_height = 0; 686 unsigned int data_pitch = 0; 687 unsigned int meta_pitch = 0; 688 unsigned int ppe = mode_422 ? 2 : 1; 689 690 // FIXME check if ppe apply for both luma and chroma in 422 case 691 if (is_chroma) { 692 vp_width = pipe_param.src.viewport_width_c / ppe; 693 vp_height = pipe_param.src.viewport_height_c; 694 data_pitch = pipe_param.src.data_pitch_c; 695 meta_pitch = pipe_param.src.meta_pitch_c; 696 } else { 697 vp_width = pipe_param.src.viewport_width / ppe; 698 vp_height = pipe_param.src.viewport_height; 699 data_pitch = pipe_param.src.data_pitch; 700 meta_pitch = pipe_param.src.meta_pitch; 701 } 702 703 if (pipe_param.dest.odm_combine) { 704 unsigned int access_dir; 705 unsigned int full_src_vp_width; 706 unsigned int hactive_half; 707 unsigned int src_hactive_half; 708 access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 709 hactive_half = pipe_param.dest.hactive / 2; 710 if (is_chroma) { 711 full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width; 712 src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half; 713 } else { 714 full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width; 715 src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half; 716 } 717 718 if (access_dir == 0) { 719 vp_width = dml_min(full_src_vp_width, src_hactive_half); 720 dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); 721 } else { 722 vp_height = dml_min(full_src_vp_width, src_hactive_half); 723 dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); 724 725 } 726 dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); 727 dml_print("DML_DLG: %s: hactive_half = %d\n", __func__, hactive_half); 728 dml_print("DML_DLG: %s: src_hactive_half = %d\n", __func__, src_hactive_half); 729 } 730 rq_sizing_param->chunk_bytes = 8192; 731 732 if (rq_sizing_param->chunk_bytes == 64 * 1024) 733 rq_sizing_param->min_chunk_bytes = 0; 734 else 735 rq_sizing_param->min_chunk_bytes = 1024; 736 737 rq_sizing_param->meta_chunk_bytes = 2048; 738 rq_sizing_param->min_meta_chunk_bytes = 256; 739 740 if (pipe_param.src.hostvm) 741 rq_sizing_param->mpte_group_bytes = 512; 742 else 743 rq_sizing_param->mpte_group_bytes = 2048; 744 745 get_meta_and_pte_attr( 746 mode_lib, 747 rq_dlg_param, 748 rq_misc_param, 749 rq_sizing_param, 750 vp_width, 751 vp_height, 752 data_pitch, 753 meta_pitch, 754 pipe_param.src.source_format, 755 pipe_param.src.sw_mode, 756 pipe_param.src.macro_tile_size, 757 pipe_param.src.source_scan, 758 pipe_param.src.hostvm, 759 is_chroma); 760 } 761 762 static void dml_rq_dlg_get_rq_params( 763 struct display_mode_lib *mode_lib, 764 display_rq_params_st *rq_param, 765 const display_pipe_params_st pipe_param) 766 { 767 // get param for luma surface 768 rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 769 || pipe_param.src.source_format == dm_420_10; 770 rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10; 771 772 get_surf_rq_param( 773 mode_lib, 774 &(rq_param->sizing.rq_l), 775 &(rq_param->dlg.rq_l), 776 &(rq_param->misc.rq_l), 777 pipe_param, 778 0); 779 780 if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) { 781 // get param for chroma surface 782 get_surf_rq_param( 783 mode_lib, 784 &(rq_param->sizing.rq_c), 785 &(rq_param->dlg.rq_c), 786 &(rq_param->misc.rq_c), 787 pipe_param, 788 1); 789 } 790 791 // calculate how to split the det buffer space between luma and chroma 792 handle_det_buf_split(mode_lib, rq_param, pipe_param.src); 793 print__rq_params_st(mode_lib, *rq_param); 794 } 795 796 void dml21_rq_dlg_get_rq_reg( 797 struct display_mode_lib *mode_lib, 798 display_rq_regs_st *rq_regs, 799 const display_pipe_params_st pipe_param) 800 { 801 display_rq_params_st rq_param = {0}; 802 803 memset(rq_regs, 0, sizeof(*rq_regs)); 804 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); 805 extract_rq_regs(mode_lib, rq_regs, rq_param); 806 807 print__rq_regs_st(mode_lib, *rq_regs); 808 } 809 810 // Note: currently taken in as is. 811 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 812 static void dml_rq_dlg_get_dlg_params( 813 struct display_mode_lib *mode_lib, 814 const display_e2e_pipe_params_st *e2e_pipe_param, 815 const unsigned int num_pipes, 816 const unsigned int pipe_idx, 817 display_dlg_regs_st *disp_dlg_regs, 818 display_ttu_regs_st *disp_ttu_regs, 819 const display_rq_dlg_params_st rq_dlg_param, 820 const display_dlg_sys_params_st dlg_sys_param, 821 const bool cstate_en, 822 const bool pstate_en) 823 { 824 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 825 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 826 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 827 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 828 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 829 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 830 831 // ------------------------- 832 // Section 1.15.2.1: OTG dependent Params 833 // ------------------------- 834 // Timing 835 unsigned int htotal = dst->htotal; 836 // unsigned int hblank_start = dst.hblank_start; // TODO: Remove 837 unsigned int hblank_end = dst->hblank_end; 838 unsigned int vblank_start = dst->vblank_start; 839 unsigned int vblank_end = dst->vblank_end; 840 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 841 842 double dppclk_freq_in_mhz = clks->dppclk_mhz; 843 double dispclk_freq_in_mhz = clks->dispclk_mhz; 844 double refclk_freq_in_mhz = clks->refclk_mhz; 845 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 846 bool interlaced = dst->interlaced; 847 848 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 849 850 double min_dcfclk_mhz; 851 double t_calc_us; 852 double min_ttu_vblank; 853 854 double min_dst_y_ttu_vblank; 855 unsigned int dlg_vblank_start; 856 bool dual_plane; 857 bool mode_422; 858 unsigned int access_dir; 859 unsigned int vp_height_l; 860 unsigned int vp_width_l; 861 unsigned int vp_height_c; 862 unsigned int vp_width_c; 863 864 // Scaling 865 unsigned int htaps_l; 866 unsigned int htaps_c; 867 double hratio_l; 868 double hratio_c; 869 double vratio_l; 870 double vratio_c; 871 bool scl_enable; 872 873 double line_time_in_us; 874 // double vinit_l; 875 // double vinit_c; 876 // double vinit_bot_l; 877 // double vinit_bot_c; 878 879 // unsigned int swath_height_l; 880 unsigned int swath_width_ub_l; 881 // unsigned int dpte_bytes_per_row_ub_l; 882 unsigned int dpte_groups_per_row_ub_l; 883 // unsigned int meta_pte_bytes_per_frame_ub_l; 884 // unsigned int meta_bytes_per_row_ub_l; 885 886 // unsigned int swath_height_c; 887 unsigned int swath_width_ub_c; 888 // unsigned int dpte_bytes_per_row_ub_c; 889 unsigned int dpte_groups_per_row_ub_c; 890 891 unsigned int meta_chunks_per_row_ub_l; 892 unsigned int meta_chunks_per_row_ub_c; 893 unsigned int vupdate_offset; 894 unsigned int vupdate_width; 895 unsigned int vready_offset; 896 897 unsigned int dppclk_delay_subtotal; 898 unsigned int dispclk_delay_subtotal; 899 unsigned int pixel_rate_delay_subtotal; 900 901 unsigned int vstartup_start; 902 unsigned int dst_x_after_scaler; 903 unsigned int dst_y_after_scaler; 904 double line_wait; 905 double dst_y_prefetch; 906 double dst_y_per_vm_vblank; 907 double dst_y_per_row_vblank; 908 double dst_y_per_vm_flip; 909 double dst_y_per_row_flip; 910 double max_dst_y_per_vm_vblank; 911 double max_dst_y_per_row_vblank; 912 double lsw; 913 double vratio_pre_l; 914 double vratio_pre_c; 915 unsigned int req_per_swath_ub_l; 916 unsigned int req_per_swath_ub_c; 917 unsigned int meta_row_height_l; 918 unsigned int meta_row_height_c; 919 unsigned int swath_width_pixels_ub_l; 920 unsigned int swath_width_pixels_ub_c; 921 unsigned int scaler_rec_in_width_l; 922 unsigned int scaler_rec_in_width_c; 923 unsigned int dpte_row_height_l; 924 unsigned int dpte_row_height_c; 925 double hscale_pixel_rate_l; 926 double hscale_pixel_rate_c; 927 double min_hratio_fact_l; 928 double min_hratio_fact_c; 929 double refcyc_per_line_delivery_pre_l; 930 double refcyc_per_line_delivery_pre_c; 931 double refcyc_per_line_delivery_l; 932 double refcyc_per_line_delivery_c; 933 934 double refcyc_per_req_delivery_pre_l; 935 double refcyc_per_req_delivery_pre_c; 936 double refcyc_per_req_delivery_l; 937 double refcyc_per_req_delivery_c; 938 939 unsigned int full_recout_width; 940 double xfc_transfer_delay; 941 double xfc_precharge_delay; 942 double xfc_remote_surface_flip_latency; 943 double xfc_dst_y_delta_drq_limit; 944 double xfc_prefetch_margin; 945 double refcyc_per_req_delivery_pre_cur0; 946 double refcyc_per_req_delivery_cur0; 947 double refcyc_per_req_delivery_pre_cur1; 948 double refcyc_per_req_delivery_cur1; 949 950 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 951 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 952 953 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 954 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 955 956 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 957 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); 958 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 959 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 960 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 961 ASSERT(ref_freq_to_pix_freq < 4.0); 962 963 disp_dlg_regs->ref_freq_to_pix_freq = 964 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 965 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 966 * dml_pow(2, 8)); 967 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 968 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 969 * (double) ref_freq_to_pix_freq); 970 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 971 972 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 973 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 974 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 975 976 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 977 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 978 979 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); 980 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 981 982 dml_print( 983 "DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", 984 __func__, 985 min_dcfclk_mhz); 986 dml_print( 987 "DML_DLG: %s: min_ttu_vblank = %3.2f\n", 988 __func__, 989 min_ttu_vblank); 990 dml_print( 991 "DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", 992 __func__, 993 min_dst_y_ttu_vblank); 994 dml_print( 995 "DML_DLG: %s: t_calc_us = %3.2f\n", 996 __func__, 997 t_calc_us); 998 dml_print( 999 "DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", 1000 __func__, 1001 disp_dlg_regs->min_dst_y_next_start); 1002 dml_print( 1003 "DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", 1004 __func__, 1005 ref_freq_to_pix_freq); 1006 1007 // ------------------------- 1008 // Section 1.15.2.2: Prefetch, Active and TTU 1009 // ------------------------- 1010 // Prefetch Calc 1011 // Source 1012 // dcc_en = src.dcc; 1013 dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); 1014 mode_422 = 0; // FIXME 1015 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 1016 // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); 1017 // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); 1018 vp_height_l = src->viewport_height; 1019 vp_width_l = src->viewport_width; 1020 vp_height_c = src->viewport_height_c; 1021 vp_width_c = src->viewport_width_c; 1022 1023 // Scaling 1024 htaps_l = taps->htaps; 1025 htaps_c = taps->htaps_c; 1026 hratio_l = scl->hscl_ratio; 1027 hratio_c = scl->hscl_ratio_c; 1028 vratio_l = scl->vscl_ratio; 1029 vratio_c = scl->vscl_ratio_c; 1030 scl_enable = scl->scl_enable; 1031 1032 line_time_in_us = (htotal / pclk_freq_in_mhz); 1033 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1034 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1035 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1036 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1037 1038 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1039 meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1040 vupdate_offset = dst->vupdate_offset; 1041 vupdate_width = dst->vupdate_width; 1042 vready_offset = dst->vready_offset; 1043 1044 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1045 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1046 1047 if (scl_enable) 1048 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; 1049 else 1050 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; 1051 1052 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter 1053 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; 1054 1055 if (dout->dsc_enable) { 1056 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1057 1058 dispclk_delay_subtotal += dsc_delay; 1059 } 1060 1061 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1062 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1063 1064 vstartup_start = dst->vstartup_start; 1065 if (interlaced) { 1066 if (vstartup_start / 2.0 1067 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1068 <= vblank_end / 2.0) 1069 disp_dlg_regs->vready_after_vcount0 = 1; 1070 else 1071 disp_dlg_regs->vready_after_vcount0 = 0; 1072 } else { 1073 if (vstartup_start 1074 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1075 <= vblank_end) 1076 disp_dlg_regs->vready_after_vcount0 = 1; 1077 else 1078 disp_dlg_regs->vready_after_vcount0 = 0; 1079 } 1080 1081 // TODO: Where is this coming from? 1082 if (interlaced) 1083 vstartup_start = vstartup_start / 2; 1084 1085 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? 1086 if (vstartup_start >= min_vblank) { 1087 dml_print( 1088 "WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", 1089 __func__, 1090 vblank_start, 1091 vblank_end); 1092 dml_print( 1093 "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1094 __func__, 1095 vstartup_start, 1096 min_vblank); 1097 min_vblank = vstartup_start + 1; 1098 dml_print( 1099 "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1100 __func__, 1101 vstartup_start, 1102 min_vblank); 1103 } 1104 1105 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1106 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1107 1108 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1109 dml_print( 1110 "DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", 1111 __func__, 1112 pixel_rate_delay_subtotal); 1113 dml_print( 1114 "DML_DLG: %s: dst_x_after_scaler = %d\n", 1115 __func__, 1116 dst_x_after_scaler); 1117 dml_print( 1118 "DML_DLG: %s: dst_y_after_scaler = %d\n", 1119 __func__, 1120 dst_y_after_scaler); 1121 1122 // Lwait 1123 // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? 1124 line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us; 1125 if (cstate_en) 1126 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1127 if (pstate_en) 1128 line_wait = dml_max( 1129 mode_lib->soc.dram_clock_change_latency_us 1130 + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? 1131 line_wait); 1132 line_wait = line_wait / line_time_in_us; 1133 1134 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1135 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1136 1137 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank( 1138 mode_lib, 1139 e2e_pipe_param, 1140 num_pipes, 1141 pipe_idx); 1142 dst_y_per_row_vblank = get_dst_y_per_row_vblank( 1143 mode_lib, 1144 e2e_pipe_param, 1145 num_pipes, 1146 pipe_idx); 1147 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1148 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1149 1150 max_dst_y_per_vm_vblank = 32.0; 1151 max_dst_y_per_row_vblank = 16.0; 1152 1153 // magic! 1154 if (htotal <= 75) { 1155 min_vblank = 300; 1156 max_dst_y_per_vm_vblank = 100.0; 1157 max_dst_y_per_row_vblank = 100.0; 1158 } 1159 1160 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); 1161 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); 1162 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1163 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1164 1165 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); 1166 ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); 1167 1168 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1169 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1170 1171 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); 1172 1173 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1174 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1175 1176 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); 1177 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1178 1179 // Active 1180 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1181 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1182 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1183 meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1184 swath_width_pixels_ub_l = 0; 1185 swath_width_pixels_ub_c = 0; 1186 scaler_rec_in_width_l = 0; 1187 scaler_rec_in_width_c = 0; 1188 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1189 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1190 1191 if (mode_422) { 1192 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element 1193 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1194 } else { 1195 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1196 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1197 } 1198 1199 hscale_pixel_rate_l = 0.; 1200 hscale_pixel_rate_c = 0.; 1201 min_hratio_fact_l = 1.0; 1202 min_hratio_fact_c = 1.0; 1203 1204 if (htaps_l <= 1) 1205 min_hratio_fact_l = 2.0; 1206 else if (htaps_l <= 6) { 1207 if ((hratio_l * 2.0) > 4.0) 1208 min_hratio_fact_l = 4.0; 1209 else 1210 min_hratio_fact_l = hratio_l * 2.0; 1211 } else { 1212 if (hratio_l > 4.0) 1213 min_hratio_fact_l = 4.0; 1214 else 1215 min_hratio_fact_l = hratio_l; 1216 } 1217 1218 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1219 1220 if (htaps_c <= 1) 1221 min_hratio_fact_c = 2.0; 1222 else if (htaps_c <= 6) { 1223 if ((hratio_c * 2.0) > 4.0) 1224 min_hratio_fact_c = 4.0; 1225 else 1226 min_hratio_fact_c = hratio_c * 2.0; 1227 } else { 1228 if (hratio_c > 4.0) 1229 min_hratio_fact_c = 4.0; 1230 else 1231 min_hratio_fact_c = hratio_c; 1232 } 1233 1234 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1235 1236 refcyc_per_line_delivery_pre_l = 0.; 1237 refcyc_per_line_delivery_pre_c = 0.; 1238 refcyc_per_line_delivery_l = 0.; 1239 refcyc_per_line_delivery_c = 0.; 1240 1241 refcyc_per_req_delivery_pre_l = 0.; 1242 refcyc_per_req_delivery_pre_c = 0.; 1243 refcyc_per_req_delivery_l = 0.; 1244 refcyc_per_req_delivery_c = 0.; 1245 1246 full_recout_width = 0; 1247 // In ODM 1248 if (src->is_hsplit) { 1249 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1250 // combine, you MUST specify the full_recout_width...according to Oswin 1251 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1252 dml_print( 1253 "DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", 1254 __func__); 1255 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1256 } else 1257 full_recout_width = dst->full_recout_width; 1258 } else 1259 full_recout_width = dst->recout_width; 1260 1261 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1262 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1263 mode_lib, 1264 refclk_freq_in_mhz, 1265 pclk_freq_in_mhz, 1266 dst->odm_combine, 1267 full_recout_width, 1268 dst->hactive, 1269 vratio_pre_l, 1270 hscale_pixel_rate_l, 1271 swath_width_pixels_ub_l, 1272 1); // per line 1273 1274 refcyc_per_line_delivery_l = get_refcyc_per_delivery( 1275 mode_lib, 1276 refclk_freq_in_mhz, 1277 pclk_freq_in_mhz, 1278 dst->odm_combine, 1279 full_recout_width, 1280 dst->hactive, 1281 vratio_l, 1282 hscale_pixel_rate_l, 1283 swath_width_pixels_ub_l, 1284 1); // per line 1285 1286 dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width); 1287 dml_print( 1288 "DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", 1289 __func__, 1290 hscale_pixel_rate_l); 1291 dml_print( 1292 "DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1293 __func__, 1294 refcyc_per_line_delivery_pre_l); 1295 dml_print( 1296 "DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", 1297 __func__, 1298 refcyc_per_line_delivery_l); 1299 1300 if (dual_plane) { 1301 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( 1302 mode_lib, 1303 refclk_freq_in_mhz, 1304 pclk_freq_in_mhz, 1305 dst->odm_combine, 1306 full_recout_width, 1307 dst->hactive, 1308 vratio_pre_c, 1309 hscale_pixel_rate_c, 1310 swath_width_pixels_ub_c, 1311 1); // per line 1312 1313 refcyc_per_line_delivery_c = get_refcyc_per_delivery( 1314 mode_lib, 1315 refclk_freq_in_mhz, 1316 pclk_freq_in_mhz, 1317 dst->odm_combine, 1318 full_recout_width, 1319 dst->hactive, 1320 vratio_c, 1321 hscale_pixel_rate_c, 1322 swath_width_pixels_ub_c, 1323 1); // per line 1324 1325 dml_print( 1326 "DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 1327 __func__, 1328 refcyc_per_line_delivery_pre_c); 1329 dml_print( 1330 "DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 1331 __func__, 1332 refcyc_per_line_delivery_c); 1333 } 1334 1335 // TTU - Luma / Chroma 1336 if (access_dir) { // vertical access 1337 scaler_rec_in_width_l = vp_height_l; 1338 scaler_rec_in_width_c = vp_height_c; 1339 } else { 1340 scaler_rec_in_width_l = vp_width_l; 1341 scaler_rec_in_width_c = vp_width_c; 1342 } 1343 1344 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( 1345 mode_lib, 1346 refclk_freq_in_mhz, 1347 pclk_freq_in_mhz, 1348 dst->odm_combine, 1349 full_recout_width, 1350 dst->hactive, 1351 vratio_pre_l, 1352 hscale_pixel_rate_l, 1353 scaler_rec_in_width_l, 1354 req_per_swath_ub_l); // per req 1355 refcyc_per_req_delivery_l = get_refcyc_per_delivery( 1356 mode_lib, 1357 refclk_freq_in_mhz, 1358 pclk_freq_in_mhz, 1359 dst->odm_combine, 1360 full_recout_width, 1361 dst->hactive, 1362 vratio_l, 1363 hscale_pixel_rate_l, 1364 scaler_rec_in_width_l, 1365 req_per_swath_ub_l); // per req 1366 1367 dml_print( 1368 "DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", 1369 __func__, 1370 refcyc_per_req_delivery_pre_l); 1371 dml_print( 1372 "DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", 1373 __func__, 1374 refcyc_per_req_delivery_l); 1375 1376 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1377 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1378 1379 if (dual_plane) { 1380 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( 1381 mode_lib, 1382 refclk_freq_in_mhz, 1383 pclk_freq_in_mhz, 1384 dst->odm_combine, 1385 full_recout_width, 1386 dst->hactive, 1387 vratio_pre_c, 1388 hscale_pixel_rate_c, 1389 scaler_rec_in_width_c, 1390 req_per_swath_ub_c); // per req 1391 refcyc_per_req_delivery_c = get_refcyc_per_delivery( 1392 mode_lib, 1393 refclk_freq_in_mhz, 1394 pclk_freq_in_mhz, 1395 dst->odm_combine, 1396 full_recout_width, 1397 dst->hactive, 1398 vratio_c, 1399 hscale_pixel_rate_c, 1400 scaler_rec_in_width_c, 1401 req_per_swath_ub_c); // per req 1402 1403 dml_print( 1404 "DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 1405 __func__, 1406 refcyc_per_req_delivery_pre_c); 1407 dml_print( 1408 "DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", 1409 __func__, 1410 refcyc_per_req_delivery_c); 1411 1412 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1413 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1414 } 1415 1416 // XFC 1417 xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1418 xfc_precharge_delay = get_xfc_precharge_delay( 1419 mode_lib, 1420 e2e_pipe_param, 1421 num_pipes, 1422 pipe_idx); 1423 xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency( 1424 mode_lib, 1425 e2e_pipe_param, 1426 num_pipes, 1427 pipe_idx); 1428 xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency; 1429 xfc_prefetch_margin = get_xfc_prefetch_margin( 1430 mode_lib, 1431 e2e_pipe_param, 1432 num_pipes, 1433 pipe_idx); 1434 1435 // TTU - Cursor 1436 refcyc_per_req_delivery_pre_cur0 = 0.0; 1437 refcyc_per_req_delivery_cur0 = 0.0; 1438 if (src->num_cursors > 0) { 1439 calculate_ttu_cursor( 1440 mode_lib, 1441 &refcyc_per_req_delivery_pre_cur0, 1442 &refcyc_per_req_delivery_cur0, 1443 refclk_freq_in_mhz, 1444 ref_freq_to_pix_freq, 1445 hscale_pixel_rate_l, 1446 scl->hscl_ratio, 1447 vratio_pre_l, 1448 vratio_l, 1449 src->cur0_src_width, 1450 (enum cursor_bpp) (src->cur0_bpp)); 1451 } 1452 1453 refcyc_per_req_delivery_pre_cur1 = 0.0; 1454 refcyc_per_req_delivery_cur1 = 0.0; 1455 if (src->num_cursors > 1) { 1456 calculate_ttu_cursor( 1457 mode_lib, 1458 &refcyc_per_req_delivery_pre_cur1, 1459 &refcyc_per_req_delivery_cur1, 1460 refclk_freq_in_mhz, 1461 ref_freq_to_pix_freq, 1462 hscale_pixel_rate_l, 1463 scl->hscl_ratio, 1464 vratio_pre_l, 1465 vratio_l, 1466 src->cur1_src_width, 1467 (enum cursor_bpp) (src->cur1_bpp)); 1468 } 1469 1470 // TTU - Misc 1471 // all hard-coded 1472 1473 // Assignment to register structures 1474 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1475 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1476 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); 1477 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1478 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1479 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1480 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 1481 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 1482 1483 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1484 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1485 1486 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank); 1487 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank); 1488 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); 1489 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); 1490 1491 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1492 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1493 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1494 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); 1495 1496 if (dual_plane) { 1497 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank 1498 * (double) htotal * ref_freq_to_pix_freq 1499 / (double) dpte_groups_per_row_ub_c); 1500 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c 1501 < (unsigned int)dml_pow(2, 13)); 1502 } 1503 1504 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1505 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1506 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1507 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); 1508 1509 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1510 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1511 1512 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1513 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1514 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1515 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1516 1517 if (dual_plane) { 1518 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip 1519 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1520 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip 1521 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1522 } 1523 1524 disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; 1525 disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; 1526 disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; 1527 disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; 1528 1529 // Clamp to max for now 1530 if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) 1531 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; 1532 1533 if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) 1534 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; 1535 1536 if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) 1537 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; 1538 1539 if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) 1540 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; 1541 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1542 / (double) vratio_l * dml_pow(2, 2)); 1543 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); 1544 1545 if (dual_plane) { 1546 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1547 / (double) vratio_c * dml_pow(2, 2)); 1548 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 1549 dml_print( 1550 "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1551 __func__, 1552 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1553 (unsigned int)dml_pow(2, 17) - 1); 1554 } 1555 } 1556 1557 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1558 / (double) vratio_l * dml_pow(2, 2)); 1559 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); 1560 1561 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1562 1563 dml_print( 1564 "DML: Trow: %fus\n", 1565 line_time_in_us * (double)dpte_row_height_l / (double)vratio_l); 1566 1567 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1568 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1569 / (double) dpte_groups_per_row_ub_l); 1570 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1571 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1572 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1573 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1574 / (double) meta_chunks_per_row_ub_l); 1575 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1576 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1577 1578 if (dual_plane) { 1579 disp_dlg_regs->refcyc_per_pte_group_nom_c = 1580 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c 1581 * (double) htotal * ref_freq_to_pix_freq 1582 / (double) dpte_groups_per_row_ub_c); 1583 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1584 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1585 1586 // TODO: Is this the right calculation? Does htotal need to be halved? 1587 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = 1588 (unsigned int) ((double) meta_row_height_c / (double) vratio_c 1589 * (double) htotal * ref_freq_to_pix_freq 1590 / (double) meta_chunks_per_row_ub_c); 1591 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 1592 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1593 } 1594 1595 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( 1596 refcyc_per_line_delivery_pre_l, 1); 1597 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( 1598 refcyc_per_line_delivery_l, 1); 1599 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); 1600 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); 1601 1602 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( 1603 refcyc_per_line_delivery_pre_c, 1); 1604 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( 1605 refcyc_per_line_delivery_c, 1); 1606 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); 1607 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); 1608 1609 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1610 disp_dlg_regs->dst_y_offset_cur0 = 0; 1611 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1612 disp_dlg_regs->dst_y_offset_cur1 = 0; 1613 1614 disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; 1615 disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; 1616 disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; 1617 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil( 1618 xfc_prefetch_margin * refclk_freq_in_mhz, 1); 1619 1620 // slave has to have this value also set to off 1621 if (src->xfc_enable && !src->xfc_slave) 1622 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); 1623 else 1624 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1625 1626 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1627 * dml_pow(2, 10)); 1628 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1629 * dml_pow(2, 10)); 1630 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c 1631 * dml_pow(2, 10)); 1632 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1633 * dml_pow(2, 10)); 1634 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1635 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1636 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 1637 * dml_pow(2, 10)); 1638 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = 1639 (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1640 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 1641 * dml_pow(2, 10)); 1642 disp_ttu_regs->qos_level_low_wm = 0; 1643 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1644 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1645 * ref_freq_to_pix_freq); 1646 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 1647 1648 disp_ttu_regs->qos_level_flip = 14; 1649 disp_ttu_regs->qos_level_fixed_l = 8; 1650 disp_ttu_regs->qos_level_fixed_c = 8; 1651 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1652 disp_ttu_regs->qos_ramp_disable_l = 0; 1653 disp_ttu_regs->qos_ramp_disable_c = 0; 1654 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1655 1656 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1657 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1658 1659 print__ttu_regs_st(mode_lib, *disp_ttu_regs); 1660 print__dlg_regs_st(mode_lib, *disp_dlg_regs); 1661 } 1662 1663 void dml21_rq_dlg_get_dlg_reg( 1664 struct display_mode_lib *mode_lib, 1665 display_dlg_regs_st *dlg_regs, 1666 display_ttu_regs_st *ttu_regs, 1667 display_e2e_pipe_params_st *e2e_pipe_param, 1668 const unsigned int num_pipes, 1669 const unsigned int pipe_idx, 1670 const bool cstate_en, 1671 const bool pstate_en, 1672 const bool vm_en, 1673 const bool ignore_viewport_pos, 1674 const bool immediate_flip_support) 1675 { 1676 display_rq_params_st rq_param = {0}; 1677 display_dlg_sys_params_st dlg_sys_param = {0}; 1678 1679 // Get watermark and Tex. 1680 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1681 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep( 1682 mode_lib, 1683 e2e_pipe_param, 1684 num_pipes); 1685 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1686 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1687 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1688 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1689 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw( 1690 mode_lib, 1691 e2e_pipe_param, 1692 num_pipes); 1693 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes( 1694 mode_lib, 1695 e2e_pipe_param, 1696 num_pipes); 1697 dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency 1698 / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated 1699 1700 print__dlg_sys_params_st(mode_lib, dlg_sys_param); 1701 1702 // system parameter calculation done 1703 1704 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1705 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe); 1706 dml_rq_dlg_get_dlg_params( 1707 mode_lib, 1708 e2e_pipe_param, 1709 num_pipes, 1710 pipe_idx, 1711 dlg_regs, 1712 ttu_regs, 1713 rq_param.dlg, 1714 dlg_sys_param, 1715 cstate_en, 1716 pstate_en); 1717 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1718 } 1719 1720 void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param) 1721 { 1722 memset(arb_param, 0, sizeof(*arb_param)); 1723 arb_param->max_req_outstanding = 256; 1724 arb_param->min_req_outstanding = 68; 1725 arb_param->sat_level_us = 60; 1726 } 1727 1728 static void calculate_ttu_cursor( 1729 struct display_mode_lib *mode_lib, 1730 double *refcyc_per_req_delivery_pre_cur, 1731 double *refcyc_per_req_delivery_cur, 1732 double refclk_freq_in_mhz, 1733 double ref_freq_to_pix_freq, 1734 double hscale_pixel_rate_l, 1735 double hscl_ratio, 1736 double vratio_pre_l, 1737 double vratio_l, 1738 unsigned int cur_width, 1739 enum cursor_bpp cur_bpp) 1740 { 1741 unsigned int cur_src_width = cur_width; 1742 unsigned int cur_req_size = 0; 1743 unsigned int cur_req_width = 0; 1744 double cur_width_ub = 0.0; 1745 double cur_req_per_width = 0.0; 1746 double hactive_cur = 0.0; 1747 1748 ASSERT(cur_src_width <= 256); 1749 1750 *refcyc_per_req_delivery_pre_cur = 0.0; 1751 *refcyc_per_req_delivery_cur = 0.0; 1752 if (cur_src_width > 0) { 1753 unsigned int cur_bit_per_pixel = 0; 1754 1755 if (cur_bpp == dm_cur_2bit) { 1756 cur_req_size = 64; // byte 1757 cur_bit_per_pixel = 2; 1758 } else { // 32bit 1759 cur_bit_per_pixel = 32; 1760 if (cur_src_width >= 1 && cur_src_width <= 16) 1761 cur_req_size = 64; 1762 else if (cur_src_width >= 17 && cur_src_width <= 31) 1763 cur_req_size = 128; 1764 else 1765 cur_req_size = 256; 1766 } 1767 1768 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); 1769 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) 1770 * (double) cur_req_width; 1771 cur_req_per_width = cur_width_ub / (double) cur_req_width; 1772 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor 1773 1774 if (vratio_pre_l <= 1.0) { 1775 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq 1776 / (double) cur_req_per_width; 1777 } else { 1778 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz 1779 * (double) cur_src_width / hscale_pixel_rate_l 1780 / (double) cur_req_per_width; 1781 } 1782 1783 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 1784 1785 if (vratio_l <= 1.0) { 1786 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq 1787 / (double) cur_req_per_width; 1788 } else { 1789 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz 1790 * (double) cur_src_width / hscale_pixel_rate_l 1791 / (double) cur_req_per_width; 1792 } 1793 1794 dml_print( 1795 "DML_DLG: %s: cur_req_width = %d\n", 1796 __func__, 1797 cur_req_width); 1798 dml_print( 1799 "DML_DLG: %s: cur_width_ub = %3.2f\n", 1800 __func__, 1801 cur_width_ub); 1802 dml_print( 1803 "DML_DLG: %s: cur_req_per_width = %3.2f\n", 1804 __func__, 1805 cur_req_per_width); 1806 dml_print( 1807 "DML_DLG: %s: hactive_cur = %3.2f\n", 1808 __func__, 1809 hactive_cur); 1810 dml_print( 1811 "DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", 1812 __func__, 1813 *refcyc_per_req_delivery_pre_cur); 1814 dml_print( 1815 "DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", 1816 __func__, 1817 *refcyc_per_req_delivery_cur); 1818 1819 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1820 } 1821 } 1822 1823 #endif 1824