1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "clk_mgr.h" 28 #include "resource.h" 29 #include "dcn321_fpu.h" 30 #include "dcn32/dcn32_resource.h" 31 #include "dcn321/dcn321_resource.h" 32 #include "dml/dcn32/display_mode_vba_util_32.h" 33 34 #define DCN3_2_DEFAULT_DET_SIZE 256 35 36 struct _vcs_dpi_ip_params_st dcn3_21_ip = { 37 .gpuvm_enable = 0, 38 .gpuvm_max_page_table_levels = 4, 39 .hostvm_enable = 0, 40 .rob_buffer_size_kbytes = 128, 41 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 42 .config_return_buffer_size_in_kbytes = 1280, 43 .compressed_buffer_segment_size_in_kbytes = 64, 44 .meta_fifo_size_in_kentries = 22, 45 .zero_size_buffer_entries = 512, 46 .compbuf_reserved_space_64b = 256, 47 .compbuf_reserved_space_zs = 64, 48 .dpp_output_buffer_pixels = 2560, 49 .opp_output_buffer_lines = 1, 50 .pixel_chunk_size_kbytes = 8, 51 .alpha_pixel_chunk_size_kbytes = 4, 52 .min_pixel_chunk_size_bytes = 1024, 53 .dcc_meta_buffer_size_bytes = 6272, 54 .meta_chunk_size_kbytes = 2, 55 .min_meta_chunk_size_bytes = 256, 56 .writeback_chunk_size_kbytes = 8, 57 .ptoi_supported = false, 58 .num_dsc = 4, 59 .maximum_dsc_bits_per_component = 12, 60 .maximum_pixels_per_line_per_dsc_unit = 6016, 61 .dsc422_native_support = true, 62 .is_line_buffer_bpp_fixed = true, 63 .line_buffer_fixed_bpp = 57, 64 .line_buffer_size_bits = 1171920, 65 .max_line_buffer_lines = 32, 66 .writeback_interface_buffer_size_kbytes = 90, 67 .max_num_dpp = 4, 68 .max_num_otg = 4, 69 .max_num_hdmi_frl_outputs = 1, 70 .max_num_wb = 1, 71 .max_dchub_pscl_bw_pix_per_clk = 4, 72 .max_pscl_lb_bw_pix_per_clk = 2, 73 .max_lb_vscl_bw_pix_per_clk = 4, 74 .max_vscl_hscl_bw_pix_per_clk = 4, 75 .max_hscl_ratio = 6, 76 .max_vscl_ratio = 6, 77 .max_hscl_taps = 8, 78 .max_vscl_taps = 8, 79 .dpte_buffer_size_in_pte_reqs_luma = 64, 80 .dpte_buffer_size_in_pte_reqs_chroma = 34, 81 .dispclk_ramp_margin_percent = 1, 82 .max_inter_dcn_tile_repeaters = 8, 83 .cursor_buffer_size = 16, 84 .cursor_chunk_size = 2, 85 .writeback_line_buffer_buffer_size = 0, 86 .writeback_min_hscl_ratio = 1, 87 .writeback_min_vscl_ratio = 1, 88 .writeback_max_hscl_ratio = 1, 89 .writeback_max_vscl_ratio = 1, 90 .writeback_max_hscl_taps = 1, 91 .writeback_max_vscl_taps = 1, 92 .dppclk_delay_subtotal = 47, 93 .dppclk_delay_scl = 50, 94 .dppclk_delay_scl_lb_only = 16, 95 .dppclk_delay_cnvc_formatter = 28, 96 .dppclk_delay_cnvc_cursor = 6, 97 .dispclk_delay_subtotal = 125, 98 .dynamic_metadata_vm_enabled = false, 99 .odm_combine_4to1_supported = false, 100 .dcc_supported = true, 101 .max_num_dp2p0_outputs = 2, 102 .max_num_dp2p0_streams = 4, 103 }; 104 105 struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 106 .clock_limits = { 107 { 108 .state = 0, 109 .dcfclk_mhz = 1564.0, 110 .fabricclk_mhz = 400.0, 111 .dispclk_mhz = 2150.0, 112 .dppclk_mhz = 2150.0, 113 .phyclk_mhz = 810.0, 114 .phyclk_d18_mhz = 667.0, 115 .phyclk_d32_mhz = 625.0, 116 .socclk_mhz = 1200.0, 117 .dscclk_mhz = 716.667, 118 .dram_speed_mts = 1600.0, 119 .dtbclk_mhz = 1564.0, 120 }, 121 }, 122 .num_states = 1, 123 .sr_exit_time_us = 19.95, 124 .sr_enter_plus_exit_time_us = 24.36, 125 .sr_exit_z8_time_us = 285.0, 126 .sr_enter_plus_exit_z8_time_us = 320, 127 .writeback_latency_us = 12.0, 128 .round_trip_ping_latency_dcfclk_cycles = 263, 129 .urgent_latency_pixel_data_only_us = 4, 130 .urgent_latency_pixel_mixed_with_vm_data_us = 4, 131 .urgent_latency_vm_data_only_us = 4, 132 .fclk_change_latency_us = 20, 133 .usr_retraining_latency_us = 2, 134 .smn_latency_us = 2, 135 .mall_allocated_for_dcn_mbytes = 64, 136 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 137 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 138 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 139 .pct_ideal_sdp_bw_after_urgent = 100.0, 140 .pct_ideal_fabric_bw_after_urgent = 67.0, 141 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 142 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 143 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 144 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 145 .max_avg_sdp_bw_use_normal_percent = 80.0, 146 .max_avg_fabric_bw_use_normal_percent = 60.0, 147 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 148 .max_avg_dram_bw_use_normal_percent = 15.0, 149 .num_chans = 8, 150 .dram_channel_width_bytes = 2, 151 .fabric_datapath_to_dcn_data_return_bytes = 64, 152 .return_bus_width_bytes = 64, 153 .downspread_percent = 0.38, 154 .dcn_downspread_percent = 0.5, 155 .dram_clock_change_latency_us = 400, 156 .dispclk_dppclk_vco_speed_mhz = 4300.0, 157 .do_urgent_latency_adjustment = true, 158 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 159 .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, 160 }; 161 162 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 163 { 164 if (entry->dcfclk_mhz > 0) { 165 float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 166 167 entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 168 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * 169 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 170 } else if (entry->fabricclk_mhz > 0) { 171 float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 172 173 entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 174 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * 175 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 176 } else if (entry->dram_speed_mts > 0) { 177 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * 178 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 179 180 entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); 181 entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); 182 } 183 } 184 185 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 186 { 187 float memory_bw_kbytes_sec; 188 float fabric_bw_kbytes_sec; 189 float sdp_bw_kbytes_sec; 190 float limiting_bw_kbytes_sec; 191 192 memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * 193 dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 194 195 fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); 196 197 sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); 198 199 limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 200 201 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 202 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 203 204 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 205 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 206 207 return limiting_bw_kbytes_sec; 208 } 209 210 void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 211 unsigned int *num_entries, 212 struct _vcs_dpi_voltage_scaling_st *entry) 213 { 214 int i = 0; 215 int index = 0; 216 float net_bw_of_new_state = 0; 217 218 dc_assert_fp_enabled(); 219 220 get_optimal_ntuple(entry); 221 222 if (*num_entries == 0) { 223 table[0] = *entry; 224 (*num_entries)++; 225 } else { 226 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); 227 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { 228 index++; 229 if (index >= *num_entries) 230 break; 231 } 232 233 for (i = *num_entries; i > index; i--) 234 table[i] = table[i - 1]; 235 236 table[index] = *entry; 237 (*num_entries)++; 238 } 239 } 240 241 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 242 unsigned int index) 243 { 244 int i; 245 246 if (*num_entries == 0) 247 return; 248 249 for (i = index; i < *num_entries - 1; i++) { 250 table[i] = table[i + 1]; 251 } 252 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 253 } 254 255 static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 256 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 257 { 258 int i, j; 259 struct _vcs_dpi_voltage_scaling_st entry = {0}; 260 261 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 262 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 263 264 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 265 266 static const unsigned int num_dcfclk_stas = 5; 267 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 268 269 unsigned int num_uclk_dpms = 0; 270 unsigned int num_fclk_dpms = 0; 271 unsigned int num_dcfclk_dpms = 0; 272 273 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 274 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 275 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 276 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 277 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 278 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 279 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 280 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 281 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 282 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 283 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 284 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 285 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 286 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 287 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 288 289 if (bw_params->clk_table.entries[i].memclk_mhz > 0) 290 num_uclk_dpms++; 291 if (bw_params->clk_table.entries[i].fclk_mhz > 0) 292 num_fclk_dpms++; 293 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) 294 num_dcfclk_dpms++; 295 } 296 297 if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) 298 return -1; 299 300 if (max_dppclk_mhz == 0) 301 max_dppclk_mhz = max_dispclk_mhz; 302 303 if (max_fclk_mhz == 0) 304 max_fclk_mhz = max_dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / dcn3_21_soc.pct_ideal_fabric_bw_after_urgent; 305 306 if (max_phyclk_mhz == 0) 307 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 308 309 *num_entries = 0; 310 entry.dispclk_mhz = max_dispclk_mhz; 311 entry.dscclk_mhz = max_dispclk_mhz / 3; 312 entry.dppclk_mhz = max_dppclk_mhz; 313 entry.dtbclk_mhz = max_dtbclk_mhz; 314 entry.phyclk_mhz = max_phyclk_mhz; 315 entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 316 entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 317 318 // Insert all the DCFCLK STAs 319 for (i = 0; i < num_dcfclk_stas; i++) { 320 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 321 entry.fabricclk_mhz = 0; 322 entry.dram_speed_mts = 0; 323 324 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 325 } 326 327 // Insert the max DCFCLK 328 entry.dcfclk_mhz = max_dcfclk_mhz; 329 entry.fabricclk_mhz = 0; 330 entry.dram_speed_mts = 0; 331 332 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 333 334 // Insert the UCLK DPMS 335 for (i = 0; i < num_uclk_dpms; i++) { 336 entry.dcfclk_mhz = 0; 337 entry.fabricclk_mhz = 0; 338 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 339 340 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 341 } 342 343 // If FCLK is coarse grained, insert individual DPMs. 344 if (num_fclk_dpms > 2) { 345 for (i = 0; i < num_fclk_dpms; i++) { 346 entry.dcfclk_mhz = 0; 347 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 348 entry.dram_speed_mts = 0; 349 350 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 351 } 352 } 353 // If FCLK fine grained, only insert max 354 else { 355 entry.dcfclk_mhz = 0; 356 entry.fabricclk_mhz = max_fclk_mhz; 357 entry.dram_speed_mts = 0; 358 359 dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); 360 } 361 362 // At this point, the table contains all "points of interest" based on 363 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 364 // ratios (by derate, are exact). 365 366 // Remove states that require higher clocks than are supported 367 for (i = *num_entries - 1; i >= 0 ; i--) { 368 if (table[i].dcfclk_mhz > max_dcfclk_mhz || 369 table[i].fabricclk_mhz > max_fclk_mhz || 370 table[i].dram_speed_mts > max_uclk_mhz * 16) 371 remove_entry_from_table_at_index(table, num_entries, i); 372 } 373 374 // At this point, the table only contains supported points of interest 375 // it could be used as is, but some states may be redundant due to 376 // coarse grained nature of some clocks, so we want to round up to 377 // coarse grained DPMs and remove duplicates. 378 379 // Round up UCLKs 380 for (i = *num_entries - 1; i >= 0 ; i--) { 381 for (j = 0; j < num_uclk_dpms; j++) { 382 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 383 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 384 break; 385 } 386 } 387 } 388 389 // If FCLK is coarse grained, round up to next DPMs 390 if (num_fclk_dpms > 2) { 391 for (i = *num_entries - 1; i >= 0 ; i--) { 392 for (j = 0; j < num_fclk_dpms; j++) { 393 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 394 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 395 break; 396 } 397 } 398 } 399 } 400 // Otherwise, round up to minimum. 401 else { 402 for (i = *num_entries - 1; i >= 0 ; i--) { 403 if (table[i].fabricclk_mhz < min_fclk_mhz) { 404 table[i].fabricclk_mhz = min_fclk_mhz; 405 break; 406 } 407 } 408 } 409 410 // Round DCFCLKs up to minimum 411 for (i = *num_entries - 1; i >= 0 ; i--) { 412 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 413 table[i].dcfclk_mhz = min_dcfclk_mhz; 414 break; 415 } 416 } 417 418 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 419 i = 0; 420 while (i < *num_entries - 1) { 421 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 422 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 423 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 424 remove_entry_from_table_at_index(table, num_entries, i + 1); 425 else 426 i++; 427 } 428 429 // Fix up the state indicies 430 for (i = *num_entries - 1; i >= 0 ; i--) { 431 table[i].state = i; 432 } 433 434 return 0; 435 } 436 437 static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 438 unsigned int *optimal_dcfclk, 439 unsigned int *optimal_fclk) 440 { 441 double bw_from_dram, bw_from_dram1, bw_from_dram2; 442 443 bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * 444 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); 445 bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * 446 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); 447 448 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 449 450 if (optimal_fclk) 451 *optimal_fclk = bw_from_dram / 452 (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 453 454 if (optimal_dcfclk) 455 *optimal_dcfclk = bw_from_dram / 456 (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); 457 } 458 459 /** dcn321_update_bw_bounding_box 460 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet 461 * with actual values as per dGPU SKU: 462 * -with passed few options from dc->config 463 * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) 464 * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes 465 * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU 466 * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) 467 * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different 468 * clocks (which might differ for certain dGPU SKU of the same ASIC) 469 */ 470 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 471 { 472 dc_assert_fp_enabled(); 473 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 474 /* Overrides from dc->config options */ 475 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 476 477 /* Override from passed dc->bb_overrides if available*/ 478 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 479 && dc->bb_overrides.sr_exit_time_ns) { 480 dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 481 } 482 483 if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000) 484 != dc->bb_overrides.sr_enter_plus_exit_time_ns 485 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 486 dcn3_21_soc.sr_enter_plus_exit_time_us = 487 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 488 } 489 490 if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 491 && dc->bb_overrides.urgent_latency_ns) { 492 dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 493 dcn3_21_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 494 } 495 496 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) 497 != dc->bb_overrides.dram_clock_change_latency_ns 498 && dc->bb_overrides.dram_clock_change_latency_ns) { 499 dcn3_21_soc.dram_clock_change_latency_us = 500 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 501 } 502 503 if ((int)(dcn3_21_soc.fclk_change_latency_us * 1000) 504 != dc->bb_overrides.fclk_clock_change_latency_ns 505 && dc->bb_overrides.fclk_clock_change_latency_ns) { 506 dcn3_21_soc.fclk_change_latency_us = 507 dc->bb_overrides.fclk_clock_change_latency_ns / 1000; 508 } 509 510 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) 511 != dc->bb_overrides.dummy_clock_change_latency_ns 512 && dc->bb_overrides.dummy_clock_change_latency_ns) { 513 dcn3_21_soc.dummy_pstate_latency_us = 514 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 515 } 516 517 /* Override from VBIOS if VBIOS bb_info available */ 518 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 519 struct bp_soc_bb_info bb_info = {0}; 520 521 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 522 if (bb_info.dram_clock_change_latency_100ns > 0) 523 dcn3_21_soc.dram_clock_change_latency_us = 524 bb_info.dram_clock_change_latency_100ns * 10; 525 526 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 527 dcn3_21_soc.sr_enter_plus_exit_time_us = 528 bb_info.dram_sr_enter_exit_latency_100ns * 10; 529 530 if (bb_info.dram_sr_exit_latency_100ns > 0) 531 dcn3_21_soc.sr_exit_time_us = 532 bb_info.dram_sr_exit_latency_100ns * 10; 533 } 534 } 535 536 /* Override from VBIOS for num_chan */ 537 if (dc->ctx->dc_bios->vram_info.num_chans) 538 dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 539 540 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 541 dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 542 } 543 544 /* DML DSC delay factor workaround */ 545 dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; 546 547 dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; 548 549 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 550 dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 551 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 552 553 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 554 if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { 555 if (dc->debug.use_legacy_soc_bb_mechanism) { 556 unsigned int i = 0, j = 0, num_states = 0; 557 558 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 559 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 560 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 561 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 562 563 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; 564 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 565 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 566 567 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 568 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 569 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 570 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 571 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 572 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 573 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 574 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 575 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 576 } 577 if (!max_dcfclk_mhz) 578 max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; 579 if (!max_dispclk_mhz) 580 max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; 581 if (!max_dppclk_mhz) 582 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; 583 if (!max_phyclk_mhz) 584 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; 585 586 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 587 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 588 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 589 num_dcfclk_sta_targets++; 590 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 591 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 592 for (i = 0; i < num_dcfclk_sta_targets; i++) { 593 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 594 dcfclk_sta_targets[i] = max_dcfclk_mhz; 595 break; 596 } 597 } 598 // Update size of array since we "removed" duplicates 599 num_dcfclk_sta_targets = i + 1; 600 } 601 602 num_uclk_states = bw_params->clk_table.num_entries; 603 604 // Calculate optimal dcfclk for each uclk 605 for (i = 0; i < num_uclk_states; i++) { 606 dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 607 &optimal_dcfclk_for_uclk[i], NULL); 608 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 609 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 610 } 611 } 612 613 // Calculate optimal uclk for each dcfclk sta target 614 for (i = 0; i < num_dcfclk_sta_targets; i++) { 615 for (j = 0; j < num_uclk_states; j++) { 616 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 617 optimal_uclk_for_dcfclk_sta_targets[i] = 618 bw_params->clk_table.entries[j].memclk_mhz * 16; 619 break; 620 } 621 } 622 } 623 624 i = 0; 625 j = 0; 626 // create the final dcfclk and uclk table 627 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 628 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 629 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 630 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 631 } else { 632 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 633 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 634 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 635 } else { 636 j = num_uclk_states; 637 } 638 } 639 } 640 641 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 642 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 643 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 644 } 645 646 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 647 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 648 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 649 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 650 } 651 652 dcn3_21_soc.num_states = num_states; 653 for (i = 0; i < dcn3_21_soc.num_states; i++) { 654 dcn3_21_soc.clock_limits[i].state = i; 655 dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 656 dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 657 658 /* Fill all states with max values of all these clocks */ 659 dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 660 dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 661 dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 662 dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 663 664 /* Populate from bw_params for DTBCLK, SOCCLK */ 665 if (i > 0) { 666 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 667 dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; 668 } else { 669 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 670 } 671 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 672 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 673 } 674 675 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 676 dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; 677 else 678 dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 679 680 if (!dram_speed_mts[i] && i > 0) 681 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; 682 else 683 dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 684 685 /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ 686 /* PHYCLK_D18, PHYCLK_D32 */ 687 dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; 688 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; 689 } 690 } else { 691 build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states); 692 } 693 694 /* Re-init DML with updated bb */ 695 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 696 if (dc->current_state) 697 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); 698 } 699 } 700 701