1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "display_mode_lib.h" 27 #include "dc_features.h" 28 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 29 #include "dcn20/display_mode_vba_20.h" 30 #include "dcn20/display_rq_dlg_calc_20.h" 31 #include "dcn20/display_mode_vba_20v2.h" 32 #include "dcn20/display_rq_dlg_calc_20v2.h" 33 #endif 34 #ifdef CONFIG_DRM_AMD_DC_DCN2_1 35 #include "dcn21/display_mode_vba_21.h" 36 #include "dcn21/display_rq_dlg_calc_21.h" 37 #endif 38 39 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 40 const struct dml_funcs dml20_funcs = { 41 .validate = dml20_ModeSupportAndSystemConfigurationFull, 42 .recalculate = dml20_recalculate, 43 .rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg, 44 .rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg 45 }; 46 47 const struct dml_funcs dml20v2_funcs = { 48 .validate = dml20v2_ModeSupportAndSystemConfigurationFull, 49 .recalculate = dml20v2_recalculate, 50 .rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg, 51 .rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg 52 }; 53 #endif 54 55 #ifdef CONFIG_DRM_AMD_DC_DCN2_1 56 const struct dml_funcs dml21_funcs = { 57 .validate = dml21_ModeSupportAndSystemConfigurationFull, 58 .recalculate = dml21_recalculate, 59 .rq_dlg_get_dlg_reg = dml21_rq_dlg_get_dlg_reg, 60 .rq_dlg_get_rq_reg = dml21_rq_dlg_get_rq_reg 61 }; 62 #endif 63 64 void dml_init_instance(struct display_mode_lib *lib, 65 const struct _vcs_dpi_soc_bounding_box_st *soc_bb, 66 const struct _vcs_dpi_ip_params_st *ip_params, 67 enum dml_project project) 68 { 69 lib->soc = *soc_bb; 70 lib->ip = *ip_params; 71 lib->project = project; 72 switch (project) { 73 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 74 case DML_PROJECT_NAVI10: 75 lib->funcs = dml20_funcs; 76 break; 77 case DML_PROJECT_NAVI10v2: 78 lib->funcs = dml20v2_funcs; 79 break; 80 #endif 81 #ifdef CONFIG_DRM_AMD_DC_DCN2_1 82 case DML_PROJECT_DCN21: 83 lib->funcs = dml21_funcs; 84 break; 85 #endif 86 87 default: 88 break; 89 } 90 } 91 92 const char *dml_get_status_message(enum dm_validation_status status) 93 { 94 switch (status) { 95 case DML_VALIDATION_OK: return "Validation OK"; 96 case DML_FAIL_SCALE_RATIO_TAP: return "Scale ratio/tap"; 97 case DML_FAIL_SOURCE_PIXEL_FORMAT: return "Source pixel format"; 98 case DML_FAIL_VIEWPORT_SIZE: return "Viewport size"; 99 case DML_FAIL_TOTAL_V_ACTIVE_BW: return "Total vertical active bandwidth"; 100 case DML_FAIL_DIO_SUPPORT: return "DIO support"; 101 case DML_FAIL_NOT_ENOUGH_DSC: return "Not enough DSC Units"; 102 case DML_FAIL_DSC_CLK_REQUIRED: return "DSC clock required"; 103 case DML_FAIL_URGENT_LATENCY: return "Urgent latency"; 104 case DML_FAIL_REORDERING_BUFFER: return "Re-ordering buffer"; 105 case DML_FAIL_DISPCLK_DPPCLK: return "Dispclk and Dppclk"; 106 case DML_FAIL_TOTAL_AVAILABLE_PIPES: return "Total available pipes"; 107 case DML_FAIL_NUM_OTG: return "Number of OTG"; 108 case DML_FAIL_WRITEBACK_MODE: return "Writeback mode"; 109 case DML_FAIL_WRITEBACK_LATENCY: return "Writeback latency"; 110 case DML_FAIL_WRITEBACK_SCALE_RATIO_TAP: return "Writeback scale ratio/tap"; 111 case DML_FAIL_CURSOR_SUPPORT: return "Cursor support"; 112 case DML_FAIL_PITCH_SUPPORT: return "Pitch support"; 113 case DML_FAIL_PTE_BUFFER_SIZE: return "PTE buffer size"; 114 case DML_FAIL_DSC_INPUT_BPC: return "DSC input bpc"; 115 case DML_FAIL_PREFETCH_SUPPORT: return "Prefetch support"; 116 case DML_FAIL_V_RATIO_PREFETCH: return "Vertical ratio prefetch"; 117 default: return "Unknown Status"; 118 } 119 } 120