1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* 27 * Pre-requisites: headers required by header of this unit 28 */ 29 #include "hw_translate_dcn20.h" 30 31 #include "dm_services.h" 32 #include "include/gpio_types.h" 33 #include "../hw_translate.h" 34 35 #include "dcn/dcn_1_0_offset.h" 36 #include "dcn/dcn_1_0_sh_mask.h" 37 #include "soc15_hw_ip.h" 38 #include "vega10_ip_offset.h" 39 40 41 42 /* begin ********************* 43 * macros to expend register list macro defined in HW object header file */ 44 45 /* DCN */ 46 #define block HPD 47 #define reg_num 0 48 49 #undef BASE_INNER 50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 51 52 #define BASE(seg) BASE_INNER(seg) 53 54 #undef REG 55 #define REG(reg_name)\ 56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 57 #define SF_HPD(reg_name, field_name, post_fix)\ 58 .field_name = reg_name ## __ ## field_name ## post_fix 59 60 61 /* macros to expend register list macro defined in HW object header file 62 * end *********************/ 63 64 65 static bool offset_to_id( 66 uint32_t offset, 67 uint32_t mask, 68 enum gpio_id *id, 69 uint32_t *en) 70 { 71 switch (offset) { 72 /* GENERIC */ 73 case REG(DC_GPIO_GENERIC_A): 74 *id = GPIO_ID_GENERIC; 75 switch (mask) { 76 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: 77 *en = GPIO_GENERIC_A; 78 return true; 79 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: 80 *en = GPIO_GENERIC_B; 81 return true; 82 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: 83 *en = GPIO_GENERIC_C; 84 return true; 85 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: 86 *en = GPIO_GENERIC_D; 87 return true; 88 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: 89 *en = GPIO_GENERIC_E; 90 return true; 91 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: 92 *en = GPIO_GENERIC_F; 93 return true; 94 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK: 95 *en = GPIO_GENERIC_G; 96 return true; 97 default: 98 ASSERT_CRITICAL(false); 99 return false; 100 } 101 break; 102 /* HPD */ 103 case REG(DC_GPIO_HPD_A): 104 *id = GPIO_ID_HPD; 105 switch (mask) { 106 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: 107 *en = GPIO_HPD_1; 108 return true; 109 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: 110 *en = GPIO_HPD_2; 111 return true; 112 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: 113 *en = GPIO_HPD_3; 114 return true; 115 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: 116 *en = GPIO_HPD_4; 117 return true; 118 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: 119 *en = GPIO_HPD_5; 120 return true; 121 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK: 122 *en = GPIO_HPD_6; 123 return true; 124 default: 125 ASSERT_CRITICAL(false); 126 return false; 127 } 128 break; 129 /* REG(DC_GPIO_GENLK_MASK */ 130 case REG(DC_GPIO_GENLK_A): 131 *id = GPIO_ID_GSL; 132 switch (mask) { 133 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: 134 *en = GPIO_GSL_GENLOCK_CLOCK; 135 return true; 136 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: 137 *en = GPIO_GSL_GENLOCK_VSYNC; 138 return true; 139 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: 140 *en = GPIO_GSL_SWAPLOCK_A; 141 return true; 142 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: 143 *en = GPIO_GSL_SWAPLOCK_B; 144 return true; 145 default: 146 ASSERT_CRITICAL(false); 147 return false; 148 } 149 break; 150 /* DDC */ 151 /* we don't care about the GPIO_ID for DDC 152 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK 153 * directly in the create method */ 154 case REG(DC_GPIO_DDC1_A): 155 *en = GPIO_DDC_LINE_DDC1; 156 return true; 157 case REG(DC_GPIO_DDC2_A): 158 *en = GPIO_DDC_LINE_DDC2; 159 return true; 160 case REG(DC_GPIO_DDC3_A): 161 *en = GPIO_DDC_LINE_DDC3; 162 return true; 163 case REG(DC_GPIO_DDC4_A): 164 *en = GPIO_DDC_LINE_DDC4; 165 return true; 166 case REG(DC_GPIO_DDC5_A): 167 *en = GPIO_DDC_LINE_DDC5; 168 return true; 169 case REG(DC_GPIO_DDC6_A): 170 *en = GPIO_DDC_LINE_DDC6; 171 return true; 172 case REG(DC_GPIO_DDCVGA_A): 173 *en = GPIO_DDC_LINE_DDC_VGA; 174 return true; 175 176 // case REG(DC_GPIO_I2CPAD_A): not exit 177 // case REG(DC_GPIO_PWRSEQ_A): 178 // case REG(DC_GPIO_PAD_STRENGTH_1): 179 // case REG(DC_GPIO_PAD_STRENGTH_2): 180 // case REG(DC_GPIO_DEBUG): 181 /* UNEXPECTED */ 182 default: 183 // case REG(DC_GPIO_SYNCA_A): not exist 184 ASSERT_CRITICAL(false); 185 return false; 186 } 187 } 188 189 static bool id_to_offset( 190 enum gpio_id id, 191 uint32_t en, 192 struct gpio_pin_info *info) 193 { 194 bool result = true; 195 196 switch (id) { 197 case GPIO_ID_DDC_DATA: 198 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; 199 switch (en) { 200 case GPIO_DDC_LINE_DDC1: 201 info->offset = REG(DC_GPIO_DDC1_A); 202 break; 203 case GPIO_DDC_LINE_DDC2: 204 info->offset = REG(DC_GPIO_DDC2_A); 205 break; 206 case GPIO_DDC_LINE_DDC3: 207 info->offset = REG(DC_GPIO_DDC3_A); 208 break; 209 case GPIO_DDC_LINE_DDC4: 210 info->offset = REG(DC_GPIO_DDC4_A); 211 break; 212 case GPIO_DDC_LINE_DDC5: 213 info->offset = REG(DC_GPIO_DDC5_A); 214 break; 215 case GPIO_DDC_LINE_DDC6: 216 info->offset = REG(DC_GPIO_DDC6_A); 217 break; 218 case GPIO_DDC_LINE_DDC_VGA: 219 info->offset = REG(DC_GPIO_DDCVGA_A); 220 break; 221 case GPIO_DDC_LINE_I2C_PAD: 222 default: 223 ASSERT_CRITICAL(false); 224 result = false; 225 } 226 break; 227 case GPIO_ID_DDC_CLOCK: 228 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; 229 switch (en) { 230 case GPIO_DDC_LINE_DDC1: 231 info->offset = REG(DC_GPIO_DDC1_A); 232 break; 233 case GPIO_DDC_LINE_DDC2: 234 info->offset = REG(DC_GPIO_DDC2_A); 235 break; 236 case GPIO_DDC_LINE_DDC3: 237 info->offset = REG(DC_GPIO_DDC3_A); 238 break; 239 case GPIO_DDC_LINE_DDC4: 240 info->offset = REG(DC_GPIO_DDC4_A); 241 break; 242 case GPIO_DDC_LINE_DDC5: 243 info->offset = REG(DC_GPIO_DDC5_A); 244 break; 245 case GPIO_DDC_LINE_DDC6: 246 info->offset = REG(DC_GPIO_DDC6_A); 247 break; 248 case GPIO_DDC_LINE_DDC_VGA: 249 info->offset = REG(DC_GPIO_DDCVGA_A); 250 break; 251 case GPIO_DDC_LINE_I2C_PAD: 252 default: 253 ASSERT_CRITICAL(false); 254 result = false; 255 } 256 break; 257 case GPIO_ID_GENERIC: 258 info->offset = REG(DC_GPIO_GENERIC_A); 259 switch (en) { 260 case GPIO_GENERIC_A: 261 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; 262 break; 263 case GPIO_GENERIC_B: 264 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; 265 break; 266 case GPIO_GENERIC_C: 267 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; 268 break; 269 case GPIO_GENERIC_D: 270 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; 271 break; 272 case GPIO_GENERIC_E: 273 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; 274 break; 275 case GPIO_GENERIC_F: 276 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; 277 break; 278 case GPIO_GENERIC_G: 279 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; 280 break; 281 default: 282 ASSERT_CRITICAL(false); 283 result = false; 284 } 285 break; 286 case GPIO_ID_HPD: 287 info->offset = REG(DC_GPIO_HPD_A); 288 switch (en) { 289 case GPIO_HPD_1: 290 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; 291 break; 292 case GPIO_HPD_2: 293 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; 294 break; 295 case GPIO_HPD_3: 296 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; 297 break; 298 case GPIO_HPD_4: 299 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; 300 break; 301 case GPIO_HPD_5: 302 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; 303 break; 304 case GPIO_HPD_6: 305 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; 306 break; 307 default: 308 ASSERT_CRITICAL(false); 309 result = false; 310 } 311 break; 312 case GPIO_ID_GSL: 313 switch (en) { 314 case GPIO_GSL_GENLOCK_CLOCK: 315 /*not implmented*/ 316 ASSERT_CRITICAL(false); 317 result = false; 318 break; 319 case GPIO_GSL_GENLOCK_VSYNC: 320 /*not implmented*/ 321 ASSERT_CRITICAL(false); 322 result = false; 323 break; 324 case GPIO_GSL_SWAPLOCK_A: 325 /*not implmented*/ 326 ASSERT_CRITICAL(false); 327 result = false; 328 break; 329 case GPIO_GSL_SWAPLOCK_B: 330 /*not implmented*/ 331 ASSERT_CRITICAL(false); 332 result = false; 333 334 break; 335 default: 336 ASSERT_CRITICAL(false); 337 result = false; 338 } 339 break; 340 case GPIO_ID_SYNC: 341 case GPIO_ID_VIP_PAD: 342 default: 343 ASSERT_CRITICAL(false); 344 result = false; 345 } 346 347 if (result) { 348 info->offset_y = info->offset + 2; 349 info->offset_en = info->offset + 1; 350 info->offset_mask = info->offset - 1; 351 352 info->mask_y = info->mask; 353 info->mask_en = info->mask; 354 info->mask_mask = info->mask; 355 } 356 357 return result; 358 } 359 360 /* function table */ 361 static const struct hw_translate_funcs funcs = { 362 .offset_to_id = offset_to_id, 363 .id_to_offset = id_to_offset, 364 }; 365 366 /* 367 * dal_hw_translate_dcn10_init 368 * 369 * @brief 370 * Initialize Hw translate function pointers. 371 * 372 * @param 373 * struct hw_translate *tr - [out] struct of function pointers 374 * 375 */ 376 void dal_hw_translate_dcn20_init(struct hw_translate *tr) 377 { 378 tr->funcs = &funcs; 379 } 380 381