1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "link.h" 49 #include "dcn10/dcn10_hwseq.h" 50 #include "inc/link_enc_cfg.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dce/dce_i2c_hw.h" 53 54 #define DC_LOGGER_INIT(logger) 55 56 #define CTX \ 57 hws->ctx 58 #define REG(reg)\ 59 hws->regs->reg 60 #define DC_LOGGER \ 61 dc->ctx->logger 62 63 64 #undef FN 65 #define FN(reg_name, field_name) \ 66 hws->shifts->field_name, hws->masks->field_name 67 68 static void enable_memory_low_power(struct dc *dc) 69 { 70 struct dce_hwseq *hws = dc->hwseq; 71 int i; 72 73 if (dc->debug.enable_mem_low_power.bits.dmcu) { 74 // Force ERAM to shutdown if DMCU is not enabled 75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 76 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 77 } 78 } 79 80 // Set default OPTC memory power states 81 if (dc->debug.enable_mem_low_power.bits.optc) { 82 // Shutdown when unassigned and light sleep in VBLANK 83 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 84 } 85 86 if (dc->debug.enable_mem_low_power.bits.vga) { 87 // Power down VGA memory 88 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 89 } 90 91 if (dc->debug.enable_mem_low_power.bits.mpc && 92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 if (dc->res_pool->stream_enc[i]->vpg) 100 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 101 #if defined(CONFIG_DRM_AMD_DC_FP) 102 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 103 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 104 #endif 105 } 106 107 } 108 109 void dcn31_init_hw(struct dc *dc) 110 { 111 struct abm **abms = dc->res_pool->multiple_abms; 112 struct dce_hwseq *hws = dc->hwseq; 113 struct dc_bios *dcb = dc->ctx->dc_bios; 114 struct resource_pool *res_pool = dc->res_pool; 115 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 116 uint32_t user_level = MAX_BACKLIGHT_LEVEL; 117 int i; 118 119 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 120 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 121 122 if (!dcb->funcs->is_accelerated_mode(dcb)) { 123 hws->funcs.bios_golden_init(dc); 124 if (hws->funcs.disable_vga) 125 hws->funcs.disable_vga(dc->hwseq); 126 } 127 // Initialize the dccg 128 if (res_pool->dccg->funcs->dccg_init) 129 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 130 131 enable_memory_low_power(dc); 132 133 if (dc->ctx->dc_bios->fw_info_valid) { 134 res_pool->ref_clocks.xtalin_clock_inKhz = 135 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 136 137 if (res_pool->dccg && res_pool->hubbub) { 138 139 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 140 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 141 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 142 143 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 144 res_pool->ref_clocks.dccg_ref_clock_inKhz, 145 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 146 } else { 147 // Not all ASICs have DCCG sw component 148 res_pool->ref_clocks.dccg_ref_clock_inKhz = 149 res_pool->ref_clocks.xtalin_clock_inKhz; 150 res_pool->ref_clocks.dchub_ref_clock_inKhz = 151 res_pool->ref_clocks.xtalin_clock_inKhz; 152 } 153 } else 154 ASSERT_CRITICAL(false); 155 156 for (i = 0; i < dc->link_count; i++) { 157 /* Power up AND update implementation according to the 158 * required signal (which may be different from the 159 * default signal on connector). 160 */ 161 struct dc_link *link = dc->links[i]; 162 163 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 164 continue; 165 166 link->link_enc->funcs->hw_init(link->link_enc); 167 168 /* Check for enabled DIG to identify enabled display */ 169 if (link->link_enc->funcs->is_dig_enabled && 170 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 171 link->link_status.link_active = true; 172 if (link->link_enc->funcs->fec_is_active && 173 link->link_enc->funcs->fec_is_active(link->link_enc)) 174 link->fec_state = dc_link_fec_enabled; 175 } 176 } 177 178 /* we want to turn off all dp displays before doing detection */ 179 dc->link_srv->blank_all_dp_displays(dc); 180 181 if (hws->funcs.enable_power_gating_plane) 182 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 183 184 /* If taking control over from VBIOS, we may want to optimize our first 185 * mode set, so we need to skip powering down pipes until we know which 186 * pipes we want to use. 187 * Otherwise, if taking control is not possible, we need to power 188 * everything down. 189 */ 190 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 191 192 // we want to turn off edp displays if odm is enabled and no seamless boot 193 if (!dc->caps.seamless_odm) { 194 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 195 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 196 uint32_t num_opps, opp_id_src0, opp_id_src1; 197 198 num_opps = 1; 199 if (tg) { 200 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { 201 tg->funcs->get_optc_source(tg, &num_opps, 202 &opp_id_src0, &opp_id_src1); 203 } 204 } 205 206 if (num_opps > 1) { 207 dc->link_srv->blank_all_edp_displays(dc); 208 break; 209 } 210 } 211 } 212 213 hws->funcs.init_pipes(dc, dc->current_state); 214 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 215 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 216 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 217 } 218 219 for (i = 0; i < res_pool->audio_count; i++) { 220 struct audio *audio = res_pool->audios[i]; 221 222 audio->funcs->hw_init(audio); 223 } 224 225 for (i = 0; i < dc->link_count; i++) { 226 struct dc_link *link = dc->links[i]; 227 228 if (link->panel_cntl) { 229 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 230 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL; 231 } 232 } 233 234 for (i = 0; i < dc->res_pool->pipe_count; i++) { 235 if (abms[i] != NULL) 236 abms[i]->funcs->abm_init(abms[i], backlight, user_level); 237 } 238 239 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 240 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 241 242 // Set i2c to light sleep until engine is setup 243 if (dc->debug.enable_mem_low_power.bits.i2c) 244 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 245 246 if (hws->funcs.setup_hpo_hw_control) 247 hws->funcs.setup_hpo_hw_control(hws, false); 248 249 if (!dc->debug.disable_clock_gate) { 250 /* enable all DCN clock gating */ 251 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 252 253 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 254 255 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 256 } 257 258 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 259 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 260 261 if (dc->clk_mgr->funcs->notify_wm_ranges) 262 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 263 264 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 265 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 266 267 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 268 dc->res_pool->hubbub->funcs->force_pstate_change_control( 269 dc->res_pool->hubbub, false, false); 270 #if defined(CONFIG_DRM_AMD_DC_FP) 271 if (dc->res_pool->hubbub->funcs->init_crb) 272 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 273 #endif 274 275 // Get DMCUB capabilities 276 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); 277 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 278 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 279 } 280 281 void dcn31_dsc_pg_control( 282 struct dce_hwseq *hws, 283 unsigned int dsc_inst, 284 bool power_on) 285 { 286 uint32_t power_gate = power_on ? 0 : 1; 287 uint32_t pwr_status = power_on ? 0 : 2; 288 uint32_t org_ip_request_cntl = 0; 289 290 if (hws->ctx->dc->debug.disable_dsc_power_gate) 291 return; 292 293 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 294 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 295 power_on) 296 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 297 hws->ctx->dc->res_pool->dccg, dsc_inst); 298 299 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 300 if (org_ip_request_cntl == 0) 301 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 302 303 switch (dsc_inst) { 304 case 0: /* DSC0 */ 305 REG_UPDATE(DOMAIN16_PG_CONFIG, 306 DOMAIN_POWER_GATE, power_gate); 307 308 REG_WAIT(DOMAIN16_PG_STATUS, 309 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 310 1, 1000); 311 break; 312 case 1: /* DSC1 */ 313 REG_UPDATE(DOMAIN17_PG_CONFIG, 314 DOMAIN_POWER_GATE, power_gate); 315 316 REG_WAIT(DOMAIN17_PG_STATUS, 317 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 318 1, 1000); 319 break; 320 case 2: /* DSC2 */ 321 REG_UPDATE(DOMAIN18_PG_CONFIG, 322 DOMAIN_POWER_GATE, power_gate); 323 324 REG_WAIT(DOMAIN18_PG_STATUS, 325 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 326 1, 1000); 327 break; 328 default: 329 BREAK_TO_DEBUGGER(); 330 break; 331 } 332 333 if (org_ip_request_cntl == 0) 334 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 335 336 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 337 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 338 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 339 hws->ctx->dc->res_pool->dccg, dsc_inst); 340 } 341 342 } 343 344 345 void dcn31_enable_power_gating_plane( 346 struct dce_hwseq *hws, 347 bool enable) 348 { 349 bool force_on = true; /* disable power gating */ 350 uint32_t org_ip_request_cntl = 0; 351 352 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 353 force_on = false; 354 355 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 356 if (org_ip_request_cntl == 0) 357 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 358 /* DCHUBP0/1/2/3/4/5 */ 359 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 360 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 361 /* DPP0/1/2/3/4/5 */ 362 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 363 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 364 365 force_on = true; /* disable power gating */ 366 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 367 force_on = false; 368 369 /* DCS0/1/2/3/4/5 */ 370 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 371 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 372 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 373 374 if (org_ip_request_cntl == 0) 375 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 376 } 377 378 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 379 { 380 bool is_hdmi_tmds; 381 bool is_dp; 382 383 ASSERT(pipe_ctx->stream); 384 385 if (pipe_ctx->stream_res.stream_enc == NULL) 386 return; /* this is not root pipe */ 387 388 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 389 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 390 391 if (!is_hdmi_tmds && !is_dp) 392 return; 393 394 if (is_hdmi_tmds) 395 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 396 pipe_ctx->stream_res.stream_enc, 397 &pipe_ctx->stream_res.encoder_info_frame); 398 else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 399 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( 400 pipe_ctx->stream_res.hpo_dp_stream_enc, 401 &pipe_ctx->stream_res.encoder_info_frame); 402 return; 403 } else { 404 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 405 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 406 pipe_ctx->stream_res.stream_enc, 407 &pipe_ctx->stream_res.encoder_info_frame); 408 409 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 410 pipe_ctx->stream_res.stream_enc, 411 &pipe_ctx->stream_res.encoder_info_frame); 412 } 413 } 414 void dcn31_z10_save_init(struct dc *dc) 415 { 416 union dmub_rb_cmd cmd; 417 418 memset(&cmd, 0, sizeof(cmd)); 419 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 420 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 421 422 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 423 } 424 425 void dcn31_z10_restore(const struct dc *dc) 426 { 427 union dmub_rb_cmd cmd; 428 429 /* 430 * DMUB notifies whether restore is required. 431 * Optimization to avoid sending commands when not required. 432 */ 433 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 434 return; 435 436 memset(&cmd, 0, sizeof(cmd)); 437 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 438 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 439 440 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 441 } 442 443 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 444 { 445 uint32_t power_gate = power_on ? 0 : 1; 446 uint32_t pwr_status = power_on ? 0 : 2; 447 uint32_t org_ip_request_cntl; 448 if (hws->ctx->dc->debug.disable_hubp_power_gate) 449 return; 450 451 if (REG(DOMAIN0_PG_CONFIG) == 0) 452 return; 453 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 454 if (org_ip_request_cntl == 0) 455 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 456 457 switch (hubp_inst) { 458 case 0: 459 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 460 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 461 break; 462 case 1: 463 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 464 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 465 break; 466 case 2: 467 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 468 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 469 break; 470 case 3: 471 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 472 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 473 break; 474 default: 475 BREAK_TO_DEBUGGER(); 476 break; 477 } 478 if (org_ip_request_cntl == 0) 479 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 480 } 481 482 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 483 { 484 struct dcn_hubbub_phys_addr_config config; 485 486 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 487 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 488 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 489 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 490 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 491 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 492 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 493 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 494 495 if (pa_config->gart_config.base_addr_is_mc_addr) { 496 /* Convert from MC address to offset into FB */ 497 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 498 pa_config->system_aperture.fb_base + 499 pa_config->system_aperture.fb_offset; 500 } else 501 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 502 503 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 504 } 505 506 static void dcn31_reset_back_end_for_pipe( 507 struct dc *dc, 508 struct pipe_ctx *pipe_ctx, 509 struct dc_state *context) 510 { 511 struct dc_link *link; 512 513 DC_LOGGER_INIT(dc->ctx->logger); 514 if (pipe_ctx->stream_res.stream_enc == NULL) { 515 pipe_ctx->stream = NULL; 516 return; 517 } 518 ASSERT(!pipe_ctx->top_pipe); 519 520 dc->hwss.set_abm_immediate_disable(pipe_ctx); 521 522 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 523 pipe_ctx->stream_res.tg, 524 OPTC_DSC_DISABLED, 0, 0); 525 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 526 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 527 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 528 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 529 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 530 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 531 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; 532 533 if (pipe_ctx->stream_res.tg->funcs->set_drr) 534 pipe_ctx->stream_res.tg->funcs->set_drr( 535 pipe_ctx->stream_res.tg, NULL); 536 537 link = pipe_ctx->stream->link; 538 /* DPMS may already disable or */ 539 /* dpms_off status is incorrect due to fastboot 540 * feature. When system resume from S4 with second 541 * screen only, the dpms_off would be true but 542 * VBIOS lit up eDP, so check link status too. 543 */ 544 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 545 dc->link_srv->set_dpms_off(pipe_ctx); 546 else if (pipe_ctx->stream_res.audio) 547 dc->hwss.disable_audio_stream(pipe_ctx); 548 549 /* free acquired resources */ 550 if (pipe_ctx->stream_res.audio) { 551 /*disable az_endpoint*/ 552 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 553 554 /*free audio*/ 555 if (dc->caps.dynamic_audio == true) { 556 /*we have to dynamic arbitrate the audio endpoints*/ 557 /*we free the resource, need reset is_audio_acquired*/ 558 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 559 pipe_ctx->stream_res.audio, false); 560 pipe_ctx->stream_res.audio = NULL; 561 } 562 } 563 564 pipe_ctx->stream = NULL; 565 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 566 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 567 } 568 569 void dcn31_reset_hw_ctx_wrap( 570 struct dc *dc, 571 struct dc_state *context) 572 { 573 int i; 574 struct dce_hwseq *hws = dc->hwseq; 575 576 /* Reset Back End*/ 577 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 578 struct pipe_ctx *pipe_ctx_old = 579 &dc->current_state->res_ctx.pipe_ctx[i]; 580 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 581 582 if (!pipe_ctx_old->stream) 583 continue; 584 585 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 586 continue; 587 588 if (!pipe_ctx->stream || 589 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 590 struct clock_source *old_clk = pipe_ctx_old->clock_source; 591 592 /* Reset pipe which is seamless boot stream. */ 593 if (!pipe_ctx_old->plane_state && 594 dc->res_pool->hubbub->funcs->program_det_size && 595 dc->res_pool->hubbub->funcs->wait_for_det_apply) { 596 dc->res_pool->hubbub->funcs->program_det_size( 597 dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0); 598 /* Wait det size changed. */ 599 dc->res_pool->hubbub->funcs->wait_for_det_apply( 600 dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst); 601 } 602 603 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 604 if (hws->funcs.enable_stream_gating) 605 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 606 if (old_clk) 607 old_clk->funcs->cs_power_down(old_clk); 608 } 609 } 610 611 /* New dc_state in the process of being applied to hardware. */ 612 link_enc_cfg_set_transient_mode(dc, dc->current_state, context); 613 } 614 615 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 616 { 617 if (hws->ctx->dc->debug.hpo_optimization) 618 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 619 } 620