1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_HWSS_DCN35_H__ 28 #define __DC_HWSS_DCN35_H__ 29 30 #include "hw_sequencer_private.h" 31 32 struct dc; 33 34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 35 36 void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); 37 38 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on); 39 40 void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable); 41 42 void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable); 43 44 void dcn35_init_hw(struct dc *dc); 45 46 void dcn35_disable_link_output(struct dc_link *link, 47 const struct link_resource *link_res, 48 enum signal_type signal); 49 50 void dcn35_power_down_on_boot(struct dc *dc); 51 52 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable); 53 54 void dcn35_z10_restore(const struct dc *dc); 55 56 void dcn35_init_pipes(struct dc *dc, struct dc_state *context); 57 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx); 58 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 59 struct dc_state *context); 60 void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 61 62 void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, 63 struct pg_block_update *update_state); 64 void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, 65 struct pg_block_update *update_state); 66 void dcn35_hw_block_power_up(struct dc *dc, 67 struct pg_block_update *update_state); 68 void dcn35_hw_block_power_down(struct dc *dc, 69 struct pg_block_update *update_state); 70 void dcn35_root_clock_control(struct dc *dc, 71 struct pg_block_update *update_state, bool power_on); 72 73 void dcn35_prepare_bandwidth( 74 struct dc *dc, 75 struct dc_state *context); 76 77 void dcn35_optimize_bandwidth( 78 struct dc *dc, 79 struct dc_state *context); 80 81 void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable); 82 void dcn35_dsc_pg_control( 83 struct dce_hwseq *hws, 84 unsigned int dsc_inst, 85 bool power_on); 86 87 void dcn35_set_idle_state(const struct dc *dc, bool allow_idle); 88 uint32_t dcn35_get_idle_state(const struct dc *dc); 89 90 void dcn35_set_drr(struct pipe_ctx **pipe_ctx, 91 int num_pipes, struct dc_crtc_timing_adjust adjust); 92 93 void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx, 94 int num_pipes, const struct dc_static_screen_params *params); 95 96 #endif /* __DC_HWSS_DCN35_H__ */ 97