1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 37 #include "mpc.h" 38 #endif 39 40 #define MAX_CLOCK_SOURCES 7 41 42 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 43 uint32_t controller_id); 44 45 #include "grph_object_id.h" 46 #include "link_encoder.h" 47 #include "stream_encoder.h" 48 #include "clock_source.h" 49 #include "audio.h" 50 #include "dm_pp_smu.h" 51 52 53 /************ link *****************/ 54 struct link_init_data { 55 const struct dc *dc; 56 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 57 uint32_t connector_index; /* this will be mapped to the HPD pins */ 58 uint32_t link_index; /* this is mapped to DAL display_index 59 TODO: remove it when DC is complete. */ 60 }; 61 62 enum { 63 FREE_ACQUIRED_RESOURCE = 0, 64 KEEP_ACQUIRED_RESOURCE = 1, 65 }; 66 67 struct dc_link *link_create(const struct link_init_data *init_params); 68 void link_destroy(struct dc_link **link); 69 70 enum dc_status dc_link_validate_mode_timing( 71 const struct dc_stream_state *stream, 72 struct dc_link *link, 73 const struct dc_crtc_timing *timing); 74 75 void core_link_resume(struct dc_link *link); 76 77 void core_link_enable_stream( 78 struct dc_state *state, 79 struct pipe_ctx *pipe_ctx); 80 81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option); 82 83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 84 /********** DAL Core*********************/ 85 #include "hw/clk_mgr.h" 86 #include "transform.h" 87 #include "dpp.h" 88 89 struct resource_pool; 90 struct dc_state; 91 struct resource_context; 92 93 struct resource_funcs { 94 void (*destroy)(struct resource_pool **pool); 95 void (*link_init)(struct dc_link *link); 96 struct link_encoder *(*link_enc_create)( 97 const struct encoder_init_data *init); 98 bool (*validate_bandwidth)( 99 struct dc *dc, 100 struct dc_state *context, 101 bool fast_validate); 102 103 enum dc_status (*validate_global)( 104 struct dc *dc, 105 struct dc_state *context); 106 107 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 108 struct dc_state *context, 109 const struct resource_pool *pool, 110 struct dc_stream_state *stream); 111 112 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 113 114 enum dc_status (*add_stream_to_ctx)( 115 struct dc *dc, 116 struct dc_state *new_ctx, 117 struct dc_stream_state *dc_stream); 118 119 enum dc_status (*remove_stream_from_ctx)( 120 struct dc *dc, 121 struct dc_state *new_ctx, 122 struct dc_stream_state *stream); 123 enum dc_status (*get_default_swizzle_mode)( 124 struct dc_plane_state *plane_state); 125 126 }; 127 128 struct audio_support{ 129 bool dp_audio; 130 bool hdmi_audio_on_dongle; 131 bool hdmi_audio_native; 132 }; 133 134 #define NO_UNDERLAY_PIPE -1 135 136 struct resource_pool { 137 struct mem_input *mis[MAX_PIPES]; 138 struct hubp *hubps[MAX_PIPES]; 139 struct input_pixel_processor *ipps[MAX_PIPES]; 140 struct transform *transforms[MAX_PIPES]; 141 struct dpp *dpps[MAX_PIPES]; 142 struct output_pixel_processor *opps[MAX_PIPES]; 143 struct timing_generator *timing_generators[MAX_PIPES]; 144 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 145 struct hubbub *hubbub; 146 struct mpc *mpc; 147 struct pp_smu_funcs *pp_smu; 148 struct dce_aux *engines[MAX_PIPES]; 149 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 150 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 151 bool i2c_hw_buffer_in_use; 152 153 unsigned int pipe_count; 154 unsigned int underlay_pipe_index; 155 unsigned int stream_enc_count; 156 157 struct { 158 unsigned int xtalin_clock_inKhz; 159 unsigned int dccg_ref_clock_inKhz; 160 unsigned int dchub_ref_clock_inKhz; 161 } ref_clocks; 162 unsigned int timing_generator_count; 163 164 /* 165 * reserved clock source for DP 166 */ 167 struct clock_source *dp_clock_source; 168 169 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 170 unsigned int clk_src_count; 171 172 struct audio *audios[MAX_PIPES]; 173 unsigned int audio_count; 174 struct audio_support audio_support; 175 176 struct clk_mgr *clk_mgr; 177 struct dccg *dccg; 178 struct irq_service *irqs; 179 180 struct abm *abm; 181 struct dmcu *dmcu; 182 183 const struct resource_funcs *funcs; 184 const struct resource_caps *res_cap; 185 }; 186 187 struct dcn_fe_bandwidth { 188 int dppclk_khz; 189 }; 190 191 struct stream_resource { 192 struct output_pixel_processor *opp; 193 struct timing_generator *tg; 194 struct stream_encoder *stream_enc; 195 struct audio *audio; 196 197 struct pixel_clk_params pix_clk_params; 198 struct encoder_info_frame encoder_info_frame; 199 200 struct abm *abm; 201 }; 202 203 struct plane_resource { 204 struct scaler_data scl_data; 205 struct hubp *hubp; 206 struct mem_input *mi; 207 struct input_pixel_processor *ipp; 208 struct transform *xfm; 209 struct dpp *dpp; 210 uint8_t mpcc_inst; 211 212 struct dcn_fe_bandwidth bw; 213 }; 214 215 struct pipe_ctx { 216 struct dc_plane_state *plane_state; 217 struct dc_stream_state *stream; 218 219 struct plane_resource plane_res; 220 struct stream_resource stream_res; 221 222 struct clock_source *clock_source; 223 224 struct pll_settings pll_settings; 225 226 uint8_t pipe_idx; 227 228 struct pipe_ctx *top_pipe; 229 struct pipe_ctx *bottom_pipe; 230 231 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 232 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 233 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 234 struct _vcs_dpi_display_rq_regs_st rq_regs; 235 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 236 #endif 237 }; 238 239 struct resource_context { 240 struct pipe_ctx pipe_ctx[MAX_PIPES]; 241 bool is_stream_enc_acquired[MAX_PIPES * 2]; 242 bool is_audio_acquired[MAX_PIPES]; 243 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 244 uint8_t dp_clock_source_ref_count; 245 }; 246 247 struct dce_bw_output { 248 bool cpuc_state_change_enable; 249 bool cpup_state_change_enable; 250 bool stutter_mode_enable; 251 bool nbp_state_change_enable; 252 bool all_displays_in_sync; 253 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 254 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 255 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 256 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 257 int sclk_khz; 258 int sclk_deep_sleep_khz; 259 int yclk_khz; 260 int dispclk_khz; 261 int blackout_recovery_time_us; 262 }; 263 264 struct dcn_bw_output { 265 struct dc_clocks clk; 266 struct dcn_watermark_set watermarks; 267 }; 268 269 union bw_output { 270 struct dcn_bw_output dcn; 271 struct dce_bw_output dce; 272 }; 273 274 struct bw_context { 275 union bw_output bw; 276 struct display_mode_lib dml; 277 }; 278 /** 279 * struct dc_state - The full description of a state requested by a user 280 * 281 * @streams: Stream properties 282 * @stream_status: The planes on a given stream 283 * @res_ctx: Persistent state of resources 284 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 285 * @pp_display_cfg: PowerPlay clocks and settings 286 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 287 * 288 */ 289 struct dc_state { 290 struct dc_stream_state *streams[MAX_PIPES]; 291 struct dc_stream_status stream_status[MAX_PIPES]; 292 uint8_t stream_count; 293 294 struct resource_context res_ctx; 295 296 struct bw_context bw_ctx; 297 298 /* Note: these are big structures, do *not* put on stack! */ 299 struct dm_pp_display_configuration pp_display_cfg; 300 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 301 struct dcn_bw_internal_vars dcn_bw_vars; 302 #endif 303 304 struct clk_mgr *clk_mgr; 305 306 struct { 307 bool full_update_needed : 1; 308 } commit_hints; 309 310 struct kref refcount; 311 }; 312 313 #endif /* _CORE_TYPES_H_ */ 314