1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 #include "dmub/inc/dmub_cmd.h" 41 #include "pg_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 #define MAX_SVP_PHANTOM_STREAMS 2 45 #define MAX_SVP_PHANTOM_PLANES 2 46 47 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 48 uint32_t controller_id); 49 50 #include "grph_object_id.h" 51 #include "link_encoder.h" 52 #include "stream_encoder.h" 53 #include "clock_source.h" 54 #include "audio.h" 55 #include "dm_pp_smu.h" 56 #include "dm_cp_psp.h" 57 #include "link_hwss.h" 58 59 /********** DAL Core*********************/ 60 #include "transform.h" 61 #include "dpp.h" 62 63 struct resource_pool; 64 struct dc_state; 65 struct resource_context; 66 struct clk_bw_params; 67 68 struct resource_funcs { 69 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 70 void (*destroy)(struct resource_pool **pool); 71 void (*link_init)(struct dc_link *link); 72 struct panel_cntl*(*panel_cntl_create)( 73 const struct panel_cntl_init_data *panel_cntl_init_data); 74 struct link_encoder *(*link_enc_create)( 75 struct dc_context *ctx, 76 const struct encoder_init_data *init); 77 /* Create a minimal link encoder object with no dc_link object 78 * associated with it. */ 79 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 80 81 bool (*validate_bandwidth)( 82 struct dc *dc, 83 struct dc_state *context, 84 bool fast_validate); 85 void (*calculate_wm_and_dlg)( 86 struct dc *dc, struct dc_state *context, 87 display_e2e_pipe_params_st *pipes, 88 int pipe_cnt, 89 int vlevel); 90 void (*update_soc_for_wm_a)( 91 struct dc *dc, struct dc_state *context); 92 93 /** 94 * @populate_dml_pipes - Populate pipe data struct 95 * 96 * Returns: 97 * Total of pipes available in the specific ASIC. 98 */ 99 int (*populate_dml_pipes)( 100 struct dc *dc, 101 struct dc_state *context, 102 display_e2e_pipe_params_st *pipes, 103 bool fast_validate); 104 105 /* 106 * Algorithm for assigning available link encoders to links. 107 * 108 * Update link_enc_assignments table and link_enc_avail list accordingly in 109 * struct resource_context. 110 */ 111 void (*link_encs_assign)( 112 struct dc *dc, 113 struct dc_state *state, 114 struct dc_stream_state *streams[], 115 uint8_t stream_count); 116 /* 117 * Unassign a link encoder from a stream. 118 * 119 * Update link_enc_assignments table and link_enc_avail list accordingly in 120 * struct resource_context. 121 */ 122 void (*link_enc_unassign)( 123 struct dc_state *state, 124 struct dc_stream_state *stream); 125 126 enum dc_status (*validate_global)( 127 struct dc *dc, 128 struct dc_state *context); 129 130 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 131 const struct dc_state *cur_ctx, 132 struct dc_state *new_ctx, 133 const struct resource_pool *pool, 134 const struct pipe_ctx *opp_head_pipe); 135 136 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 137 const struct dc_state *cur_ctx, 138 struct dc_state *new_ctx, 139 const struct resource_pool *pool, 140 const struct pipe_ctx *otg_master); 141 142 void (*release_pipe)(struct dc_state *context, 143 struct pipe_ctx *pipe, 144 const struct resource_pool *pool); 145 146 enum dc_status (*validate_plane)( 147 const struct dc_plane_state *plane_state, 148 struct dc_caps *caps); 149 150 enum dc_status (*add_stream_to_ctx)( 151 struct dc *dc, 152 struct dc_state *new_ctx, 153 struct dc_stream_state *dc_stream); 154 155 enum dc_status (*remove_stream_from_ctx)( 156 struct dc *dc, 157 struct dc_state *new_ctx, 158 struct dc_stream_state *stream); 159 enum dc_status (*patch_unknown_plane_state)( 160 struct dc_plane_state *plane_state); 161 162 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 163 struct resource_context *res_ctx, 164 const struct resource_pool *pool, 165 struct dc_stream_state *stream); 166 void (*populate_dml_writeback_from_context)( 167 struct dc *dc, 168 struct resource_context *res_ctx, 169 display_e2e_pipe_params_st *pipes); 170 171 void (*set_mcif_arb_params)( 172 struct dc *dc, 173 struct dc_state *context, 174 display_e2e_pipe_params_st *pipes, 175 int pipe_cnt); 176 void (*update_bw_bounding_box)( 177 struct dc *dc, 178 struct clk_bw_params *bw_params); 179 bool (*acquire_post_bldn_3dlut)( 180 struct resource_context *res_ctx, 181 const struct resource_pool *pool, 182 int mpcc_id, 183 struct dc_3dlut **lut, 184 struct dc_transfer_func **shaper); 185 186 bool (*release_post_bldn_3dlut)( 187 struct resource_context *res_ctx, 188 const struct resource_pool *pool, 189 struct dc_3dlut **lut, 190 struct dc_transfer_func **shaper); 191 192 enum dc_status (*add_dsc_to_stream_resource)( 193 struct dc *dc, struct dc_state *state, 194 struct dc_stream_state *stream); 195 196 void (*add_phantom_pipes)( 197 struct dc *dc, 198 struct dc_state *context, 199 display_e2e_pipe_params_st *pipes, 200 unsigned int pipe_cnt, 201 unsigned int index); 202 203 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update); 204 void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context); 205 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 206 void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 207 void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 208 }; 209 210 struct audio_support{ 211 bool dp_audio; 212 bool hdmi_audio_on_dongle; 213 bool hdmi_audio_native; 214 }; 215 216 #define NO_UNDERLAY_PIPE -1 217 218 struct resource_pool { 219 struct mem_input *mis[MAX_PIPES]; 220 struct hubp *hubps[MAX_PIPES]; 221 struct input_pixel_processor *ipps[MAX_PIPES]; 222 struct transform *transforms[MAX_PIPES]; 223 struct dpp *dpps[MAX_PIPES]; 224 struct output_pixel_processor *opps[MAX_PIPES]; 225 struct timing_generator *timing_generators[MAX_PIPES]; 226 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 227 struct hubbub *hubbub; 228 struct mpc *mpc; 229 struct pp_smu_funcs *pp_smu; 230 struct dce_aux *engines[MAX_PIPES]; 231 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 232 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 233 bool i2c_hw_buffer_in_use; 234 235 struct dwbc *dwbc[MAX_DWB_PIPES]; 236 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 237 struct { 238 unsigned int gsl_0:1; 239 unsigned int gsl_1:1; 240 unsigned int gsl_2:1; 241 } gsl_groups; 242 243 struct display_stream_compressor *dscs[MAX_PIPES]; 244 245 unsigned int pipe_count; 246 unsigned int underlay_pipe_index; 247 unsigned int stream_enc_count; 248 249 /* An array for accessing the link encoder objects that have been created. 250 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 251 */ 252 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 253 /* Number of DIG link encoder objects created - i.e. number of valid 254 * entries in link_encoders array. 255 */ 256 unsigned int dig_link_enc_count; 257 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 258 unsigned int usb4_dpia_count; 259 260 unsigned int hpo_dp_stream_enc_count; 261 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 262 unsigned int hpo_dp_link_enc_count; 263 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 264 struct dc_3dlut *mpc_lut[MAX_PIPES]; 265 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 266 267 struct { 268 unsigned int xtalin_clock_inKhz; 269 unsigned int dccg_ref_clock_inKhz; 270 unsigned int dchub_ref_clock_inKhz; 271 } ref_clocks; 272 unsigned int timing_generator_count; 273 unsigned int mpcc_count; 274 275 unsigned int writeback_pipe_count; 276 /* 277 * reserved clock source for DP 278 */ 279 struct clock_source *dp_clock_source; 280 281 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 282 unsigned int clk_src_count; 283 284 struct audio *audios[MAX_AUDIOS]; 285 unsigned int audio_count; 286 struct audio_support audio_support; 287 288 struct dccg *dccg; 289 struct pg_cntl *pg_cntl; 290 struct irq_service *irqs; 291 292 struct abm *abm; 293 struct dmcu *dmcu; 294 struct dmub_psr *psr; 295 296 struct dmub_replay *replay; 297 298 struct abm *multiple_abms[MAX_PIPES]; 299 300 const struct resource_funcs *funcs; 301 const struct resource_caps *res_cap; 302 303 struct ddc_service *oem_device; 304 }; 305 306 struct dcn_fe_bandwidth { 307 int dppclk_khz; 308 309 }; 310 311 /* Parameters needed to call set_disp_pattern_generator */ 312 struct test_pattern_params { 313 enum controller_dp_test_pattern test_pattern; 314 enum controller_dp_color_space color_space; 315 enum dc_color_depth color_depth; 316 int width; 317 int height; 318 int offset; 319 }; 320 321 struct stream_resource { 322 struct output_pixel_processor *opp; 323 struct display_stream_compressor *dsc; 324 struct timing_generator *tg; 325 struct stream_encoder *stream_enc; 326 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 327 struct audio *audio; 328 329 struct pixel_clk_params pix_clk_params; 330 struct encoder_info_frame encoder_info_frame; 331 332 struct abm *abm; 333 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 334 * otherwise it's using group number 'gsl_group-1' 335 */ 336 uint8_t gsl_group; 337 338 struct test_pattern_params test_pattern_params; 339 }; 340 341 struct plane_resource { 342 struct scaler_data scl_data; 343 struct hubp *hubp; 344 struct mem_input *mi; 345 struct input_pixel_processor *ipp; 346 struct transform *xfm; 347 struct dpp *dpp; 348 uint8_t mpcc_inst; 349 350 struct dcn_fe_bandwidth bw; 351 }; 352 353 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 354 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 355 356 /* all mappable hardware resources used to enable a link */ 357 struct link_resource { 358 struct hpo_dp_link_encoder *hpo_dp_link_enc; 359 }; 360 361 struct link_config { 362 struct dc_link_settings dp_link_settings; 363 }; 364 union pipe_update_flags { 365 struct { 366 uint32_t enable : 1; 367 uint32_t disable : 1; 368 uint32_t odm : 1; 369 uint32_t global_sync : 1; 370 uint32_t opp_changed : 1; 371 uint32_t tg_changed : 1; 372 uint32_t mpcc : 1; 373 uint32_t dppclk : 1; 374 uint32_t hubp_interdependent : 1; 375 uint32_t hubp_rq_dlg_ttu : 1; 376 uint32_t gamut_remap : 1; 377 uint32_t scaler : 1; 378 uint32_t viewport : 1; 379 uint32_t plane_changed : 1; 380 uint32_t det_size : 1; 381 uint32_t unbounded_req : 1; 382 uint32_t test_pattern_changed : 1; 383 } bits; 384 uint32_t raw; 385 }; 386 387 struct pipe_ctx { 388 struct dc_plane_state *plane_state; 389 struct dc_stream_state *stream; 390 391 struct plane_resource plane_res; 392 393 /** 394 * @stream_res: Reference to DCN resource components such OPP and DSC. 395 */ 396 struct stream_resource stream_res; 397 struct link_resource link_res; 398 399 struct clock_source *clock_source; 400 401 struct pll_settings pll_settings; 402 403 /** 404 * @link_config: 405 * 406 * link config records software decision for what link config should be 407 * enabled given current link capability and stream during hw resource 408 * mapping. This is to decouple the dependency on link capability during 409 * dc commit or update. 410 */ 411 struct link_config link_config; 412 413 uint8_t pipe_idx; 414 uint8_t pipe_idx_syncd; 415 416 struct pipe_ctx *top_pipe; 417 struct pipe_ctx *bottom_pipe; 418 struct pipe_ctx *next_odm_pipe; 419 struct pipe_ctx *prev_odm_pipe; 420 421 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 422 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 423 struct _vcs_dpi_display_rq_regs_st rq_regs; 424 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 425 struct _vcs_dpi_display_rq_params_st dml_rq_param; 426 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 427 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 428 int det_buffer_size_kb; 429 bool unbounded_req; 430 unsigned int surface_size_in_mall_bytes; 431 432 struct dwbc *dwbc; 433 struct mcif_wb *mcif_wb; 434 union pipe_update_flags update_flags; 435 struct tg_color visual_confirm_color; 436 bool has_vactive_margin; 437 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 438 uint8_t subvp_index; 439 }; 440 441 /* Data used for dynamic link encoder assignment. 442 * Tracks current and future assignments; available link encoders; 443 * and mode of operation (whether to use current or future assignments). 444 */ 445 struct link_enc_cfg_context { 446 enum link_enc_cfg_mode mode; 447 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 448 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 449 struct link_enc_assignment transient_assignments[MAX_PIPES]; 450 }; 451 452 struct resource_context { 453 struct pipe_ctx pipe_ctx[MAX_PIPES]; 454 bool is_stream_enc_acquired[MAX_PIPES * 2]; 455 bool is_audio_acquired[MAX_PIPES]; 456 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 457 uint8_t dp_clock_source_ref_count; 458 bool is_dsc_acquired[MAX_PIPES]; 459 struct link_enc_cfg_context link_enc_cfg_ctx; 460 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 461 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 462 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 463 bool is_mpc_3dlut_acquired[MAX_PIPES]; 464 }; 465 466 struct dce_bw_output { 467 bool cpuc_state_change_enable; 468 bool cpup_state_change_enable; 469 bool stutter_mode_enable; 470 bool nbp_state_change_enable; 471 bool all_displays_in_sync; 472 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 473 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 474 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 475 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 476 int sclk_khz; 477 int sclk_deep_sleep_khz; 478 int yclk_khz; 479 int dispclk_khz; 480 int blackout_recovery_time_us; 481 }; 482 483 struct dcn_bw_writeback { 484 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 485 }; 486 487 struct dcn_bw_output { 488 struct dc_clocks clk; 489 struct dcn_watermark_set watermarks; 490 struct dcn_bw_writeback bw_writeback; 491 int compbuf_size_kb; 492 unsigned int mall_ss_size_bytes; 493 unsigned int mall_ss_psr_active_size_bytes; 494 unsigned int mall_subvp_size_bytes; 495 unsigned int legacy_svp_drr_stream_index; 496 bool legacy_svp_drr_stream_index_valid; 497 }; 498 499 union bw_output { 500 struct dcn_bw_output dcn; 501 struct dce_bw_output dce; 502 }; 503 504 struct bw_context { 505 union bw_output bw; 506 struct display_mode_lib dml; 507 struct dml2_context *dml2; 508 }; 509 510 struct dc_dmub_cmd { 511 union dmub_rb_cmd dmub_cmd; 512 enum dm_dmub_wait_type wait_type; 513 }; 514 515 /** 516 * struct dc_state - The full description of a state requested by users 517 */ 518 struct dc_state { 519 /** 520 * @streams: Stream state properties 521 */ 522 struct dc_stream_state *streams[MAX_PIPES]; 523 524 /** 525 * @stream_status: Planes status on a given stream 526 */ 527 struct dc_stream_status stream_status[MAX_PIPES]; 528 529 /** 530 * @stream_count: Total of streams in use 531 */ 532 uint8_t stream_count; 533 uint8_t stream_mask; 534 535 /** 536 * @res_ctx: Persistent state of resources 537 */ 538 struct resource_context res_ctx; 539 540 /** 541 * @pp_display_cfg: PowerPlay clocks and settings 542 * Note: this is a big struct, do *not* put on stack! 543 */ 544 struct dm_pp_display_configuration pp_display_cfg; 545 546 /** 547 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 548 * Note: this is a big struct, do *not* put on stack! 549 */ 550 struct dcn_bw_internal_vars dcn_bw_vars; 551 552 struct clk_mgr *clk_mgr; 553 554 /** 555 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 556 * 557 * Each context must have its own instance of VBA, and in order to 558 * initialize and obtain IP and SOC, the base DML instance from DC is 559 * initially copied into every context. 560 */ 561 struct bw_context bw_ctx; 562 563 struct block_sequence block_sequence[50]; 564 unsigned int block_sequence_steps; 565 struct dc_dmub_cmd dc_dmub_cmd[10]; 566 unsigned int dmub_cmd_count; 567 568 /** 569 * @refcount: refcount reference 570 * 571 * Notice that dc_state is used around the code to capture the current 572 * context, so we need to pass it everywhere. That's why we want to use 573 * kref in this struct. 574 */ 575 struct kref refcount; 576 577 struct { 578 unsigned int stutter_period_us; 579 } perf_params; 580 581 struct { 582 /* used to temporarily backup plane states of a stream during 583 * dc update. The reason is that plane states are overwritten 584 * with surface updates in dc update. Once they are overwritten 585 * current state is no longer valid. We want to temporarily 586 * store current value in plane states so we can still recover 587 * a valid current state during dc update. 588 */ 589 struct dc_plane_state plane_states[MAX_SURFACE_NUM]; 590 } scratch; 591 }; 592 593 struct replay_context { 594 /* ddc line */ 595 enum channel_id aux_inst; 596 /* Transmitter id */ 597 enum transmitter digbe_inst; 598 /* Engine Id is used for Dig Be source select */ 599 enum engine_id digfe_inst; 600 /* Controller Id used for Dig Fe source select */ 601 enum controller_id controllerId; 602 unsigned int line_time_in_ns; 603 }; 604 605 enum dc_replay_enable { 606 DC_REPLAY_DISABLE = 0, 607 DC_REPLAY_ENABLE = 1, 608 }; 609 610 struct dc_bounding_box_max_clk { 611 int max_dcfclk_mhz; 612 int max_dispclk_mhz; 613 int max_dppclk_mhz; 614 int max_phyclk_mhz; 615 }; 616 617 #endif /* _CORE_TYPES_H_ */ 618