1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_INTERNAL_H__ 27 #define __DAL_CLK_MGR_INTERNAL_H__ 28 29 #include "clk_mgr.h" 30 #include "dc.h" 31 32 /* 33 * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also 34 * used in resource, perhaps this should be defined somewhere more common. 35 */ 36 #include "resource.h" 37 38 39 /* Starting DID for each range */ 40 enum dentist_base_divider_id { 41 DENTIST_BASE_DID_1 = 0x08, 42 DENTIST_BASE_DID_2 = 0x40, 43 DENTIST_BASE_DID_3 = 0x60, 44 DENTIST_BASE_DID_4 = 0x7e, 45 DENTIST_MAX_DID = 0x7f 46 }; 47 48 /* Starting point and step size for each divider range.*/ 49 enum dentist_divider_range { 50 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */ 51 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */ 52 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */ 53 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */ 54 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */ 55 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */ 56 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */ 57 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */ 58 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4 59 }; 60 61 /* 62 *************************************************************************************** 63 ****************** Clock Manager Private Macros and Defines *************************** 64 *************************************************************************************** 65 */ 66 67 /* Macros */ 68 69 #define TO_CLK_MGR_INTERNAL(clk_mgr)\ 70 container_of(clk_mgr, struct clk_mgr_internal, base) 71 72 #define CTX \ 73 clk_mgr->base.ctx 74 #define DC_LOGGER \ 75 clk_mgr->ctx->logger 76 77 78 79 80 #define CLK_BASE(inst) \ 81 CLK_BASE_INNER(inst) 82 83 #define CLK_SRI(reg_name, block, inst)\ 84 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 85 mm ## block ## _ ## inst ## _ ## reg_name 86 87 #define CLK_COMMON_REG_LIST_DCE_BASE() \ 88 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ 89 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL 90 91 #define CLK_COMMON_REG_LIST_DCN_BASE() \ 92 SR(DENTIST_DISPCLK_CNTL) 93 94 #define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \ 95 .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \ 96 .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \ 97 .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67 98 99 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 100 #define CLK_REG_LIST_NV10() \ 101 SR(DENTIST_DISPCLK_CNTL), \ 102 CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ 103 CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) 104 #endif 105 106 #define CLK_SF(reg_name, field_name, post_fix)\ 107 .field_name = reg_name ## __ ## field_name ## post_fix 108 109 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 110 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ 111 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) 112 113 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 114 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ 115 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) 116 117 #define CLK_MASK_SH_LIST_RV1(mask_sh) \ 118 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 119 CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\ 120 CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ 121 CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh), 122 123 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 124 #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \ 125 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 126 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ 127 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh) 128 129 #define CLK_MASK_SH_LIST_NV10(mask_sh) \ 130 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ 131 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\ 132 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh) 133 #endif 134 135 #define CLK_REG_FIELD_LIST(type) \ 136 type DPREFCLK_SRC_SEL; \ 137 type DENTIST_DPREFCLK_WDIVIDER; \ 138 type DENTIST_DISPCLK_WDIVIDER; \ 139 type DENTIST_DISPCLK_CHG_DONE; 140 141 /* 142 *************************************************************************************** 143 ****************** Clock Manager Private Structures *********************************** 144 *************************************************************************************** 145 */ 146 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 147 #define CLK20_REG_FIELD_LIST(type) \ 148 type DENTIST_DPPCLK_WDIVIDER; \ 149 type DENTIST_DPPCLK_CHG_DONE; \ 150 type FbMult_int; \ 151 type FbMult_frac; 152 #endif 153 154 #define VBIOS_SMU_REG_FIELD_LIST(type) \ 155 type CONTENT; 156 157 struct clk_mgr_shift { 158 CLK_REG_FIELD_LIST(uint8_t) 159 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 160 CLK20_REG_FIELD_LIST(uint8_t) 161 #endif 162 VBIOS_SMU_REG_FIELD_LIST(uint32_t) 163 }; 164 165 struct clk_mgr_mask { 166 CLK_REG_FIELD_LIST(uint32_t) 167 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 168 CLK20_REG_FIELD_LIST(uint32_t) 169 #endif 170 VBIOS_SMU_REG_FIELD_LIST(uint32_t) 171 }; 172 173 struct clk_mgr_registers { 174 uint32_t DPREFCLK_CNTL; 175 uint32_t DENTIST_DISPCLK_CNTL; 176 177 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 178 uint32_t CLK3_CLK2_DFS_CNTL; 179 uint32_t CLK3_CLK_PLL_REQ; 180 #endif 181 182 uint32_t MP1_SMN_C2PMSG_67; 183 uint32_t MP1_SMN_C2PMSG_83; 184 uint32_t MP1_SMN_C2PMSG_91; 185 }; 186 187 struct state_dependent_clocks { 188 int display_clk_khz; 189 int pixel_clk_khz; 190 }; 191 192 struct clk_mgr_internal { 193 struct clk_mgr base; 194 int smu_ver; 195 struct pp_smu_funcs *pp_smu; 196 struct clk_mgr_internal_funcs *funcs; 197 198 struct dccg *dccg; 199 200 /* 201 * For backwards compatbility with previous implementation 202 * TODO: remove these after everything transitions to new pattern 203 * Rationale is that clk registers change a lot across DCE versions 204 * and a shared data structure doesn't really make sense. 205 */ 206 const struct clk_mgr_registers *regs; 207 const struct clk_mgr_shift *clk_mgr_shift; 208 const struct clk_mgr_mask *clk_mgr_mask; 209 210 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; 211 212 /*TODO: figure out which of the below fields should be here vs in asic specific portion */ 213 int dentist_vco_freq_khz; 214 215 /* Cache the status of DFS-bypass feature*/ 216 bool dfs_bypass_enabled; 217 /* True if the DFS-bypass feature is enabled and active. */ 218 bool dfs_bypass_active; 219 220 uint32_t dfs_ref_freq_khz; 221 /* 222 * Cache the display clock returned by VBIOS if DFS-bypass is enabled. 223 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency 224 */ 225 int dfs_bypass_disp_clk; 226 227 /** 228 * @ss_on_dprefclk: 229 * 230 * True if spread spectrum is enabled on the DP ref clock. 231 */ 232 bool ss_on_dprefclk; 233 234 /** 235 * @xgmi_enabled: 236 * 237 * True if xGMI is enabled. On VG20, both audio and display clocks need 238 * to be adjusted with the WAFL link's SS info if xGMI is enabled. 239 */ 240 bool xgmi_enabled; 241 242 /** 243 * @dprefclk_ss_percentage: 244 * 245 * DPREFCLK SS percentage (if down-spread enabled). 246 * 247 * Note that if XGMI is enabled, the SS info (percentage and divider) 248 * from the WAFL link is used instead. This is decided during 249 * dce_clk_mgr initialization. 250 */ 251 int dprefclk_ss_percentage; 252 253 /** 254 * @dprefclk_ss_divider: 255 * 256 * DPREFCLK SS percentage Divider (100 or 1000). 257 */ 258 int dprefclk_ss_divider; 259 260 enum dm_pp_clocks_state max_clks_state; 261 enum dm_pp_clocks_state cur_min_clks_state; 262 }; 263 264 struct clk_mgr_internal_funcs { 265 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 266 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr); 267 }; 268 269 270 /* 271 *************************************************************************************** 272 ****************** Clock Manager Level Helper functions ******************************* 273 *************************************************************************************** 274 */ 275 276 277 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) 278 { 279 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); 280 } 281 282 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) 283 { 284 if (cur_support != calc_support) { 285 if (calc_support == true && safe_to_lower) 286 return true; 287 else if (calc_support == false && !safe_to_lower) 288 return true; 289 } 290 291 return false; 292 } 293 294 int clk_mgr_helper_get_active_display_cnt( 295 struct dc *dc, 296 struct dc_state *context); 297 298 299 300 #endif //__DAL_CLK_MGR_INTERNAL_H__ 301