1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "link_hwss_hpo_dp.h" 26 #include "dm_helpers.h" 27 #include "core_types.h" 28 #include "dccg.h" 29 #include "clk_mgr.h" 30 31 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 32 { 33 switch (link->link_enc->transmitter) { 34 case TRANSMITTER_UNIPHY_A: 35 return PHYD32CLKA; 36 case TRANSMITTER_UNIPHY_B: 37 return PHYD32CLKB; 38 case TRANSMITTER_UNIPHY_C: 39 return PHYD32CLKC; 40 case TRANSMITTER_UNIPHY_D: 41 return PHYD32CLKD; 42 case TRANSMITTER_UNIPHY_E: 43 return PHYD32CLKE; 44 default: 45 return PHYD32CLKA; 46 } 47 } 48 49 static void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx, 50 struct fixed31_32 throttled_vcp_size) 51 { 52 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = 53 pipe_ctx->stream_res.hpo_dp_stream_enc; 54 struct hpo_dp_link_encoder *hpo_dp_link_encoder = 55 pipe_ctx->link_res.hpo_dp_link_enc; 56 57 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(hpo_dp_link_encoder, 58 hpo_dp_stream_encoder->inst, 59 throttled_vcp_size); 60 } 61 62 static void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, 63 const struct dc_link_settings *link_settings, 64 struct fixed31_32 throttled_vcp_size) 65 { 66 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = 67 pipe_ctx->stream_res.hpo_dp_stream_enc; 68 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 69 struct fixed31_32 h_blank_in_ms, time_slot_in_ms, mtp_cnt_per_h_blank; 70 uint32_t link_bw_in_kbps = 71 hpo_dp_stream_encoder->ctx->dc->link_srv->dp_link_bandwidth_kbps( 72 pipe_ctx->stream->link, link_settings); 73 uint16_t hblank_min_symbol_width = 0; 74 75 if (link_bw_in_kbps > 0) { 76 h_blank_in_ms = dc_fixpt_div(dc_fixpt_from_int( 77 timing->h_total - timing->h_addressable), 78 dc_fixpt_from_fraction(timing->pix_clk_100hz, 10)); 79 time_slot_in_ms = dc_fixpt_from_fraction(32 * 4, link_bw_in_kbps); 80 mtp_cnt_per_h_blank = dc_fixpt_div(h_blank_in_ms, 81 dc_fixpt_mul_int(time_slot_in_ms, 64)); 82 hblank_min_symbol_width = dc_fixpt_floor( 83 dc_fixpt_mul(mtp_cnt_per_h_blank, throttled_vcp_size)); 84 } 85 86 hpo_dp_stream_encoder->funcs->set_hblank_min_symbol_width(hpo_dp_stream_encoder, 87 hblank_min_symbol_width); 88 } 89 90 static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) 91 { 92 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 93 struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc; 94 95 stream_enc->funcs->enable_stream(stream_enc); 96 stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst); 97 } 98 99 static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) 100 { 101 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 102 103 stream_enc->funcs->disable(stream_enc); 104 } 105 106 static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx) 107 { 108 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 109 struct dc_stream_state *stream = pipe_ctx->stream; 110 struct dc_link *link = stream->link; 111 112 stream_enc->funcs->set_stream_attribute( 113 stream_enc, 114 &stream->timing, 115 stream->output_color_space, 116 stream->use_vsc_sdp_for_colorimetry, 117 stream->timing.flags.DSC, 118 false); 119 link->dc->link_srv->dp_trace_source_sequence(link, 120 DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR); 121 } 122 123 static void enable_hpo_dp_fpga_link_output(struct dc_link *link, 124 const struct link_resource *link_res, 125 enum signal_type signal, 126 enum clock_source_id clock_source, 127 const struct dc_link_settings *link_settings) 128 { 129 const struct dc *dc = link->dc; 130 enum phyd32clk_clock_source phyd32clk = get_phyd32clk_src(link); 131 int phyd32clk_freq_khz = link_settings->link_rate == LINK_RATE_UHBR10 ? 312500 : 132 link_settings->link_rate == LINK_RATE_UHBR13_5 ? 412875 : 133 link_settings->link_rate == LINK_RATE_UHBR20 ? 625000 : 0; 134 135 dm_set_phyd32clk(dc->ctx, phyd32clk_freq_khz); 136 dc->res_pool->dccg->funcs->set_physymclk( 137 dc->res_pool->dccg, 138 link->link_enc_hw_inst, 139 PHYSYMCLK_FORCE_SRC_PHYD32CLK, 140 true); 141 dc->res_pool->dccg->funcs->enable_symclk32_le( 142 dc->res_pool->dccg, 143 link_res->hpo_dp_link_enc->inst, 144 phyd32clk); 145 link_res->hpo_dp_link_enc->funcs->link_enable( 146 link_res->hpo_dp_link_enc, 147 link_settings->lane_count); 148 149 } 150 151 static void enable_hpo_dp_link_output(struct dc_link *link, 152 const struct link_resource *link_res, 153 enum signal_type signal, 154 enum clock_source_id clock_source, 155 const struct dc_link_settings *link_settings) 156 { 157 if (IS_FPGA_MAXIMUS_DC(link->dc->ctx->dce_environment)) 158 enable_hpo_dp_fpga_link_output(link, link_res, signal, 159 clock_source, link_settings); 160 else 161 link_res->hpo_dp_link_enc->funcs->enable_link_phy( 162 link_res->hpo_dp_link_enc, 163 link_settings, 164 link->link_enc->transmitter, 165 link->link_enc->hpd_source); 166 } 167 168 169 static void disable_hpo_dp_fpga_link_output(struct dc_link *link, 170 const struct link_resource *link_res, 171 enum signal_type signal) 172 { 173 const struct dc *dc = link->dc; 174 175 link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc); 176 dc->res_pool->dccg->funcs->disable_symclk32_le( 177 dc->res_pool->dccg, 178 link_res->hpo_dp_link_enc->inst); 179 dc->res_pool->dccg->funcs->set_physymclk( 180 dc->res_pool->dccg, 181 link->link_enc_hw_inst, 182 PHYSYMCLK_FORCE_SRC_SYMCLK, 183 false); 184 dm_set_phyd32clk(dc->ctx, 0); 185 } 186 187 static void disable_hpo_dp_link_output(struct dc_link *link, 188 const struct link_resource *link_res, 189 enum signal_type signal) 190 { 191 if (IS_FPGA_MAXIMUS_DC(link->dc->ctx->dce_environment)) { 192 disable_hpo_dp_fpga_link_output(link, link_res, signal); 193 } else { 194 link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc); 195 link_res->hpo_dp_link_enc->funcs->disable_link_phy( 196 link_res->hpo_dp_link_enc, signal); 197 } 198 } 199 200 static void set_hpo_dp_link_test_pattern(struct dc_link *link, 201 const struct link_resource *link_res, 202 struct encoder_set_dp_phy_pattern_param *tp_params) 203 { 204 link_res->hpo_dp_link_enc->funcs->set_link_test_pattern( 205 link_res->hpo_dp_link_enc, tp_params); 206 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); 207 } 208 209 static void set_hpo_dp_lane_settings(struct dc_link *link, 210 const struct link_resource *link_res, 211 const struct dc_link_settings *link_settings, 212 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 213 { 214 link_res->hpo_dp_link_enc->funcs->set_ffe( 215 link_res->hpo_dp_link_enc, 216 link_settings, 217 lane_settings[0].FFE_PRESET.raw); 218 } 219 220 static void update_hpo_dp_stream_allocation_table(struct dc_link *link, 221 const struct link_resource *link_res, 222 const struct link_mst_stream_allocation_table *table) 223 { 224 link_res->hpo_dp_link_enc->funcs->update_stream_allocation_table( 225 link_res->hpo_dp_link_enc, 226 table); 227 } 228 229 static void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx, 230 struct audio_output *audio_output, uint32_t audio_inst) 231 { 232 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 233 pipe_ctx->stream_res.hpo_dp_stream_enc, 234 audio_inst, 235 &pipe_ctx->stream->audio_info); 236 } 237 238 static void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx) 239 { 240 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( 241 pipe_ctx->stream_res.hpo_dp_stream_enc); 242 } 243 244 static void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx) 245 { 246 if (pipe_ctx->stream_res.audio) 247 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( 248 pipe_ctx->stream_res.hpo_dp_stream_enc); 249 } 250 251 static const struct link_hwss hpo_dp_link_hwss = { 252 .setup_stream_encoder = setup_hpo_dp_stream_encoder, 253 .reset_stream_encoder = reset_hpo_dp_stream_encoder, 254 .setup_stream_attribute = setup_hpo_dp_stream_attribute, 255 .disable_link_output = disable_hpo_dp_link_output, 256 .setup_audio_output = setup_hpo_dp_audio_output, 257 .enable_audio_packet = enable_hpo_dp_audio_packet, 258 .disable_audio_packet = disable_hpo_dp_audio_packet, 259 .ext = { 260 .set_throttled_vcp_size = set_hpo_dp_throttled_vcp_size, 261 .set_hblank_min_symbol_width = set_hpo_dp_hblank_min_symbol_width, 262 .enable_dp_link_output = enable_hpo_dp_link_output, 263 .set_dp_link_test_pattern = set_hpo_dp_link_test_pattern, 264 .set_dp_lane_settings = set_hpo_dp_lane_settings, 265 .update_stream_allocation_table = update_hpo_dp_stream_allocation_table, 266 }, 267 }; 268 269 bool can_use_hpo_dp_link_hwss(const struct dc_link *link, 270 const struct link_resource *link_res) 271 { 272 return link_res->hpo_dp_link_enc != NULL; 273 } 274 275 const struct link_hwss *get_hpo_dp_link_hwss(void) 276 { 277 return &hpo_dp_link_hwss; 278 } 279 280