1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file manages link detection states and receiver states by using various 28 * link protocols. It also provides helper functions to interpret certain 29 * capabilities or status based on the states it manages or retrieve them 30 * directly from connected receivers. 31 */ 32 33 #include "link_dpms.h" 34 #include "link_detection.h" 35 #include "link_hwss.h" 36 #include "protocols/link_edp_panel_control.h" 37 #include "protocols/link_ddc.h" 38 #include "protocols/link_hpd.h" 39 #include "protocols/link_dpcd.h" 40 #include "protocols/link_dp_capability.h" 41 #include "protocols/link_dp_dpia.h" 42 #include "protocols/link_dp_phy.h" 43 #include "protocols/link_dp_training.h" 44 #include "accessories/link_dp_trace.h" 45 46 #include "link_enc_cfg.h" 47 #include "dm_helpers.h" 48 #include "clk_mgr.h" 49 50 #define DC_LOGGER_INIT(logger) 51 52 #define LINK_INFO(...) \ 53 DC_LOG_HW_HOTPLUG( \ 54 __VA_ARGS__) 55 /* 56 * Some receivers fail to train on first try and are good 57 * on subsequent tries. 2 retries should be plenty. If we 58 * don't have a successful training then we don't expect to 59 * ever get one. 60 */ 61 #define LINK_TRAINING_MAX_VERIFY_RETRY 2 62 63 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal) 64 { 65 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; 66 67 switch (sink_signal) { 68 case SIGNAL_TYPE_DVI_SINGLE_LINK: 69 case SIGNAL_TYPE_DVI_DUAL_LINK: 70 case SIGNAL_TYPE_HDMI_TYPE_A: 71 case SIGNAL_TYPE_LVDS: 72 case SIGNAL_TYPE_RGB: 73 transaction_type = DDC_TRANSACTION_TYPE_I2C; 74 break; 75 76 case SIGNAL_TYPE_DISPLAY_PORT: 77 case SIGNAL_TYPE_EDP: 78 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 79 break; 80 81 case SIGNAL_TYPE_DISPLAY_PORT_MST: 82 /* MST does not use I2COverAux, but there is the 83 * SPECIAL use case for "immediate dwnstrm device 84 * access" (EPR#370830). 85 */ 86 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 87 break; 88 89 default: 90 break; 91 } 92 93 return transaction_type; 94 } 95 96 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, 97 struct graphics_object_id downstream) 98 { 99 if (downstream.type == OBJECT_TYPE_CONNECTOR) { 100 switch (downstream.id) { 101 case CONNECTOR_ID_SINGLE_LINK_DVII: 102 switch (encoder.id) { 103 case ENCODER_ID_INTERNAL_DAC1: 104 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 105 case ENCODER_ID_INTERNAL_DAC2: 106 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 107 return SIGNAL_TYPE_RGB; 108 default: 109 return SIGNAL_TYPE_DVI_SINGLE_LINK; 110 } 111 break; 112 case CONNECTOR_ID_DUAL_LINK_DVII: 113 { 114 switch (encoder.id) { 115 case ENCODER_ID_INTERNAL_DAC1: 116 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 117 case ENCODER_ID_INTERNAL_DAC2: 118 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 119 return SIGNAL_TYPE_RGB; 120 default: 121 return SIGNAL_TYPE_DVI_DUAL_LINK; 122 } 123 } 124 break; 125 case CONNECTOR_ID_SINGLE_LINK_DVID: 126 return SIGNAL_TYPE_DVI_SINGLE_LINK; 127 case CONNECTOR_ID_DUAL_LINK_DVID: 128 return SIGNAL_TYPE_DVI_DUAL_LINK; 129 case CONNECTOR_ID_VGA: 130 return SIGNAL_TYPE_RGB; 131 case CONNECTOR_ID_HDMI_TYPE_A: 132 return SIGNAL_TYPE_HDMI_TYPE_A; 133 case CONNECTOR_ID_LVDS: 134 return SIGNAL_TYPE_LVDS; 135 case CONNECTOR_ID_DISPLAY_PORT: 136 case CONNECTOR_ID_USBC: 137 return SIGNAL_TYPE_DISPLAY_PORT; 138 case CONNECTOR_ID_EDP: 139 return SIGNAL_TYPE_EDP; 140 default: 141 return SIGNAL_TYPE_NONE; 142 } 143 } else if (downstream.type == OBJECT_TYPE_ENCODER) { 144 switch (downstream.id) { 145 case ENCODER_ID_EXTERNAL_NUTMEG: 146 case ENCODER_ID_EXTERNAL_TRAVIS: 147 return SIGNAL_TYPE_DISPLAY_PORT; 148 default: 149 return SIGNAL_TYPE_NONE; 150 } 151 } 152 153 return SIGNAL_TYPE_NONE; 154 } 155 156 /* 157 * @brief 158 * Detect output sink type 159 */ 160 static enum signal_type link_detect_sink_signal_type(struct dc_link *link, 161 enum dc_detect_reason reason) 162 { 163 enum signal_type result; 164 struct graphics_object_id enc_id; 165 166 if (link->is_dig_mapping_flexible) 167 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; 168 else 169 enc_id = link->link_enc->id; 170 result = get_basic_signal_type(enc_id, link->link_id); 171 172 /* Use basic signal type for link without physical connector. */ 173 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 174 return result; 175 176 /* Internal digital encoder will detect only dongles 177 * that require digital signal 178 */ 179 180 /* Detection mechanism is different 181 * for different native connectors. 182 * LVDS connector supports only LVDS signal; 183 * PCIE is a bus slot, the actual connector needs to be detected first; 184 * eDP connector supports only eDP signal; 185 * HDMI should check straps for audio 186 */ 187 188 /* PCIE detects the actual connector on add-on board */ 189 if (link->link_id.id == CONNECTOR_ID_PCIE) { 190 /* ZAZTODO implement PCIE add-on card detection */ 191 } 192 193 switch (link->link_id.id) { 194 case CONNECTOR_ID_HDMI_TYPE_A: { 195 /* check audio support: 196 * if native HDMI is not supported, switch to DVI 197 */ 198 struct audio_support *aud_support = 199 &link->dc->res_pool->audio_support; 200 201 if (!aud_support->hdmi_audio_native) 202 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A) 203 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 204 } 205 break; 206 case CONNECTOR_ID_DISPLAY_PORT: 207 case CONNECTOR_ID_USBC: { 208 /* DP HPD short pulse. Passive DP dongle will not 209 * have short pulse 210 */ 211 if (reason != DETECT_REASON_HPDRX) { 212 /* Check whether DP signal detected: if not - 213 * we assume signal is DVI; it could be corrected 214 * to HDMI after dongle detection 215 */ 216 if (!dm_helpers_is_dp_sink_present(link)) 217 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 218 } 219 } 220 break; 221 default: 222 break; 223 } 224 225 return result; 226 } 227 228 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type, 229 struct audio_support *audio_support) 230 { 231 enum signal_type signal = SIGNAL_TYPE_NONE; 232 233 switch (dongle_type) { 234 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 235 if (audio_support->hdmi_audio_on_dongle) 236 signal = SIGNAL_TYPE_HDMI_TYPE_A; 237 else 238 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 239 break; 240 case DISPLAY_DONGLE_DP_DVI_DONGLE: 241 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 242 break; 243 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 244 if (audio_support->hdmi_audio_native) 245 signal = SIGNAL_TYPE_HDMI_TYPE_A; 246 else 247 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 248 break; 249 default: 250 signal = SIGNAL_TYPE_NONE; 251 break; 252 } 253 254 return signal; 255 } 256 257 static void read_scdc_caps(struct ddc_service *ddc_service, 258 struct dc_sink *sink) 259 { 260 uint8_t slave_address = HDMI_SCDC_ADDRESS; 261 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI; 262 263 link_query_ddc_data(ddc_service, slave_address, &offset, 264 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte, 265 sizeof(sink->scdc_caps.manufacturer_OUI.byte)); 266 267 offset = HDMI_SCDC_DEVICE_ID; 268 269 link_query_ddc_data(ddc_service, slave_address, &offset, 270 sizeof(offset), &(sink->scdc_caps.device_id.byte), 271 sizeof(sink->scdc_caps.device_id.byte)); 272 } 273 274 static bool i2c_read( 275 struct ddc_service *ddc, 276 uint32_t address, 277 uint8_t *buffer, 278 uint32_t len) 279 { 280 uint8_t offs_data = 0; 281 struct i2c_payload payloads[2] = { 282 { 283 .write = true, 284 .address = address, 285 .length = 1, 286 .data = &offs_data }, 287 { 288 .write = false, 289 .address = address, 290 .length = len, 291 .data = buffer } }; 292 293 struct i2c_command command = { 294 .payloads = payloads, 295 .number_of_payloads = 2, 296 .engine = DDC_I2C_COMMAND_ENGINE, 297 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; 298 299 return dm_helpers_submit_i2c( 300 ddc->ctx, 301 ddc->link, 302 &command); 303 } 304 305 enum { 306 DP_SINK_CAP_SIZE = 307 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1 308 }; 309 310 static void query_dp_dual_mode_adaptor( 311 struct ddc_service *ddc, 312 struct display_sink_capability *sink_cap) 313 { 314 uint8_t i; 315 bool is_valid_hdmi_signature; 316 enum display_dongle_type *dongle = &sink_cap->dongle_type; 317 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE]; 318 bool is_type2_dongle = false; 319 int retry_count = 2; 320 struct dp_hdmi_dongle_signature_data *dongle_signature; 321 322 /* Assume we have no valid DP passive dongle connected */ 323 *dongle = DISPLAY_DONGLE_NONE; 324 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 325 326 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 327 if (!i2c_read( 328 ddc, 329 DP_HDMI_DONGLE_ADDRESS, 330 type2_dongle_buf, 331 sizeof(type2_dongle_buf))) { 332 /* Passive HDMI dongles can sometimes fail here without retrying*/ 333 while (retry_count > 0) { 334 if (i2c_read(ddc, 335 DP_HDMI_DONGLE_ADDRESS, 336 type2_dongle_buf, 337 sizeof(type2_dongle_buf))) 338 break; 339 retry_count--; 340 } 341 if (retry_count == 0) { 342 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 343 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 344 345 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), 346 "DP-DVI passive dongle %dMhz: ", 347 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 348 return; 349 } 350 } 351 352 /* Check if Type 2 dongle.*/ 353 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID) 354 is_type2_dongle = true; 355 356 dongle_signature = 357 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf; 358 359 is_valid_hdmi_signature = true; 360 361 /* Check EOT */ 362 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) { 363 is_valid_hdmi_signature = false; 364 } 365 366 /* Check signature */ 367 for (i = 0; i < sizeof(dongle_signature->id); ++i) { 368 /* If its not the right signature, 369 * skip mismatch in subversion byte.*/ 370 if (dongle_signature->id[i] != 371 dp_hdmi_dongle_signature_str[i] && i != 3) { 372 373 if (is_type2_dongle) { 374 is_valid_hdmi_signature = false; 375 break; 376 } 377 378 } 379 } 380 381 if (is_type2_dongle) { 382 uint32_t max_tmds_clk = 383 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK]; 384 385 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2; 386 387 if (0 == max_tmds_clk || 388 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK || 389 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) { 390 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 391 392 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 393 sizeof(type2_dongle_buf), 394 "DP-DVI passive dongle %dMhz: ", 395 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 396 } else { 397 if (is_valid_hdmi_signature == true) { 398 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 399 400 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 401 sizeof(type2_dongle_buf), 402 "Type 2 DP-HDMI passive dongle %dMhz: ", 403 max_tmds_clk); 404 } else { 405 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 406 407 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 408 sizeof(type2_dongle_buf), 409 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ", 410 max_tmds_clk); 411 412 } 413 414 /* Multiply by 1000 to convert to kHz. */ 415 sink_cap->max_hdmi_pixel_clock = 416 max_tmds_clk * 1000; 417 } 418 sink_cap->is_dongle_type_one = false; 419 420 } else { 421 if (is_valid_hdmi_signature == true) { 422 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 423 424 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 425 sizeof(type2_dongle_buf), 426 "Type 1 DP-HDMI passive dongle %dMhz: ", 427 sink_cap->max_hdmi_pixel_clock / 1000); 428 } else { 429 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 430 431 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 432 sizeof(type2_dongle_buf), 433 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ", 434 sink_cap->max_hdmi_pixel_clock / 1000); 435 } 436 sink_cap->is_dongle_type_one = true; 437 } 438 439 return; 440 } 441 442 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc, 443 struct display_sink_capability *sink_cap, 444 struct audio_support *audio_support) 445 { 446 query_dp_dual_mode_adaptor(ddc, sink_cap); 447 448 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type, 449 audio_support); 450 } 451 452 static void link_disconnect_sink(struct dc_link *link) 453 { 454 if (link->local_sink) { 455 dc_sink_release(link->local_sink); 456 link->local_sink = NULL; 457 } 458 459 link->dpcd_sink_count = 0; 460 //link->dpcd_caps.dpcd_rev.raw = 0; 461 } 462 463 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link) 464 { 465 dc_sink_release(link->local_sink); 466 link->local_sink = prev_sink; 467 } 468 469 #if defined(CONFIG_DRM_AMD_DC_HDCP) 470 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) 471 { 472 struct hdcp_protection_message msg22; 473 struct hdcp_protection_message msg14; 474 475 memset(&msg22, 0, sizeof(struct hdcp_protection_message)); 476 memset(&msg14, 0, sizeof(struct hdcp_protection_message)); 477 memset(link->hdcp_caps.rx_caps.raw, 0, 478 sizeof(link->hdcp_caps.rx_caps.raw)); 479 480 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 481 link->ddc->transaction_type == 482 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) || 483 link->connector_signal == SIGNAL_TYPE_EDP) { 484 msg22.data = link->hdcp_caps.rx_caps.raw; 485 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw); 486 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS; 487 } else { 488 msg22.data = &link->hdcp_caps.rx_caps.fields.version; 489 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version); 490 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION; 491 } 492 msg22.version = HDCP_VERSION_22; 493 msg22.link = HDCP_LINK_PRIMARY; 494 msg22.max_retries = 5; 495 dc_process_hdcp_msg(signal, link, &msg22); 496 497 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 498 enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED; 499 500 msg14.data = &link->hdcp_caps.bcaps.raw; 501 msg14.length = sizeof(link->hdcp_caps.bcaps.raw); 502 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS; 503 msg14.version = HDCP_VERSION_14; 504 msg14.link = HDCP_LINK_PRIMARY; 505 msg14.max_retries = 5; 506 507 status = dc_process_hdcp_msg(signal, link, &msg14); 508 } 509 510 } 511 #endif // CONFIG_DRM_AMD_DC_HDCP 512 static void read_current_link_settings_on_detect(struct dc_link *link) 513 { 514 union lane_count_set lane_count_set = {0}; 515 uint8_t link_bw_set; 516 uint8_t link_rate_set; 517 uint32_t read_dpcd_retry_cnt = 10; 518 enum dc_status status = DC_ERROR_UNEXPECTED; 519 int i; 520 union max_down_spread max_down_spread = {0}; 521 522 // Read DPCD 00101h to find out the number of lanes currently set 523 for (i = 0; i < read_dpcd_retry_cnt; i++) { 524 status = core_link_read_dpcd(link, 525 DP_LANE_COUNT_SET, 526 &lane_count_set.raw, 527 sizeof(lane_count_set)); 528 /* First DPCD read after VDD ON can fail if the particular board 529 * does not have HPD pin wired correctly. So if DPCD read fails, 530 * which it should never happen, retry a few times. Target worst 531 * case scenario of 80 ms. 532 */ 533 if (status == DC_OK) { 534 link->cur_link_settings.lane_count = 535 lane_count_set.bits.LANE_COUNT_SET; 536 break; 537 } 538 539 msleep(8); 540 } 541 542 // Read DPCD 00100h to find if standard link rates are set 543 core_link_read_dpcd(link, DP_LINK_BW_SET, 544 &link_bw_set, sizeof(link_bw_set)); 545 546 if (link_bw_set == 0) { 547 if (link->connector_signal == SIGNAL_TYPE_EDP) { 548 /* If standard link rates are not being used, 549 * Read DPCD 00115h to find the edp link rate set used 550 */ 551 core_link_read_dpcd(link, DP_LINK_RATE_SET, 552 &link_rate_set, sizeof(link_rate_set)); 553 554 // edp_supported_link_rates_count = 0 for DP 555 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 556 link->cur_link_settings.link_rate = 557 link->dpcd_caps.edp_supported_link_rates[link_rate_set]; 558 link->cur_link_settings.link_rate_set = link_rate_set; 559 link->cur_link_settings.use_link_rate_set = true; 560 } 561 } else { 562 // Link Rate not found. Seamless boot may not work. 563 ASSERT(false); 564 } 565 } else { 566 link->cur_link_settings.link_rate = link_bw_set; 567 link->cur_link_settings.use_link_rate_set = false; 568 } 569 // Read DPCD 00003h to find the max down spread. 570 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, 571 &max_down_spread.raw, sizeof(max_down_spread)); 572 link->cur_link_settings.link_spread = 573 max_down_spread.bits.MAX_DOWN_SPREAD ? 574 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 575 } 576 577 static bool detect_dp(struct dc_link *link, 578 struct display_sink_capability *sink_caps, 579 enum dc_detect_reason reason) 580 { 581 struct audio_support *audio_support = &link->dc->res_pool->audio_support; 582 583 sink_caps->signal = link_detect_sink_signal_type(link, reason); 584 sink_caps->transaction_type = 585 get_ddc_transaction_type(sink_caps->signal); 586 587 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 588 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 589 if (!detect_dp_sink_caps(link)) 590 return false; 591 592 if (is_dp_branch_device(link)) 593 /* DP SST branch */ 594 link->type = dc_connection_sst_branch; 595 } else { 596 /* DP passive dongles */ 597 sink_caps->signal = dp_passive_dongle_detection(link->ddc, 598 sink_caps, 599 audio_support); 600 link->dpcd_caps.dongle_type = sink_caps->dongle_type; 601 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one; 602 link->dpcd_caps.dpcd_rev.raw = 0; 603 } 604 605 return true; 606 } 607 608 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 609 { 610 if (old_edid->length != new_edid->length) 611 return false; 612 613 if (new_edid->length == 0) 614 return false; 615 616 return (memcmp(old_edid->raw_edid, 617 new_edid->raw_edid, new_edid->length) == 0); 618 } 619 620 static bool wait_for_entering_dp_alt_mode(struct dc_link *link) 621 { 622 623 /** 624 * something is terribly wrong if time out is > 200ms. (5Hz) 625 * 500 microseconds * 400 tries us 200 ms 626 **/ 627 unsigned int sleep_time_in_microseconds = 500; 628 unsigned int tries_allowed = 400; 629 bool is_in_alt_mode; 630 unsigned long long enter_timestamp; 631 unsigned long long finish_timestamp; 632 unsigned long long time_taken_in_ns; 633 int tries_taken; 634 635 DC_LOGGER_INIT(link->ctx->logger); 636 637 /** 638 * this function will only exist if we are on dcn21 (is_in_alt_mode is a 639 * function pointer, so checking to see if it is equal to 0 is the same 640 * as checking to see if it is null 641 **/ 642 if (!link->link_enc->funcs->is_in_alt_mode) 643 return true; 644 645 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); 646 DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode); 647 648 if (is_in_alt_mode) 649 return true; 650 651 enter_timestamp = dm_get_timestamp(link->ctx); 652 653 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { 654 udelay(sleep_time_in_microseconds); 655 /* ask the link if alt mode is enabled, if so return ok */ 656 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { 657 finish_timestamp = dm_get_timestamp(link->ctx); 658 time_taken_in_ns = 659 dm_get_elapse_time_in_ns(link->ctx, 660 finish_timestamp, 661 enter_timestamp); 662 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n", 663 div_u64(time_taken_in_ns, 1000000)); 664 return true; 665 } 666 } 667 finish_timestamp = dm_get_timestamp(link->ctx); 668 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, 669 enter_timestamp); 670 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n", 671 div_u64(time_taken_in_ns, 1000000)); 672 return false; 673 } 674 675 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 676 { 677 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock 678 * reports DSC support. 679 */ 680 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 681 link->type == dc_connection_mst_branch && 682 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 683 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 && 684 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 685 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) 686 link->wa_flags.dpia_mst_dsc_always_on = true; 687 } 688 689 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) 690 { 691 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */ 692 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 693 link->wa_flags.dpia_mst_dsc_always_on = false; 694 } 695 696 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) 697 { 698 DC_LOGGER_INIT(link->ctx->logger); 699 700 LINK_INFO("link=%d, mst branch is now Connected\n", 701 link->link_index); 702 703 link->type = dc_connection_mst_branch; 704 apply_dpia_mst_dsc_always_on_wa(link); 705 706 dm_helpers_dp_update_branch_info(link->ctx, link); 707 if (dm_helpers_dp_mst_start_top_mgr(link->ctx, 708 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) { 709 link_disconnect_sink(link); 710 } else { 711 link->type = dc_connection_sst_branch; 712 } 713 714 return link->type == dc_connection_mst_branch; 715 } 716 717 bool link_reset_cur_dp_mst_topology(struct dc_link *link) 718 { 719 DC_LOGGER_INIT(link->ctx->logger); 720 721 LINK_INFO("link=%d, mst branch is now Disconnected\n", 722 link->link_index); 723 724 revert_dpia_mst_dsc_always_on_wa(link); 725 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); 726 } 727 728 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc, 729 enum dc_detect_reason reason) 730 { 731 int i; 732 bool can_apply_seamless_boot = false; 733 734 for (i = 0; i < dc->current_state->stream_count; i++) { 735 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { 736 can_apply_seamless_boot = true; 737 break; 738 } 739 } 740 741 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT; 742 } 743 744 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc) 745 { 746 dc_z10_restore(dc); 747 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 748 } 749 750 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc) 751 { 752 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 753 } 754 755 static void verify_link_capability_destructive(struct dc_link *link, 756 struct dc_sink *sink, 757 enum dc_detect_reason reason) 758 { 759 bool should_prepare_phy_clocks = 760 should_prepare_phy_clocks_for_link_verification(link->dc, reason); 761 762 if (should_prepare_phy_clocks) 763 prepare_phy_clocks_for_destructive_link_verification(link->dc); 764 765 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 766 struct dc_link_settings known_limit_link_setting = 767 dp_get_max_link_cap(link); 768 link_set_all_streams_dpms_off_for_link(link); 769 dp_verify_link_cap_with_retries( 770 link, &known_limit_link_setting, 771 LINK_TRAINING_MAX_VERIFY_RETRY); 772 } else { 773 ASSERT(0); 774 } 775 776 if (should_prepare_phy_clocks) 777 restore_phy_clocks_for_destructive_link_verification(link->dc); 778 } 779 780 static void verify_link_capability_non_destructive(struct dc_link *link) 781 { 782 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 783 if (dc_is_embedded_signal(link->local_sink->sink_signal) || 784 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 785 /* TODO - should we check link encoder's max link caps here? 786 * How do we know which link encoder to check from? 787 */ 788 link->verified_link_cap = link->reported_link_cap; 789 else 790 link->verified_link_cap = dp_get_max_link_cap(link); 791 } 792 } 793 794 static bool should_verify_link_capability_destructively(struct dc_link *link, 795 enum dc_detect_reason reason) 796 { 797 bool destrictive = false; 798 struct dc_link_settings max_link_cap; 799 bool is_link_enc_unavailable = link->link_enc && 800 link->dc->res_pool->funcs->link_encs_assign && 801 !link_enc_cfg_is_link_enc_avail( 802 link->ctx->dc, 803 link->link_enc->preferred_engine, 804 link); 805 806 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 807 max_link_cap = dp_get_max_link_cap(link); 808 destrictive = true; 809 810 if (link->dc->debug.skip_detection_link_training || 811 dc_is_embedded_signal(link->local_sink->sink_signal) || 812 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 813 destrictive = false; 814 } else if (link_dp_get_encoding_format(&max_link_cap) == 815 DP_8b_10b_ENCODING) { 816 if (link->dpcd_caps.is_mst_capable || 817 is_link_enc_unavailable) { 818 destrictive = false; 819 } 820 } 821 } 822 823 return destrictive; 824 } 825 826 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, 827 enum dc_detect_reason reason) 828 { 829 if (should_verify_link_capability_destructively(link, reason)) 830 verify_link_capability_destructive(link, sink, reason); 831 else 832 verify_link_capability_non_destructive(link); 833 } 834 835 /** 836 * detect_link_and_local_sink() - Detect if a sink is attached to a given link 837 * 838 * link->local_sink is created or destroyed as needed. 839 * 840 * This does not create remote sinks. 841 */ 842 static bool detect_link_and_local_sink(struct dc_link *link, 843 enum dc_detect_reason reason) 844 { 845 struct dc_sink_init_data sink_init_data = { 0 }; 846 struct display_sink_capability sink_caps = { 0 }; 847 uint32_t i; 848 bool converter_disable_audio = false; 849 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 850 bool same_edid = false; 851 enum dc_edid_status edid_status; 852 struct dc_context *dc_ctx = link->ctx; 853 struct dc *dc = dc_ctx->dc; 854 struct dc_sink *sink = NULL; 855 struct dc_sink *prev_sink = NULL; 856 struct dpcd_caps prev_dpcd_caps; 857 enum dc_connection_type new_connection_type = dc_connection_none; 858 enum dc_connection_type pre_connection_type = link->type; 859 const uint32_t post_oui_delay = 30; // 30ms 860 861 DC_LOGGER_INIT(link->ctx->logger); 862 863 if (dc_is_virtual_signal(link->connector_signal)) 864 return false; 865 866 if (((link->connector_signal == SIGNAL_TYPE_LVDS || 867 link->connector_signal == SIGNAL_TYPE_EDP) && 868 (!link->dc->config.allow_edp_hotplug_detection)) && 869 link->local_sink) { 870 // need to re-write OUI and brightness in resume case 871 if (link->connector_signal == SIGNAL_TYPE_EDP && 872 (link->dpcd_sink_ext_caps.bits.oled == 1)) { 873 dpcd_set_source_specific_data(link); 874 msleep(post_oui_delay); 875 set_default_brightness_aux(link); 876 //TODO: use cached 877 } 878 879 return true; 880 } 881 882 if (!dc_link_detect_connection_type(link, &new_connection_type)) { 883 BREAK_TO_DEBUGGER(); 884 return false; 885 } 886 887 prev_sink = link->local_sink; 888 if (prev_sink) { 889 dc_sink_retain(prev_sink); 890 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps)); 891 } 892 893 link_disconnect_sink(link); 894 if (new_connection_type != dc_connection_none) { 895 link->type = new_connection_type; 896 link->link_state_valid = false; 897 898 /* From Disconnected-to-Connected. */ 899 switch (link->connector_signal) { 900 case SIGNAL_TYPE_HDMI_TYPE_A: { 901 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 902 if (aud_support->hdmi_audio_native) 903 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 904 else 905 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 906 break; 907 } 908 909 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 910 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 911 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 912 break; 913 } 914 915 case SIGNAL_TYPE_DVI_DUAL_LINK: { 916 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 917 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 918 break; 919 } 920 921 case SIGNAL_TYPE_LVDS: { 922 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 923 sink_caps.signal = SIGNAL_TYPE_LVDS; 924 break; 925 } 926 927 case SIGNAL_TYPE_EDP: { 928 detect_edp_sink_caps(link); 929 read_current_link_settings_on_detect(link); 930 931 /* Disable power sequence on MIPI panel + converter 932 */ 933 if (dc->config.enable_mipi_converter_optimization && 934 dc_ctx->dce_version == DCN_VERSION_3_01 && 935 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && 936 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, 937 sizeof(link->dpcd_caps.branch_dev_name)) == 0) { 938 dc->config.edp_no_power_sequencing = true; 939 940 if (!link->dpcd_caps.set_power_state_capable_edp) 941 link->wa_flags.dp_keep_receiver_powered = true; 942 } 943 944 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 945 sink_caps.signal = SIGNAL_TYPE_EDP; 946 break; 947 } 948 949 case SIGNAL_TYPE_DISPLAY_PORT: { 950 951 /* wa HPD high coming too early*/ 952 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 953 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { 954 955 /* if alt mode times out, return false */ 956 if (!wait_for_entering_dp_alt_mode(link)) 957 return false; 958 } 959 960 if (!detect_dp(link, &sink_caps, reason)) { 961 link->type = pre_connection_type; 962 963 if (prev_sink) 964 dc_sink_release(prev_sink); 965 return false; 966 } 967 968 /* Active SST downstream branch device unplug*/ 969 if (link->type == dc_connection_sst_branch && 970 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { 971 if (prev_sink) 972 /* Downstream unplug */ 973 dc_sink_release(prev_sink); 974 return true; 975 } 976 977 /* disable audio for non DP to HDMI active sst converter */ 978 if (link->type == dc_connection_sst_branch && 979 is_dp_active_dongle(link) && 980 (link->dpcd_caps.dongle_type != 981 DISPLAY_DONGLE_DP_HDMI_CONVERTER)) 982 converter_disable_audio = true; 983 break; 984 } 985 986 default: 987 DC_ERROR("Invalid connector type! signal:%d\n", 988 link->connector_signal); 989 if (prev_sink) 990 dc_sink_release(prev_sink); 991 return false; 992 } /* switch() */ 993 994 if (link->dpcd_caps.sink_count.bits.SINK_COUNT) 995 link->dpcd_sink_count = 996 link->dpcd_caps.sink_count.bits.SINK_COUNT; 997 else 998 link->dpcd_sink_count = 1; 999 1000 set_ddc_transaction_type(link->ddc, 1001 sink_caps.transaction_type); 1002 1003 link->aux_mode = 1004 link_is_in_aux_transaction_mode(link->ddc); 1005 1006 sink_init_data.link = link; 1007 sink_init_data.sink_signal = sink_caps.signal; 1008 1009 sink = dc_sink_create(&sink_init_data); 1010 if (!sink) { 1011 DC_ERROR("Failed to create sink!\n"); 1012 if (prev_sink) 1013 dc_sink_release(prev_sink); 1014 return false; 1015 } 1016 1017 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; 1018 sink->converter_disable_audio = converter_disable_audio; 1019 1020 /* dc_sink_create returns a new reference */ 1021 link->local_sink = sink; 1022 1023 edid_status = dm_helpers_read_local_edid(link->ctx, 1024 link, sink); 1025 1026 switch (edid_status) { 1027 case EDID_BAD_CHECKSUM: 1028 DC_LOG_ERROR("EDID checksum invalid.\n"); 1029 break; 1030 case EDID_PARTIAL_VALID: 1031 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); 1032 break; 1033 case EDID_NO_RESPONSE: 1034 DC_LOG_ERROR("No EDID read.\n"); 1035 /* 1036 * Abort detection for non-DP connectors if we have 1037 * no EDID 1038 * 1039 * DP needs to report as connected if HDP is high 1040 * even if we have no EDID in order to go to 1041 * fail-safe mode 1042 */ 1043 if (dc_is_hdmi_signal(link->connector_signal) || 1044 dc_is_dvi_signal(link->connector_signal)) { 1045 if (prev_sink) 1046 dc_sink_release(prev_sink); 1047 1048 return false; 1049 } 1050 1051 if (link->type == dc_connection_sst_branch && 1052 link->dpcd_caps.dongle_type == 1053 DISPLAY_DONGLE_DP_VGA_CONVERTER && 1054 reason == DETECT_REASON_HPDRX) { 1055 /* Abort detection for DP-VGA adapters when EDID 1056 * can't be read and detection reason is VGA-side 1057 * hotplug 1058 */ 1059 if (prev_sink) 1060 dc_sink_release(prev_sink); 1061 link_disconnect_sink(link); 1062 1063 return true; 1064 } 1065 1066 break; 1067 default: 1068 break; 1069 } 1070 1071 // Check if edid is the same 1072 if ((prev_sink) && 1073 (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) 1074 same_edid = is_same_edid(&prev_sink->dc_edid, 1075 &sink->dc_edid); 1076 1077 if (sink->edid_caps.panel_patch.skip_scdc_overwrite) 1078 link->ctx->dc->debug.hdmi20_disable = true; 1079 1080 if (dc_is_hdmi_signal(link->connector_signal)) 1081 read_scdc_caps(link->ddc, link->local_sink); 1082 1083 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 1084 sink_caps.transaction_type == 1085 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 1086 /* 1087 * TODO debug why certain monitors don't like 1088 * two link trainings 1089 */ 1090 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1091 query_hdcp_capability(sink->sink_signal, link); 1092 #endif 1093 } else { 1094 // If edid is the same, then discard new sink and revert back to original sink 1095 if (same_edid) { 1096 link_disconnect_remap(prev_sink, link); 1097 sink = prev_sink; 1098 prev_sink = NULL; 1099 } 1100 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1101 query_hdcp_capability(sink->sink_signal, link); 1102 #endif 1103 } 1104 1105 /* HDMI-DVI Dongle */ 1106 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && 1107 !sink->edid_caps.edid_hdmi) 1108 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1109 1110 if (link->local_sink && dc_is_dp_signal(sink_caps.signal)) 1111 dp_trace_init(link); 1112 1113 /* Connectivity log: detection */ 1114 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) { 1115 CONN_DATA_DETECT(link, 1116 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE], 1117 DC_EDID_BLOCK_SIZE, 1118 "%s: [Block %d] ", sink->edid_caps.display_name, i); 1119 } 1120 1121 DC_LOG_DETECTION_EDID_PARSER("%s: " 1122 "manufacturer_id = %X, " 1123 "product_id = %X, " 1124 "serial_number = %X, " 1125 "manufacture_week = %d, " 1126 "manufacture_year = %d, " 1127 "display_name = %s, " 1128 "speaker_flag = %d, " 1129 "audio_mode_count = %d\n", 1130 __func__, 1131 sink->edid_caps.manufacturer_id, 1132 sink->edid_caps.product_id, 1133 sink->edid_caps.serial_number, 1134 sink->edid_caps.manufacture_week, 1135 sink->edid_caps.manufacture_year, 1136 sink->edid_caps.display_name, 1137 sink->edid_caps.speaker_flags, 1138 sink->edid_caps.audio_mode_count); 1139 1140 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { 1141 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, " 1142 "format_code = %d, " 1143 "channel_count = %d, " 1144 "sample_rate = %d, " 1145 "sample_size = %d\n", 1146 __func__, 1147 i, 1148 sink->edid_caps.audio_modes[i].format_code, 1149 sink->edid_caps.audio_modes[i].channel_count, 1150 sink->edid_caps.audio_modes[i].sample_rate, 1151 sink->edid_caps.audio_modes[i].sample_size); 1152 } 1153 1154 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1155 // Init dc_panel_config by HW config 1156 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) 1157 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); 1158 // Pickup base DM settings 1159 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); 1160 // Override dc_panel_config if system has specific settings 1161 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); 1162 } 1163 1164 } else { 1165 /* From Connected-to-Disconnected. */ 1166 link->type = dc_connection_none; 1167 sink_caps.signal = SIGNAL_TYPE_NONE; 1168 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1169 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps)); 1170 #endif 1171 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk 1172 * is not cleared. If we emulate a DP signal on this connection, it thinks 1173 * the dongle is still there and limits the number of modes we can emulate. 1174 * Clear dongle_max_pix_clk on disconnect to fix this 1175 */ 1176 link->dongle_max_pix_clk = 0; 1177 1178 dc_link_clear_dprx_states(link); 1179 dp_trace_reset(link); 1180 } 1181 1182 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n", 1183 link->link_index, sink, 1184 (sink_caps.signal == 1185 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"), 1186 prev_sink, same_edid); 1187 1188 if (prev_sink) 1189 dc_sink_release(prev_sink); 1190 1191 return true; 1192 } 1193 1194 /** 1195 * dc_link_detect_connection_type() - Determine if there is a sink connected 1196 * 1197 * @type: Returned connection type 1198 * Does not detect downstream devices, such as MST sinks 1199 * or display connected through active dongles 1200 */ 1201 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type) 1202 { 1203 uint32_t is_hpd_high = 0; 1204 1205 if (link->connector_signal == SIGNAL_TYPE_LVDS) { 1206 *type = dc_connection_single; 1207 return true; 1208 } 1209 1210 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1211 /*in case it is not on*/ 1212 if (!link->dc->config.edp_no_power_sequencing) 1213 link->dc->hwss.edp_power_control(link, true); 1214 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1215 } 1216 1217 /* Link may not have physical HPD pin. */ 1218 if (link->ep_type != DISPLAY_ENDPOINT_PHY) { 1219 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link)) 1220 *type = dc_connection_none; 1221 else 1222 *type = dc_connection_single; 1223 1224 return true; 1225 } 1226 1227 1228 if (!query_hpd_status(link, &is_hpd_high)) 1229 goto hpd_gpio_failure; 1230 1231 if (is_hpd_high) { 1232 *type = dc_connection_single; 1233 /* TODO: need to do the actual detection */ 1234 } else { 1235 *type = dc_connection_none; 1236 } 1237 1238 return true; 1239 1240 hpd_gpio_failure: 1241 return false; 1242 } 1243 1244 bool link_detect(struct dc_link *link, enum dc_detect_reason reason) 1245 { 1246 bool is_local_sink_detect_success; 1247 bool is_delegated_to_mst_top_mgr = false; 1248 enum dc_connection_type pre_link_type = link->type; 1249 1250 DC_LOGGER_INIT(link->ctx->logger); 1251 1252 is_local_sink_detect_success = detect_link_and_local_sink(link, reason); 1253 1254 if (is_local_sink_detect_success && link->local_sink) 1255 verify_link_capability(link, link->local_sink, reason); 1256 1257 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, 1258 link->link_index, is_local_sink_detect_success, pre_link_type, link->type); 1259 1260 if (is_local_sink_detect_success && link->local_sink && 1261 dc_is_dp_signal(link->local_sink->sink_signal) && 1262 link->dpcd_caps.is_mst_capable) 1263 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason); 1264 1265 if (is_local_sink_detect_success && 1266 pre_link_type == dc_connection_mst_branch && 1267 link->type != dc_connection_mst_branch) 1268 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link); 1269 1270 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr; 1271 } 1272 1273 void link_clear_dprx_states(struct dc_link *link) 1274 { 1275 memset(&link->dprx_states, 0, sizeof(link->dprx_states)); 1276 } 1277 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1278 1279 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal) 1280 { 1281 bool ret = false; 1282 1283 switch (signal) { 1284 case SIGNAL_TYPE_DISPLAY_PORT: 1285 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1286 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE; 1287 break; 1288 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1289 case SIGNAL_TYPE_DVI_DUAL_LINK: 1290 case SIGNAL_TYPE_HDMI_TYPE_A: 1291 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable, 1292 * we can poll for bksv but some displays have an issue with this. Since its so rare 1293 * for a display to not be 1.4 capable, this assumtion is ok 1294 */ 1295 ret = true; 1296 break; 1297 default: 1298 break; 1299 } 1300 return ret; 1301 } 1302 1303 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal) 1304 { 1305 bool ret = false; 1306 1307 switch (signal) { 1308 case SIGNAL_TYPE_DISPLAY_PORT: 1309 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1310 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE && 1311 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable && 1312 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0; 1313 break; 1314 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1315 case SIGNAL_TYPE_DVI_DUAL_LINK: 1316 case SIGNAL_TYPE_HDMI_TYPE_A: 1317 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0; 1318 break; 1319 default: 1320 break; 1321 } 1322 1323 return ret; 1324 } 1325 #endif // CONFIG_DRM_AMD_DC_HDCP 1326 1327 const struct dc_link_status *link_get_status(const struct dc_link *link) 1328 { 1329 return &link->link_status; 1330 } 1331 1332