1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file implements basic dp phy functionality such as enable/disable phy 28 * output and set lane/drive settings. This file is responsible for maintaining 29 * and update software state representing current phy status such as current 30 * link settings. 31 */ 32 33 #include "link_dp_phy.h" 34 #include "link_dpcd.h" 35 #include "link_dp_training.h" 36 #include "link_dp_capability.h" 37 #include "clk_mgr.h" 38 #include "resource.h" 39 #include "link_enc_cfg.h" 40 #define DC_LOGGER \ 41 link->ctx->logger 42 43 void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on) 44 { 45 uint8_t state; 46 47 state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3; 48 49 if (link->sync_lt_in_progress) 50 return; 51 52 core_link_write_dpcd(link, DP_SET_POWER, &state, 53 sizeof(state)); 54 55 } 56 57 void dp_enable_link_phy( 58 struct dc_link *link, 59 const struct link_resource *link_res, 60 enum signal_type signal, 61 enum clock_source_id clock_source, 62 const struct dc_link_settings *link_settings) 63 { 64 link->cur_link_settings = *link_settings; 65 link->dc->hwss.enable_dp_link_output(link, link_res, signal, 66 clock_source, link_settings); 67 dpcd_write_rx_power_ctrl(link, true); 68 } 69 70 void dp_disable_link_phy(struct dc_link *link, 71 const struct link_resource *link_res, 72 enum signal_type signal) 73 { 74 struct dc *dc = link->ctx->dc; 75 76 if (!link->wa_flags.dp_keep_receiver_powered && 77 !link->skip_implict_edp_power_control) 78 dpcd_write_rx_power_ctrl(link, false); 79 80 dc->hwss.disable_link_output(link, link_res, signal); 81 /* Clear current link setting.*/ 82 memset(&link->cur_link_settings, 0, 83 sizeof(link->cur_link_settings)); 84 85 if (dc->clk_mgr->funcs->notify_link_rate_change) 86 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); 87 } 88 89 static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset) 90 { 91 return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 92 offset); 93 } 94 95 void dp_set_hw_lane_settings( 96 struct dc_link *link, 97 const struct link_resource *link_res, 98 const struct link_training_settings *link_settings, 99 uint32_t offset) 100 { 101 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 102 103 if ((link_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && 104 !is_immediate_downstream(link, offset)) 105 return; 106 107 if (link_hwss->ext.set_dp_lane_settings) 108 link_hwss->ext.set_dp_lane_settings(link, link_res, 109 &link_settings->link_settings, 110 link_settings->hw_lane_settings); 111 112 memmove(link->cur_lane_setting, 113 link_settings->hw_lane_settings, 114 sizeof(link->cur_lane_setting)); 115 } 116 117 void dp_set_drive_settings( 118 struct dc_link *link, 119 const struct link_resource *link_res, 120 struct link_training_settings *lt_settings) 121 { 122 /* program ASIC PHY settings*/ 123 dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX); 124 125 dp_hw_to_dpcd_lane_settings(lt_settings, 126 lt_settings->hw_lane_settings, 127 lt_settings->dpcd_lane_settings); 128 129 /* Notify DP sink the PHY settings from source */ 130 dpcd_set_lane_settings(link, lt_settings, DPRX); 131 } 132 133 enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) 134 { 135 /* FEC has to be "set ready" before the link training. 136 * The policy is to always train with FEC 137 * if the sink supports it and leave it enabled on link. 138 * If FEC is not supported, disable it. 139 */ 140 struct link_encoder *link_enc = NULL; 141 enum dc_status status = DC_OK; 142 uint8_t fec_config = 0; 143 144 link_enc = link_enc_cfg_get_link_enc(link); 145 ASSERT(link_enc); 146 147 if (!dp_should_enable_fec(link)) 148 return status; 149 150 if (link_enc->funcs->fec_set_ready && 151 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { 152 if (ready) { 153 fec_config = 1; 154 status = core_link_write_dpcd(link, 155 DP_FEC_CONFIGURATION, 156 &fec_config, 157 sizeof(fec_config)); 158 if (status == DC_OK) { 159 link_enc->funcs->fec_set_ready(link_enc, true); 160 link->fec_state = dc_link_fec_ready; 161 } else { 162 link_enc->funcs->fec_set_ready(link_enc, false); 163 link->fec_state = dc_link_fec_not_ready; 164 dm_error("dpcd write failed to set fec_ready"); 165 } 166 } else if (link->fec_state == dc_link_fec_ready) { 167 fec_config = 0; 168 status = core_link_write_dpcd(link, 169 DP_FEC_CONFIGURATION, 170 &fec_config, 171 sizeof(fec_config)); 172 link_enc->funcs->fec_set_ready(link_enc, false); 173 link->fec_state = dc_link_fec_not_ready; 174 } 175 } 176 177 return status; 178 } 179 180 void dp_set_fec_enable(struct dc_link *link, bool enable) 181 { 182 struct link_encoder *link_enc = NULL; 183 184 link_enc = link_enc_cfg_get_link_enc(link); 185 ASSERT(link_enc); 186 187 if (!dp_should_enable_fec(link)) 188 return; 189 190 if (link_enc->funcs->fec_set_enable && 191 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { 192 if (link->fec_state == dc_link_fec_ready && enable) { 193 /* Accord to DP spec, FEC enable sequence can first 194 * be transmitted anytime after 1000 LL codes have 195 * been transmitted on the link after link training 196 * completion. Using 1 lane RBR should have the maximum 197 * time for transmitting 1000 LL codes which is 6.173 us. 198 * So use 7 microseconds delay instead. 199 */ 200 udelay(7); 201 link_enc->funcs->fec_set_enable(link_enc, true); 202 link->fec_state = dc_link_fec_enabled; 203 } else if (link->fec_state == dc_link_fec_enabled && !enable) { 204 link_enc->funcs->fec_set_enable(link_enc, false); 205 link->fec_state = dc_link_fec_ready; 206 } 207 } 208 } 209 210