1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 /** 174 * union dmub_addr - DMUB physical/virtual 64-bit address. 175 */ 176 union dmub_addr { 177 struct { 178 uint32_t low_part; /**< Lower 32 bits */ 179 uint32_t high_part; /**< Upper 32 bits */ 180 } u; /*<< Low/high bit access */ 181 uint64_t quad_part; /*<< 64 bit address */ 182 }; 183 #pragma pack(pop) 184 185 /** 186 * Dirty rect definition. 187 */ 188 struct dmub_rect { 189 /** 190 * Dirty rect x offset. 191 */ 192 uint32_t x; 193 194 /** 195 * Dirty rect y offset. 196 */ 197 uint32_t y; 198 199 /** 200 * Dirty rect width. 201 */ 202 uint32_t width; 203 204 /** 205 * Dirty rect height. 206 */ 207 uint32_t height; 208 }; 209 210 /** 211 * Flags that can be set by driver to change some PSR behaviour. 212 */ 213 union dmub_psr_debug_flags { 214 /** 215 * Debug flags. 216 */ 217 struct { 218 /** 219 * Enable visual confirm in FW. 220 */ 221 uint32_t visual_confirm : 1; 222 223 /** 224 * Force all selective updates to bw full frame updates. 225 */ 226 uint32_t force_full_frame_update : 1; 227 228 /** 229 * Use HW Lock Mgr object to do HW locking in FW. 230 */ 231 uint32_t use_hw_lock_mgr : 1; 232 233 /** 234 * Use TPS3 signal when restore main link. 235 */ 236 uint32_t force_wakeup_by_tps3 : 1; 237 238 /** 239 * Back to back flip, therefore cannot power down PHY 240 */ 241 uint32_t back_to_back_flip : 1; 242 243 } bitfields; 244 245 /** 246 * Union for debug flags. 247 */ 248 uint32_t u32All; 249 }; 250 251 /** 252 * DMUB visual confirm color 253 */ 254 struct dmub_feature_caps { 255 /** 256 * Max PSR version supported by FW. 257 */ 258 uint8_t psr; 259 uint8_t fw_assisted_mclk_switch; 260 uint8_t reserved[6]; 261 }; 262 263 struct dmub_visual_confirm_color { 264 /** 265 * Maximum 10 bits color value 266 */ 267 uint16_t color_r_cr; 268 uint16_t color_g_y; 269 uint16_t color_b_cb; 270 uint16_t panel_inst; 271 }; 272 273 #if defined(__cplusplus) 274 } 275 #endif 276 277 //============================================================================== 278 //</DMUB_TYPES>================================================================= 279 //============================================================================== 280 //< DMUB_META>================================================================== 281 //============================================================================== 282 #pragma pack(push, 1) 283 284 /* Magic value for identifying dmub_fw_meta_info */ 285 #define DMUB_FW_META_MAGIC 0x444D5542 286 287 /* Offset from the end of the file to the dmub_fw_meta_info */ 288 #define DMUB_FW_META_OFFSET 0x24 289 290 /** 291 * struct dmub_fw_meta_info - metadata associated with fw binary 292 * 293 * NOTE: This should be considered a stable API. Fields should 294 * not be repurposed or reordered. New fields should be 295 * added instead to extend the structure. 296 * 297 * @magic_value: magic value identifying DMUB firmware meta info 298 * @fw_region_size: size of the firmware state region 299 * @trace_buffer_size: size of the tracebuffer region 300 * @fw_version: the firmware version information 301 * @dal_fw: 1 if the firmware is DAL 302 */ 303 struct dmub_fw_meta_info { 304 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 305 uint32_t fw_region_size; /**< size of the firmware state region */ 306 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 307 uint32_t fw_version; /**< the firmware version information */ 308 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 309 uint8_t reserved[3]; /**< padding bits */ 310 }; 311 312 /** 313 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 314 */ 315 union dmub_fw_meta { 316 struct dmub_fw_meta_info info; /**< metadata info */ 317 uint8_t reserved[64]; /**< padding bits */ 318 }; 319 320 #pragma pack(pop) 321 322 //============================================================================== 323 //< DMUB Trace Buffer>================================================================ 324 //============================================================================== 325 /** 326 * dmub_trace_code_t - firmware trace code, 32-bits 327 */ 328 typedef uint32_t dmub_trace_code_t; 329 330 /** 331 * struct dmcub_trace_buf_entry - Firmware trace entry 332 */ 333 struct dmcub_trace_buf_entry { 334 dmub_trace_code_t trace_code; /**< trace code for the event */ 335 uint32_t tick_count; /**< the tick count at time of trace */ 336 uint32_t param0; /**< trace defined parameter 0 */ 337 uint32_t param1; /**< trace defined parameter 1 */ 338 }; 339 340 //============================================================================== 341 //< DMUB_STATUS>================================================================ 342 //============================================================================== 343 344 /** 345 * DMCUB scratch registers can be used to determine firmware status. 346 * Current scratch register usage is as follows: 347 * 348 * SCRATCH0: FW Boot Status register 349 * SCRATCH5: LVTMA Status Register 350 * SCRATCH15: FW Boot Options register 351 */ 352 353 /** 354 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 355 */ 356 union dmub_fw_boot_status { 357 struct { 358 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 359 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 360 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 361 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 362 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 363 uint32_t reserved : 1; 364 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 365 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 366 } bits; /**< status bits */ 367 uint32_t all; /**< 32-bit access to status bits */ 368 }; 369 370 /** 371 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 372 */ 373 enum dmub_fw_boot_status_bit { 374 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 375 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 376 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 377 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 378 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 379 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 380 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 381 }; 382 383 /* Register bit definition for SCRATCH5 */ 384 union dmub_lvtma_status { 385 struct { 386 uint32_t psp_ok : 1; 387 uint32_t edp_on : 1; 388 uint32_t reserved : 30; 389 } bits; 390 uint32_t all; 391 }; 392 393 enum dmub_lvtma_status_bit { 394 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 395 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 396 }; 397 398 /** 399 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 400 */ 401 union dmub_fw_boot_options { 402 struct { 403 uint32_t pemu_env : 1; /**< 1 if PEMU */ 404 uint32_t fpga_env : 1; /**< 1 if FPGA */ 405 uint32_t optimized_init : 1; /**< 1 if optimized init */ 406 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 407 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 408 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 409 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 410 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 411 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 412 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 413 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 414 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 415 uint32_t power_optimization: 1; 416 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 417 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 418 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 419 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 420 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 421 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 422 uint32_t reserved : 14; /**< reserved */ 423 } bits; /**< boot bits */ 424 uint32_t all; /**< 32-bit access to bits */ 425 }; 426 427 enum dmub_fw_boot_options_bit { 428 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 429 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 430 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 431 }; 432 433 //============================================================================== 434 //</DMUB_STATUS>================================================================ 435 //============================================================================== 436 //< DMUB_VBIOS>================================================================= 437 //============================================================================== 438 439 /* 440 * enum dmub_cmd_vbios_type - VBIOS commands. 441 * 442 * Command IDs should be treated as stable ABI. 443 * Do not reuse or modify IDs. 444 */ 445 enum dmub_cmd_vbios_type { 446 /** 447 * Configures the DIG encoder. 448 */ 449 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 450 /** 451 * Controls the PHY. 452 */ 453 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 454 /** 455 * Sets the pixel clock/symbol clock. 456 */ 457 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 458 /** 459 * Enables or disables power gating. 460 */ 461 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 462 /** 463 * Controls embedded panels. 464 */ 465 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 466 /** 467 * Query DP alt status on a transmitter. 468 */ 469 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 470 /** 471 * Controls domain power gating 472 */ 473 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 474 }; 475 476 //============================================================================== 477 //</DMUB_VBIOS>================================================================= 478 //============================================================================== 479 //< DMUB_GPINT>================================================================= 480 //============================================================================== 481 482 /** 483 * The shifts and masks below may alternatively be used to format and read 484 * the command register bits. 485 */ 486 487 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 488 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 489 490 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 491 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 492 493 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 494 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 495 496 /** 497 * Command responses. 498 */ 499 500 /** 501 * Return response for DMUB_GPINT__STOP_FW command. 502 */ 503 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 504 505 /** 506 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 507 */ 508 union dmub_gpint_data_register { 509 struct { 510 uint32_t param : 16; /**< 16-bit parameter */ 511 uint32_t command_code : 12; /**< GPINT command */ 512 uint32_t status : 4; /**< Command status bit */ 513 } bits; /**< GPINT bit access */ 514 uint32_t all; /**< GPINT 32-bit access */ 515 }; 516 517 /* 518 * enum dmub_gpint_command - GPINT command to DMCUB FW 519 * 520 * Command IDs should be treated as stable ABI. 521 * Do not reuse or modify IDs. 522 */ 523 enum dmub_gpint_command { 524 /** 525 * Invalid command, ignored. 526 */ 527 DMUB_GPINT__INVALID_COMMAND = 0, 528 /** 529 * DESC: Queries the firmware version. 530 * RETURN: Firmware version. 531 */ 532 DMUB_GPINT__GET_FW_VERSION = 1, 533 /** 534 * DESC: Halts the firmware. 535 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 536 */ 537 DMUB_GPINT__STOP_FW = 2, 538 /** 539 * DESC: Get PSR state from FW. 540 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 541 */ 542 DMUB_GPINT__GET_PSR_STATE = 7, 543 /** 544 * DESC: Notifies DMCUB of the currently active streams. 545 * ARGS: Stream mask, 1 bit per active stream index. 546 */ 547 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 548 /** 549 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 550 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 551 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 552 * RETURN: PSR residency in milli-percent. 553 */ 554 DMUB_GPINT__PSR_RESIDENCY = 9, 555 556 /** 557 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 558 */ 559 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 560 }; 561 562 /** 563 * INBOX0 generic command definition 564 */ 565 union dmub_inbox0_cmd_common { 566 struct { 567 uint32_t command_code: 8; /**< INBOX0 command code */ 568 uint32_t param: 24; /**< 24-bit parameter */ 569 } bits; 570 uint32_t all; 571 }; 572 573 /** 574 * INBOX0 hw_lock command definition 575 */ 576 union dmub_inbox0_cmd_lock_hw { 577 struct { 578 uint32_t command_code: 8; 579 580 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 581 uint32_t hw_lock_client: 2; 582 583 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 584 uint32_t otg_inst: 3; 585 uint32_t opp_inst: 3; 586 uint32_t dig_inst: 3; 587 588 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 589 uint32_t lock_pipe: 1; 590 uint32_t lock_cursor: 1; 591 uint32_t lock_dig: 1; 592 uint32_t triple_buffer_lock: 1; 593 594 uint32_t lock: 1; /**< Lock */ 595 uint32_t should_release: 1; /**< Release */ 596 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 597 } bits; 598 uint32_t all; 599 }; 600 601 union dmub_inbox0_data_register { 602 union dmub_inbox0_cmd_common inbox0_cmd_common; 603 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 604 }; 605 606 enum dmub_inbox0_command { 607 /** 608 * DESC: Invalid command, ignored. 609 */ 610 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 611 /** 612 * DESC: Notification to acquire/release HW lock 613 * ARGS: 614 */ 615 DMUB_INBOX0_CMD__HW_LOCK = 1, 616 }; 617 //============================================================================== 618 //</DMUB_GPINT>================================================================= 619 //============================================================================== 620 //< DMUB_CMD>=================================================================== 621 //============================================================================== 622 623 /** 624 * Size in bytes of each DMUB command. 625 */ 626 #define DMUB_RB_CMD_SIZE 64 627 628 /** 629 * Maximum number of items in the DMUB ringbuffer. 630 */ 631 #define DMUB_RB_MAX_ENTRY 128 632 633 /** 634 * Ringbuffer size in bytes. 635 */ 636 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 637 638 /** 639 * REG_SET mask for reg offload. 640 */ 641 #define REG_SET_MASK 0xFFFF 642 643 /* 644 * enum dmub_cmd_type - DMUB inbox command. 645 * 646 * Command IDs should be treated as stable ABI. 647 * Do not reuse or modify IDs. 648 */ 649 enum dmub_cmd_type { 650 /** 651 * Invalid command. 652 */ 653 DMUB_CMD__NULL = 0, 654 /** 655 * Read modify write register sequence offload. 656 */ 657 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 658 /** 659 * Field update register sequence offload. 660 */ 661 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 662 /** 663 * Burst write sequence offload. 664 */ 665 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 666 /** 667 * Reg wait sequence offload. 668 */ 669 DMUB_CMD__REG_REG_WAIT = 4, 670 /** 671 * Workaround to avoid HUBP underflow during NV12 playback. 672 */ 673 DMUB_CMD__PLAT_54186_WA = 5, 674 /** 675 * Command type used to query FW feature caps. 676 */ 677 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 678 /** 679 * Command type used to get visual confirm color. 680 */ 681 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 682 /** 683 * Command type used for all PSR commands. 684 */ 685 DMUB_CMD__PSR = 64, 686 /** 687 * Command type used for all MALL commands. 688 */ 689 DMUB_CMD__MALL = 65, 690 /** 691 * Command type used for all ABM commands. 692 */ 693 DMUB_CMD__ABM = 66, 694 /** 695 * Command type used to update dirty rects in FW. 696 */ 697 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 698 /** 699 * Command type used to update cursor info in FW. 700 */ 701 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 702 /** 703 * Command type used for HW locking in FW. 704 */ 705 DMUB_CMD__HW_LOCK = 69, 706 /** 707 * Command type used to access DP AUX. 708 */ 709 DMUB_CMD__DP_AUX_ACCESS = 70, 710 /** 711 * Command type used for OUTBOX1 notification enable 712 */ 713 DMUB_CMD__OUTBOX1_ENABLE = 71, 714 715 /** 716 * Command type used for all idle optimization commands. 717 */ 718 DMUB_CMD__IDLE_OPT = 72, 719 /** 720 * Command type used for all clock manager commands. 721 */ 722 DMUB_CMD__CLK_MGR = 73, 723 /** 724 * Command type used for all panel control commands. 725 */ 726 DMUB_CMD__PANEL_CNTL = 74, 727 /** 728 * Command type used for <TODO:description> 729 */ 730 DMUB_CMD__CAB_FOR_SS = 75, 731 732 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 733 734 /** 735 * Command type used for interfacing with DPIA. 736 */ 737 DMUB_CMD__DPIA = 77, 738 /** 739 * Command type used for EDID CEA parsing 740 */ 741 DMUB_CMD__EDID_CEA = 79, 742 /** 743 * Command type used for getting usbc cable ID 744 */ 745 DMUB_CMD_GET_USBC_CABLE_ID = 81, 746 /** 747 * Command type used to query HPD state. 748 */ 749 DMUB_CMD__QUERY_HPD_STATE = 82, 750 /** 751 * Command type used for all VBIOS interface commands. 752 */ 753 754 /** 755 * Command type used for all SECURE_DISPLAY commands. 756 */ 757 DMUB_CMD__SECURE_DISPLAY = 85, 758 759 /** 760 * Command type used to set DPIA HPD interrupt state 761 */ 762 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 763 764 DMUB_CMD__VBIOS = 128, 765 }; 766 767 /** 768 * enum dmub_out_cmd_type - DMUB outbox commands. 769 */ 770 enum dmub_out_cmd_type { 771 /** 772 * Invalid outbox command, ignored. 773 */ 774 DMUB_OUT_CMD__NULL = 0, 775 /** 776 * Command type used for DP AUX Reply data notification 777 */ 778 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 779 /** 780 * Command type used for DP HPD event notification 781 */ 782 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 783 /** 784 * Command type used for SET_CONFIG Reply notification 785 */ 786 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 787 /** 788 * Command type used for USB4 DPIA notification 789 */ 790 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 791 }; 792 793 /* DMUB_CMD__DPIA command sub-types. */ 794 enum dmub_cmd_dpia_type { 795 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 796 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 797 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 798 }; 799 800 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 801 enum dmub_cmd_dpia_notification_type { 802 DPIA_NOTIFY__BW_ALLOCATION = 0, 803 }; 804 805 #pragma pack(push, 1) 806 807 /** 808 * struct dmub_cmd_header - Common command header fields. 809 */ 810 struct dmub_cmd_header { 811 unsigned int type : 8; /**< command type */ 812 unsigned int sub_type : 8; /**< command sub type */ 813 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 814 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 815 unsigned int reserved0 : 6; /**< reserved bits */ 816 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 817 unsigned int reserved1 : 2; /**< reserved bits */ 818 }; 819 820 /* 821 * struct dmub_cmd_read_modify_write_sequence - Read modify write 822 * 823 * 60 payload bytes can hold up to 5 sets of read modify writes, 824 * each take 3 dwords. 825 * 826 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 827 * 828 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 829 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 830 */ 831 struct dmub_cmd_read_modify_write_sequence { 832 uint32_t addr; /**< register address */ 833 uint32_t modify_mask; /**< modify mask */ 834 uint32_t modify_value; /**< modify value */ 835 }; 836 837 /** 838 * Maximum number of ops in read modify write sequence. 839 */ 840 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 841 842 /** 843 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 844 */ 845 struct dmub_rb_cmd_read_modify_write { 846 struct dmub_cmd_header header; /**< command header */ 847 /** 848 * Read modify write sequence. 849 */ 850 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 851 }; 852 853 /* 854 * Update a register with specified masks and values sequeunce 855 * 856 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 857 * 858 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 859 * 860 * 861 * USE CASE: 862 * 1. auto-increment register where additional read would update pointer and produce wrong result 863 * 2. toggle a bit without read in the middle 864 */ 865 866 struct dmub_cmd_reg_field_update_sequence { 867 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 868 uint32_t modify_value; /**< value to update with */ 869 }; 870 871 /** 872 * Maximum number of ops in field update sequence. 873 */ 874 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 875 876 /** 877 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 878 */ 879 struct dmub_rb_cmd_reg_field_update_sequence { 880 struct dmub_cmd_header header; /**< command header */ 881 uint32_t addr; /**< register address */ 882 /** 883 * Field update sequence. 884 */ 885 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 886 }; 887 888 889 /** 890 * Maximum number of burst write values. 891 */ 892 #define DMUB_BURST_WRITE_VALUES__MAX 14 893 894 /* 895 * struct dmub_rb_cmd_burst_write - Burst write 896 * 897 * support use case such as writing out LUTs. 898 * 899 * 60 payload bytes can hold up to 14 values to write to given address 900 * 901 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 902 */ 903 struct dmub_rb_cmd_burst_write { 904 struct dmub_cmd_header header; /**< command header */ 905 uint32_t addr; /**< register start address */ 906 /** 907 * Burst write register values. 908 */ 909 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 910 }; 911 912 /** 913 * struct dmub_rb_cmd_common - Common command header 914 */ 915 struct dmub_rb_cmd_common { 916 struct dmub_cmd_header header; /**< command header */ 917 /** 918 * Padding to RB_CMD_SIZE 919 */ 920 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 921 }; 922 923 /** 924 * struct dmub_cmd_reg_wait_data - Register wait data 925 */ 926 struct dmub_cmd_reg_wait_data { 927 uint32_t addr; /**< Register address */ 928 uint32_t mask; /**< Mask for register bits */ 929 uint32_t condition_field_value; /**< Value to wait for */ 930 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 931 }; 932 933 /** 934 * struct dmub_rb_cmd_reg_wait - Register wait command 935 */ 936 struct dmub_rb_cmd_reg_wait { 937 struct dmub_cmd_header header; /**< Command header */ 938 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 939 }; 940 941 /** 942 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 943 * 944 * Reprograms surface parameters to avoid underflow. 945 */ 946 struct dmub_cmd_PLAT_54186_wa { 947 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 948 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 949 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 950 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 951 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 952 struct { 953 uint8_t hubp_inst : 4; /**< HUBP instance */ 954 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 955 uint8_t immediate :1; /**< Immediate flip */ 956 uint8_t vmid : 4; /**< VMID */ 957 uint8_t grph_stereo : 1; /**< 1 if stereo */ 958 uint32_t reserved : 21; /**< Reserved */ 959 } flip_params; /**< Pageflip parameters */ 960 uint32_t reserved[9]; /**< Reserved bits */ 961 }; 962 963 /** 964 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 965 */ 966 struct dmub_rb_cmd_PLAT_54186_wa { 967 struct dmub_cmd_header header; /**< Command header */ 968 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 969 }; 970 971 /** 972 * struct dmub_rb_cmd_mall - MALL command data. 973 */ 974 struct dmub_rb_cmd_mall { 975 struct dmub_cmd_header header; /**< Common command header */ 976 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 977 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 978 uint32_t tmr_delay; /**< Timer delay */ 979 uint32_t tmr_scale; /**< Timer scale */ 980 uint16_t cursor_width; /**< Cursor width in pixels */ 981 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 982 uint16_t cursor_height; /**< Cursor height in pixels */ 983 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 984 uint8_t debug_bits; /**< Debug bits */ 985 986 uint8_t reserved1; /**< Reserved bits */ 987 uint8_t reserved2; /**< Reserved bits */ 988 }; 989 990 /** 991 * enum dmub_cmd_cab_type - TODO: 992 */ 993 enum dmub_cmd_cab_type { 994 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 995 DMUB_CMD__CAB_NO_DCN_REQ = 1, 996 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 997 }; 998 999 /** 1000 * struct dmub_rb_cmd_cab_for_ss - TODO: 1001 */ 1002 struct dmub_rb_cmd_cab_for_ss { 1003 struct dmub_cmd_header header; 1004 uint8_t cab_alloc_ways; /* total number of ways */ 1005 uint8_t debug_bits; /* debug bits */ 1006 }; 1007 1008 enum mclk_switch_mode { 1009 NONE = 0, 1010 FPO = 1, 1011 SUBVP = 2, 1012 VBLANK = 3, 1013 }; 1014 1015 /* Per pipe struct which stores the MCLK switch mode 1016 * data to be sent to DMUB. 1017 * Named "v2" for now -- once FPO and SUBVP are fully merged 1018 * the type name can be updated 1019 */ 1020 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1021 union { 1022 struct { 1023 uint32_t pix_clk_100hz; 1024 uint16_t main_vblank_start; 1025 uint16_t main_vblank_end; 1026 uint16_t mall_region_lines; 1027 uint16_t prefetch_lines; 1028 uint16_t prefetch_to_mall_start_lines; 1029 uint16_t processing_delay_lines; 1030 uint16_t htotal; // required to calculate line time for multi-display cases 1031 uint16_t vtotal; 1032 uint8_t main_pipe_index; 1033 uint8_t phantom_pipe_index; 1034 /* Since the microschedule is calculated in terms of OTG lines, 1035 * include any scaling factors to make sure when we get accurate 1036 * conversion when programming MALL_START_LINE (which is in terms 1037 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1038 * is 1/2 (numerator = 1, denominator = 2). 1039 */ 1040 uint8_t scale_factor_numerator; 1041 uint8_t scale_factor_denominator; 1042 uint8_t is_drr; 1043 uint8_t main_split_pipe_index; 1044 uint8_t phantom_split_pipe_index; 1045 } subvp_data; 1046 1047 struct { 1048 uint32_t pix_clk_100hz; 1049 uint16_t vblank_start; 1050 uint16_t vblank_end; 1051 uint16_t vstartup_start; 1052 uint16_t vtotal; 1053 uint16_t htotal; 1054 uint8_t vblank_pipe_index; 1055 uint8_t padding[1]; 1056 struct { 1057 uint8_t drr_in_use; 1058 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1059 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1060 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1061 uint8_t use_ramping; // Use ramping or not 1062 uint8_t drr_vblank_start_margin; 1063 } drr_info; // DRR considered as part of SubVP + VBLANK case 1064 } vblank_data; 1065 } pipe_config; 1066 1067 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1068 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1069 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1070 */ 1071 uint8_t mode; // enum mclk_switch_mode 1072 }; 1073 1074 /** 1075 * Config data for Sub-VP and FPO 1076 * Named "v2" for now -- once FPO and SUBVP are fully merged 1077 * the type name can be updated 1078 */ 1079 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1080 uint16_t watermark_a_cache; 1081 uint8_t vertical_int_margin_us; 1082 uint8_t pstate_allow_width_us; 1083 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1084 }; 1085 1086 /** 1087 * DMUB rb command definition for Sub-VP and FPO 1088 * Named "v2" for now -- once FPO and SUBVP are fully merged 1089 * the type name can be updated 1090 */ 1091 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1092 struct dmub_cmd_header header; 1093 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1094 }; 1095 1096 /** 1097 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1098 */ 1099 enum dmub_cmd_idle_opt_type { 1100 /** 1101 * DCN hardware restore. 1102 */ 1103 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1104 1105 /** 1106 * DCN hardware save. 1107 */ 1108 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1109 1110 /** 1111 * DCN hardware notify idle. 1112 */ 1113 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1114 }; 1115 1116 /** 1117 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1118 */ 1119 struct dmub_rb_cmd_idle_opt_dcn_restore { 1120 struct dmub_cmd_header header; /**< header */ 1121 }; 1122 1123 /** 1124 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1125 */ 1126 struct dmub_dcn_notify_idle_cntl_data { 1127 uint8_t driver_idle; 1128 uint8_t d3_entry; 1129 uint8_t trigger; 1130 uint8_t pad[1]; 1131 }; 1132 1133 /** 1134 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1135 */ 1136 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1137 struct dmub_cmd_header header; /**< header */ 1138 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1139 }; 1140 1141 /** 1142 * struct dmub_clocks - Clock update notification. 1143 */ 1144 struct dmub_clocks { 1145 uint32_t dispclk_khz; /**< dispclk kHz */ 1146 uint32_t dppclk_khz; /**< dppclk kHz */ 1147 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1148 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1149 }; 1150 1151 /** 1152 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1153 */ 1154 enum dmub_cmd_clk_mgr_type { 1155 /** 1156 * Notify DMCUB of clock update. 1157 */ 1158 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1159 }; 1160 1161 /** 1162 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1163 */ 1164 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1165 struct dmub_cmd_header header; /**< header */ 1166 struct dmub_clocks clocks; /**< clock data */ 1167 }; 1168 1169 /** 1170 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1171 */ 1172 struct dmub_cmd_digx_encoder_control_data { 1173 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1174 }; 1175 1176 /** 1177 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1178 */ 1179 struct dmub_rb_cmd_digx_encoder_control { 1180 struct dmub_cmd_header header; /**< header */ 1181 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1182 }; 1183 1184 /** 1185 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1186 */ 1187 struct dmub_cmd_set_pixel_clock_data { 1188 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1189 }; 1190 1191 /** 1192 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1193 */ 1194 struct dmub_rb_cmd_set_pixel_clock { 1195 struct dmub_cmd_header header; /**< header */ 1196 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1197 }; 1198 1199 /** 1200 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1201 */ 1202 struct dmub_cmd_enable_disp_power_gating_data { 1203 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1204 }; 1205 1206 /** 1207 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1208 */ 1209 struct dmub_rb_cmd_enable_disp_power_gating { 1210 struct dmub_cmd_header header; /**< header */ 1211 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1212 }; 1213 1214 /** 1215 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1216 */ 1217 struct dmub_dig_transmitter_control_data_v1_7 { 1218 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1219 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1220 union { 1221 uint8_t digmode; /**< enum atom_encode_mode_def */ 1222 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1223 } mode_laneset; 1224 uint8_t lanenum; /**< Number of lanes */ 1225 union { 1226 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1227 } symclk_units; 1228 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1229 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1230 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1231 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1232 uint8_t reserved1; /**< For future use */ 1233 uint8_t reserved2[3]; /**< For future use */ 1234 uint32_t reserved3[11]; /**< For future use */ 1235 }; 1236 1237 /** 1238 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1239 */ 1240 union dmub_cmd_dig1_transmitter_control_data { 1241 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1242 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1243 }; 1244 1245 /** 1246 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1247 */ 1248 struct dmub_rb_cmd_dig1_transmitter_control { 1249 struct dmub_cmd_header header; /**< header */ 1250 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1251 }; 1252 1253 /** 1254 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1255 */ 1256 struct dmub_rb_cmd_domain_control_data { 1257 uint8_t inst : 6; /**< DOMAIN instance to control */ 1258 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1259 uint8_t reserved[3]; /**< Reserved for future use */ 1260 }; 1261 1262 /** 1263 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1264 */ 1265 struct dmub_rb_cmd_domain_control { 1266 struct dmub_cmd_header header; /**< header */ 1267 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1268 }; 1269 1270 /** 1271 * DPIA tunnel command parameters. 1272 */ 1273 struct dmub_cmd_dig_dpia_control_data { 1274 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1275 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1276 union { 1277 uint8_t digmode; /** enum atom_encode_mode_def */ 1278 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1279 } mode_laneset; 1280 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1281 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1282 uint8_t hpdsel; /** =0: HPD is not assigned */ 1283 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1284 uint8_t dpia_id; /** Index of DPIA */ 1285 uint8_t fec_rdy : 1; 1286 uint8_t reserved : 7; 1287 uint32_t reserved1; 1288 }; 1289 1290 /** 1291 * DMUB command for DPIA tunnel control. 1292 */ 1293 struct dmub_rb_cmd_dig1_dpia_control { 1294 struct dmub_cmd_header header; 1295 struct dmub_cmd_dig_dpia_control_data dpia_control; 1296 }; 1297 1298 /** 1299 * SET_CONFIG Command Payload 1300 */ 1301 struct set_config_cmd_payload { 1302 uint8_t msg_type; /* set config message type */ 1303 uint8_t msg_data; /* set config message data */ 1304 }; 1305 1306 /** 1307 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1308 */ 1309 struct dmub_cmd_set_config_control_data { 1310 struct set_config_cmd_payload cmd_pkt; 1311 uint8_t instance; /* DPIA instance */ 1312 uint8_t immed_status; /* Immediate status returned in case of error */ 1313 }; 1314 1315 /** 1316 * DMUB command structure for SET_CONFIG command. 1317 */ 1318 struct dmub_rb_cmd_set_config_access { 1319 struct dmub_cmd_header header; /* header */ 1320 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1321 }; 1322 1323 /** 1324 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1325 */ 1326 struct dmub_cmd_mst_alloc_slots_control_data { 1327 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1328 uint8_t instance; /* DPIA instance */ 1329 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1330 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1331 }; 1332 1333 /** 1334 * DMUB command structure for SET_ command. 1335 */ 1336 struct dmub_rb_cmd_set_mst_alloc_slots { 1337 struct dmub_cmd_header header; /* header */ 1338 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1339 }; 1340 1341 /** 1342 * DMUB command structure for DPIA HPD int enable control. 1343 */ 1344 struct dmub_rb_cmd_dpia_hpd_int_enable { 1345 struct dmub_cmd_header header; /* header */ 1346 uint32_t enable; /* dpia hpd interrupt enable */ 1347 }; 1348 1349 /** 1350 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1351 */ 1352 struct dmub_rb_cmd_dpphy_init { 1353 struct dmub_cmd_header header; /**< header */ 1354 uint8_t reserved[60]; /**< reserved bits */ 1355 }; 1356 1357 /** 1358 * enum dp_aux_request_action - DP AUX request command listing. 1359 * 1360 * 4 AUX request command bits are shifted to high nibble. 1361 */ 1362 enum dp_aux_request_action { 1363 /** I2C-over-AUX write request */ 1364 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1365 /** I2C-over-AUX read request */ 1366 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1367 /** I2C-over-AUX write status request */ 1368 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1369 /** I2C-over-AUX write request with MOT=1 */ 1370 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1371 /** I2C-over-AUX read request with MOT=1 */ 1372 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1373 /** I2C-over-AUX write status request with MOT=1 */ 1374 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1375 /** Native AUX write request */ 1376 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1377 /** Native AUX read request */ 1378 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1379 }; 1380 1381 /** 1382 * enum aux_return_code_type - DP AUX process return code listing. 1383 */ 1384 enum aux_return_code_type { 1385 /** AUX process succeeded */ 1386 AUX_RET_SUCCESS = 0, 1387 /** AUX process failed with unknown reason */ 1388 AUX_RET_ERROR_UNKNOWN, 1389 /** AUX process completed with invalid reply */ 1390 AUX_RET_ERROR_INVALID_REPLY, 1391 /** AUX process timed out */ 1392 AUX_RET_ERROR_TIMEOUT, 1393 /** HPD was low during AUX process */ 1394 AUX_RET_ERROR_HPD_DISCON, 1395 /** Failed to acquire AUX engine */ 1396 AUX_RET_ERROR_ENGINE_ACQUIRE, 1397 /** AUX request not supported */ 1398 AUX_RET_ERROR_INVALID_OPERATION, 1399 /** AUX process not available */ 1400 AUX_RET_ERROR_PROTOCOL_ERROR, 1401 }; 1402 1403 /** 1404 * enum aux_channel_type - DP AUX channel type listing. 1405 */ 1406 enum aux_channel_type { 1407 /** AUX thru Legacy DP AUX */ 1408 AUX_CHANNEL_LEGACY_DDC, 1409 /** AUX thru DPIA DP tunneling */ 1410 AUX_CHANNEL_DPIA 1411 }; 1412 1413 /** 1414 * struct aux_transaction_parameters - DP AUX request transaction data 1415 */ 1416 struct aux_transaction_parameters { 1417 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1418 uint8_t action; /**< enum dp_aux_request_action */ 1419 uint8_t length; /**< DP AUX request data length */ 1420 uint8_t reserved; /**< For future use */ 1421 uint32_t address; /**< DP AUX address */ 1422 uint8_t data[16]; /**< DP AUX write data */ 1423 }; 1424 1425 /** 1426 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1427 */ 1428 struct dmub_cmd_dp_aux_control_data { 1429 uint8_t instance; /**< AUX instance or DPIA instance */ 1430 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1431 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1432 uint8_t reserved0; /**< For future use */ 1433 uint16_t timeout; /**< timeout time in us */ 1434 uint16_t reserved1; /**< For future use */ 1435 enum aux_channel_type type; /**< enum aux_channel_type */ 1436 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1437 }; 1438 1439 /** 1440 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1441 */ 1442 struct dmub_rb_cmd_dp_aux_access { 1443 /** 1444 * Command header. 1445 */ 1446 struct dmub_cmd_header header; 1447 /** 1448 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1449 */ 1450 struct dmub_cmd_dp_aux_control_data aux_control; 1451 }; 1452 1453 /** 1454 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1455 */ 1456 struct dmub_rb_cmd_outbox1_enable { 1457 /** 1458 * Command header. 1459 */ 1460 struct dmub_cmd_header header; 1461 /** 1462 * enable: 0x0 -> disable outbox1 notification (default value) 1463 * 0x1 -> enable outbox1 notification 1464 */ 1465 uint32_t enable; 1466 }; 1467 1468 /* DP AUX Reply command - OutBox Cmd */ 1469 /** 1470 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1471 */ 1472 struct aux_reply_data { 1473 /** 1474 * Aux cmd 1475 */ 1476 uint8_t command; 1477 /** 1478 * Aux reply data length (max: 16 bytes) 1479 */ 1480 uint8_t length; 1481 /** 1482 * Alignment only 1483 */ 1484 uint8_t pad[2]; 1485 /** 1486 * Aux reply data 1487 */ 1488 uint8_t data[16]; 1489 }; 1490 1491 /** 1492 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1493 */ 1494 struct aux_reply_control_data { 1495 /** 1496 * Reserved for future use 1497 */ 1498 uint32_t handle; 1499 /** 1500 * Aux Instance 1501 */ 1502 uint8_t instance; 1503 /** 1504 * Aux transaction result: definition in enum aux_return_code_type 1505 */ 1506 uint8_t result; 1507 /** 1508 * Alignment only 1509 */ 1510 uint16_t pad; 1511 }; 1512 1513 /** 1514 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1515 */ 1516 struct dmub_rb_cmd_dp_aux_reply { 1517 /** 1518 * Command header. 1519 */ 1520 struct dmub_cmd_header header; 1521 /** 1522 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1523 */ 1524 struct aux_reply_control_data control; 1525 /** 1526 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1527 */ 1528 struct aux_reply_data reply_data; 1529 }; 1530 1531 /* DP HPD Notify command - OutBox Cmd */ 1532 /** 1533 * DP HPD Type 1534 */ 1535 enum dp_hpd_type { 1536 /** 1537 * Normal DP HPD 1538 */ 1539 DP_HPD = 0, 1540 /** 1541 * DP HPD short pulse 1542 */ 1543 DP_IRQ 1544 }; 1545 1546 /** 1547 * DP HPD Status 1548 */ 1549 enum dp_hpd_status { 1550 /** 1551 * DP_HPD status low 1552 */ 1553 DP_HPD_UNPLUG = 0, 1554 /** 1555 * DP_HPD status high 1556 */ 1557 DP_HPD_PLUG 1558 }; 1559 1560 /** 1561 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1562 */ 1563 struct dp_hpd_data { 1564 /** 1565 * DP HPD instance 1566 */ 1567 uint8_t instance; 1568 /** 1569 * HPD type 1570 */ 1571 uint8_t hpd_type; 1572 /** 1573 * HPD status: only for type: DP_HPD to indicate status 1574 */ 1575 uint8_t hpd_status; 1576 /** 1577 * Alignment only 1578 */ 1579 uint8_t pad; 1580 }; 1581 1582 /** 1583 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1584 */ 1585 struct dmub_rb_cmd_dp_hpd_notify { 1586 /** 1587 * Command header. 1588 */ 1589 struct dmub_cmd_header header; 1590 /** 1591 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1592 */ 1593 struct dp_hpd_data hpd_data; 1594 }; 1595 1596 /** 1597 * Definition of a SET_CONFIG reply from DPOA. 1598 */ 1599 enum set_config_status { 1600 SET_CONFIG_PENDING = 0, 1601 SET_CONFIG_ACK_RECEIVED, 1602 SET_CONFIG_RX_TIMEOUT, 1603 SET_CONFIG_UNKNOWN_ERROR, 1604 }; 1605 1606 /** 1607 * Definition of a set_config reply 1608 */ 1609 struct set_config_reply_control_data { 1610 uint8_t instance; /* DPIA Instance */ 1611 uint8_t status; /* Set Config reply */ 1612 uint16_t pad; /* Alignment */ 1613 }; 1614 1615 /** 1616 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1617 */ 1618 struct dmub_rb_cmd_dp_set_config_reply { 1619 struct dmub_cmd_header header; 1620 struct set_config_reply_control_data set_config_reply_control; 1621 }; 1622 1623 /** 1624 * Definition of a DPIA notification header 1625 */ 1626 struct dpia_notification_header { 1627 uint8_t instance; /**< DPIA Instance */ 1628 uint8_t reserved[3]; 1629 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1630 }; 1631 1632 /** 1633 * Definition of the common data struct of DPIA notification 1634 */ 1635 struct dpia_notification_common { 1636 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1637 - sizeof(struct dpia_notification_header)]; 1638 }; 1639 1640 /** 1641 * Definition of a DPIA notification data 1642 */ 1643 struct dpia_bw_allocation_notify_data { 1644 union { 1645 struct { 1646 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1647 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1648 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1649 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1650 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1651 uint16_t reserved: 11; /**< Reserved */ 1652 } bits; 1653 1654 uint16_t flags; 1655 }; 1656 1657 uint8_t cm_id; /**< CM ID */ 1658 uint8_t group_id; /**< Group ID */ 1659 uint8_t granularity; /**< BW Allocation Granularity */ 1660 uint8_t estimated_bw; /**< Estimated_BW */ 1661 uint8_t allocated_bw; /**< Allocated_BW */ 1662 uint8_t reserved; 1663 }; 1664 1665 /** 1666 * union dpia_notify_data_type - DPIA Notification in Outbox command 1667 */ 1668 union dpia_notification_data { 1669 /** 1670 * DPIA Notification for common data struct 1671 */ 1672 struct dpia_notification_common common_data; 1673 1674 /** 1675 * DPIA Notification for DP BW Allocation support 1676 */ 1677 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1678 }; 1679 1680 /** 1681 * Definition of a DPIA notification payload 1682 */ 1683 struct dpia_notification_payload { 1684 struct dpia_notification_header header; 1685 union dpia_notification_data data; /**< DPIA notification payload data */ 1686 }; 1687 1688 /** 1689 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1690 */ 1691 struct dmub_rb_cmd_dpia_notification { 1692 struct dmub_cmd_header header; /**< DPIA notification header */ 1693 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1694 }; 1695 1696 /** 1697 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1698 */ 1699 struct dmub_cmd_hpd_state_query_data { 1700 uint8_t instance; /**< HPD instance or DPIA instance */ 1701 uint8_t result; /**< For returning HPD state */ 1702 uint16_t pad; /** < Alignment */ 1703 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1704 enum aux_return_code_type status; /**< for returning the status of command */ 1705 }; 1706 1707 /** 1708 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1709 */ 1710 struct dmub_rb_cmd_query_hpd_state { 1711 /** 1712 * Command header. 1713 */ 1714 struct dmub_cmd_header header; 1715 /** 1716 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1717 */ 1718 struct dmub_cmd_hpd_state_query_data data; 1719 }; 1720 1721 /* 1722 * Command IDs should be treated as stable ABI. 1723 * Do not reuse or modify IDs. 1724 */ 1725 1726 /** 1727 * PSR command sub-types. 1728 */ 1729 enum dmub_cmd_psr_type { 1730 /** 1731 * Set PSR version support. 1732 */ 1733 DMUB_CMD__PSR_SET_VERSION = 0, 1734 /** 1735 * Copy driver-calculated parameters to PSR state. 1736 */ 1737 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1738 /** 1739 * Enable PSR. 1740 */ 1741 DMUB_CMD__PSR_ENABLE = 2, 1742 1743 /** 1744 * Disable PSR. 1745 */ 1746 DMUB_CMD__PSR_DISABLE = 3, 1747 1748 /** 1749 * Set PSR level. 1750 * PSR level is a 16-bit value dicated by driver that 1751 * will enable/disable different functionality. 1752 */ 1753 DMUB_CMD__PSR_SET_LEVEL = 4, 1754 1755 /** 1756 * Forces PSR enabled until an explicit PSR disable call. 1757 */ 1758 DMUB_CMD__PSR_FORCE_STATIC = 5, 1759 /** 1760 * Set vtotal in psr active for FreeSync PSR. 1761 */ 1762 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1763 /** 1764 * Set PSR power option 1765 */ 1766 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1767 }; 1768 1769 enum dmub_cmd_fams_type { 1770 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1771 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1772 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1773 /** 1774 * For SubVP set manual trigger in FW because it 1775 * triggers DRR_UPDATE_PENDING which SubVP relies 1776 * on (for any SubVP cases that use a DRR display) 1777 */ 1778 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1779 }; 1780 1781 /** 1782 * PSR versions. 1783 */ 1784 enum psr_version { 1785 /** 1786 * PSR version 1. 1787 */ 1788 PSR_VERSION_1 = 0, 1789 /** 1790 * Freesync PSR SU. 1791 */ 1792 PSR_VERSION_SU_1 = 1, 1793 /** 1794 * PSR not supported. 1795 */ 1796 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1797 }; 1798 1799 /** 1800 * enum dmub_cmd_mall_type - MALL commands 1801 */ 1802 enum dmub_cmd_mall_type { 1803 /** 1804 * Allows display refresh from MALL. 1805 */ 1806 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1807 /** 1808 * Disallows display refresh from MALL. 1809 */ 1810 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1811 /** 1812 * Cursor copy for MALL. 1813 */ 1814 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1815 /** 1816 * Controls DF requests. 1817 */ 1818 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1819 }; 1820 1821 /** 1822 * PHY Link rate for DP. 1823 */ 1824 enum phy_link_rate { 1825 /** 1826 * not supported. 1827 */ 1828 PHY_RATE_UNKNOWN = 0, 1829 /** 1830 * Rate_1 (RBR) - 1.62 Gbps/Lane 1831 */ 1832 PHY_RATE_162 = 1, 1833 /** 1834 * Rate_2 - 2.16 Gbps/Lane 1835 */ 1836 PHY_RATE_216 = 2, 1837 /** 1838 * Rate_3 - 2.43 Gbps/Lane 1839 */ 1840 PHY_RATE_243 = 3, 1841 /** 1842 * Rate_4 (HBR) - 2.70 Gbps/Lane 1843 */ 1844 PHY_RATE_270 = 4, 1845 /** 1846 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1847 */ 1848 PHY_RATE_324 = 5, 1849 /** 1850 * Rate_6 - 4.32 Gbps/Lane 1851 */ 1852 PHY_RATE_432 = 6, 1853 /** 1854 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1855 */ 1856 PHY_RATE_540 = 7, 1857 /** 1858 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1859 */ 1860 PHY_RATE_810 = 8, 1861 /** 1862 * UHBR10 - 10.0 Gbps/Lane 1863 */ 1864 PHY_RATE_1000 = 9, 1865 /** 1866 * UHBR13.5 - 13.5 Gbps/Lane 1867 */ 1868 PHY_RATE_1350 = 10, 1869 /** 1870 * UHBR10 - 20.0 Gbps/Lane 1871 */ 1872 PHY_RATE_2000 = 11, 1873 }; 1874 1875 /** 1876 * enum dmub_phy_fsm_state - PHY FSM states. 1877 * PHY FSM state to transit to during PSR enable/disable. 1878 */ 1879 enum dmub_phy_fsm_state { 1880 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1881 DMUB_PHY_FSM_RESET, 1882 DMUB_PHY_FSM_RESET_RELEASED, 1883 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1884 DMUB_PHY_FSM_INITIALIZED, 1885 DMUB_PHY_FSM_CALIBRATED, 1886 DMUB_PHY_FSM_CALIBRATED_LP, 1887 DMUB_PHY_FSM_CALIBRATED_PG, 1888 DMUB_PHY_FSM_POWER_DOWN, 1889 DMUB_PHY_FSM_PLL_EN, 1890 DMUB_PHY_FSM_TX_EN, 1891 DMUB_PHY_FSM_FAST_LP, 1892 }; 1893 1894 /** 1895 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1896 */ 1897 struct dmub_cmd_psr_copy_settings_data { 1898 /** 1899 * Flags that can be set by driver to change some PSR behaviour. 1900 */ 1901 union dmub_psr_debug_flags debug; 1902 /** 1903 * 16-bit value dicated by driver that will enable/disable different functionality. 1904 */ 1905 uint16_t psr_level; 1906 /** 1907 * DPP HW instance. 1908 */ 1909 uint8_t dpp_inst; 1910 /** 1911 * MPCC HW instance. 1912 * Not used in dmub fw, 1913 * dmub fw will get active opp by reading odm registers. 1914 */ 1915 uint8_t mpcc_inst; 1916 /** 1917 * OPP HW instance. 1918 * Not used in dmub fw, 1919 * dmub fw will get active opp by reading odm registers. 1920 */ 1921 uint8_t opp_inst; 1922 /** 1923 * OTG HW instance. 1924 */ 1925 uint8_t otg_inst; 1926 /** 1927 * DIG FE HW instance. 1928 */ 1929 uint8_t digfe_inst; 1930 /** 1931 * DIG BE HW instance. 1932 */ 1933 uint8_t digbe_inst; 1934 /** 1935 * DP PHY HW instance. 1936 */ 1937 uint8_t dpphy_inst; 1938 /** 1939 * AUX HW instance. 1940 */ 1941 uint8_t aux_inst; 1942 /** 1943 * Determines if SMU optimzations are enabled/disabled. 1944 */ 1945 uint8_t smu_optimizations_en; 1946 /** 1947 * Unused. 1948 * TODO: Remove. 1949 */ 1950 uint8_t frame_delay; 1951 /** 1952 * If RFB setup time is greater than the total VBLANK time, 1953 * it is not possible for the sink to capture the video frame 1954 * in the same frame the SDP is sent. In this case, 1955 * the frame capture indication bit should be set and an extra 1956 * static frame should be transmitted to the sink. 1957 */ 1958 uint8_t frame_cap_ind; 1959 /** 1960 * Granularity of Y offset supported by sink. 1961 */ 1962 uint8_t su_y_granularity; 1963 /** 1964 * Indicates whether sink should start capturing 1965 * immediately following active scan line, 1966 * or starting with the 2nd active scan line. 1967 */ 1968 uint8_t line_capture_indication; 1969 /** 1970 * Multi-display optimizations are implemented on certain ASICs. 1971 */ 1972 uint8_t multi_disp_optimizations_en; 1973 /** 1974 * The last possible line SDP may be transmitted without violating 1975 * the RFB setup time or entering the active video frame. 1976 */ 1977 uint16_t init_sdp_deadline; 1978 /** 1979 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1980 */ 1981 uint8_t rate_control_caps ; 1982 /* 1983 * Force PSRSU always doing full frame update 1984 */ 1985 uint8_t force_ffu_mode; 1986 /** 1987 * Length of each horizontal line in us. 1988 */ 1989 uint32_t line_time_in_us; 1990 /** 1991 * FEC enable status in driver 1992 */ 1993 uint8_t fec_enable_status; 1994 /** 1995 * FEC re-enable delay when PSR exit. 1996 * unit is 100us, range form 0~255(0xFF). 1997 */ 1998 uint8_t fec_enable_delay_in100us; 1999 /** 2000 * PSR control version. 2001 */ 2002 uint8_t cmd_version; 2003 /** 2004 * Panel Instance. 2005 * Panel instance to identify which psr_state to use 2006 * Currently the support is only for 0 or 1 2007 */ 2008 uint8_t panel_inst; 2009 /* 2010 * DSC enable status in driver 2011 */ 2012 uint8_t dsc_enable_status; 2013 /* 2014 * Use FSM state for PSR power up/down 2015 */ 2016 uint8_t use_phy_fsm; 2017 /** 2018 * frame delay for frame re-lock 2019 */ 2020 uint8_t relock_delay_frame_cnt; 2021 /** 2022 * Explicit padding to 2 byte boundary. 2023 */ 2024 uint8_t pad3; 2025 /** 2026 * DSC Slice height. 2027 */ 2028 uint16_t dsc_slice_height; 2029 /** 2030 * Explicit padding to 4 byte boundary. 2031 */ 2032 uint16_t pad; 2033 }; 2034 2035 /** 2036 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2037 */ 2038 struct dmub_rb_cmd_psr_copy_settings { 2039 /** 2040 * Command header. 2041 */ 2042 struct dmub_cmd_header header; 2043 /** 2044 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2045 */ 2046 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2047 }; 2048 2049 /** 2050 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2051 */ 2052 struct dmub_cmd_psr_set_level_data { 2053 /** 2054 * 16-bit value dicated by driver that will enable/disable different functionality. 2055 */ 2056 uint16_t psr_level; 2057 /** 2058 * PSR control version. 2059 */ 2060 uint8_t cmd_version; 2061 /** 2062 * Panel Instance. 2063 * Panel instance to identify which psr_state to use 2064 * Currently the support is only for 0 or 1 2065 */ 2066 uint8_t panel_inst; 2067 }; 2068 2069 /** 2070 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2071 */ 2072 struct dmub_rb_cmd_psr_set_level { 2073 /** 2074 * Command header. 2075 */ 2076 struct dmub_cmd_header header; 2077 /** 2078 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2079 */ 2080 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2081 }; 2082 2083 struct dmub_rb_cmd_psr_enable_data { 2084 /** 2085 * PSR control version. 2086 */ 2087 uint8_t cmd_version; 2088 /** 2089 * Panel Instance. 2090 * Panel instance to identify which psr_state to use 2091 * Currently the support is only for 0 or 1 2092 */ 2093 uint8_t panel_inst; 2094 /** 2095 * Phy state to enter. 2096 * Values to use are defined in dmub_phy_fsm_state 2097 */ 2098 uint8_t phy_fsm_state; 2099 /** 2100 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2101 * Set this using enum phy_link_rate. 2102 * This does not support HDMI/DP2 for now. 2103 */ 2104 uint8_t phy_rate; 2105 }; 2106 2107 /** 2108 * Definition of a DMUB_CMD__PSR_ENABLE command. 2109 * PSR enable/disable is controlled using the sub_type. 2110 */ 2111 struct dmub_rb_cmd_psr_enable { 2112 /** 2113 * Command header. 2114 */ 2115 struct dmub_cmd_header header; 2116 2117 struct dmub_rb_cmd_psr_enable_data data; 2118 }; 2119 2120 /** 2121 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2122 */ 2123 struct dmub_cmd_psr_set_version_data { 2124 /** 2125 * PSR version that FW should implement. 2126 */ 2127 enum psr_version version; 2128 /** 2129 * PSR control version. 2130 */ 2131 uint8_t cmd_version; 2132 /** 2133 * Panel Instance. 2134 * Panel instance to identify which psr_state to use 2135 * Currently the support is only for 0 or 1 2136 */ 2137 uint8_t panel_inst; 2138 /** 2139 * Explicit padding to 4 byte boundary. 2140 */ 2141 uint8_t pad[2]; 2142 }; 2143 2144 /** 2145 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2146 */ 2147 struct dmub_rb_cmd_psr_set_version { 2148 /** 2149 * Command header. 2150 */ 2151 struct dmub_cmd_header header; 2152 /** 2153 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2154 */ 2155 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2156 }; 2157 2158 struct dmub_cmd_psr_force_static_data { 2159 /** 2160 * PSR control version. 2161 */ 2162 uint8_t cmd_version; 2163 /** 2164 * Panel Instance. 2165 * Panel instance to identify which psr_state to use 2166 * Currently the support is only for 0 or 1 2167 */ 2168 uint8_t panel_inst; 2169 /** 2170 * Explicit padding to 4 byte boundary. 2171 */ 2172 uint8_t pad[2]; 2173 }; 2174 2175 /** 2176 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2177 */ 2178 struct dmub_rb_cmd_psr_force_static { 2179 /** 2180 * Command header. 2181 */ 2182 struct dmub_cmd_header header; 2183 /** 2184 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2185 */ 2186 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2187 }; 2188 2189 /** 2190 * PSR SU debug flags. 2191 */ 2192 union dmub_psr_su_debug_flags { 2193 /** 2194 * PSR SU debug flags. 2195 */ 2196 struct { 2197 /** 2198 * Update dirty rect in SW only. 2199 */ 2200 uint8_t update_dirty_rect_only : 1; 2201 /** 2202 * Reset the cursor/plane state before processing the call. 2203 */ 2204 uint8_t reset_state : 1; 2205 } bitfields; 2206 2207 /** 2208 * Union for debug flags. 2209 */ 2210 uint32_t u32All; 2211 }; 2212 2213 /** 2214 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2215 * This triggers a selective update for PSR SU. 2216 */ 2217 struct dmub_cmd_update_dirty_rect_data { 2218 /** 2219 * Dirty rects from OS. 2220 */ 2221 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2222 /** 2223 * PSR SU debug flags. 2224 */ 2225 union dmub_psr_su_debug_flags debug_flags; 2226 /** 2227 * OTG HW instance. 2228 */ 2229 uint8_t pipe_idx; 2230 /** 2231 * Number of dirty rects. 2232 */ 2233 uint8_t dirty_rect_count; 2234 /** 2235 * PSR control version. 2236 */ 2237 uint8_t cmd_version; 2238 /** 2239 * Panel Instance. 2240 * Panel instance to identify which psr_state to use 2241 * Currently the support is only for 0 or 1 2242 */ 2243 uint8_t panel_inst; 2244 }; 2245 2246 /** 2247 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2248 */ 2249 struct dmub_rb_cmd_update_dirty_rect { 2250 /** 2251 * Command header. 2252 */ 2253 struct dmub_cmd_header header; 2254 /** 2255 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2256 */ 2257 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2258 }; 2259 2260 /** 2261 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2262 */ 2263 union dmub_reg_cursor_control_cfg { 2264 struct { 2265 uint32_t cur_enable: 1; 2266 uint32_t reser0: 3; 2267 uint32_t cur_2x_magnify: 1; 2268 uint32_t reser1: 3; 2269 uint32_t mode: 3; 2270 uint32_t reser2: 5; 2271 uint32_t pitch: 2; 2272 uint32_t reser3: 6; 2273 uint32_t line_per_chunk: 5; 2274 uint32_t reser4: 3; 2275 } bits; 2276 uint32_t raw; 2277 }; 2278 struct dmub_cursor_position_cache_hubp { 2279 union dmub_reg_cursor_control_cfg cur_ctl; 2280 union dmub_reg_position_cfg { 2281 struct { 2282 uint32_t cur_x_pos: 16; 2283 uint32_t cur_y_pos: 16; 2284 } bits; 2285 uint32_t raw; 2286 } position; 2287 union dmub_reg_hot_spot_cfg { 2288 struct { 2289 uint32_t hot_x: 16; 2290 uint32_t hot_y: 16; 2291 } bits; 2292 uint32_t raw; 2293 } hot_spot; 2294 union dmub_reg_dst_offset_cfg { 2295 struct { 2296 uint32_t dst_x_offset: 13; 2297 uint32_t reserved: 19; 2298 } bits; 2299 uint32_t raw; 2300 } dst_offset; 2301 }; 2302 2303 union dmub_reg_cur0_control_cfg { 2304 struct { 2305 uint32_t cur0_enable: 1; 2306 uint32_t expansion_mode: 1; 2307 uint32_t reser0: 1; 2308 uint32_t cur0_rom_en: 1; 2309 uint32_t mode: 3; 2310 uint32_t reserved: 25; 2311 } bits; 2312 uint32_t raw; 2313 }; 2314 struct dmub_cursor_position_cache_dpp { 2315 union dmub_reg_cur0_control_cfg cur0_ctl; 2316 }; 2317 struct dmub_cursor_position_cfg { 2318 struct dmub_cursor_position_cache_hubp pHubp; 2319 struct dmub_cursor_position_cache_dpp pDpp; 2320 uint8_t pipe_idx; 2321 /* 2322 * Padding is required. To be 4 Bytes Aligned. 2323 */ 2324 uint8_t padding[3]; 2325 }; 2326 2327 struct dmub_cursor_attribute_cache_hubp { 2328 uint32_t SURFACE_ADDR_HIGH; 2329 uint32_t SURFACE_ADDR; 2330 union dmub_reg_cursor_control_cfg cur_ctl; 2331 union dmub_reg_cursor_size_cfg { 2332 struct { 2333 uint32_t width: 16; 2334 uint32_t height: 16; 2335 } bits; 2336 uint32_t raw; 2337 } size; 2338 union dmub_reg_cursor_settings_cfg { 2339 struct { 2340 uint32_t dst_y_offset: 8; 2341 uint32_t chunk_hdl_adjust: 2; 2342 uint32_t reserved: 22; 2343 } bits; 2344 uint32_t raw; 2345 } settings; 2346 }; 2347 struct dmub_cursor_attribute_cache_dpp { 2348 union dmub_reg_cur0_control_cfg cur0_ctl; 2349 }; 2350 struct dmub_cursor_attributes_cfg { 2351 struct dmub_cursor_attribute_cache_hubp aHubp; 2352 struct dmub_cursor_attribute_cache_dpp aDpp; 2353 }; 2354 2355 struct dmub_cmd_update_cursor_payload0 { 2356 /** 2357 * Cursor dirty rects. 2358 */ 2359 struct dmub_rect cursor_rect; 2360 /** 2361 * PSR SU debug flags. 2362 */ 2363 union dmub_psr_su_debug_flags debug_flags; 2364 /** 2365 * Cursor enable/disable. 2366 */ 2367 uint8_t enable; 2368 /** 2369 * OTG HW instance. 2370 */ 2371 uint8_t pipe_idx; 2372 /** 2373 * PSR control version. 2374 */ 2375 uint8_t cmd_version; 2376 /** 2377 * Panel Instance. 2378 * Panel instance to identify which psr_state to use 2379 * Currently the support is only for 0 or 1 2380 */ 2381 uint8_t panel_inst; 2382 /** 2383 * Cursor Position Register. 2384 * Registers contains Hubp & Dpp modules 2385 */ 2386 struct dmub_cursor_position_cfg position_cfg; 2387 }; 2388 2389 struct dmub_cmd_update_cursor_payload1 { 2390 struct dmub_cursor_attributes_cfg attribute_cfg; 2391 }; 2392 2393 union dmub_cmd_update_cursor_info_data { 2394 struct dmub_cmd_update_cursor_payload0 payload0; 2395 struct dmub_cmd_update_cursor_payload1 payload1; 2396 }; 2397 /** 2398 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2399 */ 2400 struct dmub_rb_cmd_update_cursor_info { 2401 /** 2402 * Command header. 2403 */ 2404 struct dmub_cmd_header header; 2405 /** 2406 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2407 */ 2408 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2409 }; 2410 2411 /** 2412 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2413 */ 2414 struct dmub_cmd_psr_set_vtotal_data { 2415 /** 2416 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2417 */ 2418 uint16_t psr_vtotal_idle; 2419 /** 2420 * PSR control version. 2421 */ 2422 uint8_t cmd_version; 2423 /** 2424 * Panel Instance. 2425 * Panel instance to identify which psr_state to use 2426 * Currently the support is only for 0 or 1 2427 */ 2428 uint8_t panel_inst; 2429 /* 2430 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2431 */ 2432 uint16_t psr_vtotal_su; 2433 /** 2434 * Explicit padding to 4 byte boundary. 2435 */ 2436 uint8_t pad2[2]; 2437 }; 2438 2439 /** 2440 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2441 */ 2442 struct dmub_rb_cmd_psr_set_vtotal { 2443 /** 2444 * Command header. 2445 */ 2446 struct dmub_cmd_header header; 2447 /** 2448 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2449 */ 2450 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2451 }; 2452 2453 /** 2454 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2455 */ 2456 struct dmub_cmd_psr_set_power_opt_data { 2457 /** 2458 * PSR control version. 2459 */ 2460 uint8_t cmd_version; 2461 /** 2462 * Panel Instance. 2463 * Panel instance to identify which psr_state to use 2464 * Currently the support is only for 0 or 1 2465 */ 2466 uint8_t panel_inst; 2467 /** 2468 * Explicit padding to 4 byte boundary. 2469 */ 2470 uint8_t pad[2]; 2471 /** 2472 * PSR power option 2473 */ 2474 uint32_t power_opt; 2475 }; 2476 2477 /** 2478 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2479 */ 2480 struct dmub_rb_cmd_psr_set_power_opt { 2481 /** 2482 * Command header. 2483 */ 2484 struct dmub_cmd_header header; 2485 /** 2486 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2487 */ 2488 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2489 }; 2490 2491 /** 2492 * Set of HW components that can be locked. 2493 * 2494 * Note: If updating with more HW components, fields 2495 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2496 */ 2497 union dmub_hw_lock_flags { 2498 /** 2499 * Set of HW components that can be locked. 2500 */ 2501 struct { 2502 /** 2503 * Lock/unlock OTG master update lock. 2504 */ 2505 uint8_t lock_pipe : 1; 2506 /** 2507 * Lock/unlock cursor. 2508 */ 2509 uint8_t lock_cursor : 1; 2510 /** 2511 * Lock/unlock global update lock. 2512 */ 2513 uint8_t lock_dig : 1; 2514 /** 2515 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2516 */ 2517 uint8_t triple_buffer_lock : 1; 2518 } bits; 2519 2520 /** 2521 * Union for HW Lock flags. 2522 */ 2523 uint8_t u8All; 2524 }; 2525 2526 /** 2527 * Instances of HW to be locked. 2528 * 2529 * Note: If updating with more HW components, fields 2530 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2531 */ 2532 struct dmub_hw_lock_inst_flags { 2533 /** 2534 * OTG HW instance for OTG master update lock. 2535 */ 2536 uint8_t otg_inst; 2537 /** 2538 * OPP instance for cursor lock. 2539 */ 2540 uint8_t opp_inst; 2541 /** 2542 * OTG HW instance for global update lock. 2543 * TODO: Remove, and re-use otg_inst. 2544 */ 2545 uint8_t dig_inst; 2546 /** 2547 * Explicit pad to 4 byte boundary. 2548 */ 2549 uint8_t pad; 2550 }; 2551 2552 /** 2553 * Clients that can acquire the HW Lock Manager. 2554 * 2555 * Note: If updating with more clients, fields in 2556 * dmub_inbox0_cmd_lock_hw must be updated to match. 2557 */ 2558 enum hw_lock_client { 2559 /** 2560 * Driver is the client of HW Lock Manager. 2561 */ 2562 HW_LOCK_CLIENT_DRIVER = 0, 2563 /** 2564 * PSR SU is the client of HW Lock Manager. 2565 */ 2566 HW_LOCK_CLIENT_PSR_SU = 1, 2567 /** 2568 * Invalid client. 2569 */ 2570 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2571 }; 2572 2573 /** 2574 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2575 */ 2576 struct dmub_cmd_lock_hw_data { 2577 /** 2578 * Specifies the client accessing HW Lock Manager. 2579 */ 2580 enum hw_lock_client client; 2581 /** 2582 * HW instances to be locked. 2583 */ 2584 struct dmub_hw_lock_inst_flags inst_flags; 2585 /** 2586 * Which components to be locked. 2587 */ 2588 union dmub_hw_lock_flags hw_locks; 2589 /** 2590 * Specifies lock/unlock. 2591 */ 2592 uint8_t lock; 2593 /** 2594 * HW can be unlocked separately from releasing the HW Lock Mgr. 2595 * This flag is set if the client wishes to release the object. 2596 */ 2597 uint8_t should_release; 2598 /** 2599 * Explicit padding to 4 byte boundary. 2600 */ 2601 uint8_t pad; 2602 }; 2603 2604 /** 2605 * Definition of a DMUB_CMD__HW_LOCK command. 2606 * Command is used by driver and FW. 2607 */ 2608 struct dmub_rb_cmd_lock_hw { 2609 /** 2610 * Command header. 2611 */ 2612 struct dmub_cmd_header header; 2613 /** 2614 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2615 */ 2616 struct dmub_cmd_lock_hw_data lock_hw_data; 2617 }; 2618 2619 /** 2620 * ABM command sub-types. 2621 */ 2622 enum dmub_cmd_abm_type { 2623 /** 2624 * Initialize parameters for ABM algorithm. 2625 * Data is passed through an indirect buffer. 2626 */ 2627 DMUB_CMD__ABM_INIT_CONFIG = 0, 2628 /** 2629 * Set OTG and panel HW instance. 2630 */ 2631 DMUB_CMD__ABM_SET_PIPE = 1, 2632 /** 2633 * Set user requested backklight level. 2634 */ 2635 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2636 /** 2637 * Set ABM operating/aggression level. 2638 */ 2639 DMUB_CMD__ABM_SET_LEVEL = 3, 2640 /** 2641 * Set ambient light level. 2642 */ 2643 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2644 /** 2645 * Enable/disable fractional duty cycle for backlight PWM. 2646 */ 2647 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2648 2649 /** 2650 * unregister vertical interrupt after steady state is reached 2651 */ 2652 DMUB_CMD__ABM_PAUSE = 6, 2653 }; 2654 2655 /** 2656 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2657 * Requirements: 2658 * - Padded explicitly to 32-bit boundary. 2659 * - Must ensure this structure matches the one on driver-side, 2660 * otherwise it won't be aligned. 2661 */ 2662 struct abm_config_table { 2663 /** 2664 * Gamma curve thresholds, used for crgb conversion. 2665 */ 2666 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2667 /** 2668 * Gamma curve offsets, used for crgb conversion. 2669 */ 2670 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2671 /** 2672 * Gamma curve slopes, used for crgb conversion. 2673 */ 2674 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2675 /** 2676 * Custom backlight curve thresholds. 2677 */ 2678 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2679 /** 2680 * Custom backlight curve offsets. 2681 */ 2682 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2683 /** 2684 * Ambient light thresholds. 2685 */ 2686 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2687 /** 2688 * Minimum programmable backlight. 2689 */ 2690 uint16_t min_abm_backlight; // 122B 2691 /** 2692 * Minimum reduction values. 2693 */ 2694 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2695 /** 2696 * Maximum reduction values. 2697 */ 2698 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2699 /** 2700 * Bright positive gain. 2701 */ 2702 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2703 /** 2704 * Dark negative gain. 2705 */ 2706 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2707 /** 2708 * Hybrid factor. 2709 */ 2710 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2711 /** 2712 * Contrast factor. 2713 */ 2714 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2715 /** 2716 * Deviation gain. 2717 */ 2718 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2719 /** 2720 * Minimum knee. 2721 */ 2722 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2723 /** 2724 * Maximum knee. 2725 */ 2726 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2727 /** 2728 * Unused. 2729 */ 2730 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2731 /** 2732 * Explicit padding to 4 byte boundary. 2733 */ 2734 uint8_t pad3[3]; // 229B 2735 /** 2736 * Backlight ramp reduction. 2737 */ 2738 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2739 /** 2740 * Backlight ramp start. 2741 */ 2742 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2743 }; 2744 2745 /** 2746 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2747 */ 2748 struct dmub_cmd_abm_set_pipe_data { 2749 /** 2750 * OTG HW instance. 2751 */ 2752 uint8_t otg_inst; 2753 2754 /** 2755 * Panel Control HW instance. 2756 */ 2757 uint8_t panel_inst; 2758 2759 /** 2760 * Controls how ABM will interpret a set pipe or set level command. 2761 */ 2762 uint8_t set_pipe_option; 2763 2764 /** 2765 * Unused. 2766 * TODO: Remove. 2767 */ 2768 uint8_t ramping_boundary; 2769 }; 2770 2771 /** 2772 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2773 */ 2774 struct dmub_rb_cmd_abm_set_pipe { 2775 /** 2776 * Command header. 2777 */ 2778 struct dmub_cmd_header header; 2779 2780 /** 2781 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2782 */ 2783 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2784 }; 2785 2786 /** 2787 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2788 */ 2789 struct dmub_cmd_abm_set_backlight_data { 2790 /** 2791 * Number of frames to ramp to backlight user level. 2792 */ 2793 uint32_t frame_ramp; 2794 2795 /** 2796 * Requested backlight level from user. 2797 */ 2798 uint32_t backlight_user_level; 2799 2800 /** 2801 * ABM control version. 2802 */ 2803 uint8_t version; 2804 2805 /** 2806 * Panel Control HW instance mask. 2807 * Bit 0 is Panel Control HW instance 0. 2808 * Bit 1 is Panel Control HW instance 1. 2809 */ 2810 uint8_t panel_mask; 2811 2812 /** 2813 * Explicit padding to 4 byte boundary. 2814 */ 2815 uint8_t pad[2]; 2816 }; 2817 2818 /** 2819 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2820 */ 2821 struct dmub_rb_cmd_abm_set_backlight { 2822 /** 2823 * Command header. 2824 */ 2825 struct dmub_cmd_header header; 2826 2827 /** 2828 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2829 */ 2830 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2831 }; 2832 2833 /** 2834 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2835 */ 2836 struct dmub_cmd_abm_set_level_data { 2837 /** 2838 * Set current ABM operating/aggression level. 2839 */ 2840 uint32_t level; 2841 2842 /** 2843 * ABM control version. 2844 */ 2845 uint8_t version; 2846 2847 /** 2848 * Panel Control HW instance mask. 2849 * Bit 0 is Panel Control HW instance 0. 2850 * Bit 1 is Panel Control HW instance 1. 2851 */ 2852 uint8_t panel_mask; 2853 2854 /** 2855 * Explicit padding to 4 byte boundary. 2856 */ 2857 uint8_t pad[2]; 2858 }; 2859 2860 /** 2861 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2862 */ 2863 struct dmub_rb_cmd_abm_set_level { 2864 /** 2865 * Command header. 2866 */ 2867 struct dmub_cmd_header header; 2868 2869 /** 2870 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2871 */ 2872 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2873 }; 2874 2875 /** 2876 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2877 */ 2878 struct dmub_cmd_abm_set_ambient_level_data { 2879 /** 2880 * Ambient light sensor reading from OS. 2881 */ 2882 uint32_t ambient_lux; 2883 2884 /** 2885 * ABM control version. 2886 */ 2887 uint8_t version; 2888 2889 /** 2890 * Panel Control HW instance mask. 2891 * Bit 0 is Panel Control HW instance 0. 2892 * Bit 1 is Panel Control HW instance 1. 2893 */ 2894 uint8_t panel_mask; 2895 2896 /** 2897 * Explicit padding to 4 byte boundary. 2898 */ 2899 uint8_t pad[2]; 2900 }; 2901 2902 /** 2903 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2904 */ 2905 struct dmub_rb_cmd_abm_set_ambient_level { 2906 /** 2907 * Command header. 2908 */ 2909 struct dmub_cmd_header header; 2910 2911 /** 2912 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2913 */ 2914 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2915 }; 2916 2917 /** 2918 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2919 */ 2920 struct dmub_cmd_abm_set_pwm_frac_data { 2921 /** 2922 * Enable/disable fractional duty cycle for backlight PWM. 2923 * TODO: Convert to uint8_t. 2924 */ 2925 uint32_t fractional_pwm; 2926 2927 /** 2928 * ABM control version. 2929 */ 2930 uint8_t version; 2931 2932 /** 2933 * Panel Control HW instance mask. 2934 * Bit 0 is Panel Control HW instance 0. 2935 * Bit 1 is Panel Control HW instance 1. 2936 */ 2937 uint8_t panel_mask; 2938 2939 /** 2940 * Explicit padding to 4 byte boundary. 2941 */ 2942 uint8_t pad[2]; 2943 }; 2944 2945 /** 2946 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2947 */ 2948 struct dmub_rb_cmd_abm_set_pwm_frac { 2949 /** 2950 * Command header. 2951 */ 2952 struct dmub_cmd_header header; 2953 2954 /** 2955 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2956 */ 2957 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2958 }; 2959 2960 /** 2961 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2962 */ 2963 struct dmub_cmd_abm_init_config_data { 2964 /** 2965 * Location of indirect buffer used to pass init data to ABM. 2966 */ 2967 union dmub_addr src; 2968 2969 /** 2970 * Indirect buffer length. 2971 */ 2972 uint16_t bytes; 2973 2974 2975 /** 2976 * ABM control version. 2977 */ 2978 uint8_t version; 2979 2980 /** 2981 * Panel Control HW instance mask. 2982 * Bit 0 is Panel Control HW instance 0. 2983 * Bit 1 is Panel Control HW instance 1. 2984 */ 2985 uint8_t panel_mask; 2986 2987 /** 2988 * Explicit padding to 4 byte boundary. 2989 */ 2990 uint8_t pad[2]; 2991 }; 2992 2993 /** 2994 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2995 */ 2996 struct dmub_rb_cmd_abm_init_config { 2997 /** 2998 * Command header. 2999 */ 3000 struct dmub_cmd_header header; 3001 3002 /** 3003 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3004 */ 3005 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3006 }; 3007 3008 /** 3009 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3010 */ 3011 3012 struct dmub_cmd_abm_pause_data { 3013 3014 /** 3015 * Panel Control HW instance mask. 3016 * Bit 0 is Panel Control HW instance 0. 3017 * Bit 1 is Panel Control HW instance 1. 3018 */ 3019 uint8_t panel_mask; 3020 3021 /** 3022 * OTG hw instance 3023 */ 3024 uint8_t otg_inst; 3025 3026 /** 3027 * Enable or disable ABM pause 3028 */ 3029 uint8_t enable; 3030 3031 /** 3032 * Explicit padding to 4 byte boundary. 3033 */ 3034 uint8_t pad[1]; 3035 }; 3036 3037 /** 3038 * Definition of a DMUB_CMD__ABM_PAUSE command. 3039 */ 3040 struct dmub_rb_cmd_abm_pause { 3041 /** 3042 * Command header. 3043 */ 3044 struct dmub_cmd_header header; 3045 3046 /** 3047 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3048 */ 3049 struct dmub_cmd_abm_pause_data abm_pause_data; 3050 }; 3051 3052 /** 3053 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3054 */ 3055 struct dmub_cmd_query_feature_caps_data { 3056 /** 3057 * DMUB feature capabilities. 3058 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3059 */ 3060 struct dmub_feature_caps feature_caps; 3061 }; 3062 3063 /** 3064 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3065 */ 3066 struct dmub_rb_cmd_query_feature_caps { 3067 /** 3068 * Command header. 3069 */ 3070 struct dmub_cmd_header header; 3071 /** 3072 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3073 */ 3074 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3075 }; 3076 3077 /** 3078 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3079 */ 3080 struct dmub_cmd_visual_confirm_color_data { 3081 /** 3082 * DMUB feature capabilities. 3083 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3084 */ 3085 struct dmub_visual_confirm_color visual_confirm_color; 3086 }; 3087 3088 /** 3089 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3090 */ 3091 struct dmub_rb_cmd_get_visual_confirm_color { 3092 /** 3093 * Command header. 3094 */ 3095 struct dmub_cmd_header header; 3096 /** 3097 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3098 */ 3099 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3100 }; 3101 3102 struct dmub_optc_state { 3103 uint32_t v_total_max; 3104 uint32_t v_total_min; 3105 uint32_t tg_inst; 3106 }; 3107 3108 struct dmub_rb_cmd_drr_update { 3109 struct dmub_cmd_header header; 3110 struct dmub_optc_state dmub_optc_state_req; 3111 }; 3112 3113 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3114 uint32_t pix_clk_100hz; 3115 uint8_t max_ramp_step; 3116 uint8_t pipes; 3117 uint8_t min_refresh_in_hz; 3118 uint8_t pipe_count; 3119 uint8_t pipe_index[4]; 3120 }; 3121 3122 struct dmub_cmd_fw_assisted_mclk_switch_config { 3123 uint8_t fams_enabled; 3124 uint8_t visual_confirm_enabled; 3125 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3126 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3127 }; 3128 3129 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3130 struct dmub_cmd_header header; 3131 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3132 }; 3133 3134 /** 3135 * enum dmub_cmd_panel_cntl_type - Panel control command. 3136 */ 3137 enum dmub_cmd_panel_cntl_type { 3138 /** 3139 * Initializes embedded panel hardware blocks. 3140 */ 3141 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3142 /** 3143 * Queries backlight info for the embedded panel. 3144 */ 3145 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3146 }; 3147 3148 /** 3149 * struct dmub_cmd_panel_cntl_data - Panel control data. 3150 */ 3151 struct dmub_cmd_panel_cntl_data { 3152 uint32_t inst; /**< panel instance */ 3153 uint32_t current_backlight; /* in/out */ 3154 uint32_t bl_pwm_cntl; /* in/out */ 3155 uint32_t bl_pwm_period_cntl; /* in/out */ 3156 uint32_t bl_pwm_ref_div1; /* in/out */ 3157 uint8_t is_backlight_on : 1; /* in/out */ 3158 uint8_t is_powered_on : 1; /* in/out */ 3159 uint8_t padding[3]; 3160 uint32_t bl_pwm_ref_div2; /* in/out */ 3161 uint8_t reserved[4]; 3162 }; 3163 3164 /** 3165 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3166 */ 3167 struct dmub_rb_cmd_panel_cntl { 3168 struct dmub_cmd_header header; /**< header */ 3169 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3170 }; 3171 3172 /** 3173 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3174 */ 3175 struct dmub_cmd_lvtma_control_data { 3176 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3177 uint8_t bypass_panel_control_wait; 3178 uint8_t reserved_0[2]; /**< For future use */ 3179 uint8_t panel_inst; /**< LVTMA control instance */ 3180 uint8_t reserved_1[3]; /**< For future use */ 3181 }; 3182 3183 /** 3184 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3185 */ 3186 struct dmub_rb_cmd_lvtma_control { 3187 /** 3188 * Command header. 3189 */ 3190 struct dmub_cmd_header header; 3191 /** 3192 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3193 */ 3194 struct dmub_cmd_lvtma_control_data data; 3195 }; 3196 3197 /** 3198 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3199 */ 3200 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3201 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3202 uint8_t is_usb; /**< is phy is usb */ 3203 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3204 uint8_t is_dp4; /**< is dp in 4 lane */ 3205 }; 3206 3207 /** 3208 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3209 */ 3210 struct dmub_rb_cmd_transmitter_query_dp_alt { 3211 struct dmub_cmd_header header; /**< header */ 3212 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3213 }; 3214 3215 /** 3216 * Maximum number of bytes a chunk sent to DMUB for parsing 3217 */ 3218 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3219 3220 /** 3221 * Represent a chunk of CEA blocks sent to DMUB for parsing 3222 */ 3223 struct dmub_cmd_send_edid_cea { 3224 uint16_t offset; /**< offset into the CEA block */ 3225 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3226 uint16_t cea_total_length; /**< total length of the CEA block */ 3227 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3228 uint8_t pad[3]; /**< padding and for future expansion */ 3229 }; 3230 3231 /** 3232 * Result of VSDB parsing from CEA block 3233 */ 3234 struct dmub_cmd_edid_cea_amd_vsdb { 3235 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3236 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3237 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3238 uint16_t min_frame_rate; /**< Maximum frame rate */ 3239 uint16_t max_frame_rate; /**< Minimum frame rate */ 3240 }; 3241 3242 /** 3243 * Result of sending a CEA chunk 3244 */ 3245 struct dmub_cmd_edid_cea_ack { 3246 uint16_t offset; /**< offset of the chunk into the CEA block */ 3247 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3248 uint8_t pad; /**< padding and for future expansion */ 3249 }; 3250 3251 /** 3252 * Specify whether the result is an ACK/NACK or the parsing has finished 3253 */ 3254 enum dmub_cmd_edid_cea_reply_type { 3255 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3256 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3257 }; 3258 3259 /** 3260 * Definition of a DMUB_CMD__EDID_CEA command. 3261 */ 3262 struct dmub_rb_cmd_edid_cea { 3263 struct dmub_cmd_header header; /**< Command header */ 3264 union dmub_cmd_edid_cea_data { 3265 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3266 struct dmub_cmd_edid_cea_output { /**< output with results */ 3267 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3268 union { 3269 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3270 struct dmub_cmd_edid_cea_ack ack; 3271 }; 3272 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3273 } data; /**< Command data */ 3274 3275 }; 3276 3277 /** 3278 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3279 */ 3280 struct dmub_cmd_cable_id_input { 3281 uint8_t phy_inst; /**< phy inst for cable id data */ 3282 }; 3283 3284 /** 3285 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3286 */ 3287 struct dmub_cmd_cable_id_output { 3288 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3289 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3290 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3291 uint8_t RESERVED :2; /**< reserved means not defined */ 3292 }; 3293 3294 /** 3295 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3296 */ 3297 struct dmub_rb_cmd_get_usbc_cable_id { 3298 struct dmub_cmd_header header; /**< Command header */ 3299 /** 3300 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3301 */ 3302 union dmub_cmd_cable_id_data { 3303 struct dmub_cmd_cable_id_input input; /**< Input */ 3304 struct dmub_cmd_cable_id_output output; /**< Output */ 3305 uint8_t output_raw; /**< Raw data output */ 3306 } data; 3307 }; 3308 3309 /** 3310 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3311 */ 3312 enum dmub_cmd_secure_display_type { 3313 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3314 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3315 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3316 }; 3317 3318 /** 3319 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3320 */ 3321 struct dmub_rb_cmd_secure_display { 3322 struct dmub_cmd_header header; 3323 /** 3324 * Data passed from driver to dmub firmware. 3325 */ 3326 struct dmub_cmd_roi_info { 3327 uint16_t x_start; 3328 uint16_t x_end; 3329 uint16_t y_start; 3330 uint16_t y_end; 3331 uint8_t otg_id; 3332 uint8_t phy_id; 3333 } roi_info; 3334 }; 3335 3336 /** 3337 * union dmub_rb_cmd - DMUB inbox command. 3338 */ 3339 union dmub_rb_cmd { 3340 /** 3341 * Elements shared with all commands. 3342 */ 3343 struct dmub_rb_cmd_common cmd_common; 3344 /** 3345 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3346 */ 3347 struct dmub_rb_cmd_read_modify_write read_modify_write; 3348 /** 3349 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3350 */ 3351 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3352 /** 3353 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3354 */ 3355 struct dmub_rb_cmd_burst_write burst_write; 3356 /** 3357 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3358 */ 3359 struct dmub_rb_cmd_reg_wait reg_wait; 3360 /** 3361 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3362 */ 3363 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3364 /** 3365 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3366 */ 3367 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3368 /** 3369 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3370 */ 3371 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3372 /** 3373 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3374 */ 3375 struct dmub_rb_cmd_dpphy_init dpphy_init; 3376 /** 3377 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3378 */ 3379 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3380 /** 3381 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3382 */ 3383 struct dmub_rb_cmd_domain_control domain_control; 3384 /** 3385 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3386 */ 3387 struct dmub_rb_cmd_psr_set_version psr_set_version; 3388 /** 3389 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3390 */ 3391 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3392 /** 3393 * Definition of a DMUB_CMD__PSR_ENABLE command. 3394 */ 3395 struct dmub_rb_cmd_psr_enable psr_enable; 3396 /** 3397 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3398 */ 3399 struct dmub_rb_cmd_psr_set_level psr_set_level; 3400 /** 3401 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3402 */ 3403 struct dmub_rb_cmd_psr_force_static psr_force_static; 3404 /** 3405 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3406 */ 3407 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3408 /** 3409 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3410 */ 3411 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3412 /** 3413 * Definition of a DMUB_CMD__HW_LOCK command. 3414 * Command is used by driver and FW. 3415 */ 3416 struct dmub_rb_cmd_lock_hw lock_hw; 3417 /** 3418 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3419 */ 3420 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3421 /** 3422 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3423 */ 3424 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3425 /** 3426 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3427 */ 3428 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3429 /** 3430 * Definition of a DMUB_CMD__MALL command. 3431 */ 3432 struct dmub_rb_cmd_mall mall; 3433 /** 3434 * Definition of a DMUB_CMD__CAB command. 3435 */ 3436 struct dmub_rb_cmd_cab_for_ss cab; 3437 3438 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3439 3440 /** 3441 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3442 */ 3443 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3444 3445 /** 3446 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3447 */ 3448 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3449 3450 /** 3451 * Definition of DMUB_CMD__PANEL_CNTL commands. 3452 */ 3453 struct dmub_rb_cmd_panel_cntl panel_cntl; 3454 /** 3455 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3456 */ 3457 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3458 3459 /** 3460 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3461 */ 3462 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3463 3464 /** 3465 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3466 */ 3467 struct dmub_rb_cmd_abm_set_level abm_set_level; 3468 3469 /** 3470 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3471 */ 3472 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3473 3474 /** 3475 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3476 */ 3477 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3478 3479 /** 3480 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3481 */ 3482 struct dmub_rb_cmd_abm_init_config abm_init_config; 3483 3484 /** 3485 * Definition of a DMUB_CMD__ABM_PAUSE command. 3486 */ 3487 struct dmub_rb_cmd_abm_pause abm_pause; 3488 3489 /** 3490 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3491 */ 3492 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3493 3494 /** 3495 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3496 */ 3497 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3498 3499 /** 3500 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3501 */ 3502 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3503 3504 /** 3505 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3506 */ 3507 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3508 struct dmub_rb_cmd_drr_update drr_update; 3509 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3510 3511 /** 3512 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3513 */ 3514 struct dmub_rb_cmd_lvtma_control lvtma_control; 3515 /** 3516 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3517 */ 3518 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3519 /** 3520 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3521 */ 3522 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3523 /** 3524 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3525 */ 3526 struct dmub_rb_cmd_set_config_access set_config_access; 3527 /** 3528 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3529 */ 3530 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3531 /** 3532 * Definition of a DMUB_CMD__EDID_CEA command. 3533 */ 3534 struct dmub_rb_cmd_edid_cea edid_cea; 3535 /** 3536 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3537 */ 3538 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3539 3540 /** 3541 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3542 */ 3543 struct dmub_rb_cmd_query_hpd_state query_hpd; 3544 /** 3545 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3546 */ 3547 struct dmub_rb_cmd_secure_display secure_display; 3548 3549 /** 3550 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3551 */ 3552 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3553 }; 3554 3555 /** 3556 * union dmub_rb_out_cmd - Outbox command 3557 */ 3558 union dmub_rb_out_cmd { 3559 /** 3560 * Parameters common to every command. 3561 */ 3562 struct dmub_rb_cmd_common cmd_common; 3563 /** 3564 * AUX reply command. 3565 */ 3566 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3567 /** 3568 * HPD notify command. 3569 */ 3570 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3571 /** 3572 * SET_CONFIG reply command. 3573 */ 3574 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3575 /** 3576 * DPIA notification command. 3577 */ 3578 struct dmub_rb_cmd_dpia_notification dpia_notification; 3579 }; 3580 #pragma pack(pop) 3581 3582 3583 //============================================================================== 3584 //</DMUB_CMD>=================================================================== 3585 //============================================================================== 3586 //< DMUB_RB>==================================================================== 3587 //============================================================================== 3588 3589 #if defined(__cplusplus) 3590 extern "C" { 3591 #endif 3592 3593 /** 3594 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3595 */ 3596 struct dmub_rb_init_params { 3597 void *ctx; /**< Caller provided context pointer */ 3598 void *base_address; /**< CPU base address for ring's data */ 3599 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3600 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3601 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3602 }; 3603 3604 /** 3605 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3606 */ 3607 struct dmub_rb { 3608 void *base_address; /**< CPU address for the ring's data */ 3609 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3610 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3611 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3612 3613 void *ctx; /**< Caller provided context pointer */ 3614 void *dmub; /**< Pointer to the DMUB interface */ 3615 }; 3616 3617 /** 3618 * @brief Checks if the ringbuffer is empty. 3619 * 3620 * @param rb DMUB Ringbuffer 3621 * @return true if empty 3622 * @return false otherwise 3623 */ 3624 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3625 { 3626 return (rb->wrpt == rb->rptr); 3627 } 3628 3629 /** 3630 * @brief Checks if the ringbuffer is full 3631 * 3632 * @param rb DMUB Ringbuffer 3633 * @return true if full 3634 * @return false otherwise 3635 */ 3636 static inline bool dmub_rb_full(struct dmub_rb *rb) 3637 { 3638 uint32_t data_count; 3639 3640 if (rb->wrpt >= rb->rptr) 3641 data_count = rb->wrpt - rb->rptr; 3642 else 3643 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3644 3645 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3646 } 3647 3648 /** 3649 * @brief Pushes a command into the ringbuffer 3650 * 3651 * @param rb DMUB ringbuffer 3652 * @param cmd The command to push 3653 * @return true if the ringbuffer was not full 3654 * @return false otherwise 3655 */ 3656 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3657 const union dmub_rb_cmd *cmd) 3658 { 3659 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3660 const uint64_t *src = (const uint64_t *)cmd; 3661 uint8_t i; 3662 3663 if (dmub_rb_full(rb)) 3664 return false; 3665 3666 // copying data 3667 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3668 *dst++ = *src++; 3669 3670 rb->wrpt += DMUB_RB_CMD_SIZE; 3671 3672 if (rb->wrpt >= rb->capacity) 3673 rb->wrpt %= rb->capacity; 3674 3675 return true; 3676 } 3677 3678 /** 3679 * @brief Pushes a command into the DMUB outbox ringbuffer 3680 * 3681 * @param rb DMUB outbox ringbuffer 3682 * @param cmd Outbox command 3683 * @return true if not full 3684 * @return false otherwise 3685 */ 3686 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3687 const union dmub_rb_out_cmd *cmd) 3688 { 3689 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3690 const uint8_t *src = (const uint8_t *)cmd; 3691 3692 if (dmub_rb_full(rb)) 3693 return false; 3694 3695 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3696 3697 rb->wrpt += DMUB_RB_CMD_SIZE; 3698 3699 if (rb->wrpt >= rb->capacity) 3700 rb->wrpt %= rb->capacity; 3701 3702 return true; 3703 } 3704 3705 /** 3706 * @brief Returns the next unprocessed command in the ringbuffer. 3707 * 3708 * @param rb DMUB ringbuffer 3709 * @param cmd The command to return 3710 * @return true if not empty 3711 * @return false otherwise 3712 */ 3713 static inline bool dmub_rb_front(struct dmub_rb *rb, 3714 union dmub_rb_cmd **cmd) 3715 { 3716 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3717 3718 if (dmub_rb_empty(rb)) 3719 return false; 3720 3721 *cmd = (union dmub_rb_cmd *)rb_cmd; 3722 3723 return true; 3724 } 3725 3726 /** 3727 * @brief Determines the next ringbuffer offset. 3728 * 3729 * @param rb DMUB inbox ringbuffer 3730 * @param num_cmds Number of commands 3731 * @param next_rptr The next offset in the ringbuffer 3732 */ 3733 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3734 uint32_t num_cmds, 3735 uint32_t *next_rptr) 3736 { 3737 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3738 3739 if (*next_rptr >= rb->capacity) 3740 *next_rptr %= rb->capacity; 3741 } 3742 3743 /** 3744 * @brief Returns a pointer to a command in the inbox. 3745 * 3746 * @param rb DMUB inbox ringbuffer 3747 * @param cmd The inbox command to return 3748 * @param rptr The ringbuffer offset 3749 * @return true if not empty 3750 * @return false otherwise 3751 */ 3752 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3753 union dmub_rb_cmd **cmd, 3754 uint32_t rptr) 3755 { 3756 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3757 3758 if (dmub_rb_empty(rb)) 3759 return false; 3760 3761 *cmd = (union dmub_rb_cmd *)rb_cmd; 3762 3763 return true; 3764 } 3765 3766 /** 3767 * @brief Returns the next unprocessed command in the outbox. 3768 * 3769 * @param rb DMUB outbox ringbuffer 3770 * @param cmd The outbox command to return 3771 * @return true if not empty 3772 * @return false otherwise 3773 */ 3774 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3775 union dmub_rb_out_cmd *cmd) 3776 { 3777 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3778 uint64_t *dst = (uint64_t *)cmd; 3779 uint8_t i; 3780 3781 if (dmub_rb_empty(rb)) 3782 return false; 3783 3784 // copying data 3785 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3786 *dst++ = *src++; 3787 3788 return true; 3789 } 3790 3791 /** 3792 * @brief Removes the front entry in the ringbuffer. 3793 * 3794 * @param rb DMUB ringbuffer 3795 * @return true if the command was removed 3796 * @return false if there were no commands 3797 */ 3798 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3799 { 3800 if (dmub_rb_empty(rb)) 3801 return false; 3802 3803 rb->rptr += DMUB_RB_CMD_SIZE; 3804 3805 if (rb->rptr >= rb->capacity) 3806 rb->rptr %= rb->capacity; 3807 3808 return true; 3809 } 3810 3811 /** 3812 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3813 * 3814 * Avoids a race condition where DMCUB accesses memory while 3815 * there are still writes in flight to framebuffer. 3816 * 3817 * @param rb DMUB ringbuffer 3818 */ 3819 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3820 { 3821 uint32_t rptr = rb->rptr; 3822 uint32_t wptr = rb->wrpt; 3823 3824 while (rptr != wptr) { 3825 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3826 uint8_t i; 3827 3828 /* Don't remove this. 3829 * The contents need to actually be read from the ring buffer 3830 * for this function to be effective. 3831 */ 3832 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3833 (void)READ_ONCE(*data++); 3834 3835 rptr += DMUB_RB_CMD_SIZE; 3836 if (rptr >= rb->capacity) 3837 rptr %= rb->capacity; 3838 } 3839 } 3840 3841 /** 3842 * @brief Initializes a DMCUB ringbuffer 3843 * 3844 * @param rb DMUB ringbuffer 3845 * @param init_params initial configuration for the ringbuffer 3846 */ 3847 static inline void dmub_rb_init(struct dmub_rb *rb, 3848 struct dmub_rb_init_params *init_params) 3849 { 3850 rb->base_address = init_params->base_address; 3851 rb->capacity = init_params->capacity; 3852 rb->rptr = init_params->read_ptr; 3853 rb->wrpt = init_params->write_ptr; 3854 } 3855 3856 /** 3857 * @brief Copies output data from in/out commands into the given command. 3858 * 3859 * @param rb DMUB ringbuffer 3860 * @param cmd Command to copy data into 3861 */ 3862 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3863 union dmub_rb_cmd *cmd) 3864 { 3865 // Copy rb entry back into command 3866 uint8_t *rd_ptr = (rb->rptr == 0) ? 3867 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3868 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3869 3870 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3871 } 3872 3873 #if defined(__cplusplus) 3874 } 3875 #endif 3876 3877 //============================================================================== 3878 //</DMUB_RB>==================================================================== 3879 //============================================================================== 3880 3881 #endif /* _DMUB_CMD_H_ */ 3882