1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_DCN20_H_ 27 #define _DMUB_DCN20_H_ 28 29 #include "../inc/dmub_types.h" 30 31 struct dmub_srv; 32 33 /* DCN20 register definitions. */ 34 35 #define DMUB_COMMON_REGS() \ 36 DMUB_SR(DMCUB_CNTL) \ 37 DMUB_SR(DMCUB_MEM_CNTL) \ 38 DMUB_SR(DMCUB_SEC_CNTL) \ 39 DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \ 40 DMUB_SR(DMCUB_INBOX1_SIZE) \ 41 DMUB_SR(DMCUB_INBOX1_RPTR) \ 42 DMUB_SR(DMCUB_INBOX1_WPTR) \ 43 DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \ 44 DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \ 45 DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \ 46 DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \ 47 DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \ 48 DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \ 49 DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \ 50 DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \ 51 DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \ 52 DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \ 53 DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \ 54 DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \ 55 DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \ 56 DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \ 57 DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \ 58 DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \ 59 DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \ 60 DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \ 61 DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \ 62 DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \ 63 DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \ 64 DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \ 65 DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \ 66 DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \ 67 DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \ 68 DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \ 69 DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \ 70 DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \ 71 DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \ 72 DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \ 73 DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \ 74 DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \ 75 DMUB_SR(DMCUB_REGION4_OFFSET) \ 76 DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \ 77 DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \ 78 DMUB_SR(DMCUB_SCRATCH0) \ 79 DMUB_SR(DMCUB_SCRATCH1) \ 80 DMUB_SR(DMCUB_SCRATCH2) \ 81 DMUB_SR(DMCUB_SCRATCH3) \ 82 DMUB_SR(DMCUB_SCRATCH4) \ 83 DMUB_SR(DMCUB_SCRATCH5) \ 84 DMUB_SR(DMCUB_SCRATCH6) \ 85 DMUB_SR(DMCUB_SCRATCH7) \ 86 DMUB_SR(DMCUB_SCRATCH8) \ 87 DMUB_SR(DMCUB_SCRATCH9) \ 88 DMUB_SR(DMCUB_SCRATCH10) \ 89 DMUB_SR(DMCUB_SCRATCH11) \ 90 DMUB_SR(DMCUB_SCRATCH12) \ 91 DMUB_SR(DMCUB_SCRATCH13) \ 92 DMUB_SR(DMCUB_SCRATCH14) \ 93 DMUB_SR(DMCUB_SCRATCH15) \ 94 DMUB_SR(CC_DC_PIPE_DIS) \ 95 DMUB_SR(MMHUBBUB_SOFT_RESET) \ 96 DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ 97 DMUB_SR(DCN_VM_FB_OFFSET) 98 99 #define DMUB_COMMON_FIELDS() \ 100 DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ 101 DMUB_SF(DMCUB_CNTL, DMCUB_SOFT_RESET) \ 102 DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \ 103 DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE) \ 104 DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_WRITE_SPACE) \ 105 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \ 106 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \ 107 DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \ 108 DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \ 109 DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \ 110 DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \ 111 DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \ 112 DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \ 113 DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \ 114 DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \ 115 DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \ 116 DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \ 117 DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \ 118 DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \ 119 DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \ 120 DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \ 121 DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \ 122 DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \ 123 DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \ 124 DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ 125 DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ 126 DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ 127 DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ 128 DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) 129 130 struct dmub_srv_common_reg_offset { 131 #define DMUB_SR(reg) uint32_t reg; 132 DMUB_COMMON_REGS() 133 #undef DMUB_SR 134 }; 135 136 struct dmub_srv_common_reg_shift { 137 #define DMUB_SF(reg, field) uint8_t reg##__##field; 138 DMUB_COMMON_FIELDS() 139 #undef DMUB_SF 140 }; 141 142 struct dmub_srv_common_reg_mask { 143 #define DMUB_SF(reg, field) uint32_t reg##__##field; 144 DMUB_COMMON_FIELDS() 145 #undef DMUB_SF 146 }; 147 148 struct dmub_srv_common_regs { 149 const struct dmub_srv_common_reg_offset offset; 150 const struct dmub_srv_common_reg_mask mask; 151 const struct dmub_srv_common_reg_shift shift; 152 }; 153 154 extern const struct dmub_srv_common_regs dmub_srv_dcn20_regs; 155 156 /* Hardware functions. */ 157 158 void dmub_dcn20_init(struct dmub_srv *dmub); 159 160 void dmub_dcn20_reset(struct dmub_srv *dmub); 161 162 void dmub_dcn20_reset_release(struct dmub_srv *dmub); 163 164 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, 165 const struct dmub_window *cw0, 166 const struct dmub_window *cw1); 167 168 void dmub_dcn20_setup_windows(struct dmub_srv *dmub, 169 const struct dmub_window *cw2, 170 const struct dmub_window *cw3, 171 const struct dmub_window *cw4, 172 const struct dmub_window *cw5, 173 const struct dmub_window *cw6); 174 175 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, 176 const struct dmub_region *inbox1); 177 178 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub); 179 180 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); 181 182 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub); 183 184 bool dmub_dcn20_is_supported(struct dmub_srv *dmub); 185 186 #endif /* _DMUB_DCN20_H_ */ 187