1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright (C) 2021 Advanced Micro Devices, Inc.
4  *
5  * Authors: AMD
6  */
7 
8 #include "../dmub_srv.h"
9 #include "dmub_reg.h"
10 #include "dmub_dcn303.h"
11 
12 #include "sienna_cichlid_ip_offset.h"
13 #include "dcn/dcn_3_0_3_offset.h"
14 #include "dcn/dcn_3_0_3_sh_mask.h"
15 
16 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
17 #define CTX dmub
18 #define REGS dmub->regs
19 
20 /* Registers. */
21 
22 const struct dmub_srv_common_regs dmub_srv_dcn303_regs = {
23 #define DMUB_SR(reg) REG_OFFSET(reg),
24 	{
25 		DMUB_COMMON_REGS()
26 		DMCUB_INTERNAL_REGS()
27 	},
28 #undef DMUB_SR
29 
30 #define DMUB_SF(reg, field) FD_MASK(reg, field),
31 	{ DMUB_COMMON_FIELDS() },
32 #undef DMUB_SF
33 
34 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
35 	{ DMUB_COMMON_FIELDS() },
36 #undef DMUB_SF
37 };
38 
39 /* Shared functions. */
40 
41