1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "mod_info_packet.h" 27 #include "core_types.h" 28 #include "dc_types.h" 29 #include "mod_shared.h" 30 #include "mod_freesync.h" 31 #include "dc.h" 32 33 enum vsc_packet_revision { 34 vsc_packet_undefined = 0, 35 //01h = VSC SDP supports only 3D stereo. 36 vsc_packet_rev1 = 1, 37 //02h = 3D stereo + PSR. 38 vsc_packet_rev2 = 2, 39 //03h = 3D stereo + PSR2. 40 vsc_packet_rev3 = 3, 41 //04h = 3D stereo + PSR/PSR2 + Y-coordinate. 42 vsc_packet_rev4 = 4, 43 //05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format 44 vsc_packet_rev5 = 5, 45 }; 46 47 #define HDMI_INFOFRAME_TYPE_VENDOR 0x81 48 #define HF_VSIF_VERSION 1 49 50 // VTEM Byte Offset 51 #define VTEM_PB0 0 52 #define VTEM_PB1 1 53 #define VTEM_PB2 2 54 #define VTEM_PB3 3 55 #define VTEM_PB4 4 56 #define VTEM_PB5 5 57 #define VTEM_PB6 6 58 59 #define VTEM_MD0 7 60 #define VTEM_MD1 8 61 #define VTEM_MD2 9 62 #define VTEM_MD3 10 63 64 65 // VTEM Byte Masks 66 //PB0 67 #define MASK_VTEM_PB0__RESERVED0 0x01 68 #define MASK_VTEM_PB0__SYNC 0x02 69 #define MASK_VTEM_PB0__VFR 0x04 70 #define MASK_VTEM_PB0__AFR 0x08 71 #define MASK_VTEM_PB0__DS_TYPE 0x30 72 //0: Periodic pseudo-static EM Data Set 73 //1: Periodic dynamic EM Data Set 74 //2: Unique EM Data Set 75 //3: Reserved 76 #define MASK_VTEM_PB0__END 0x40 77 #define MASK_VTEM_PB0__NEW 0x80 78 79 //PB1 80 #define MASK_VTEM_PB1__RESERVED1 0xFF 81 82 //PB2 83 #define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF 84 //0: This is a Vendor Specific EM Data Set 85 //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean) 86 //2: This EM Data Set is defined by CTA-861-G 87 //3: This EM Data Set is defined by VESA 88 //PB3 89 #define MASK_VTEM_PB3__DATA_SET_TAG_MSB 0xFF 90 //PB4 91 #define MASK_VTEM_PB4__DATA_SET_TAG_LSB 0xFF 92 //PB5 93 #define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF 94 //PB6 95 #define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF 96 97 98 99 //PB7-27 (20 bytes): 100 //PB7 = MD0 101 #define MASK_VTEM_MD0__VRR_EN 0x01 102 #define MASK_VTEM_MD0__M_CONST 0x02 103 #define MASK_VTEM_MD0__QMS_EN 0x04 104 #define MASK_VTEM_MD0__RESERVED2 0x08 105 #define MASK_VTEM_MD0__FVA_FACTOR_M1 0xF0 106 107 //MD1 108 #define MASK_VTEM_MD1__BASE_VFRONT 0xFF 109 110 //MD2 111 #define MASK_VTEM_MD2__BASE_REFRESH_RATE_98 0x03 112 #define MASK_VTEM_MD2__RB 0x04 113 #define MASK_VTEM_MD2__NEXT_TFR 0xF8 114 115 //MD3 116 #define MASK_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF 117 118 enum ColorimetryRGBDP { 119 ColorimetryRGB_DP_sRGB = 0, 120 ColorimetryRGB_DP_AdobeRGB = 3, 121 ColorimetryRGB_DP_P3 = 4, 122 ColorimetryRGB_DP_CustomColorProfile = 5, 123 ColorimetryRGB_DP_ITU_R_BT2020RGB = 6, 124 }; 125 enum ColorimetryYCCDP { 126 ColorimetryYCC_DP_ITU601 = 0, 127 ColorimetryYCC_DP_ITU709 = 1, 128 ColorimetryYCC_DP_AdobeYCC = 5, 129 ColorimetryYCC_DP_ITU2020YCC = 6, 130 ColorimetryYCC_DP_ITU2020YCbCr = 7, 131 }; 132 133 void mod_build_vsc_infopacket(const struct dc_stream_state *stream, 134 struct dc_info_packet *info_packet, 135 enum dc_color_space cs, 136 enum color_transfer_func tf) 137 { 138 unsigned int vsc_packet_revision = vsc_packet_undefined; 139 unsigned int i; 140 unsigned int pixelEncoding = 0; 141 unsigned int colorimetryFormat = 0; 142 bool stereo3dSupport = false; 143 144 if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) { 145 vsc_packet_revision = vsc_packet_rev1; 146 stereo3dSupport = true; 147 } 148 149 /* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */ 150 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 151 vsc_packet_revision = vsc_packet_rev4; 152 else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) 153 vsc_packet_revision = vsc_packet_rev2; 154 155 /* Update to revision 5 for extended colorimetry support */ 156 if (stream->use_vsc_sdp_for_colorimetry) 157 vsc_packet_revision = vsc_packet_rev5; 158 159 /* VSC packet not needed based on the features 160 * supported by this DP display 161 */ 162 if (vsc_packet_revision == vsc_packet_undefined) 163 return; 164 165 if (vsc_packet_revision == vsc_packet_rev4) { 166 /* Secondary-data Packet ID = 0*/ 167 info_packet->hb0 = 0x00; 168 /* 07h - Packet Type Value indicating Video 169 * Stream Configuration packet 170 */ 171 info_packet->hb1 = 0x07; 172 /* 04h = VSC SDP supporting 3D stereo + PSR/PSR2 + Y-coordinate 173 * (applies to eDP v1.4 or higher). 174 */ 175 info_packet->hb2 = 0x04; 176 /* 0Eh = VSC SDP supporting 3D stereo + PSR2 177 * (HB2 = 04h), with Y-coordinate of first scan 178 * line of the SU region 179 */ 180 info_packet->hb3 = 0x0E; 181 182 for (i = 0; i < 28; i++) 183 info_packet->sb[i] = 0; 184 185 info_packet->valid = true; 186 } 187 188 if (vsc_packet_revision == vsc_packet_rev2) { 189 /* Secondary-data Packet ID = 0*/ 190 info_packet->hb0 = 0x00; 191 /* 07h - Packet Type Value indicating Video 192 * Stream Configuration packet 193 */ 194 info_packet->hb1 = 0x07; 195 /* 02h = VSC SDP supporting 3D stereo and PSR 196 * (applies to eDP v1.3 or higher). 197 */ 198 info_packet->hb2 = 0x02; 199 /* 08h = VSC packet supporting 3D stereo + PSR 200 * (HB2 = 02h). 201 */ 202 info_packet->hb3 = 0x08; 203 204 for (i = 0; i < 28; i++) 205 info_packet->sb[i] = 0; 206 207 info_packet->valid = true; 208 } 209 210 if (vsc_packet_revision == vsc_packet_rev1) { 211 212 info_packet->hb0 = 0x00; // Secondary-data Packet ID = 0 213 info_packet->hb1 = 0x07; // 07h = Packet Type Value indicating Video Stream Configuration packet 214 info_packet->hb2 = 0x01; // 01h = Revision number. VSC SDP supporting 3D stereo only 215 info_packet->hb3 = 0x01; // 01h = VSC SDP supporting 3D stereo only (HB2 = 01h). 216 217 info_packet->valid = true; 218 } 219 220 if (stereo3dSupport) { 221 /* ==============================================================================================================| 222 * A. STEREO 3D 223 * ==============================================================================================================| 224 * VSC Payload (1 byte) From DP1.2 spec 225 * 226 * Bits 3:0 (Stereo Interface Method Code) | Bits 7:4 (Stereo Interface Method Specific Parameter) 227 * ----------------------------------------------------------------------------------------------------- 228 * 0 = Non Stereo Video | Must be set to 0x0 229 * ----------------------------------------------------------------------------------------------------- 230 * 1 = Frame/Field Sequential | 0x0: L + R view indication based on MISC1 bit 2:1 231 * | 0x1: Right when Stereo Signal = 1 232 * | 0x2: Left when Stereo Signal = 1 233 * | (others reserved) 234 * ----------------------------------------------------------------------------------------------------- 235 * 2 = Stacked Frame | 0x0: Left view is on top and right view on bottom 236 * | (others reserved) 237 * ----------------------------------------------------------------------------------------------------- 238 * 3 = Pixel Interleaved | 0x0: horiz interleaved, right view pixels on even lines 239 * | 0x1: horiz interleaved, right view pixels on odd lines 240 * | 0x2: checker board, start with left view pixel 241 * | 0x3: vertical interleaved, start with left view pixels 242 * | 0x4: vertical interleaved, start with right view pixels 243 * | (others reserved) 244 * ----------------------------------------------------------------------------------------------------- 245 * 4 = Side-by-side | 0x0: left half represents left eye view 246 * | 0x1: left half represents right eye view 247 */ 248 switch (stream->timing.timing_3d_format) { 249 case TIMING_3D_FORMAT_HW_FRAME_PACKING: 250 case TIMING_3D_FORMAT_SW_FRAME_PACKING: 251 case TIMING_3D_FORMAT_TOP_AND_BOTTOM: 252 case TIMING_3D_FORMAT_TB_SW_PACKED: 253 info_packet->sb[0] = 0x02; // Stacked Frame, Left view is on top and right view on bottom. 254 break; 255 case TIMING_3D_FORMAT_DP_HDMI_INBAND_FA: 256 case TIMING_3D_FORMAT_INBAND_FA: 257 info_packet->sb[0] = 0x01; // Frame/Field Sequential, L + R view indication based on MISC1 bit 2:1 258 break; 259 case TIMING_3D_FORMAT_SIDE_BY_SIDE: 260 case TIMING_3D_FORMAT_SBS_SW_PACKED: 261 info_packet->sb[0] = 0x04; // Side-by-side 262 break; 263 default: 264 info_packet->sb[0] = 0x00; // No Stereo Video, Shall be cleared to 0x0. 265 break; 266 } 267 268 } 269 270 /* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication. 271 * Added in DP1.3, a DP Source device is allowed to indicate the pixel encoding/colorimetry 272 * format to the DP Sink device with VSC SDP only when the DP Sink device supports it 273 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST 274 * register (DPCD Address 02210h, bit 3) is set to 1). 275 * (Requires VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit set to 1 in DPCD 02210h. This 276 * DPCD register is exposed in the new Extended Receiver Capability field for DPCD Rev. 1.4 277 * (and higher). When MISC1. bit 6. is Set to 1, a Source device uses a VSC SDP to indicate 278 * the Pixel Encoding/Colorimetry Format and that a Sink device must ignore MISC1, bit 7, and 279 * MISC0, bits 7:1 (MISC1, bit 7. and MISC0, bits 7:1 become "don't care").) 280 */ 281 if (vsc_packet_revision == vsc_packet_rev5) { 282 /* Secondary-data Packet ID = 0 */ 283 info_packet->hb0 = 0x00; 284 /* 07h - Packet Type Value indicating Video Stream Configuration packet */ 285 info_packet->hb1 = 0x07; 286 /* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication. */ 287 info_packet->hb2 = 0x05; 288 /* 13h = VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/Colorimetry Format indication (HB2 = 05h). */ 289 info_packet->hb3 = 0x13; 290 291 info_packet->valid = true; 292 293 /* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs 294 * Data Bytes DB 18~16 295 * Bits 3:0 (Colorimetry Format) | Bits 7:4 (Pixel Encoding) 296 * ---------------------------------------------------------------------------------------------------- 297 * 0x0 = sRGB | 0 = RGB 298 * 0x1 = RGB Wide Gamut Fixed Point 299 * 0x2 = RGB Wide Gamut Floating Point 300 * 0x3 = AdobeRGB 301 * 0x4 = DCI-P3 302 * 0x5 = CustomColorProfile 303 * (others reserved) 304 * ---------------------------------------------------------------------------------------------------- 305 * 0x0 = ITU-R BT.601 | 1 = YCbCr444 306 * 0x1 = ITU-R BT.709 307 * 0x2 = xvYCC601 308 * 0x3 = xvYCC709 309 * 0x4 = sYCC601 310 * 0x5 = AdobeYCC601 311 * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc 312 * 0x7 = ITU-R BT.2020 Y'C'bC'r 313 * (others reserved) 314 * ---------------------------------------------------------------------------------------------------- 315 * 0x0 = ITU-R BT.601 | 2 = YCbCr422 316 * 0x1 = ITU-R BT.709 317 * 0x2 = xvYCC601 318 * 0x3 = xvYCC709 319 * 0x4 = sYCC601 320 * 0x5 = AdobeYCC601 321 * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc 322 * 0x7 = ITU-R BT.2020 Y'C'bC'r 323 * (others reserved) 324 * ---------------------------------------------------------------------------------------------------- 325 * 0x0 = ITU-R BT.601 | 3 = YCbCr420 326 * 0x1 = ITU-R BT.709 327 * 0x2 = xvYCC601 328 * 0x3 = xvYCC709 329 * 0x4 = sYCC601 330 * 0x5 = AdobeYCC601 331 * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc 332 * 0x7 = ITU-R BT.2020 Y'C'bC'r 333 * (others reserved) 334 * ---------------------------------------------------------------------------------------------------- 335 * 0x0 =DICOM Part14 Grayscale | 4 = Yonly 336 * Display Function 337 * (others reserved) 338 */ 339 340 /* Set Pixel Encoding */ 341 switch (stream->timing.pixel_encoding) { 342 case PIXEL_ENCODING_RGB: 343 pixelEncoding = 0x0; /* RGB = 0h */ 344 break; 345 case PIXEL_ENCODING_YCBCR444: 346 pixelEncoding = 0x1; /* YCbCr444 = 1h */ 347 break; 348 case PIXEL_ENCODING_YCBCR422: 349 pixelEncoding = 0x2; /* YCbCr422 = 2h */ 350 break; 351 case PIXEL_ENCODING_YCBCR420: 352 pixelEncoding = 0x3; /* YCbCr420 = 3h */ 353 break; 354 default: 355 pixelEncoding = 0x0; /* default RGB = 0h */ 356 break; 357 } 358 359 /* Set Colorimetry format based on pixel encoding */ 360 switch (stream->timing.pixel_encoding) { 361 case PIXEL_ENCODING_RGB: 362 if ((cs == COLOR_SPACE_SRGB) || 363 (cs == COLOR_SPACE_SRGB_LIMITED)) 364 colorimetryFormat = ColorimetryRGB_DP_sRGB; 365 else if (cs == COLOR_SPACE_ADOBERGB) 366 colorimetryFormat = ColorimetryRGB_DP_AdobeRGB; 367 else if ((cs == COLOR_SPACE_2020_RGB_FULLRANGE) || 368 (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE)) 369 colorimetryFormat = ColorimetryRGB_DP_ITU_R_BT2020RGB; 370 break; 371 372 case PIXEL_ENCODING_YCBCR444: 373 case PIXEL_ENCODING_YCBCR422: 374 case PIXEL_ENCODING_YCBCR420: 375 /* Note: xvYCC probably not supported correctly here on DP since colorspace translation 376 * loses distinction between BT601 vs xvYCC601 in translation 377 */ 378 if (cs == COLOR_SPACE_YCBCR601) 379 colorimetryFormat = ColorimetryYCC_DP_ITU601; 380 else if (cs == COLOR_SPACE_YCBCR709) 381 colorimetryFormat = ColorimetryYCC_DP_ITU709; 382 else if (cs == COLOR_SPACE_ADOBERGB) 383 colorimetryFormat = ColorimetryYCC_DP_AdobeYCC; 384 else if (cs == COLOR_SPACE_2020_YCBCR) 385 colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr; 386 387 if (cs == COLOR_SPACE_2020_YCBCR && tf == TRANSFER_FUNC_GAMMA_22) 388 colorimetryFormat = ColorimetryYCC_DP_ITU709; 389 break; 390 391 default: 392 colorimetryFormat = ColorimetryRGB_DP_sRGB; 393 break; 394 } 395 396 info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat; 397 398 /* Set color depth */ 399 switch (stream->timing.display_color_depth) { 400 case COLOR_DEPTH_666: 401 /* NOTE: This is actually not valid for YCbCr pixel encoding to have 6 bpc 402 * as of DP1.4 spec, but value of 0 probably reserved here for potential future use. 403 */ 404 info_packet->sb[17] = 0; 405 break; 406 case COLOR_DEPTH_888: 407 info_packet->sb[17] = 1; 408 break; 409 case COLOR_DEPTH_101010: 410 info_packet->sb[17] = 2; 411 break; 412 case COLOR_DEPTH_121212: 413 info_packet->sb[17] = 3; 414 break; 415 /*case COLOR_DEPTH_141414: -- NO SUCH FORMAT IN DP SPEC */ 416 case COLOR_DEPTH_161616: 417 info_packet->sb[17] = 4; 418 break; 419 default: 420 info_packet->sb[17] = 0; 421 break; 422 } 423 424 /* all YCbCr are always limited range */ 425 if ((cs == COLOR_SPACE_SRGB_LIMITED) || 426 (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE) || 427 (pixelEncoding != 0x0)) { 428 info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */ 429 } 430 431 /* Content Type (Bits 2:0) 432 * 0 = Not defined. 433 * 1 = Graphics. 434 * 2 = Photo. 435 * 3 = Video. 436 * 4 = Game. 437 */ 438 info_packet->sb[18] = 0; 439 } 440 } 441 442 /** 443 * mod_build_hf_vsif_infopacket - Prepare HDMI Vendor Specific info frame. 444 * Follows HDMI Spec to build up Vendor Specific info frame 445 * 446 * @stream: contains data we may need to construct VSIF (i.e. timing_3d_format, etc.) 447 * @info_packet: output structure where to store VSIF 448 */ 449 void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, 450 struct dc_info_packet *info_packet) 451 { 452 unsigned int length = 5; 453 bool hdmi_vic_mode = false; 454 uint8_t checksum = 0; 455 uint32_t i = 0; 456 enum dc_timing_3d_format format; 457 458 info_packet->valid = false; 459 format = stream->timing.timing_3d_format; 460 if (stream->view_format == VIEW_3D_FORMAT_NONE) 461 format = TIMING_3D_FORMAT_NONE; 462 463 if (stream->timing.hdmi_vic != 0 464 && stream->timing.h_total >= 3840 465 && stream->timing.v_total >= 2160 466 && format == TIMING_3D_FORMAT_NONE) 467 hdmi_vic_mode = true; 468 469 if ((format == TIMING_3D_FORMAT_NONE) && !hdmi_vic_mode) 470 return; 471 472 info_packet->sb[1] = 0x03; 473 info_packet->sb[2] = 0x0C; 474 info_packet->sb[3] = 0x00; 475 476 if (format != TIMING_3D_FORMAT_NONE) 477 info_packet->sb[4] = (2 << 5); 478 479 else if (hdmi_vic_mode) 480 info_packet->sb[4] = (1 << 5); 481 482 switch (format) { 483 case TIMING_3D_FORMAT_HW_FRAME_PACKING: 484 case TIMING_3D_FORMAT_SW_FRAME_PACKING: 485 info_packet->sb[5] = (0x0 << 4); 486 break; 487 488 case TIMING_3D_FORMAT_SIDE_BY_SIDE: 489 case TIMING_3D_FORMAT_SBS_SW_PACKED: 490 info_packet->sb[5] = (0x8 << 4); 491 length = 6; 492 break; 493 494 case TIMING_3D_FORMAT_TOP_AND_BOTTOM: 495 case TIMING_3D_FORMAT_TB_SW_PACKED: 496 info_packet->sb[5] = (0x6 << 4); 497 break; 498 499 default: 500 break; 501 } 502 503 if (hdmi_vic_mode) 504 info_packet->sb[5] = stream->timing.hdmi_vic; 505 506 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; 507 info_packet->hb1 = 0x01; 508 info_packet->hb2 = (uint8_t) (length); 509 510 checksum += info_packet->hb0; 511 checksum += info_packet->hb1; 512 checksum += info_packet->hb2; 513 514 for (i = 1; i <= length; i++) 515 checksum += info_packet->sb[i]; 516 517 info_packet->sb[0] = (uint8_t) (0x100 - checksum); 518 519 info_packet->valid = true; 520 } 521 522 void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, 523 enum adaptive_sync_type asType, 524 const struct AS_Df_params *param, 525 struct dc_info_packet *info_packet) 526 { 527 info_packet->valid = false; 528 529 memset(info_packet, 0, sizeof(struct dc_info_packet)); 530 531 switch (asType) { 532 case ADAPTIVE_SYNC_TYPE_DP: 533 if (stream != NULL) 534 mod_build_adaptive_sync_infopacket_v2(stream, param, info_packet); 535 break; 536 case FREESYNC_TYPE_PCON_IN_WHITELIST: 537 mod_build_adaptive_sync_infopacket_v1(info_packet); 538 break; 539 case ADAPTIVE_SYNC_TYPE_NONE: 540 case FREESYNC_TYPE_PCON_NOT_IN_WHITELIST: 541 default: 542 break; 543 } 544 } 545 546 void mod_build_adaptive_sync_infopacket_v1(struct dc_info_packet *info_packet) 547 { 548 info_packet->valid = true; 549 // HEADER {HB0, HB1, HB2, HB3} = {00, Type, Version, Length} 550 info_packet->hb0 = 0x00; 551 info_packet->hb1 = 0x22; 552 info_packet->hb2 = AS_SDP_VER_1; 553 info_packet->hb3 = 0x00; 554 } 555 556 void mod_build_adaptive_sync_infopacket_v2(const struct dc_stream_state *stream, 557 const struct AS_Df_params *param, 558 struct dc_info_packet *info_packet) 559 { 560 info_packet->valid = true; 561 // HEADER {HB0, HB1, HB2, HB3} = {00, Type, Version, Length} 562 info_packet->hb0 = 0x00; 563 info_packet->hb1 = 0x22; 564 info_packet->hb2 = AS_SDP_VER_2; 565 info_packet->hb3 = AS_DP_SDP_LENGTH; 566 567 //Payload 568 info_packet->sb[0] = param->supportMode; //1: AVT; 0: FAVT 569 info_packet->sb[1] = (stream->timing.v_total & 0x00FF); 570 info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8; 571 //info_packet->sb[3] = 0x00; Target RR, not use fot AVT 572 info_packet->sb[4] = (param->increase.support << 6 | param->decrease.support << 7); 573 info_packet->sb[5] = param->increase.frame_duration_hex; 574 info_packet->sb[6] = param->decrease.frame_duration_hex; 575 } 576 577