1 /* 2 * BIF_4_1 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef BIF_4_1_SH_MASK_H 25 #define BIF_4_1_SH_MASK_H 26 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 37 #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 38 #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 39 #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 40 #define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 41 #define BUS_CNTL__PMI_IO_DIS_MASK 0x4 42 #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 43 #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 44 #define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 45 #define BUS_CNTL__PMI_BM_DIS_MASK 0x10 46 #define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 47 #define BUS_CNTL__PMI_INT_DIS_MASK 0x20 48 #define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 49 #define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 50 #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 51 #define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 52 #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 53 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 54 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 55 #define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 56 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa 57 #define BUS_CNTL__SET_MC_TC_MASK 0xe000 58 #define BUS_CNTL__SET_MC_TC__SHIFT 0xd 59 #define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 60 #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 61 #define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 62 #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 63 #define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 64 #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 65 #define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 66 #define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 67 #define CONFIG_CNTL__VGA_DIS_MASK 0x2 68 #define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 69 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 70 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 71 #define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 72 #define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 73 #define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff 74 #define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 75 #define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff 76 #define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 77 #define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff 78 #define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 79 #define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff 80 #define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 81 #define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff 82 #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 83 #define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff 84 #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 85 #define BX_RESET_EN__COR_RESET_EN_MASK 0x1 86 #define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 87 #define BX_RESET_EN__REG_RESET_EN_MASK 0x2 88 #define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 89 #define BX_RESET_EN__STY_RESET_EN_MASK 0x4 90 #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 91 #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 92 #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 93 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 94 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 95 #define HW_DEBUG__HW_00_DEBUG_MASK 0x1 96 #define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 97 #define HW_DEBUG__HW_01_DEBUG_MASK 0x2 98 #define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 99 #define HW_DEBUG__HW_02_DEBUG_MASK 0x4 100 #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 101 #define HW_DEBUG__HW_03_DEBUG_MASK 0x8 102 #define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 103 #define HW_DEBUG__HW_04_DEBUG_MASK 0x10 104 #define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 105 #define HW_DEBUG__HW_05_DEBUG_MASK 0x20 106 #define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 107 #define HW_DEBUG__HW_06_DEBUG_MASK 0x40 108 #define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 109 #define HW_DEBUG__HW_07_DEBUG_MASK 0x80 110 #define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 111 #define HW_DEBUG__HW_08_DEBUG_MASK 0x100 112 #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 113 #define HW_DEBUG__HW_09_DEBUG_MASK 0x200 114 #define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 115 #define HW_DEBUG__HW_10_DEBUG_MASK 0x400 116 #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 117 #define HW_DEBUG__HW_11_DEBUG_MASK 0x800 118 #define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 119 #define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 120 #define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 121 #define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 122 #define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 123 #define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 124 #define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 125 #define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 126 #define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 127 #define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 128 #define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 129 #define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 130 #define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 131 #define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 132 #define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 133 #define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 134 #define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 135 #define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 136 #define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 137 #define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 138 #define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 139 #define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 140 #define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 141 #define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 142 #define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 143 #define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 144 #define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 145 #define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 146 #define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 147 #define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 148 #define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a 149 #define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 150 #define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b 151 #define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 152 #define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c 153 #define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 154 #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d 155 #define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 156 #define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e 157 #define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 158 #define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f 159 #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f 160 #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 161 #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 162 #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 163 #define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f 164 #define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 165 #define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 166 #define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 167 #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 168 #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa 169 #define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 170 #define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf 171 #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 172 #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 173 #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 174 #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 175 #define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 176 #define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 177 #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 178 #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 179 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 180 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 181 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 182 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 183 #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 184 #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 185 #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 186 #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 187 #define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 188 #define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 189 #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 190 #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd 191 #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff 192 #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 193 #define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 194 #define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 195 #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 196 #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 197 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 198 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 199 #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 200 #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 201 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 202 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 203 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 204 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 205 #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 206 #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 207 #define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 208 #define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 209 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 210 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 211 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 212 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 213 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 214 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 215 #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 216 #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e 217 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f 218 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 219 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 220 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 221 #define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff 222 #define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 223 #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 224 #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 225 #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 226 #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 227 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 228 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 229 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 230 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 231 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 232 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 233 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 234 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 235 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 236 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 237 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 238 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 239 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 240 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 241 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 242 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 243 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 244 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 245 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 246 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa 247 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 248 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb 249 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 250 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc 251 #define SMBUS_SLV_CNTL__SMB_SOFT_RESET_MASK 0x1 252 #define SMBUS_SLV_CNTL__SMB_SOFT_RESET__SHIFT 0x0 253 #define SMBUS_SLV_CNTL__SMB_SLV_ADR_MASK 0xfe 254 #define SMBUS_SLV_CNTL__SMB_SLV_ADR__SHIFT 0x1 255 #define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD_MASK 0x3fffff 256 #define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD__SHIFT 0x0 257 #define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL_MASK 0x1000000 258 #define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL__SHIFT 0x18 259 #define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS_MASK 0x2000000 260 #define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS__SHIFT 0x19 261 #define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0xfc000000 262 #define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x1a 263 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1 264 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0 265 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2 266 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1 267 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4 268 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2 269 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18 270 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3 271 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20 272 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5 273 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40 274 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6 275 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80 276 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7 277 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100 278 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8 279 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200 280 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9 281 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400 282 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa 283 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800 284 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb 285 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000 286 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc 287 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1 288 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0 289 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2 290 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1 291 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4 292 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2 293 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18 294 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3 295 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20 296 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5 297 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40 298 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6 299 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80 300 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7 301 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100 302 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8 303 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200 304 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9 305 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400 306 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa 307 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800 308 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb 309 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000 310 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc 311 #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff 312 #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 313 #define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 314 #define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f 315 #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff 316 #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 317 #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 318 #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 319 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 320 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 321 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 322 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 323 #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 324 #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 325 #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 326 #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 327 #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 328 #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 329 #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 330 #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 331 #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 332 #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 333 #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 334 #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 335 #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 336 #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 337 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 338 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa 339 #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 340 #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb 341 #define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 342 #define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 343 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 344 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 345 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 346 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 347 #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 348 #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 349 #define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 350 #define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 351 #define BIF_FB_EN__FB_READ_EN_MASK 0x1 352 #define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 353 #define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 354 #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 355 #define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff 356 #define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 357 #define BIF_BUSNUM_LIST0__ID0_MASK 0xff 358 #define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 359 #define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 360 #define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 361 #define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 362 #define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 363 #define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 364 #define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 365 #define BIF_BUSNUM_LIST1__ID4_MASK 0xff 366 #define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 367 #define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 368 #define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 369 #define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 370 #define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 371 #define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 372 #define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 373 #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff 374 #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 375 #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 376 #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 377 #define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 378 #define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 379 #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 380 #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 381 #define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f 382 #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 383 #define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 384 #define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 385 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 386 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 387 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 388 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 389 #define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 390 #define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 391 #define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 392 #define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd 393 #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff 394 #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 395 #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff 396 #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 397 #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe 398 #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 399 #define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 400 #define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 401 #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 402 #define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 403 #define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 404 #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 405 #define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 406 #define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 407 #define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 408 #define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 409 #define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 410 #define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 411 #define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 412 #define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 413 #define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 414 #define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 415 #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 416 #define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 417 #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 418 #define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 419 #define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 420 #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa 421 #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 422 #define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb 423 #define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 424 #define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 425 #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 426 #define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 427 #define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 428 #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 429 #define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 430 #define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 431 #define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 432 #define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 433 #define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 434 #define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 435 #define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 436 #define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 437 #define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 438 #define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 439 #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 440 #define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 441 #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 442 #define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 443 #define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 444 #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa 445 #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 446 #define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb 447 #define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 448 #define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 449 #define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 450 #define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 451 #define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 452 #define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 453 #define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 454 #define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 455 #define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 456 #define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 457 #define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 458 #define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 459 #define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 460 #define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 461 #define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 462 #define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 463 #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 464 #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 465 #define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 466 #define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 467 #define HOST_BUSNUM__HOST_ID_MASK 0xffff 468 #define HOST_BUSNUM__HOST_ID__SHIFT 0x0 469 #define PEER_REG_RANGE0__START_ADDR_MASK 0xffff 470 #define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 471 #define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 472 #define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 473 #define PEER_REG_RANGE1__START_ADDR_MASK 0xffff 474 #define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 475 #define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 476 #define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 477 #define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff 478 #define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 479 #define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff 480 #define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 481 #define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 482 #define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f 483 #define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff 484 #define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 485 #define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff 486 #define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 487 #define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 488 #define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f 489 #define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff 490 #define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 491 #define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff 492 #define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 493 #define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 494 #define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f 495 #define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff 496 #define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 497 #define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff 498 #define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 499 #define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 500 #define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f 501 #define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1 502 #define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0 503 #define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e 504 #define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1 505 #define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff 506 #define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0 507 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff 508 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 509 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 510 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 511 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 512 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 513 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 514 #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 515 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff 516 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 517 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 518 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 519 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 520 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 521 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 522 #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 523 #define BACO_CNTL__BACO_EN_MASK 0x1 524 #define BACO_CNTL__BACO_EN__SHIFT 0x0 525 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 526 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 527 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 528 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 529 #define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 530 #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 531 #define BACO_CNTL__BACO_RESET_EN_MASK 0x10 532 #define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 533 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 534 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 535 #define BACO_CNTL__BACO_MODE_MASK 0x40 536 #define BACO_CNTL__BACO_MODE__SHIFT 0x6 537 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 538 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 539 #define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 540 #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 541 #define BACO_CNTL__PWRGOOD_BF_MASK 0x200 542 #define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 543 #define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 544 #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa 545 #define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 546 #define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb 547 #define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 548 #define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc 549 #define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 550 #define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd 551 #define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 552 #define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 553 #define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 554 #define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 555 #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 556 #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 557 #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 558 #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 559 #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 560 #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 561 #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 562 #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 563 #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 564 #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 565 #define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 566 #define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 567 #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 568 #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 569 #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc 570 #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 571 #define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x1 572 #define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x0 573 #define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x2 574 #define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x1 575 #define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x4 576 #define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x2 577 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x3fffc 578 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x2 579 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000 580 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x1e 581 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000 582 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x1f 583 #define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x3fffc 584 #define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x2 585 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x3fffc 586 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x2 587 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000 588 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x1e 589 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000 590 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x1f 591 #define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x3fffc 592 #define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x2 593 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x3fffc 594 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x2 595 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000 596 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x1e 597 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000 598 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x1f 599 #define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x3fffc 600 #define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x2 601 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x3fffc 602 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x2 603 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000 604 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x1e 605 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000 606 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x1f 607 #define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x3fffc 608 #define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x2 609 #define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x3fffc 610 #define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x2 611 #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000 612 #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x1e 613 #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000 614 #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x1f 615 #define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x3fffc 616 #define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x2 617 #define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x3fffc 618 #define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x2 619 #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000 620 #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d 621 #define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000 622 #define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x1e 623 #define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000 624 #define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x1f 625 #define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x3fffc 626 #define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x2 627 #define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 628 #define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 629 #define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 630 #define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 631 #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 632 #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 633 #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 634 #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 635 #define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 636 #define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 637 #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 638 #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 639 #define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 640 #define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 641 #define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 642 #define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 643 #define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 644 #define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 645 #define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 646 #define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 647 #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 648 #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 649 #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 650 #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa 651 #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 652 #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb 653 #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 654 #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc 655 #define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 656 #define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd 657 #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 658 #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe 659 #define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 660 #define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 661 #define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 662 #define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e 663 #define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 664 #define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f 665 #define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 666 #define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 667 #define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 668 #define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 669 #define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc 670 #define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 671 #define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 672 #define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 673 #define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 674 #define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 675 #define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc 676 #define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 677 #define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 678 #define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 679 #define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 680 #define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 681 #define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc 682 #define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 683 #define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 684 #define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 685 #define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 686 #define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 687 #define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc 688 #define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 689 #define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 690 #define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 691 #define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 692 #define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 693 #define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc 694 #define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 695 #define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 696 #define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 697 #define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 698 #define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 699 #define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc 700 #define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 701 #define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 702 #define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 703 #define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 704 #define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 705 #define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc 706 #define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 707 #define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 708 #define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 709 #define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 710 #define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 711 #define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc 712 #define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 713 #define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc 714 #define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 715 #define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc 716 #define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 717 #define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc 718 #define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 719 #define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc 720 #define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 721 #define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc 722 #define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 723 #define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc 724 #define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 725 #define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc 726 #define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 727 #define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc 728 #define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 729 #define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 730 #define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 731 #define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 732 #define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 733 #define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 734 #define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 735 #define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 736 #define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 737 #define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 738 #define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 739 #define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 740 #define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 741 #define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 742 #define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 743 #define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 744 #define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 745 #define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 746 #define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 747 #define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 748 #define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 749 #define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 750 #define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 751 #define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 752 #define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa 753 #define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 754 #define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb 755 #define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 756 #define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 757 #define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 758 #define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 759 #define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 760 #define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 761 #define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 762 #define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 763 #define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 764 #define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 765 #define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 766 #define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 767 #define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 768 #define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 769 #define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 770 #define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 771 #define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 772 #define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 773 #define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 774 #define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 775 #define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 776 #define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa 777 #define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 778 #define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb 779 #define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc 780 #define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2 781 #define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc 782 #define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2 783 #define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc 784 #define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2 785 #define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc 786 #define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2 787 #define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc 788 #define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 789 #define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc 790 #define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 791 #define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc 792 #define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2 793 #define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc 794 #define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2 795 #define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc 796 #define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2 797 #define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc 798 #define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2 799 #define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc 800 #define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2 801 #define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc 802 #define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2 803 #define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc 804 #define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2 805 #define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff 806 #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 807 #define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff 808 #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 809 #define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff 810 #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 811 #define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff 812 #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 813 #define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff 814 #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 815 #define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff 816 #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 817 #define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff 818 #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 819 #define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff 820 #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 821 #define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff 822 #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 823 #define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff 824 #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 825 #define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff 826 #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 827 #define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff 828 #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 829 #define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff 830 #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 831 #define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff 832 #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 833 #define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff 834 #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 835 #define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff 836 #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 837 #define VENDOR_ID__VENDOR_ID_MASK 0xffff 838 #define VENDOR_ID__VENDOR_ID__SHIFT 0x0 839 #define DEVICE_ID__DEVICE_ID_MASK 0xffff 840 #define DEVICE_ID__DEVICE_ID__SHIFT 0x0 841 #define COMMAND__IO_ACCESS_EN_MASK 0x1 842 #define COMMAND__IO_ACCESS_EN__SHIFT 0x0 843 #define COMMAND__MEM_ACCESS_EN_MASK 0x2 844 #define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 845 #define COMMAND__BUS_MASTER_EN_MASK 0x4 846 #define COMMAND__BUS_MASTER_EN__SHIFT 0x2 847 #define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 848 #define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 849 #define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 850 #define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 851 #define COMMAND__PAL_SNOOP_EN_MASK 0x20 852 #define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 853 #define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 854 #define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 855 #define COMMAND__AD_STEPPING_MASK 0x80 856 #define COMMAND__AD_STEPPING__SHIFT 0x7 857 #define COMMAND__SERR_EN_MASK 0x100 858 #define COMMAND__SERR_EN__SHIFT 0x8 859 #define COMMAND__FAST_B2B_EN_MASK 0x200 860 #define COMMAND__FAST_B2B_EN__SHIFT 0x9 861 #define COMMAND__INT_DIS_MASK 0x400 862 #define COMMAND__INT_DIS__SHIFT 0xa 863 #define STATUS__INT_STATUS_MASK 0x8 864 #define STATUS__INT_STATUS__SHIFT 0x3 865 #define STATUS__CAP_LIST_MASK 0x10 866 #define STATUS__CAP_LIST__SHIFT 0x4 867 #define STATUS__PCI_66_EN_MASK 0x20 868 #define STATUS__PCI_66_EN__SHIFT 0x5 869 #define STATUS__FAST_BACK_CAPABLE_MASK 0x80 870 #define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 871 #define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 872 #define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 873 #define STATUS__DEVSEL_TIMING_MASK 0x600 874 #define STATUS__DEVSEL_TIMING__SHIFT 0x9 875 #define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 876 #define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb 877 #define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 878 #define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc 879 #define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 880 #define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd 881 #define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 882 #define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe 883 #define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 884 #define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf 885 #define REVISION_ID__MINOR_REV_ID_MASK 0xf 886 #define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 887 #define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 888 #define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 889 #define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff 890 #define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 891 #define SUB_CLASS__SUB_CLASS_MASK 0xff 892 #define SUB_CLASS__SUB_CLASS__SHIFT 0x0 893 #define BASE_CLASS__BASE_CLASS_MASK 0xff 894 #define BASE_CLASS__BASE_CLASS__SHIFT 0x0 895 #define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff 896 #define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 897 #define LATENCY__LATENCY_TIMER_MASK 0xff 898 #define LATENCY__LATENCY_TIMER__SHIFT 0x0 899 #define HEADER__HEADER_TYPE_MASK 0x7f 900 #define HEADER__HEADER_TYPE__SHIFT 0x0 901 #define HEADER__DEVICE_TYPE_MASK 0x80 902 #define HEADER__DEVICE_TYPE__SHIFT 0x7 903 #define BIST__BIST_COMP_MASK 0xf 904 #define BIST__BIST_COMP__SHIFT 0x0 905 #define BIST__BIST_STRT_MASK 0x40 906 #define BIST__BIST_STRT__SHIFT 0x6 907 #define BIST__BIST_CAP_MASK 0x80 908 #define BIST__BIST_CAP__SHIFT 0x7 909 #define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff 910 #define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 911 #define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff 912 #define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 913 #define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff 914 #define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 915 #define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff 916 #define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 917 #define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff 918 #define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 919 #define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff 920 #define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 921 #define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff 922 #define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 923 #define CAP_PTR__CAP_PTR_MASK 0xff 924 #define CAP_PTR__CAP_PTR__SHIFT 0x0 925 #define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff 926 #define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 927 #define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff 928 #define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 929 #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff 930 #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 931 #define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 932 #define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 933 #define MIN_GRANT__MIN_GNT_MASK 0xff 934 #define MIN_GRANT__MIN_GNT__SHIFT 0x0 935 #define MAX_LATENCY__MAX_LAT_MASK 0xff 936 #define MAX_LATENCY__MAX_LAT__SHIFT 0x0 937 #define VENDOR_CAP_LIST__CAP_ID_MASK 0xff 938 #define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 939 #define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 940 #define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 941 #define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 942 #define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 943 #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff 944 #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 945 #define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 946 #define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 947 #define PMI_CAP_LIST__CAP_ID_MASK 0xff 948 #define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 949 #define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 950 #define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 951 #define PMI_CAP__VERSION_MASK 0x7 952 #define PMI_CAP__VERSION__SHIFT 0x0 953 #define PMI_CAP__PME_CLOCK_MASK 0x8 954 #define PMI_CAP__PME_CLOCK__SHIFT 0x3 955 #define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 956 #define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 957 #define PMI_CAP__AUX_CURRENT_MASK 0x1c0 958 #define PMI_CAP__AUX_CURRENT__SHIFT 0x6 959 #define PMI_CAP__D1_SUPPORT_MASK 0x200 960 #define PMI_CAP__D1_SUPPORT__SHIFT 0x9 961 #define PMI_CAP__D2_SUPPORT_MASK 0x400 962 #define PMI_CAP__D2_SUPPORT__SHIFT 0xa 963 #define PMI_CAP__PME_SUPPORT_MASK 0xf800 964 #define PMI_CAP__PME_SUPPORT__SHIFT 0xb 965 #define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 966 #define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 967 #define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 968 #define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 969 #define PMI_STATUS_CNTL__PME_EN_MASK 0x100 970 #define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 971 #define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 972 #define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 973 #define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 974 #define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd 975 #define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 976 #define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf 977 #define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 978 #define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 979 #define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 980 #define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 981 #define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 982 #define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 983 #define PCIE_CAP_LIST__CAP_ID_MASK 0xff 984 #define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 985 #define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 986 #define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 987 #define PCIE_CAP__VERSION_MASK 0xf 988 #define PCIE_CAP__VERSION__SHIFT 0x0 989 #define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 990 #define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 991 #define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 992 #define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 993 #define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 994 #define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 995 #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 996 #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 997 #define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 998 #define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 999 #define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 1000 #define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 1001 #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 1002 #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 1003 #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 1004 #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 1005 #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 1006 #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf 1007 #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 1008 #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 1009 #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 1010 #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a 1011 #define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 1012 #define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c 1013 #define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 1014 #define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 1015 #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 1016 #define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 1017 #define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 1018 #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 1019 #define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 1020 #define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 1021 #define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 1022 #define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 1023 #define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 1024 #define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 1025 #define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 1026 #define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 1027 #define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 1028 #define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 1029 #define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 1030 #define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 1031 #define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 1032 #define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb 1033 #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 1034 #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc 1035 #define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 1036 #define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf 1037 #define DEVICE_STATUS__CORR_ERR_MASK 0x1 1038 #define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 1039 #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 1040 #define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 1041 #define DEVICE_STATUS__FATAL_ERR_MASK 0x4 1042 #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 1043 #define DEVICE_STATUS__USR_DETECTED_MASK 0x8 1044 #define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 1045 #define DEVICE_STATUS__AUX_PWR_MASK 0x10 1046 #define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 1047 #define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 1048 #define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 1049 #define LINK_CAP__LINK_SPEED_MASK 0xf 1050 #define LINK_CAP__LINK_SPEED__SHIFT 0x0 1051 #define LINK_CAP__LINK_WIDTH_MASK 0x3f0 1052 #define LINK_CAP__LINK_WIDTH__SHIFT 0x4 1053 #define LINK_CAP__PM_SUPPORT_MASK 0xc00 1054 #define LINK_CAP__PM_SUPPORT__SHIFT 0xa 1055 #define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 1056 #define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc 1057 #define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 1058 #define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf 1059 #define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 1060 #define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 1061 #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 1062 #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 1063 #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 1064 #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 1065 #define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 1066 #define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 1067 #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 1068 #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 1069 #define LINK_CAP__PORT_NUMBER_MASK 0xff000000 1070 #define LINK_CAP__PORT_NUMBER__SHIFT 0x18 1071 #define LINK_CNTL__PM_CONTROL_MASK 0x3 1072 #define LINK_CNTL__PM_CONTROL__SHIFT 0x0 1073 #define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 1074 #define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 1075 #define LINK_CNTL__LINK_DIS_MASK 0x10 1076 #define LINK_CNTL__LINK_DIS__SHIFT 0x4 1077 #define LINK_CNTL__RETRAIN_LINK_MASK 0x20 1078 #define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 1079 #define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 1080 #define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 1081 #define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 1082 #define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 1083 #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 1084 #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 1085 #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 1086 #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 1087 #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 1088 #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa 1089 #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 1090 #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb 1091 #define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf 1092 #define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 1093 #define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 1094 #define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 1095 #define LINK_STATUS__LINK_TRAINING_MASK 0x800 1096 #define LINK_STATUS__LINK_TRAINING__SHIFT 0xb 1097 #define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 1098 #define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc 1099 #define LINK_STATUS__DL_ACTIVE_MASK 0x2000 1100 #define LINK_STATUS__DL_ACTIVE__SHIFT 0xd 1101 #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 1102 #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe 1103 #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 1104 #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf 1105 #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf 1106 #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 1107 #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 1108 #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 1109 #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 1110 #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 1111 #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 1112 #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 1113 #define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 1114 #define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb 1115 #define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 1116 #define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc 1117 #define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 1118 #define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 1119 #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 1120 #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 1121 #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 1122 #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 1123 #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 1124 #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 1125 #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf 1126 #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 1127 #define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 1128 #define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 1129 #define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 1130 #define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 1131 #define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 1132 #define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 1133 #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 1134 #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 1135 #define DEVICE_CNTL2__LTR_EN_MASK 0x400 1136 #define DEVICE_CNTL2__LTR_EN__SHIFT 0xa 1137 #define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 1138 #define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd 1139 #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 1140 #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf 1141 #define DEVICE_STATUS2__RESERVED_MASK 0xffff 1142 #define DEVICE_STATUS2__RESERVED__SHIFT 0x0 1143 #define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe 1144 #define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 1145 #define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 1146 #define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 1147 #define LINK_CAP2__RESERVED_MASK 0xfffffe00 1148 #define LINK_CAP2__RESERVED__SHIFT 0x9 1149 #define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf 1150 #define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 1151 #define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 1152 #define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 1153 #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 1154 #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 1155 #define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 1156 #define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 1157 #define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 1158 #define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 1159 #define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 1160 #define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa 1161 #define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 1162 #define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb 1163 #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 1164 #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc 1165 #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 1166 #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 1167 #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 1168 #define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 1169 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 1170 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 1171 #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 1172 #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 1173 #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 1174 #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 1175 #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 1176 #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 1177 #define MSI_CAP_LIST__CAP_ID_MASK 0xff 1178 #define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 1179 #define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 1180 #define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 1181 #define MSI_MSG_CNTL__MSI_EN_MASK 0x1 1182 #define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 1183 #define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe 1184 #define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 1185 #define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 1186 #define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 1187 #define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 1188 #define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 1189 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc 1190 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 1191 #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff 1192 #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 1193 #define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff 1194 #define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 1195 #define MSI_MSG_DATA__MSI_DATA_MASK 0xffff 1196 #define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 1197 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1198 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1199 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1200 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1201 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1202 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1203 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff 1204 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 1205 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 1206 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 1207 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 1208 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 1209 #define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff 1210 #define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 1211 #define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff 1212 #define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 1213 #define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1214 #define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1215 #define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1216 #define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1217 #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1218 #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1219 #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 1220 #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 1221 #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 1222 #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 1223 #define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 1224 #define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 1225 #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 1226 #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa 1227 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff 1228 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 1229 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 1230 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 1231 #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 1232 #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 1233 #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe 1234 #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 1235 #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 1236 #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 1237 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff 1238 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 1239 #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 1240 #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 1241 #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 1242 #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 1243 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 1244 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 1245 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 1246 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 1247 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe 1248 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 1249 #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 1250 #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 1251 #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 1252 #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 1253 #define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 1254 #define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 1255 #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 1256 #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 1257 #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 1258 #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 1259 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 1260 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 1261 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff 1262 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 1263 #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 1264 #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 1265 #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 1266 #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 1267 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 1268 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 1269 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 1270 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 1271 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe 1272 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 1273 #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 1274 #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 1275 #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 1276 #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 1277 #define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 1278 #define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 1279 #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 1280 #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 1281 #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 1282 #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 1283 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 1284 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 1285 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1286 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1287 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1288 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1289 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1290 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1291 #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff 1292 #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 1293 #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff 1294 #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 1295 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1296 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1297 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1298 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1299 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1300 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1301 #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 1302 #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 1303 #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 1304 #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 1305 #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 1306 #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc 1307 #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 1308 #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd 1309 #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 1310 #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe 1311 #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 1312 #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf 1313 #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 1314 #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 1315 #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 1316 #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 1317 #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 1318 #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 1319 #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 1320 #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 1321 #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 1322 #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 1323 #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 1324 #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 1325 #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 1326 #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 1327 #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 1328 #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 1329 #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 1330 #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 1331 #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 1332 #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 1333 #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 1334 #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 1335 #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 1336 #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 1337 #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 1338 #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc 1339 #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 1340 #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd 1341 #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 1342 #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe 1343 #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 1344 #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf 1345 #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 1346 #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 1347 #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 1348 #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 1349 #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 1350 #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 1351 #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 1352 #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 1353 #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 1354 #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 1355 #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 1356 #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 1357 #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 1358 #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 1359 #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 1360 #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 1361 #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 1362 #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 1363 #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 1364 #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 1365 #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 1366 #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 1367 #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 1368 #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 1369 #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 1370 #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc 1371 #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 1372 #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd 1373 #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 1374 #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe 1375 #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 1376 #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf 1377 #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 1378 #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 1379 #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 1380 #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 1381 #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 1382 #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 1383 #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 1384 #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 1385 #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 1386 #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 1387 #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 1388 #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 1389 #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 1390 #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 1391 #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 1392 #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 1393 #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 1394 #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 1395 #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 1396 #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 1397 #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 1398 #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 1399 #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 1400 #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 1401 #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 1402 #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 1403 #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 1404 #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 1405 #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 1406 #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc 1407 #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 1408 #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd 1409 #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 1410 #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe 1411 #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 1412 #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf 1413 #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 1414 #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 1415 #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 1416 #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 1417 #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 1418 #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 1419 #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 1420 #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 1421 #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 1422 #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc 1423 #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 1424 #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd 1425 #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 1426 #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe 1427 #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 1428 #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf 1429 #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f 1430 #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 1431 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 1432 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 1433 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 1434 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 1435 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 1436 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 1437 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 1438 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 1439 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 1440 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 1441 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 1442 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa 1443 #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 1444 #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb 1445 #define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff 1446 #define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 1447 #define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff 1448 #define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 1449 #define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff 1450 #define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 1451 #define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff 1452 #define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 1453 #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff 1454 #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 1455 #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff 1456 #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 1457 #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff 1458 #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 1459 #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff 1460 #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 1461 #define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1462 #define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1463 #define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1464 #define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1465 #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1466 #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1467 #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1468 #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1469 #define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 1470 #define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 1471 #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1472 #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1473 #define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 1474 #define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 1475 #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1476 #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1477 #define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 1478 #define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 1479 #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1480 #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1481 #define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 1482 #define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 1483 #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1484 #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1485 #define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 1486 #define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 1487 #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1488 #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1489 #define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 1490 #define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 1491 #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1492 #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1493 #define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 1494 #define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 1495 #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1496 #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1497 #define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 1498 #define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 1499 #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1500 #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1501 #define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 1502 #define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 1503 #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1504 #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1505 #define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 1506 #define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 1507 #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1508 #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1509 #define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 1510 #define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 1511 #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1512 #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1513 #define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 1514 #define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 1515 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1516 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1517 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1518 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1519 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1520 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1521 #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff 1522 #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 1523 #define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff 1524 #define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 1525 #define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 1526 #define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 1527 #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 1528 #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa 1529 #define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 1530 #define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd 1531 #define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 1532 #define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf 1533 #define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 1534 #define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 1535 #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 1536 #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 1537 #define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1538 #define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1539 #define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1540 #define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1541 #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1542 #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1543 #define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f 1544 #define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 1545 #define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 1546 #define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 1547 #define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 1548 #define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 1549 #define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 1550 #define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 1551 #define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 1552 #define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 1553 #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff 1554 #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 1555 #define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f 1556 #define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 1557 #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 1558 #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 1559 #define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f 1560 #define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 1561 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff 1562 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1563 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff 1564 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1565 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff 1566 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1567 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff 1568 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1569 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff 1570 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1571 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff 1572 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1573 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff 1574 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1575 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff 1576 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1577 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1578 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1579 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1580 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1581 #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1582 #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1583 #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 1584 #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 1585 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 1586 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 1587 #define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc 1588 #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 1589 #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff 1590 #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 1591 #define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 1592 #define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 1593 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1594 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1595 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1596 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1597 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1598 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1599 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1600 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1601 #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1602 #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1603 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1604 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1605 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1606 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1607 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1608 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1609 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1610 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1611 #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1612 #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1613 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1614 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1615 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1616 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1617 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1618 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1619 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1620 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1621 #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1622 #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1623 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1624 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1625 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1626 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1627 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1628 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1629 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1630 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1631 #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1632 #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1633 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1634 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1635 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1636 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1637 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1638 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1639 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1640 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1641 #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1642 #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1643 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1644 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1645 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1646 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1647 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1648 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1649 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1650 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1651 #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1652 #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1653 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1654 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1655 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1656 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1657 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1658 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1659 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1660 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1661 #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1662 #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1663 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1664 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1665 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1666 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1667 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1668 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1669 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1670 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1671 #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1672 #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1673 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1674 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1675 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1676 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1677 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1678 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1679 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1680 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1681 #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1682 #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1683 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1684 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1685 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1686 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1687 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1688 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1689 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1690 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1691 #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1692 #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1693 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1694 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1695 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1696 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1697 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1698 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1699 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1700 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1701 #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1702 #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1703 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1704 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1705 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1706 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1707 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1708 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1709 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1710 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1711 #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1712 #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1713 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1714 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1715 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1716 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1717 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1718 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1719 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1720 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1721 #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1722 #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1723 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1724 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1725 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1726 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1727 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1728 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1729 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1730 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1731 #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1732 #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1733 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1734 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1735 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1736 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1737 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1738 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1739 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1740 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1741 #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1742 #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1743 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1744 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1745 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1746 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1747 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1748 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1749 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1750 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1751 #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1752 #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1753 #define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1754 #define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1755 #define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1756 #define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1757 #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1758 #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1759 #define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 1760 #define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 1761 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 1762 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 1763 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 1764 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 1765 #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 1766 #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 1767 #define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 1768 #define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 1769 #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 1770 #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 1771 #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 1772 #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 1773 #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 1774 #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 1775 #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 1776 #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 1777 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 1778 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 1779 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 1780 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 1781 #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 1782 #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 1783 #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 1784 #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 1785 #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 1786 #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 1787 #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 1788 #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 1789 #define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1790 #define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1791 #define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1792 #define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1793 #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1794 #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1795 #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f 1796 #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 1797 #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 1798 #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 1799 #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 1800 #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 1801 #define PCIE_ATS_CNTL__STU_MASK 0x1f 1802 #define PCIE_ATS_CNTL__STU__SHIFT 0x0 1803 #define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 1804 #define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf 1805 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1806 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1807 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1808 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1809 #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1810 #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1811 #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 1812 #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 1813 #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 1814 #define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 1815 #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 1816 #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 1817 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 1818 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 1819 #define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 1820 #define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 1821 #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 1822 #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf 1823 #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff 1824 #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 1825 #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff 1826 #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 1827 #define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1828 #define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1829 #define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1830 #define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1831 #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1832 #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1833 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 1834 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 1835 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 1836 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 1837 #define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 1838 #define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 1839 #define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 1840 #define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 1841 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 1842 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 1843 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 1844 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 1845 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1846 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1847 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1848 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1849 #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1850 #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1851 #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 1852 #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 1853 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 1854 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 1855 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 1856 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 1857 #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 1858 #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 1859 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 1860 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 1861 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 1862 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 1863 #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 1864 #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 1865 #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 1866 #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 1867 #define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1868 #define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1869 #define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1870 #define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1871 #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1872 #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1873 #define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f 1874 #define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 1875 #define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 1876 #define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 1877 #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 1878 #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf 1879 #define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f 1880 #define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 1881 #define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 1882 #define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf 1883 #define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f 1884 #define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 1885 #define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 1886 #define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc 1887 #define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff 1888 #define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 1889 #define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff 1890 #define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 1891 #define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff 1892 #define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 1893 #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff 1894 #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 1895 #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff 1896 #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 1897 #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff 1898 #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 1899 #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff 1900 #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 1901 #define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1902 #define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1903 #define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1904 #define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1905 #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1906 #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1907 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff 1908 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 1909 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 1910 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa 1911 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 1912 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 1913 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 1914 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a 1915 #define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff 1916 #define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 1917 #define PCIE_DATA__PCIE_DATA_MASK 0xffffffff 1918 #define PCIE_DATA__PCIE_DATA__SHIFT 0x0 1919 #define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff 1920 #define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 1921 #define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff 1922 #define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 1923 #define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff 1924 #define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 1925 #define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff 1926 #define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 1927 #define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 1928 #define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 1929 #define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 1930 #define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 1931 #define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 1932 #define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 1933 #define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 1934 #define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 1935 #define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 1936 #define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 1937 #define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 1938 #define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 1939 #define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 1940 #define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 1941 #define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 1942 #define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 1943 #define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 1944 #define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 1945 #define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 1946 #define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 1947 #define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 1948 #define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 1949 #define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 1950 #define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 1951 #define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 1952 #define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 1953 #define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 1954 #define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 1955 #define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 1956 #define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 1957 #define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 1958 #define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 1959 #define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff 1960 #define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 1961 #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff 1962 #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 1963 #define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 1964 #define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 1965 #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe 1966 #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 1967 #define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 1968 #define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 1969 #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 1970 #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 1971 #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 1972 #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 1973 #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 1974 #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa 1975 #define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 1976 #define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf 1977 #define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 1978 #define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 1979 #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 1980 #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 1981 #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 1982 #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 1983 #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 1984 #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 1985 #define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000 1986 #define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14 1987 #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 1988 #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 1989 #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 1990 #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 1991 #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 1992 #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 1993 #define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 1994 #define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 1995 #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 1996 #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e 1997 #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 1998 #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f 1999 #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf 2000 #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 2001 #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 2002 #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 2003 #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 2004 #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 2005 #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 2006 #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 2007 #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 2008 #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 2009 #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 2010 #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 2011 #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 2012 #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 2013 #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff 2014 #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 2015 #define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 2016 #define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 2017 #define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 2018 #define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 2019 #define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 2020 #define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 2021 #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 2022 #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 2023 #define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 2024 #define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 2025 #define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 2026 #define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 2027 #define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 2028 #define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 2029 #define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 2030 #define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 2031 #define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 2032 #define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 2033 #define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 2034 #define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 2035 #define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 2036 #define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 2037 #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 2038 #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 2039 #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 2040 #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 2041 #define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 2042 #define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 2043 #define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 2044 #define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 2045 #define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 2046 #define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 2047 #define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 2048 #define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 2049 #define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 2050 #define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 2051 #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 2052 #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 2053 #define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e 2054 #define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 2055 #define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 2056 #define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 2057 #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 2058 #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb 2059 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 2060 #define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 2061 #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 2062 #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 2063 #define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 2064 #define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 2065 #define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 2066 #define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 2067 #define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 2068 #define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 2069 #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 2070 #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 2071 #define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 2072 #define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 2073 #define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 2074 #define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 2075 #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 2076 #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 2077 #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 2078 #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 2079 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 2080 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 2081 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 2082 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 2083 #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 2084 #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 2085 #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 2086 #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 2087 #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 2088 #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 2089 #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 2090 #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 2091 #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 2092 #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 2093 #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 2094 #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 2095 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 2096 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 2097 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc 2098 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 2099 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 2100 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 2101 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 2102 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 2103 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 2104 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 2105 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 2106 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa 2107 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 2108 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc 2109 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 2110 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 2111 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc 2112 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 2113 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 2114 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 2115 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 2116 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 2117 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 2118 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 2119 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 2120 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa 2121 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 2122 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc 2123 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 2124 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 2125 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 2126 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 2127 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 2128 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 2129 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 2130 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 2131 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 2132 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 2133 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 2134 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a 2135 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 2136 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c 2137 #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 2138 #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 2139 #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 2140 #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 2141 #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 2142 #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 2143 #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 2144 #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 2145 #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 2146 #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 2147 #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 2148 #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 2149 #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 2150 #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa 2151 #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 2152 #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb 2153 #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 2154 #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc 2155 #define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 2156 #define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd 2157 #define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 2158 #define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 2159 #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 2160 #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 2161 #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 2162 #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc 2163 #define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f 2164 #define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 2165 #define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 2166 #define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 2167 #define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 2168 #define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 2169 #define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 2170 #define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 2171 #define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f 2172 #define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 2173 #define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 2174 #define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 2175 #define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 2176 #define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 2177 #define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 2178 #define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 2179 #define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f 2180 #define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 2181 #define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 2182 #define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 2183 #define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 2184 #define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 2185 #define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 2186 #define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 2187 #define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f 2188 #define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 2189 #define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 2190 #define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 2191 #define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 2192 #define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 2193 #define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 2194 #define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 2195 #define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f 2196 #define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 2197 #define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 2198 #define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 2199 #define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 2200 #define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 2201 #define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 2202 #define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 2203 #define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f 2204 #define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 2205 #define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 2206 #define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 2207 #define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 2208 #define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 2209 #define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 2210 #define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 2211 #define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 2212 #define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 2213 #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 2214 #define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 2215 #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c 2216 #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 2217 #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 2218 #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 2219 #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff 2220 #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 2221 #define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 2222 #define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 2223 #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 2224 #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 2225 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 2226 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 2227 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 2228 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 2229 #define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 2230 #define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 2231 #define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 2232 #define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 2233 #define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 2234 #define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 2235 #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 2236 #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 2237 #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff 2238 #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 2239 #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff 2240 #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 2241 #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff 2242 #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 2243 #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff 2244 #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 2245 #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff 2246 #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 2247 #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff 2248 #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 2249 #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff 2250 #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 2251 #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff 2252 #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 2253 #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff 2254 #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 2255 #define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff 2256 #define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 2257 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 2258 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 2259 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 2260 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 2261 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 2262 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 2263 #define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 2264 #define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 2265 #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 2266 #define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 2267 #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 2268 #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 2269 #define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 2270 #define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 2271 #define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 2272 #define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 2273 #define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 2274 #define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 2275 #define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 2276 #define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 2277 #define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 2278 #define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 2279 #define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 2280 #define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 2281 #define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 2282 #define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc 2283 #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 2284 #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd 2285 #define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 2286 #define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe 2287 #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 2288 #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 2289 #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff 2290 #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 2291 #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 2292 #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 2293 #define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff 2294 #define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 2295 #define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff 2296 #define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 2297 #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 2298 #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 2299 #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff 2300 #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 2301 #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 2302 #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 2303 #define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 2304 #define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 2305 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 2306 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 2307 #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 2308 #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 2309 #define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 2310 #define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 2311 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 2312 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 2313 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 2314 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 2315 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 2316 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc 2317 #define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 2318 #define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 2319 #define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 2320 #define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 2321 #define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 2322 #define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 2323 #define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 2324 #define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 2325 #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 2326 #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 2327 #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 2328 #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 2329 #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 2330 #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 2331 #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 2332 #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 2333 #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 2334 #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa 2335 #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 2336 #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd 2337 #define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 2338 #define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe 2339 #define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 2340 #define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf 2341 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 2342 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 2343 #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 2344 #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 2345 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 2346 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 2347 #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff 2348 #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 2349 #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 2350 #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 2351 #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 2352 #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 2353 #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 2354 #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 2355 #define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff 2356 #define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 2357 #define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff 2358 #define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 2359 #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff 2360 #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 2361 #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 2362 #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 2363 #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 2364 #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 2365 #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 2366 #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 2367 #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff 2368 #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 2369 #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff 2370 #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 2371 #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff 2372 #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 2373 #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 2374 #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 2375 #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 2376 #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 2377 #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 2378 #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 2379 #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff 2380 #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 2381 #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff 2382 #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 2383 #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff 2384 #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 2385 #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 2386 #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 2387 #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 2388 #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 2389 #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 2390 #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 2391 #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff 2392 #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 2393 #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff 2394 #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 2395 #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff 2396 #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 2397 #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 2398 #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 2399 #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 2400 #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 2401 #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 2402 #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 2403 #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff 2404 #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 2405 #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff 2406 #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 2407 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff 2408 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 2409 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 2410 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 2411 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 2412 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 2413 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 2414 #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 2415 #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff 2416 #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 2417 #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff 2418 #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 2419 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf 2420 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 2421 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 2422 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 2423 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 2424 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 2425 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 2426 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc 2427 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 2428 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 2429 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 2430 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 2431 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 2432 #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 2433 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf 2434 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 2435 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 2436 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 2437 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 2438 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 2439 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 2440 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc 2441 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 2442 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 2443 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 2444 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 2445 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 2446 #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 2447 #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff 2448 #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 2449 #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 2450 #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 2451 #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 2452 #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 2453 #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 2454 #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 2455 #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff 2456 #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 2457 #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff 2458 #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 2459 #define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 2460 #define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 2461 #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 2462 #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 2463 #define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 2464 #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 2465 #define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 2466 #define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 2467 #define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 2468 #define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 2469 #define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 2470 #define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 2471 #define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 2472 #define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 2473 #define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 2474 #define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 2475 #define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 2476 #define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 2477 #define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 2478 #define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 2479 #define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 2480 #define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa 2481 #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 2482 #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb 2483 #define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 2484 #define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc 2485 #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 2486 #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd 2487 #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 2488 #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe 2489 #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 2490 #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf 2491 #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 2492 #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 2493 #define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 2494 #define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 2495 #define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1 2496 #define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0 2497 #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 2498 #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 2499 #define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 2500 #define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 2501 #define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 2502 #define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 2503 #define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 2504 #define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 2505 #define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 2506 #define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 2507 #define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 2508 #define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 2509 #define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 2510 #define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 2511 #define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 2512 #define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 2513 #define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 2514 #define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 2515 #define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 2516 #define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa 2517 #define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 2518 #define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb 2519 #define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 2520 #define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc 2521 #define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 2522 #define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd 2523 #define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 2524 #define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe 2525 #define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 2526 #define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf 2527 #define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 2528 #define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 2529 #define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1 2530 #define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0 2531 #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 2532 #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 2533 #define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 2534 #define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 2535 #define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 2536 #define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 2537 #define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 2538 #define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 2539 #define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 2540 #define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 2541 #define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 2542 #define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 2543 #define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 2544 #define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 2545 #define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 2546 #define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 2547 #define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 2548 #define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 2549 #define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 2550 #define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa 2551 #define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 2552 #define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb 2553 #define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 2554 #define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc 2555 #define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 2556 #define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd 2557 #define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 2558 #define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe 2559 #define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 2560 #define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf 2561 #define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 2562 #define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 2563 #define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff 2564 #define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 2565 #define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff 2566 #define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 2567 #define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff 2568 #define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 2569 #define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff 2570 #define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 2571 #define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff 2572 #define PCIE_STRAP_F7__RESERVED__SHIFT 0x0 2573 #define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf 2574 #define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0 2575 #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 2576 #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 2577 #define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 2578 #define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 2579 #define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 2580 #define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd 2581 #define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 2582 #define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe 2583 #define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 2584 #define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf 2585 #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 2586 #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 2587 #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 2588 #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 2589 #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 2590 #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a 2591 #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 2592 #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c 2593 #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 2594 #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d 2595 #define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 2596 #define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e 2597 #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 2598 #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f 2599 #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 2600 #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 2601 #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 2602 #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 2603 #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 2604 #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 2605 #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 2606 #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 2607 #define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 2608 #define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 2609 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 2610 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c 2611 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 2612 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d 2613 #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f 2614 #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 2615 #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 2616 #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 2617 #define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff 2618 #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 2619 #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 2620 #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 2621 #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff 2622 #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 2623 #define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 2624 #define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 2625 #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff 2626 #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 2627 #define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff 2628 #define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 2629 #define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 2630 #define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 2631 #define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6 2632 #define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 2633 #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8 2634 #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3 2635 #define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10 2636 #define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4 2637 #define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60 2638 #define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5 2639 #define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80 2640 #define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7 2641 #define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 2642 #define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe 2643 #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 2644 #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 2645 #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff 2646 #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 2647 #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff 2648 #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 2649 #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff 2650 #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 2651 #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff 2652 #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 2653 #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff 2654 #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 2655 #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff 2656 #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 2657 #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff 2658 #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 2659 #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff 2660 #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 2661 #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff 2662 #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 2663 #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff 2664 #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 2665 #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff 2666 #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 2667 #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff 2668 #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 2669 #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff 2670 #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 2671 #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff 2672 #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 2673 #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff 2674 #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 2675 #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff 2676 #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 2677 #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff 2678 #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 2679 #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff 2680 #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 2681 #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff 2682 #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 2683 #define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 2684 #define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 2685 #define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 2686 #define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 2687 #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 2688 #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 2689 #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 2690 #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 2691 #define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff 2692 #define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 2693 #define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f 2694 #define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 2695 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff 2696 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2697 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff 2698 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2699 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff 2700 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2701 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff 2702 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2703 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff 2704 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2705 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff 2706 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2707 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff 2708 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2709 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff 2710 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2711 #define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff 2712 #define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 2713 #define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff 2714 #define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 2715 #define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 2716 #define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 2717 #define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 2718 #define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 2719 #define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 2720 #define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 2721 #define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 2722 #define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 2723 #define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 2724 #define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 2725 #define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 2726 #define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 2727 #define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 2728 #define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 2729 #define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 2730 #define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 2731 #define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 2732 #define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 2733 #define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 2734 #define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 2735 #define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 2736 #define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 2737 #define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 2738 #define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 2739 #define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 2740 #define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 2741 #define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 2742 #define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 2743 #define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 2744 #define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 2745 #define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 2746 #define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 2747 #define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 2748 #define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 2749 #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 2750 #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 2751 #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 2752 #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 2753 #define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 2754 #define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 2755 #define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 2756 #define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 2757 #define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 2758 #define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 2759 #define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 2760 #define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 2761 #define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 2762 #define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 2763 #define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 2764 #define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 2765 #define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 2766 #define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 2767 #define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 2768 #define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa 2769 #define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 2770 #define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc 2771 #define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 2772 #define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe 2773 #define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 2774 #define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf 2775 #define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 2776 #define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 2777 #define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 2778 #define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 2779 #define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 2780 #define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 2781 #define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 2782 #define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 2783 #define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000 2784 #define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 2785 #define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000 2786 #define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 2787 #define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000 2788 #define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a 2789 #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 2790 #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 2791 #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 2792 #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 2793 #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 2794 #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 2795 #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff 2796 #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 2797 #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 2798 #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 2799 #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 2800 #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e 2801 #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 2802 #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f 2803 #define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff 2804 #define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 2805 #define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 2806 #define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 2807 #define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 2808 #define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 2809 #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 2810 #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf 2811 #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 2812 #define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 2813 #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff 2814 #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 2815 #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 2816 #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc 2817 #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff 2818 #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 2819 #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 2820 #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 2821 #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff 2822 #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 2823 #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 2824 #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 2825 #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff 2826 #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 2827 #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 2828 #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 2829 #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff 2830 #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 2831 #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 2832 #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 2833 #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff 2834 #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 2835 #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 2836 #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 2837 #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff 2838 #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 2839 #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 2840 #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 2841 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 2842 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 2843 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 2844 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 2845 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 2846 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 2847 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 2848 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 2849 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 2850 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 2851 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 2852 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 2853 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 2854 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 2855 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 2856 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 2857 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 2858 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 2859 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 2860 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 2861 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 2862 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 2863 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 2864 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 2865 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 2866 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 2867 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 2868 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 2869 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 2870 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 2871 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 2872 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 2873 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 2874 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 2875 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 2876 #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 2877 #define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 2878 #define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 2879 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e 2880 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 2881 #define PCIE_FC_P__PD_CREDITS_MASK 0xff 2882 #define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 2883 #define PCIE_FC_P__PH_CREDITS_MASK 0xff00 2884 #define PCIE_FC_P__PH_CREDITS__SHIFT 0x8 2885 #define PCIE_FC_NP__NPD_CREDITS_MASK 0xff 2886 #define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 2887 #define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 2888 #define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 2889 #define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff 2890 #define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 2891 #define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 2892 #define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 2893 #define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 2894 #define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 2895 #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 2896 #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 2897 #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 2898 #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 2899 #define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 2900 #define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 2901 #define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 2902 #define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 2903 #define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 2904 #define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 2905 #define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 2906 #define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 2907 #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 2908 #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 2909 #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 2910 #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb 2911 #define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000 2912 #define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc 2913 #define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000 2914 #define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd 2915 #define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 2916 #define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe 2917 #define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 2918 #define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf 2919 #define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 2920 #define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 2921 #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 2922 #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 2923 #define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 2924 #define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 2925 #define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 2926 #define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 2927 #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 2928 #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 2929 #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 2930 #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 2931 #define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 2932 #define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 2933 #define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 2934 #define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 2935 #define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 2936 #define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 2937 #define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 2938 #define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 2939 #define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 2940 #define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 2941 #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 2942 #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 2943 #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 2944 #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 2945 #define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 2946 #define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa 2947 #define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 2948 #define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb 2949 #define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 2950 #define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc 2951 #define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 2952 #define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd 2953 #define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 2954 #define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe 2955 #define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 2956 #define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf 2957 #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 2958 #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 2959 #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 2960 #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 2961 #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 2962 #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 2963 #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 2964 #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 2965 #define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 2966 #define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 2967 #define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 2968 #define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 2969 #define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 2970 #define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 2971 #define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 2972 #define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 2973 #define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff 2974 #define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 2975 #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff 2976 #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 2977 #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 2978 #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 2979 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 2980 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 2981 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 2982 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 2983 #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 2984 #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 2985 #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 2986 #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 2987 #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 2988 #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 2989 #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff 2990 #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 2991 #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 2992 #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 2993 #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff 2994 #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 2995 #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 2996 #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 2997 #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff 2998 #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 2999 #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 3000 #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 3001 #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 3002 #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 3003 #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 3004 #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 3005 #define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 3006 #define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 3007 #define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 3008 #define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 3009 #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 3010 #define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 3011 #define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 3012 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc 3013 #define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 3014 #define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 3015 #define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 3016 #define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 3017 #define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 3018 #define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 3019 #define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 3020 #define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 3021 #define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 3022 #define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 3023 #define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 3024 #define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 3025 #define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 3026 #define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 3027 #define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 3028 #define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 3029 #define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 3030 #define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 3031 #define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 3032 #define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b 3033 #define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 3034 #define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c 3035 #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 3036 #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d 3037 #define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 3038 #define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e 3039 #define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 3040 #define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f 3041 #define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f 3042 #define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 3043 #define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 3044 #define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 3045 #define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 3046 #define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 3047 #define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 3048 #define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 3049 #define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 3050 #define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 3051 #define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 3052 #define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa 3053 #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 3054 #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb 3055 #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 3056 #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc 3057 #define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 3058 #define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd 3059 #define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 3060 #define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe 3061 #define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 3062 #define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 3063 #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 3064 #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 3065 #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 3066 #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 3067 #define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 3068 #define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 3069 #define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 3070 #define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 3071 #define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 3072 #define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 3073 #define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 3074 #define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 3075 #define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 3076 #define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 3077 #define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 3078 #define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 3079 #define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 3080 #define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a 3081 #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 3082 #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b 3083 #define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 3084 #define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c 3085 #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 3086 #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d 3087 #define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 3088 #define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f 3089 #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 3090 #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 3091 #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 3092 #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 3093 #define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 3094 #define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 3095 #define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 3096 #define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 3097 #define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 3098 #define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 3099 #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 3100 #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 3101 #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 3102 #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 3103 #define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 3104 #define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 3105 #define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 3106 #define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa 3107 #define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 3108 #define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb 3109 #define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 3110 #define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc 3111 #define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 3112 #define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe 3113 #define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 3114 #define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 3115 #define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 3116 #define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 3117 #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 3118 #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 3119 #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 3120 #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 3121 #define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 3122 #define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 3123 #define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 3124 #define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 3125 #define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 3126 #define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 3127 #define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 3128 #define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 3129 #define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 3130 #define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a 3131 #define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 3132 #define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e 3133 #define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 3134 #define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f 3135 #define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 3136 #define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 3137 #define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 3138 #define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 3139 #define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 3140 #define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 3141 #define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 3142 #define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 3143 #define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 3144 #define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 3145 #define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 3146 #define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 3147 #define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 3148 #define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa 3149 #define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 3150 #define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb 3151 #define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 3152 #define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc 3153 #define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 3154 #define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd 3155 #define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 3156 #define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe 3157 #define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 3158 #define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf 3159 #define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 3160 #define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 3161 #define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 3162 #define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 3163 #define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 3164 #define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 3165 #define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 3166 #define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 3167 #define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 3168 #define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 3169 #define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 3170 #define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 3171 #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 3172 #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 3173 #define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 3174 #define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a 3175 #define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f 3176 #define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 3177 #define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 3178 #define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 3179 #define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 3180 #define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc 3181 #define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 3182 #define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 3183 #define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 3184 #define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 3185 #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 3186 #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 3187 #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 3188 #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 3189 #define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 3190 #define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 3191 #define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 3192 #define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 3193 #define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 3194 #define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 3195 #define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 3196 #define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 3197 #define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 3198 #define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 3199 #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 3200 #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 3201 #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 3202 #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 3203 #define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 3204 #define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa 3205 #define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf 3206 #define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 3207 #define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 3208 #define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 3209 #define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 3210 #define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 3211 #define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 3212 #define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 3213 #define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 3214 #define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 3215 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 3216 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 3217 #define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 3218 #define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb 3219 #define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 3220 #define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc 3221 #define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 3222 #define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd 3223 #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 3224 #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 3225 #define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 3226 #define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 3227 #define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 3228 #define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 3229 #define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 3230 #define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 3231 #define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 3232 #define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 3233 #define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 3234 #define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 3235 #define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 3236 #define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 3237 #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 3238 #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 3239 #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 3240 #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 3241 #define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 3242 #define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a 3243 #define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 3244 #define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b 3245 #define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 3246 #define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c 3247 #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 3248 #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d 3249 #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 3250 #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e 3251 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 3252 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 3253 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 3254 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 3255 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 3256 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 3257 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 3258 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 3259 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 3260 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 3261 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 3262 #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa 3263 #define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 3264 #define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb 3265 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 3266 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc 3267 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 3268 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd 3269 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 3270 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe 3271 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 3272 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf 3273 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 3274 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 3275 #define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 3276 #define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 3277 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 3278 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 3279 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 3280 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 3281 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 3282 #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 3283 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 3284 #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 3285 #define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 3286 #define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 3287 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff 3288 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 3289 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 3290 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 3291 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 3292 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 3293 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 3294 #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 3295 #define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 3296 #define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 3297 #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 3298 #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 3299 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 3300 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 3301 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 3302 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 3303 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 3304 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 3305 #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 3306 #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 3307 #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 3308 #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 3309 #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 3310 #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 3311 #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 3312 #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 3313 #define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 3314 #define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 3315 #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 3316 #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa 3317 #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 3318 #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc 3319 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 3320 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd 3321 #define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 3322 #define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf 3323 #define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 3324 #define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 3325 #define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 3326 #define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 3327 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 3328 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 3329 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 3330 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 3331 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 3332 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 3333 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 3334 #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 3335 #define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 3336 #define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 3337 #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 3338 #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 3339 #define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 3340 #define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 3341 #define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 3342 #define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a 3343 #define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 3344 #define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b 3345 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 3346 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c 3347 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 3348 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d 3349 #define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 3350 #define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e 3351 #define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 3352 #define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f 3353 #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff 3354 #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 3355 #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 3356 #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc 3357 #define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 3358 #define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 3359 #define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff 3360 #define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 3361 #define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 3362 #define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 3363 #define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 3364 #define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 3365 #define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e 3366 #define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 3367 #define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 3368 #define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 3369 #define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 3370 #define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd 3371 #define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 3372 #define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 3373 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf 3374 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 3375 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 3376 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 3377 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 3378 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa 3379 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 3380 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 3381 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 3382 #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 3383 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 3384 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 3385 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e 3386 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 3387 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 3388 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 3389 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 3390 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd 3391 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 3392 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 3393 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 3394 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 3395 #define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f 3396 #define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 3397 #define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 3398 #define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 3399 #define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 3400 #define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 3401 #define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 3402 #define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 3403 #define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f 3404 #define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 3405 #define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 3406 #define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 3407 #define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 3408 #define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 3409 #define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 3410 #define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 3411 #define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f 3412 #define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 3413 #define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 3414 #define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 3415 #define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 3416 #define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 3417 #define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 3418 #define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 3419 #define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f 3420 #define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 3421 #define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 3422 #define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 3423 #define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 3424 #define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 3425 #define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 3426 #define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 3427 #define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f 3428 #define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 3429 #define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 3430 #define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 3431 #define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 3432 #define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 3433 #define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 3434 #define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 3435 #define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f 3436 #define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 3437 #define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 3438 #define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 3439 #define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 3440 #define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 3441 #define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 3442 #define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 3443 #define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 3444 #define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 3445 #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc 3446 #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 3447 #define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 3448 #define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 3449 #define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 3450 #define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 3451 #define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 3452 #define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 3453 #define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 3454 #define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb 3455 #define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 3456 #define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc 3457 #define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 3458 #define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd 3459 #define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 3460 #define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe 3461 #define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 3462 #define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf 3463 #define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 3464 #define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 3465 #define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 3466 #define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 3467 #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 3468 #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 3469 #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 3470 #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 3471 #define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 3472 #define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 3473 #define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 3474 #define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 3475 #define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 3476 #define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 3477 #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 3478 #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 3479 #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 3480 #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 3481 #define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff 3482 #define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 3483 #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 3484 #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 3485 #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 3486 #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 3487 #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 3488 #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 3489 #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 3490 #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 3491 #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 3492 #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 3493 #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 3494 #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a 3495 #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 3496 #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e 3497 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 3498 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 3499 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e 3500 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 3501 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 3502 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 3503 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 3504 #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 3505 #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 3506 #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe 3507 #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 3508 #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf 3509 #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 3510 #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 3511 #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 3512 #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 3513 #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 3514 #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e 3515 #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 3516 #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f 3517 #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 3518 #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 3519 #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe 3520 #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 3521 #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 3522 #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 3523 #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 3524 #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 3525 #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 3526 #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 3527 #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 3528 #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 3529 #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 3530 #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 3531 #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 3532 #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 3533 #define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f 3534 #define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 3535 #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 3536 #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 3537 #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 3538 #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 3539 #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 3540 #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 3541 #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 3542 #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb 3543 #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 3544 #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc 3545 #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 3546 #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe 3547 #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 3548 #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 3549 #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 3550 #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 3551 #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 3552 #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 3553 #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 3554 #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 3555 #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 3556 #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b 3557 #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 3558 #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c 3559 #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 3560 #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f 3561 #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff 3562 #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 3563 #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 3564 #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 3565 #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 3566 #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 3567 #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 3568 #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 3569 #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 3570 #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a 3571 #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 3572 #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b 3573 #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 3574 #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c 3575 #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff 3576 #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 3577 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1 3578 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0 3579 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2 3580 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1 3581 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4 3582 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2 3583 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8 3584 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3 3585 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10 3586 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4 3587 #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 3588 #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 3589 #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 3590 #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc 3591 #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 3592 #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 3593 #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 3594 #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 3595 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1 3596 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0 3597 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2 3598 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1 3599 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4 3600 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2 3601 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 3602 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc 3603 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 3604 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd 3605 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 3606 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe 3607 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 3608 #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf 3609 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000 3610 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10 3611 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 3612 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 3613 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000 3614 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14 3615 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 3616 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 3617 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000 3618 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18 3619 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 3620 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a 3621 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000 3622 #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c 3623 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 3624 #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e 3625 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1 3626 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0 3627 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2 3628 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1 3629 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4 3630 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2 3631 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 3632 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc 3633 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 3634 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd 3635 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 3636 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe 3637 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 3638 #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf 3639 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000 3640 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10 3641 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 3642 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 3643 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000 3644 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14 3645 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 3646 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 3647 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000 3648 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18 3649 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 3650 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a 3651 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000 3652 #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c 3653 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 3654 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e 3655 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1 3656 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0 3657 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2 3658 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1 3659 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4 3660 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2 3661 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 3662 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc 3663 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 3664 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd 3665 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 3666 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe 3667 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 3668 #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf 3669 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000 3670 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10 3671 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 3672 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 3673 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000 3674 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14 3675 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 3676 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 3677 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000 3678 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18 3679 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 3680 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a 3681 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000 3682 #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c 3683 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 3684 #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e 3685 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1 3686 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0 3687 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2 3688 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1 3689 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4 3690 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2 3691 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 3692 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc 3693 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 3694 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd 3695 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 3696 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe 3697 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 3698 #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf 3699 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000 3700 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10 3701 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 3702 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 3703 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000 3704 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14 3705 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 3706 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 3707 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000 3708 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18 3709 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 3710 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a 3711 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000 3712 #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c 3713 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 3714 #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e 3715 #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff 3716 #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 3717 #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 3718 #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 3719 #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 3720 #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 3721 #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 3722 #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 3723 #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 3724 #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 3725 #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 3726 #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 3727 #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 3728 #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf 3729 #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 3730 #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 3731 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 3732 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 3733 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 3734 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 3735 #define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x1 3736 #define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x0 3737 #define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x2 3738 #define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x1 3739 #define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x4 3740 #define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x2 3741 #define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x8 3742 #define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x3 3743 #define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x10 3744 #define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x4 3745 #define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x20 3746 #define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x5 3747 #define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x40 3748 #define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x6 3749 #define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x80 3750 #define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x7 3751 #define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x100 3752 #define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x8 3753 #define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x200 3754 #define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x9 3755 #define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x400 3756 #define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0xa 3757 #define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x800 3758 #define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0xb 3759 #define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x1000 3760 #define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0xc 3761 #define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x2000 3762 #define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0xd 3763 #define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x4000 3764 #define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0xe 3765 #define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x8000 3766 #define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0xf 3767 #define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x10000 3768 #define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x10 3769 #define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x20000 3770 #define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x11 3771 #define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x40000 3772 #define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x12 3773 #define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x80000 3774 #define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x13 3775 #define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x100000 3776 #define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x14 3777 #define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x200000 3778 #define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x15 3779 #define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x400000 3780 #define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x16 3781 #define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x800000 3782 #define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x17 3783 #define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x1000000 3784 #define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x18 3785 #define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x2000000 3786 #define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x19 3787 #define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x4000000 3788 #define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x1a 3789 #define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x8000000 3790 #define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x1b 3791 #define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000 3792 #define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x1c 3793 #define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000 3794 #define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d 3795 #define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000 3796 #define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x1e 3797 #define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000 3798 #define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x1f 3799 #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 3800 #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 3801 #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 3802 #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 3803 #define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 3804 #define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 3805 #define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 3806 #define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 3807 #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 3808 #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 3809 #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 3810 #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc 3811 #define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 3812 #define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd 3813 #define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 3814 #define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe 3815 #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 3816 #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf 3817 #define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 3818 #define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 3819 #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 3820 #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 3821 #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 3822 #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 3823 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e 3824 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 3825 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 3826 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 3827 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 3828 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 3829 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 3830 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe 3831 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 3832 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 3833 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 3834 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 3835 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 3836 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b 3837 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 3838 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c 3839 #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 3840 #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d 3841 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 3842 #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e 3843 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e 3844 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 3845 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 3846 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 3847 #define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 3848 #define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 3849 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 3850 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 3851 #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 3852 #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 3853 #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 3854 #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa 3855 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 3856 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc 3857 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 3858 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 3859 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 3860 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 3861 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 3862 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 3863 #define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 3864 #define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c 3865 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 3866 #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f 3867 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 3868 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 3869 #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c 3870 #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 3871 #define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 3872 #define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 3873 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 3874 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 3875 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 3876 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 3877 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 3878 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb 3879 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 3880 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf 3881 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 3882 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 3883 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 3884 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d 3885 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 3886 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f 3887 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe 3888 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 3889 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 3890 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 3891 #define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 3892 #define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd 3893 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 3894 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf 3895 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 3896 #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 3897 #define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 3898 #define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 3899 #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 3900 #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 3901 #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 3902 #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 3903 #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f 3904 #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 3905 #define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 3906 #define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 3907 #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 3908 #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 3909 #define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 3910 #define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 3911 #define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 3912 #define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 3913 #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 3914 #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 3915 #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 3916 #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 3917 #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 3918 #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 3919 #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff 3920 #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 3921 #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 3922 #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 3923 #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 3924 #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 3925 #define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 3926 #define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 3927 #define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 3928 #define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 3929 #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff 3930 #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 3931 #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 3932 #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 3933 #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e 3934 #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 3935 #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff 3936 #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 3937 #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 3938 #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 3939 #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 3940 #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 3941 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 3942 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 3943 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 3944 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 3945 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 3946 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 3947 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 3948 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 3949 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 3950 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 3951 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 3952 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 3953 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 3954 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 3955 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 3956 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 3957 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 3958 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 3959 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 3960 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 3961 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 3962 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa 3963 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 3964 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb 3965 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 3966 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc 3967 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 3968 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd 3969 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 3970 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe 3971 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000 3972 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10 3973 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000 3974 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11 3975 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000 3976 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12 3977 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000 3978 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13 3979 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000 3980 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14 3981 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000 3982 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15 3983 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000 3984 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16 3985 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000 3986 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17 3987 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 3988 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 3989 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 3990 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 3991 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 3992 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 3993 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 3994 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 3995 #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 3996 #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb 3997 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff 3998 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 3999 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 4000 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 4001 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 4002 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 4003 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 4004 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc 4005 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 4006 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd 4007 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 4008 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe 4009 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 4010 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf 4011 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 4012 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c 4013 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 4014 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e 4015 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 4016 #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f 4017 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f 4018 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 4019 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 4020 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 4021 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 4022 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 4023 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 4024 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 4025 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 4026 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 4027 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 4028 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa 4029 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 4030 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb 4031 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 4032 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc 4033 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 4034 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd 4035 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 4036 #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe 4037 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 4038 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 4039 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 4040 #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 4041 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4042 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4043 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4044 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4045 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 4046 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 4047 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300 4048 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8 4049 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4050 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4051 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4052 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4053 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 4054 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 4055 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300 4056 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8 4057 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4058 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4059 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4060 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4061 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 4062 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 4063 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300 4064 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8 4065 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4066 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4067 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4068 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4069 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 4070 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 4071 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300 4072 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8 4073 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 4074 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 4075 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 4076 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 4077 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 4078 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 4079 #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 4080 #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 4081 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 4082 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 4083 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 4084 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 4085 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 4086 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 4087 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 4088 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 4089 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 4090 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 4091 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 4092 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 4093 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 4094 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa 4095 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 4096 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 4097 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 4098 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 4099 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 4100 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c 4101 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 4102 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d 4103 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 4104 #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f 4105 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 4106 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 4107 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 4108 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 4109 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 4110 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 4111 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 4112 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 4113 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 4114 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 4115 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 4116 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 4117 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 4118 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 4119 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 4120 #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 4121 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 4122 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe 4123 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 4124 #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 4125 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4126 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4127 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4128 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4129 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 4130 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 4131 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300 4132 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8 4133 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4134 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4135 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4136 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4137 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 4138 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 4139 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300 4140 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8 4141 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4142 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4143 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4144 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4145 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 4146 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 4147 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300 4148 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8 4149 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 4150 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 4151 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 4152 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 4153 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 4154 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 4155 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300 4156 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8 4157 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff 4158 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 4159 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 4160 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa 4161 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 4162 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 4163 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000 4164 #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e 4165 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf 4166 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 4167 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 4168 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 4169 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 4170 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 4171 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 4172 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc 4173 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 4174 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 4175 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 4176 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 4177 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 4178 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 4179 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 4180 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 4181 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 4182 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a 4183 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 4184 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b 4185 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 4186 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c 4187 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 4188 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d 4189 #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 4190 #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e 4191 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 4192 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc 4193 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 4194 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 4195 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 4196 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 4197 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 4198 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 4199 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 4200 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a 4201 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 4202 #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c 4203 #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 4204 #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e 4205 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 4206 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 4207 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 4208 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 4209 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 4210 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 4211 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 4212 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 4213 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 4214 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 4215 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 4216 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c 4217 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 4218 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 4219 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 4220 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 4221 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 4222 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 4223 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 4224 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 4225 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 4226 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc 4227 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 4228 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf 4229 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 4230 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 4231 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 4232 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 4233 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 4234 #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c 4235 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f 4236 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 4237 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 4238 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 4239 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 4240 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa 4241 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 4242 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf 4243 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 4244 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 4245 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 4246 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 4247 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 4248 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 4249 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 4250 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 4251 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 4252 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 4253 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 4254 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b 4255 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 4256 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c 4257 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 4258 #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d 4259 #define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000 4260 #define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e 4261 #define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 4262 #define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f 4263 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf 4264 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 4265 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 4266 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 4267 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 4268 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 4269 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 4270 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc 4271 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 4272 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 4273 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 4274 #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 4275 #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 4276 #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 4277 #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 4278 #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a 4279 #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 4280 #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b 4281 #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 4282 #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c 4283 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf 4284 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 4285 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 4286 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 4287 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 4288 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 4289 #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 4290 #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc 4291 #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 4292 #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd 4293 #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000 4294 #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11 4295 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 4296 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 4297 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 4298 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 4299 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 4300 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 4301 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 4302 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b 4303 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 4304 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c 4305 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 4306 #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d 4307 #define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 4308 #define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 4309 #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc 4310 #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 4311 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1 4312 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0 4313 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2 4314 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1 4315 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4 4316 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2 4317 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8 4318 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3 4319 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10 4320 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4 4321 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20 4322 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5 4323 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40 4324 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6 4325 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80 4326 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7 4327 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100 4328 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8 4329 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200 4330 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9 4331 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400 4332 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa 4333 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800 4334 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb 4335 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000 4336 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc 4337 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000 4338 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd 4339 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000 4340 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe 4341 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000 4342 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf 4343 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000 4344 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10 4345 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000 4346 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11 4347 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000 4348 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12 4349 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000 4350 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13 4351 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000 4352 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14 4353 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000 4354 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15 4355 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000 4356 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16 4357 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000 4358 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17 4359 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 4360 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 4361 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 4362 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 4363 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 4364 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 4365 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 4366 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 4367 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 4368 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 4369 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 4370 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 4371 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 4372 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 4373 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 4374 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa 4375 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 4376 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb 4377 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 4378 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc 4379 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 4380 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd 4381 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 4382 #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe 4383 #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 4384 #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf 4385 #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 4386 #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 4387 #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 4388 #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 4389 #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 4390 #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 4391 #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 4392 #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 4393 #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 4394 #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 4395 #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 4396 #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 4397 #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 4398 #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 4399 #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000 4400 #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17 4401 #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000 4402 #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18 4403 #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 4404 #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c 4405 #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 4406 #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d 4407 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 4408 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e 4409 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 4410 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f 4411 #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 4412 #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 4413 #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 4414 #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 4415 #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff 4416 #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 4417 #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 4418 #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa 4419 #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 4420 #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc 4421 #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 4422 #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd 4423 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 4424 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 4425 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 4426 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 4427 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70 4428 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4 4429 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 4430 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 4431 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 4432 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 4433 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 4434 #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 4435 #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff 4436 #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 4437 #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 4438 #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa 4439 #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 4440 #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc 4441 #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 4442 #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd 4443 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 4444 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 4445 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 4446 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 4447 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70 4448 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4 4449 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 4450 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 4451 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 4452 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 4453 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 4454 #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 4455 #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff 4456 #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 4457 #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 4458 #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa 4459 #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 4460 #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc 4461 #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 4462 #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd 4463 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 4464 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 4465 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 4466 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 4467 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70 4468 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4 4469 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 4470 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 4471 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 4472 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 4473 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 4474 #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 4475 #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff 4476 #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 4477 #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 4478 #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa 4479 #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 4480 #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc 4481 #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 4482 #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd 4483 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 4484 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 4485 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 4486 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 4487 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70 4488 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4 4489 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 4490 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 4491 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 4492 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 4493 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 4494 #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 4495 #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff 4496 #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 4497 #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 4498 #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa 4499 #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 4500 #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc 4501 #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 4502 #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd 4503 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 4504 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 4505 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 4506 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 4507 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70 4508 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4 4509 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 4510 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 4511 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 4512 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 4513 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 4514 #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 4515 #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff 4516 #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 4517 #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 4518 #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa 4519 #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 4520 #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc 4521 #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 4522 #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd 4523 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 4524 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 4525 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 4526 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 4527 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70 4528 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4 4529 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 4530 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 4531 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 4532 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 4533 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 4534 #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 4535 #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff 4536 #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 4537 #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 4538 #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa 4539 #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 4540 #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc 4541 #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 4542 #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd 4543 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 4544 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 4545 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 4546 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 4547 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70 4548 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4 4549 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 4550 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 4551 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 4552 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 4553 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 4554 #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 4555 #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff 4556 #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 4557 #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 4558 #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa 4559 #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 4560 #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc 4561 #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 4562 #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd 4563 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 4564 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 4565 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 4566 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 4567 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70 4568 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4 4569 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 4570 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 4571 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 4572 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 4573 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 4574 #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 4575 #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff 4576 #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 4577 #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 4578 #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa 4579 #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 4580 #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc 4581 #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 4582 #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd 4583 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 4584 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 4585 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 4586 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 4587 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70 4588 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4 4589 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 4590 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 4591 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 4592 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 4593 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 4594 #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 4595 #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff 4596 #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 4597 #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 4598 #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa 4599 #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 4600 #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc 4601 #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 4602 #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd 4603 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 4604 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 4605 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 4606 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 4607 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70 4608 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4 4609 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 4610 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 4611 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 4612 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 4613 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 4614 #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 4615 #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff 4616 #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 4617 #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 4618 #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa 4619 #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 4620 #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc 4621 #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 4622 #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd 4623 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 4624 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 4625 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 4626 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 4627 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70 4628 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4 4629 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 4630 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 4631 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 4632 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 4633 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 4634 #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 4635 #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff 4636 #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 4637 #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 4638 #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa 4639 #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 4640 #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc 4641 #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 4642 #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd 4643 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 4644 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 4645 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 4646 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 4647 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70 4648 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4 4649 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 4650 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 4651 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 4652 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 4653 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 4654 #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 4655 #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff 4656 #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 4657 #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 4658 #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa 4659 #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 4660 #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc 4661 #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 4662 #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd 4663 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 4664 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 4665 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 4666 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 4667 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70 4668 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4 4669 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 4670 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 4671 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 4672 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 4673 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 4674 #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 4675 #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff 4676 #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 4677 #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 4678 #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa 4679 #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 4680 #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc 4681 #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 4682 #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd 4683 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 4684 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 4685 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 4686 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 4687 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70 4688 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4 4689 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 4690 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 4691 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 4692 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 4693 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 4694 #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 4695 #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff 4696 #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 4697 #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 4698 #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa 4699 #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 4700 #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc 4701 #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 4702 #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd 4703 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 4704 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 4705 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 4706 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 4707 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70 4708 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4 4709 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 4710 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 4711 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 4712 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 4713 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 4714 #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 4715 #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff 4716 #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 4717 #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 4718 #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa 4719 #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 4720 #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc 4721 #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 4722 #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd 4723 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 4724 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 4725 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 4726 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 4727 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70 4728 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4 4729 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 4730 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 4731 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 4732 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 4733 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 4734 #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 4735 #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 4736 #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 4737 #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 4738 #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 4739 #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 4740 #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 4741 #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 4742 #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb 4743 #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 4744 #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe 4745 #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 4746 #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 4747 #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 4748 #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 4749 #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 4750 #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 4751 #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 4752 #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 4753 #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 4754 #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 4755 #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 4756 #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 4757 #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000 4758 #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18 4759 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 4760 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 4761 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 4762 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 4763 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 4764 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 4765 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 4766 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 4767 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 4768 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 4769 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 4770 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 4771 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 4772 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 4773 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 4774 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 4775 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 4776 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 4777 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 4778 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 4779 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 4780 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa 4781 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 4782 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb 4783 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 4784 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc 4785 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 4786 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd 4787 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 4788 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe 4789 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 4790 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf 4791 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 4792 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 4793 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 4794 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 4795 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 4796 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 4797 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 4798 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 4799 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 4800 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 4801 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 4802 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 4803 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 4804 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 4805 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 4806 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 4807 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 4808 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 4809 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 4810 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 4811 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 4812 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a 4813 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 4814 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b 4815 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 4816 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c 4817 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 4818 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d 4819 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 4820 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e 4821 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1 4822 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0 4823 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2 4824 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1 4825 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4 4826 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2 4827 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8 4828 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3 4829 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10 4830 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4 4831 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20 4832 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5 4833 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40 4834 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6 4835 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80 4836 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7 4837 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100 4838 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8 4839 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200 4840 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9 4841 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400 4842 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa 4843 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800 4844 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb 4845 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000 4846 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc 4847 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000 4848 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd 4849 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000 4850 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe 4851 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000 4852 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf 4853 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 4854 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 4855 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 4856 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 4857 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 4858 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 4859 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 4860 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 4861 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 4862 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 4863 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 4864 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 4865 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 4866 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 4867 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 4868 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 4869 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 4870 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 4871 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 4872 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 4873 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 4874 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa 4875 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 4876 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb 4877 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 4878 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc 4879 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 4880 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd 4881 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 4882 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe 4883 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 4884 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf 4885 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 4886 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 4887 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 4888 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 4889 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 4890 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 4891 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 4892 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 4893 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 4894 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 4895 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 4896 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 4897 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 4898 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 4899 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 4900 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 4901 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 4902 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 4903 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 4904 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 4905 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 4906 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a 4907 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 4908 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b 4909 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 4910 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c 4911 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 4912 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d 4913 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 4914 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e 4915 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 4916 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f 4917 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 4918 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 4919 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 4920 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 4921 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 4922 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 4923 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 4924 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 4925 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 4926 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 4927 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 4928 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 4929 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 4930 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 4931 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 4932 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 4933 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 4934 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 4935 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 4936 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 4937 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 4938 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa 4939 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 4940 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb 4941 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 4942 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc 4943 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 4944 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd 4945 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 4946 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe 4947 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 4948 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf 4949 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 4950 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 4951 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 4952 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 4953 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 4954 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 4955 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 4956 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 4957 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 4958 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 4959 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 4960 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 4961 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 4962 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 4963 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 4964 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 4965 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 4966 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 4967 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 4968 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 4969 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 4970 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a 4971 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 4972 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b 4973 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 4974 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c 4975 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 4976 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d 4977 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 4978 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e 4979 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 4980 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f 4981 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 4982 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 4983 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 4984 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 4985 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 4986 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 4987 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 4988 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 4989 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 4990 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 4991 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 4992 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 4993 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 4994 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 4995 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 4996 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 4997 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 4998 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 4999 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 5000 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 5001 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 5002 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa 5003 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 5004 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb 5005 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 5006 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc 5007 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 5008 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd 5009 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 5010 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe 5011 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 5012 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf 5013 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 5014 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 5015 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 5016 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 5017 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 5018 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 5019 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 5020 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 5021 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 5022 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 5023 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 5024 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 5025 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 5026 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 5027 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 5028 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 5029 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 5030 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 5031 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 5032 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 5033 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 5034 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a 5035 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 5036 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b 5037 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 5038 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c 5039 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 5040 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d 5041 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 5042 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e 5043 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 5044 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f 5045 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 5046 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 5047 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 5048 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 5049 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 5050 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 5051 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 5052 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 5053 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 5054 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 5055 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 5056 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 5057 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 5058 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 5059 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 5060 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 5061 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 5062 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 5063 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 5064 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 5065 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 5066 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa 5067 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 5068 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb 5069 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 5070 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc 5071 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 5072 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd 5073 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 5074 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 5075 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 5076 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 5077 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 5078 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 5079 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 5080 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 5081 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 5082 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 5083 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 5084 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd 5085 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 5086 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe 5087 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 5088 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 5089 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 5090 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 5091 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 5092 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 5093 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 5094 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a 5095 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 5096 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e 5097 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf 5098 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 5099 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 5100 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 5101 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 5102 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 5103 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 5104 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 5105 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 5106 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 5107 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 5108 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 5109 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 5110 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 5111 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 5112 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa 5113 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 5114 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb 5115 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 5116 #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc 5117 #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 5118 #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd 5119 #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 5120 #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe 5121 #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 5122 #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf 5123 #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 5124 #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 5125 #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 5126 #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a 5127 #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 5128 #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b 5129 #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 5130 #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c 5131 #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 5132 #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d 5133 #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 5134 #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e 5135 #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 5136 #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f 5137 #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 5138 #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 5139 #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 5140 #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 5141 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 5142 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 5143 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 5144 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 5145 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 5146 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 5147 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 5148 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 5149 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 5150 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 5151 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 5152 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 5153 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 5154 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 5155 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 5156 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 5157 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 5158 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa 5159 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 5160 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb 5161 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 5162 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc 5163 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 5164 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 5165 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 5166 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 5167 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 5168 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 5169 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf 5170 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 5171 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 5172 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 5173 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 5174 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 5175 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 5176 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 5177 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 5178 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa 5179 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 5180 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe 5181 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 5182 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 5183 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 5184 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 5185 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 5186 #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c 5187 #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf 5188 #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 5189 #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 5190 #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 5191 #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 5192 #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 5193 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 5194 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 5195 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 5196 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 5197 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 5198 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 5199 #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 5200 #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 5201 #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 5202 #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 5203 #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 5204 #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 5205 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 5206 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 5207 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 5208 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 5209 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 5210 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 5211 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 5212 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 5213 #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 5214 #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 5215 #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 5216 #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 5217 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 5218 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 5219 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8 5220 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3 5221 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 5222 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 5223 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 5224 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 5225 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 5226 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 5227 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 5228 #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa 5229 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 5230 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 5231 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 5232 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 5233 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 5234 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 5235 #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 5236 #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 5237 #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 5238 #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 5239 #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 5240 #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 5241 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 5242 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 5243 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 5244 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 5245 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 5246 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 5247 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 5248 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 5249 #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 5250 #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 5251 #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 5252 #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 5253 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 5254 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 5255 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8 5256 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3 5257 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 5258 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 5259 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 5260 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 5261 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 5262 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 5263 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 5264 #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa 5265 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 5266 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 5267 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 5268 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 5269 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 5270 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 5271 #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 5272 #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 5273 #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 5274 #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 5275 #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 5276 #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 5277 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 5278 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 5279 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 5280 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 5281 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 5282 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 5283 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 5284 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 5285 #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 5286 #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 5287 #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 5288 #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 5289 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 5290 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 5291 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8 5292 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3 5293 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 5294 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 5295 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 5296 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 5297 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 5298 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 5299 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 5300 #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa 5301 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 5302 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 5303 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 5304 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 5305 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 5306 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 5307 #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 5308 #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 5309 #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 5310 #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 5311 #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 5312 #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 5313 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 5314 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 5315 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 5316 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 5317 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 5318 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 5319 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 5320 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 5321 #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 5322 #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 5323 #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 5324 #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 5325 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 5326 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 5327 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8 5328 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3 5329 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 5330 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 5331 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 5332 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 5333 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 5334 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 5335 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 5336 #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa 5337 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 5338 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 5339 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 5340 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 5341 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 5342 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 5343 #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 5344 #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 5345 #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 5346 #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 5347 #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 5348 #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 5349 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 5350 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 5351 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 5352 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 5353 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 5354 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 5355 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 5356 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 5357 #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 5358 #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 5359 #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 5360 #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 5361 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 5362 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 5363 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8 5364 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3 5365 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 5366 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 5367 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 5368 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 5369 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 5370 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 5371 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 5372 #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa 5373 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 5374 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 5375 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 5376 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 5377 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 5378 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 5379 #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 5380 #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 5381 #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 5382 #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 5383 #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 5384 #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 5385 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 5386 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 5387 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 5388 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 5389 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 5390 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 5391 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 5392 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 5393 #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 5394 #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 5395 #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 5396 #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 5397 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 5398 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 5399 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8 5400 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3 5401 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 5402 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 5403 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 5404 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 5405 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 5406 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 5407 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 5408 #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa 5409 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 5410 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 5411 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 5412 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 5413 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 5414 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 5415 #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 5416 #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 5417 #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 5418 #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 5419 #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 5420 #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 5421 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 5422 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 5423 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 5424 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 5425 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 5426 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 5427 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 5428 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 5429 #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 5430 #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 5431 #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 5432 #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 5433 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 5434 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 5435 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8 5436 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3 5437 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 5438 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 5439 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 5440 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 5441 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 5442 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 5443 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 5444 #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa 5445 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 5446 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 5447 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 5448 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 5449 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 5450 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 5451 #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 5452 #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 5453 #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 5454 #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 5455 #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 5456 #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 5457 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 5458 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 5459 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 5460 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 5461 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 5462 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 5463 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 5464 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 5465 #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 5466 #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 5467 #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 5468 #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 5469 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 5470 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 5471 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8 5472 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3 5473 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 5474 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 5475 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 5476 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 5477 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 5478 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 5479 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 5480 #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa 5481 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 5482 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 5483 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 5484 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 5485 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 5486 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 5487 #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 5488 #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 5489 #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 5490 #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 5491 #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 5492 #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 5493 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 5494 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 5495 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 5496 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 5497 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 5498 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 5499 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 5500 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 5501 #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 5502 #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 5503 #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 5504 #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 5505 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 5506 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 5507 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8 5508 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3 5509 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 5510 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 5511 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 5512 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 5513 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 5514 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 5515 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 5516 #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa 5517 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 5518 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 5519 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 5520 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 5521 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 5522 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 5523 #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 5524 #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 5525 #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 5526 #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 5527 #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 5528 #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 5529 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 5530 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 5531 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 5532 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 5533 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 5534 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 5535 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 5536 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 5537 #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 5538 #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 5539 #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 5540 #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 5541 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 5542 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 5543 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8 5544 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3 5545 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 5546 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 5547 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 5548 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 5549 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 5550 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 5551 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 5552 #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa 5553 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 5554 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 5555 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 5556 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 5557 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 5558 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 5559 #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 5560 #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 5561 #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 5562 #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 5563 #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 5564 #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 5565 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 5566 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 5567 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 5568 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 5569 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 5570 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 5571 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 5572 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 5573 #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 5574 #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 5575 #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 5576 #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 5577 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 5578 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 5579 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8 5580 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3 5581 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 5582 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 5583 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 5584 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 5585 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 5586 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 5587 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 5588 #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa 5589 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 5590 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 5591 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 5592 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 5593 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 5594 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 5595 #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 5596 #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 5597 #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 5598 #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 5599 #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 5600 #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 5601 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 5602 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 5603 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 5604 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 5605 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 5606 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 5607 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 5608 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 5609 #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 5610 #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 5611 #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 5612 #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 5613 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 5614 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 5615 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8 5616 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3 5617 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 5618 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 5619 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 5620 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 5621 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 5622 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 5623 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 5624 #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa 5625 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 5626 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 5627 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 5628 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 5629 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 5630 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 5631 #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 5632 #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 5633 #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 5634 #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 5635 #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 5636 #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 5637 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 5638 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 5639 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 5640 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 5641 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 5642 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 5643 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 5644 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 5645 #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 5646 #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 5647 #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 5648 #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 5649 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 5650 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 5651 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8 5652 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3 5653 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 5654 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 5655 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 5656 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 5657 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 5658 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 5659 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 5660 #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa 5661 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 5662 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 5663 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 5664 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 5665 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 5666 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 5667 #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 5668 #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 5669 #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 5670 #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 5671 #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 5672 #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 5673 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 5674 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 5675 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 5676 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 5677 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 5678 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 5679 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 5680 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 5681 #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 5682 #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 5683 #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 5684 #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 5685 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 5686 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 5687 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8 5688 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3 5689 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 5690 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 5691 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 5692 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 5693 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 5694 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 5695 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 5696 #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa 5697 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 5698 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 5699 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 5700 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 5701 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 5702 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 5703 #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 5704 #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 5705 #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 5706 #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 5707 #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 5708 #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 5709 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 5710 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 5711 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 5712 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 5713 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 5714 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 5715 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 5716 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 5717 #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 5718 #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 5719 #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 5720 #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 5721 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 5722 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 5723 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8 5724 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3 5725 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 5726 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 5727 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 5728 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 5729 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 5730 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 5731 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 5732 #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa 5733 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 5734 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 5735 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 5736 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 5737 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 5738 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 5739 #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 5740 #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 5741 #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 5742 #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 5743 #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 5744 #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 5745 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 5746 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 5747 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 5748 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 5749 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 5750 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 5751 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 5752 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 5753 #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 5754 #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 5755 #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 5756 #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 5757 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 5758 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 5759 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8 5760 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3 5761 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 5762 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 5763 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 5764 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 5765 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 5766 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 5767 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 5768 #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa 5769 #define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff 5770 #define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 5771 #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 5772 #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 5773 #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 5774 #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 5775 #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 5776 #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 5777 #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 5778 #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 5779 #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 5780 #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 5781 #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 5782 #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a 5783 #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 5784 #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e 5785 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 5786 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 5787 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e 5788 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 5789 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 5790 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 5791 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 5792 #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 5793 #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 5794 #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe 5795 #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 5796 #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf 5797 #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 5798 #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 5799 #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 5800 #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 5801 #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 5802 #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e 5803 #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 5804 #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f 5805 #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 5806 #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 5807 #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe 5808 #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 5809 #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 5810 #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 5811 #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 5812 #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 5813 #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 5814 #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 5815 #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 5816 #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 5817 #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 5818 #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 5819 #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 5820 #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 5821 #define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f 5822 #define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 5823 #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 5824 #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 5825 #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 5826 #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 5827 #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 5828 #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 5829 #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 5830 #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb 5831 #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 5832 #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc 5833 #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 5834 #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe 5835 #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 5836 #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 5837 #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 5838 #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 5839 #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 5840 #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 5841 #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 5842 #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 5843 #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 5844 #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b 5845 #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 5846 #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c 5847 #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 5848 #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f 5849 #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff 5850 #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 5851 #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 5852 #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 5853 #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 5854 #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 5855 #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 5856 #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 5857 #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 5858 #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a 5859 #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 5860 #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b 5861 #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 5862 #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c 5863 #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff 5864 #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 5865 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1 5866 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0 5867 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2 5868 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1 5869 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4 5870 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2 5871 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8 5872 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3 5873 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10 5874 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4 5875 #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 5876 #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 5877 #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 5878 #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc 5879 #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 5880 #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 5881 #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 5882 #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 5883 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1 5884 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0 5885 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2 5886 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1 5887 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4 5888 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2 5889 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 5890 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc 5891 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 5892 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd 5893 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 5894 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe 5895 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 5896 #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf 5897 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000 5898 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10 5899 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 5900 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 5901 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000 5902 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14 5903 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 5904 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 5905 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000 5906 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18 5907 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 5908 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a 5909 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000 5910 #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c 5911 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 5912 #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e 5913 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1 5914 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0 5915 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2 5916 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1 5917 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4 5918 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2 5919 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 5920 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc 5921 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 5922 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd 5923 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 5924 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe 5925 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 5926 #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf 5927 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000 5928 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10 5929 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 5930 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 5931 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000 5932 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14 5933 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 5934 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 5935 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000 5936 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18 5937 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 5938 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a 5939 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000 5940 #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c 5941 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 5942 #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e 5943 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1 5944 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0 5945 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2 5946 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1 5947 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4 5948 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2 5949 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 5950 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc 5951 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 5952 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd 5953 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 5954 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe 5955 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 5956 #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf 5957 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000 5958 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10 5959 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 5960 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 5961 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000 5962 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14 5963 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 5964 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 5965 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000 5966 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18 5967 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 5968 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a 5969 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000 5970 #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c 5971 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 5972 #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e 5973 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1 5974 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0 5975 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2 5976 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1 5977 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4 5978 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2 5979 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 5980 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc 5981 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 5982 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd 5983 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 5984 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe 5985 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 5986 #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf 5987 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000 5988 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10 5989 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 5990 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 5991 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000 5992 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14 5993 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 5994 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 5995 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000 5996 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18 5997 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 5998 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a 5999 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000 6000 #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c 6001 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 6002 #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e 6003 #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff 6004 #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 6005 #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 6006 #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 6007 #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 6008 #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 6009 #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 6010 #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 6011 #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 6012 #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 6013 #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 6014 #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 6015 #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 6016 #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf 6017 #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 6018 #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 6019 #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 6020 #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 6021 #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 6022 #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 6023 #define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x1 6024 #define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x0 6025 #define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x2 6026 #define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x1 6027 #define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x4 6028 #define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x2 6029 #define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x8 6030 #define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x3 6031 #define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x10 6032 #define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x4 6033 #define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x20 6034 #define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x5 6035 #define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x40 6036 #define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x6 6037 #define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x80 6038 #define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x7 6039 #define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x100 6040 #define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x8 6041 #define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x200 6042 #define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x9 6043 #define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x400 6044 #define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0xa 6045 #define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x800 6046 #define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0xb 6047 #define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x1000 6048 #define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0xc 6049 #define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x2000 6050 #define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0xd 6051 #define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x4000 6052 #define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0xe 6053 #define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x8000 6054 #define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0xf 6055 #define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x10000 6056 #define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x10 6057 #define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x20000 6058 #define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x11 6059 #define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x40000 6060 #define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x12 6061 #define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x80000 6062 #define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x13 6063 #define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x100000 6064 #define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x14 6065 #define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x200000 6066 #define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x15 6067 #define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x400000 6068 #define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x16 6069 #define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x800000 6070 #define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x17 6071 #define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x1000000 6072 #define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x18 6073 #define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x2000000 6074 #define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x19 6075 #define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x4000000 6076 #define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x1a 6077 #define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x8000000 6078 #define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x1b 6079 #define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000 6080 #define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x1c 6081 #define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000 6082 #define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x1d 6083 #define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000 6084 #define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x1e 6085 #define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000 6086 #define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x1f 6087 #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 6088 #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 6089 #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 6090 #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 6091 #define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 6092 #define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 6093 #define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 6094 #define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 6095 #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 6096 #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 6097 #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 6098 #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc 6099 #define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 6100 #define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd 6101 #define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 6102 #define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe 6103 #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 6104 #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf 6105 #define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 6106 #define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 6107 #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 6108 #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 6109 #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 6110 #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 6111 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e 6112 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 6113 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 6114 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 6115 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 6116 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 6117 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 6118 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe 6119 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 6120 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 6121 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 6122 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 6123 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 6124 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b 6125 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 6126 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c 6127 #define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 6128 #define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d 6129 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 6130 #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e 6131 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e 6132 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 6133 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 6134 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 6135 #define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 6136 #define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 6137 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 6138 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 6139 #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 6140 #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 6141 #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 6142 #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa 6143 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 6144 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc 6145 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 6146 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 6147 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 6148 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 6149 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 6150 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 6151 #define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 6152 #define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c 6153 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 6154 #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f 6155 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 6156 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 6157 #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c 6158 #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 6159 #define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 6160 #define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 6161 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 6162 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 6163 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 6164 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 6165 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 6166 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb 6167 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 6168 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf 6169 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 6170 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 6171 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 6172 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d 6173 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 6174 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f 6175 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe 6176 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 6177 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 6178 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 6179 #define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 6180 #define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd 6181 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 6182 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf 6183 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 6184 #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 6185 #define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 6186 #define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 6187 #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 6188 #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 6189 #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 6190 #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 6191 #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f 6192 #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 6193 #define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 6194 #define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 6195 #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 6196 #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 6197 #define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 6198 #define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 6199 #define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 6200 #define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 6201 #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 6202 #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 6203 #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 6204 #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 6205 #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 6206 #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 6207 #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff 6208 #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 6209 #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 6210 #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 6211 #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 6212 #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 6213 #define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 6214 #define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 6215 #define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 6216 #define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 6217 #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff 6218 #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 6219 #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 6220 #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 6221 #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e 6222 #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 6223 #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff 6224 #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 6225 #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 6226 #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 6227 #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 6228 #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 6229 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 6230 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 6231 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 6232 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 6233 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 6234 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 6235 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 6236 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 6237 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 6238 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 6239 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 6240 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 6241 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 6242 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 6243 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 6244 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 6245 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 6246 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 6247 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 6248 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 6249 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 6250 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa 6251 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 6252 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb 6253 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 6254 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc 6255 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 6256 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd 6257 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 6258 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe 6259 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000 6260 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10 6261 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000 6262 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11 6263 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000 6264 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12 6265 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000 6266 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13 6267 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000 6268 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14 6269 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000 6270 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15 6271 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000 6272 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16 6273 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000 6274 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17 6275 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 6276 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 6277 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 6278 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 6279 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 6280 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 6281 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 6282 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 6283 #define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 6284 #define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb 6285 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff 6286 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 6287 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 6288 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 6289 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 6290 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 6291 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 6292 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc 6293 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 6294 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd 6295 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 6296 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe 6297 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 6298 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf 6299 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 6300 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c 6301 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 6302 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e 6303 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 6304 #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f 6305 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f 6306 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 6307 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 6308 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 6309 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 6310 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 6311 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 6312 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 6313 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 6314 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 6315 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 6316 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa 6317 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 6318 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb 6319 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 6320 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc 6321 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 6322 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd 6323 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 6324 #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe 6325 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 6326 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 6327 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 6328 #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 6329 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6330 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6331 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6332 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6333 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 6334 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 6335 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300 6336 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8 6337 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6338 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6339 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6340 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6341 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 6342 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 6343 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300 6344 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8 6345 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6346 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6347 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6348 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6349 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 6350 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 6351 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300 6352 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8 6353 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6354 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6355 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6356 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6357 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 6358 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 6359 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300 6360 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8 6361 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 6362 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 6363 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 6364 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 6365 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 6366 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 6367 #define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 6368 #define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 6369 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 6370 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 6371 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 6372 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 6373 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 6374 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 6375 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 6376 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 6377 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 6378 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 6379 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 6380 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 6381 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 6382 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa 6383 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 6384 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 6385 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 6386 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 6387 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 6388 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c 6389 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 6390 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d 6391 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 6392 #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f 6393 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 6394 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 6395 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 6396 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 6397 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 6398 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 6399 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 6400 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 6401 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 6402 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 6403 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 6404 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 6405 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 6406 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 6407 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 6408 #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 6409 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 6410 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe 6411 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 6412 #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 6413 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6414 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6415 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6416 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6417 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 6418 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 6419 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300 6420 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8 6421 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6422 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6423 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6424 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6425 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 6426 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 6427 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300 6428 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8 6429 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6430 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6431 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6432 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6433 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 6434 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 6435 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300 6436 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8 6437 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 6438 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 6439 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 6440 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 6441 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 6442 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 6443 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300 6444 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8 6445 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff 6446 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 6447 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 6448 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa 6449 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 6450 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 6451 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000 6452 #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e 6453 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf 6454 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 6455 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 6456 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 6457 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 6458 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 6459 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 6460 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc 6461 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 6462 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 6463 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 6464 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 6465 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 6466 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 6467 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 6468 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 6469 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 6470 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a 6471 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 6472 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b 6473 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 6474 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c 6475 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 6476 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d 6477 #define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 6478 #define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e 6479 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 6480 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc 6481 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 6482 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 6483 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 6484 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 6485 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 6486 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 6487 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 6488 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a 6489 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 6490 #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c 6491 #define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 6492 #define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e 6493 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 6494 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 6495 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 6496 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 6497 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 6498 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 6499 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 6500 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 6501 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 6502 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 6503 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 6504 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c 6505 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 6506 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 6507 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 6508 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 6509 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 6510 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 6511 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 6512 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 6513 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 6514 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc 6515 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 6516 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf 6517 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 6518 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 6519 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 6520 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 6521 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 6522 #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c 6523 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f 6524 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 6525 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 6526 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 6527 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 6528 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa 6529 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 6530 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf 6531 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 6532 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 6533 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 6534 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 6535 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 6536 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 6537 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 6538 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 6539 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 6540 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 6541 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 6542 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b 6543 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 6544 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c 6545 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 6546 #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d 6547 #define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000 6548 #define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e 6549 #define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 6550 #define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f 6551 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf 6552 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 6553 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 6554 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 6555 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 6556 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 6557 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 6558 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc 6559 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 6560 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 6561 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 6562 #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 6563 #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 6564 #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 6565 #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 6566 #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a 6567 #define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 6568 #define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b 6569 #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 6570 #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c 6571 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf 6572 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 6573 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 6574 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 6575 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 6576 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 6577 #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 6578 #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc 6579 #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 6580 #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd 6581 #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000 6582 #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11 6583 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 6584 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 6585 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 6586 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 6587 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 6588 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 6589 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 6590 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b 6591 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 6592 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c 6593 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 6594 #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d 6595 #define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 6596 #define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 6597 #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc 6598 #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 6599 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1 6600 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0 6601 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2 6602 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1 6603 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4 6604 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2 6605 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8 6606 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3 6607 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10 6608 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4 6609 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20 6610 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5 6611 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40 6612 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6 6613 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80 6614 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7 6615 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100 6616 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8 6617 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200 6618 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9 6619 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400 6620 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa 6621 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800 6622 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb 6623 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000 6624 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc 6625 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000 6626 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd 6627 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000 6628 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe 6629 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000 6630 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf 6631 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000 6632 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10 6633 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000 6634 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11 6635 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000 6636 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12 6637 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000 6638 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13 6639 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000 6640 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14 6641 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000 6642 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15 6643 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000 6644 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16 6645 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000 6646 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17 6647 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 6648 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 6649 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 6650 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 6651 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 6652 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 6653 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 6654 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 6655 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 6656 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 6657 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 6658 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 6659 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 6660 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 6661 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 6662 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa 6663 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 6664 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb 6665 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 6666 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc 6667 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 6668 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd 6669 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 6670 #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe 6671 #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 6672 #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf 6673 #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 6674 #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 6675 #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 6676 #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 6677 #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 6678 #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 6679 #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 6680 #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 6681 #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 6682 #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 6683 #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 6684 #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 6685 #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 6686 #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 6687 #define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000 6688 #define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17 6689 #define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000 6690 #define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18 6691 #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 6692 #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c 6693 #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 6694 #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d 6695 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 6696 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e 6697 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 6698 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f 6699 #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 6700 #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 6701 #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 6702 #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 6703 #define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff 6704 #define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 6705 #define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 6706 #define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa 6707 #define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 6708 #define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc 6709 #define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 6710 #define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd 6711 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 6712 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 6713 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 6714 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 6715 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70 6716 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4 6717 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 6718 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 6719 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 6720 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 6721 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 6722 #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 6723 #define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff 6724 #define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 6725 #define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 6726 #define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa 6727 #define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 6728 #define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc 6729 #define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 6730 #define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd 6731 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 6732 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 6733 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 6734 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 6735 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70 6736 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4 6737 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 6738 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 6739 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 6740 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 6741 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 6742 #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 6743 #define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff 6744 #define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 6745 #define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 6746 #define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa 6747 #define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 6748 #define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc 6749 #define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 6750 #define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd 6751 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 6752 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 6753 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 6754 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 6755 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70 6756 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4 6757 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 6758 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 6759 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 6760 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 6761 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 6762 #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 6763 #define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff 6764 #define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 6765 #define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 6766 #define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa 6767 #define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 6768 #define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc 6769 #define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 6770 #define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd 6771 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 6772 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 6773 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 6774 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 6775 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70 6776 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4 6777 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 6778 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 6779 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 6780 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 6781 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 6782 #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 6783 #define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff 6784 #define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 6785 #define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 6786 #define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa 6787 #define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 6788 #define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc 6789 #define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 6790 #define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd 6791 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 6792 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 6793 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 6794 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 6795 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70 6796 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4 6797 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 6798 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 6799 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 6800 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 6801 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 6802 #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 6803 #define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff 6804 #define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 6805 #define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 6806 #define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa 6807 #define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 6808 #define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc 6809 #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 6810 #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd 6811 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 6812 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 6813 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 6814 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 6815 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70 6816 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4 6817 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 6818 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 6819 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 6820 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 6821 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 6822 #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 6823 #define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff 6824 #define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 6825 #define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 6826 #define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa 6827 #define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 6828 #define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc 6829 #define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 6830 #define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd 6831 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 6832 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 6833 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 6834 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 6835 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70 6836 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4 6837 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 6838 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 6839 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 6840 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 6841 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 6842 #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 6843 #define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff 6844 #define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 6845 #define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 6846 #define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa 6847 #define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 6848 #define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc 6849 #define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 6850 #define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd 6851 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 6852 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 6853 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 6854 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 6855 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70 6856 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4 6857 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 6858 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 6859 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 6860 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 6861 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 6862 #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 6863 #define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff 6864 #define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 6865 #define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 6866 #define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa 6867 #define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 6868 #define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc 6869 #define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 6870 #define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd 6871 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 6872 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 6873 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 6874 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 6875 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70 6876 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4 6877 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 6878 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 6879 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 6880 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 6881 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 6882 #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 6883 #define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff 6884 #define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 6885 #define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 6886 #define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa 6887 #define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 6888 #define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc 6889 #define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 6890 #define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd 6891 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 6892 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 6893 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 6894 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 6895 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70 6896 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4 6897 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 6898 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 6899 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 6900 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 6901 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 6902 #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 6903 #define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff 6904 #define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 6905 #define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 6906 #define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa 6907 #define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 6908 #define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc 6909 #define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 6910 #define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd 6911 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 6912 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 6913 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 6914 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 6915 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70 6916 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4 6917 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 6918 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 6919 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 6920 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 6921 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 6922 #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 6923 #define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff 6924 #define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 6925 #define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 6926 #define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa 6927 #define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 6928 #define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc 6929 #define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 6930 #define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd 6931 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 6932 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 6933 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 6934 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 6935 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70 6936 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4 6937 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 6938 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 6939 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 6940 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 6941 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 6942 #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 6943 #define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff 6944 #define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 6945 #define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 6946 #define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa 6947 #define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 6948 #define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc 6949 #define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 6950 #define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd 6951 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 6952 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 6953 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 6954 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 6955 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70 6956 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4 6957 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 6958 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 6959 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 6960 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 6961 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 6962 #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 6963 #define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff 6964 #define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 6965 #define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 6966 #define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa 6967 #define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 6968 #define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc 6969 #define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 6970 #define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd 6971 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 6972 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 6973 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 6974 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 6975 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70 6976 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4 6977 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 6978 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 6979 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 6980 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 6981 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 6982 #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 6983 #define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff 6984 #define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 6985 #define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 6986 #define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa 6987 #define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 6988 #define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc 6989 #define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 6990 #define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd 6991 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 6992 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 6993 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 6994 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 6995 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70 6996 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4 6997 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 6998 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 6999 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 7000 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 7001 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 7002 #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 7003 #define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff 7004 #define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 7005 #define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 7006 #define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa 7007 #define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 7008 #define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc 7009 #define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 7010 #define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd 7011 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 7012 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 7013 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 7014 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 7015 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70 7016 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4 7017 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 7018 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 7019 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 7020 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 7021 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 7022 #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 7023 #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 7024 #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 7025 #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 7026 #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 7027 #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 7028 #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 7029 #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 7030 #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb 7031 #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 7032 #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe 7033 #define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 7034 #define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 7035 #define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 7036 #define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 7037 #define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 7038 #define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 7039 #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 7040 #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 7041 #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 7042 #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 7043 #define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 7044 #define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 7045 #define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000 7046 #define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18 7047 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 7048 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 7049 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 7050 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 7051 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 7052 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 7053 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 7054 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 7055 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 7056 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 7057 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 7058 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 7059 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 7060 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 7061 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 7062 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 7063 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 7064 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 7065 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 7066 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 7067 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 7068 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa 7069 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 7070 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb 7071 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 7072 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc 7073 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 7074 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd 7075 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 7076 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe 7077 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 7078 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf 7079 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 7080 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 7081 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 7082 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 7083 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 7084 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 7085 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 7086 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 7087 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 7088 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 7089 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 7090 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 7091 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 7092 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 7093 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 7094 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 7095 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 7096 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 7097 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 7098 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 7099 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 7100 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a 7101 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 7102 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b 7103 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 7104 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c 7105 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 7106 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d 7107 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 7108 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e 7109 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1 7110 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0 7111 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2 7112 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1 7113 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4 7114 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2 7115 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8 7116 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3 7117 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10 7118 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4 7119 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20 7120 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5 7121 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40 7122 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6 7123 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80 7124 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7 7125 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100 7126 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8 7127 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200 7128 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9 7129 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400 7130 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa 7131 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800 7132 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb 7133 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000 7134 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc 7135 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000 7136 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd 7137 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000 7138 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe 7139 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000 7140 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf 7141 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 7142 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 7143 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 7144 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 7145 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 7146 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 7147 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 7148 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 7149 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 7150 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 7151 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 7152 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 7153 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 7154 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 7155 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 7156 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 7157 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 7158 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 7159 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 7160 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 7161 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 7162 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa 7163 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 7164 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb 7165 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 7166 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc 7167 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 7168 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd 7169 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 7170 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe 7171 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 7172 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf 7173 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 7174 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 7175 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 7176 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 7177 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 7178 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 7179 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 7180 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 7181 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 7182 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 7183 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 7184 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 7185 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 7186 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 7187 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 7188 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 7189 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 7190 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 7191 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 7192 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 7193 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 7194 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a 7195 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 7196 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b 7197 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 7198 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c 7199 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 7200 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d 7201 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 7202 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e 7203 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 7204 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f 7205 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 7206 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 7207 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 7208 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 7209 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 7210 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 7211 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 7212 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 7213 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 7214 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 7215 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 7216 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 7217 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 7218 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 7219 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 7220 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 7221 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 7222 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 7223 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 7224 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 7225 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 7226 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa 7227 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 7228 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb 7229 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 7230 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc 7231 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 7232 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd 7233 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 7234 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe 7235 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 7236 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf 7237 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 7238 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 7239 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 7240 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 7241 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 7242 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 7243 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 7244 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 7245 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 7246 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 7247 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 7248 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 7249 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 7250 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 7251 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 7252 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 7253 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 7254 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 7255 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 7256 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 7257 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 7258 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a 7259 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 7260 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b 7261 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 7262 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c 7263 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 7264 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d 7265 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 7266 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e 7267 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 7268 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f 7269 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 7270 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 7271 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 7272 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 7273 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 7274 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 7275 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 7276 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 7277 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 7278 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 7279 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 7280 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 7281 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 7282 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 7283 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 7284 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 7285 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 7286 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 7287 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 7288 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 7289 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 7290 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa 7291 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 7292 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb 7293 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 7294 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc 7295 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 7296 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd 7297 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 7298 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe 7299 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 7300 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf 7301 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 7302 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 7303 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 7304 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 7305 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 7306 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 7307 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 7308 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 7309 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 7310 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 7311 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 7312 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 7313 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 7314 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 7315 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 7316 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 7317 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 7318 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 7319 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 7320 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 7321 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 7322 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a 7323 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 7324 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b 7325 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 7326 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c 7327 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 7328 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d 7329 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 7330 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e 7331 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 7332 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f 7333 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 7334 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 7335 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 7336 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 7337 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 7338 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 7339 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 7340 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 7341 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 7342 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 7343 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 7344 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 7345 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 7346 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 7347 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 7348 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 7349 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 7350 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 7351 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 7352 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 7353 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 7354 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa 7355 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 7356 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb 7357 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 7358 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc 7359 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 7360 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd 7361 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 7362 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 7363 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 7364 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 7365 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 7366 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 7367 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 7368 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 7369 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 7370 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 7371 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 7372 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd 7373 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 7374 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe 7375 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 7376 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 7377 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 7378 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 7379 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 7380 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 7381 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 7382 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a 7383 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 7384 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e 7385 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf 7386 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 7387 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 7388 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 7389 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 7390 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 7391 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 7392 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 7393 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 7394 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 7395 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 7396 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 7397 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 7398 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 7399 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 7400 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa 7401 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 7402 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb 7403 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 7404 #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc 7405 #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 7406 #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd 7407 #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 7408 #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe 7409 #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 7410 #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf 7411 #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 7412 #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 7413 #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 7414 #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a 7415 #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 7416 #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b 7417 #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 7418 #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c 7419 #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 7420 #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d 7421 #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 7422 #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e 7423 #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 7424 #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f 7425 #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 7426 #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 7427 #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 7428 #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 7429 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 7430 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 7431 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 7432 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 7433 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 7434 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 7435 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 7436 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 7437 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 7438 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 7439 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 7440 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 7441 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 7442 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 7443 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 7444 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 7445 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 7446 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa 7447 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 7448 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb 7449 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 7450 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc 7451 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 7452 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 7453 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 7454 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 7455 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 7456 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 7457 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf 7458 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 7459 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 7460 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 7461 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 7462 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 7463 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 7464 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 7465 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 7466 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa 7467 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 7468 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe 7469 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 7470 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 7471 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 7472 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 7473 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 7474 #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c 7475 #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf 7476 #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 7477 #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 7478 #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 7479 #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 7480 #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 7481 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 7482 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 7483 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 7484 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 7485 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 7486 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 7487 #define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 7488 #define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 7489 #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 7490 #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 7491 #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 7492 #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 7493 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 7494 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 7495 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 7496 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 7497 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 7498 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 7499 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 7500 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 7501 #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 7502 #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 7503 #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 7504 #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 7505 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 7506 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 7507 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8 7508 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3 7509 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 7510 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 7511 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 7512 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 7513 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 7514 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 7515 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 7516 #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa 7517 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 7518 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 7519 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 7520 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 7521 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 7522 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 7523 #define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 7524 #define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 7525 #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 7526 #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 7527 #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 7528 #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 7529 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 7530 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 7531 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 7532 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 7533 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 7534 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 7535 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 7536 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 7537 #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 7538 #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 7539 #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 7540 #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 7541 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 7542 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 7543 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8 7544 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3 7545 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 7546 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 7547 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 7548 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 7549 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 7550 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 7551 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 7552 #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa 7553 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 7554 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 7555 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 7556 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 7557 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 7558 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 7559 #define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 7560 #define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 7561 #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 7562 #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 7563 #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 7564 #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 7565 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 7566 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 7567 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 7568 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 7569 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 7570 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 7571 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 7572 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 7573 #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 7574 #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 7575 #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 7576 #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 7577 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 7578 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 7579 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8 7580 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3 7581 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 7582 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 7583 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 7584 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 7585 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 7586 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 7587 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 7588 #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa 7589 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 7590 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 7591 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 7592 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 7593 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 7594 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 7595 #define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 7596 #define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 7597 #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 7598 #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 7599 #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 7600 #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 7601 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 7602 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 7603 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 7604 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 7605 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 7606 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 7607 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 7608 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 7609 #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 7610 #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 7611 #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 7612 #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 7613 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 7614 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 7615 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8 7616 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3 7617 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 7618 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 7619 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 7620 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 7621 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 7622 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 7623 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 7624 #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa 7625 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 7626 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 7627 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 7628 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 7629 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 7630 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 7631 #define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 7632 #define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 7633 #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 7634 #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 7635 #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 7636 #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 7637 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 7638 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 7639 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 7640 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 7641 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 7642 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 7643 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 7644 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 7645 #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 7646 #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 7647 #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 7648 #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 7649 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 7650 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 7651 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8 7652 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3 7653 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 7654 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 7655 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 7656 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 7657 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 7658 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 7659 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 7660 #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa 7661 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 7662 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 7663 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 7664 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 7665 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 7666 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 7667 #define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 7668 #define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 7669 #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 7670 #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 7671 #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 7672 #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 7673 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 7674 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 7675 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 7676 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 7677 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 7678 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 7679 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 7680 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 7681 #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 7682 #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 7683 #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 7684 #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 7685 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 7686 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 7687 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8 7688 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3 7689 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 7690 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 7691 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 7692 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 7693 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 7694 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 7695 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 7696 #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa 7697 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 7698 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 7699 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 7700 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 7701 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 7702 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 7703 #define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 7704 #define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 7705 #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 7706 #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 7707 #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 7708 #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 7709 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 7710 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 7711 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 7712 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 7713 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 7714 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 7715 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 7716 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 7717 #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 7718 #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 7719 #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 7720 #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 7721 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 7722 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 7723 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8 7724 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3 7725 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 7726 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 7727 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 7728 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 7729 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 7730 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 7731 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 7732 #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa 7733 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 7734 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 7735 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 7736 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 7737 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 7738 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 7739 #define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 7740 #define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 7741 #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 7742 #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 7743 #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 7744 #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 7745 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 7746 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 7747 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 7748 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 7749 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 7750 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 7751 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 7752 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 7753 #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 7754 #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 7755 #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 7756 #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 7757 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 7758 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 7759 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8 7760 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3 7761 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 7762 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 7763 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 7764 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 7765 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 7766 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 7767 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 7768 #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa 7769 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 7770 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 7771 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 7772 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 7773 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 7774 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 7775 #define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 7776 #define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 7777 #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 7778 #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 7779 #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 7780 #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 7781 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 7782 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 7783 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 7784 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 7785 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 7786 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 7787 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 7788 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 7789 #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 7790 #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 7791 #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 7792 #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 7793 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 7794 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 7795 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8 7796 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3 7797 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 7798 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 7799 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 7800 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 7801 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 7802 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 7803 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 7804 #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa 7805 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 7806 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 7807 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 7808 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 7809 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 7810 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 7811 #define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 7812 #define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 7813 #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 7814 #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 7815 #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 7816 #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 7817 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 7818 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 7819 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 7820 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 7821 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 7822 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 7823 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 7824 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 7825 #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 7826 #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 7827 #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 7828 #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 7829 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 7830 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 7831 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8 7832 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3 7833 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 7834 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 7835 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 7836 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 7837 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 7838 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 7839 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 7840 #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa 7841 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 7842 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 7843 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 7844 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 7845 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 7846 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 7847 #define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 7848 #define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 7849 #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 7850 #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 7851 #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 7852 #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 7853 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 7854 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 7855 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 7856 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 7857 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 7858 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 7859 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 7860 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 7861 #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 7862 #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 7863 #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 7864 #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 7865 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 7866 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 7867 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8 7868 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3 7869 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 7870 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 7871 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 7872 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 7873 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 7874 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 7875 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 7876 #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa 7877 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 7878 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 7879 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 7880 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 7881 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 7882 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 7883 #define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 7884 #define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 7885 #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 7886 #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 7887 #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 7888 #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 7889 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 7890 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 7891 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 7892 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 7893 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 7894 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 7895 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 7896 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 7897 #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 7898 #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 7899 #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 7900 #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 7901 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 7902 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 7903 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8 7904 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3 7905 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 7906 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 7907 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 7908 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 7909 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 7910 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 7911 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 7912 #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa 7913 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 7914 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 7915 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 7916 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 7917 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 7918 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 7919 #define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 7920 #define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 7921 #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 7922 #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 7923 #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 7924 #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 7925 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 7926 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 7927 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 7928 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 7929 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 7930 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 7931 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 7932 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 7933 #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 7934 #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 7935 #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 7936 #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 7937 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 7938 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 7939 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8 7940 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3 7941 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 7942 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 7943 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 7944 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 7945 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 7946 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 7947 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 7948 #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa 7949 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 7950 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 7951 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 7952 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 7953 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 7954 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 7955 #define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 7956 #define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 7957 #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 7958 #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 7959 #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 7960 #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 7961 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 7962 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 7963 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 7964 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 7965 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 7966 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 7967 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 7968 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 7969 #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 7970 #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 7971 #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 7972 #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 7973 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 7974 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 7975 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8 7976 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3 7977 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 7978 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 7979 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 7980 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 7981 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 7982 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 7983 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 7984 #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa 7985 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 7986 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 7987 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 7988 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 7989 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 7990 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 7991 #define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 7992 #define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 7993 #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 7994 #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 7995 #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 7996 #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 7997 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 7998 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 7999 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 8000 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 8001 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 8002 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 8003 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 8004 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 8005 #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 8006 #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 8007 #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 8008 #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 8009 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 8010 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 8011 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8 8012 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3 8013 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 8014 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 8015 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 8016 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 8017 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 8018 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 8019 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 8020 #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa 8021 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 8022 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 8023 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 8024 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 8025 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 8026 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 8027 #define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 8028 #define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 8029 #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 8030 #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 8031 #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 8032 #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 8033 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 8034 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 8035 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 8036 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 8037 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 8038 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 8039 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 8040 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 8041 #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 8042 #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 8043 #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 8044 #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 8045 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 8046 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 8047 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8 8048 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3 8049 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 8050 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 8051 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 8052 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 8053 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 8054 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 8055 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 8056 #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa 8057 #define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff 8058 #define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 8059 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x1 8060 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x0 8061 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x2 8062 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x1 8063 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x4 8064 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x2 8065 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x8 8066 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x3 8067 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x10 8068 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x4 8069 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x20 8070 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x5 8071 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x40 8072 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x6 8073 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x80 8074 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x7 8075 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x100 8076 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x8 8077 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x200 8078 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x9 8079 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x400 8080 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0xa 8081 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x800 8082 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0xb 8083 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x1000 8084 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0xc 8085 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x2000 8086 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0xd 8087 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x4000 8088 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0xe 8089 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x8000 8090 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0xf 8091 #define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff 8092 #define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0 8093 #define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff 8094 #define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0 8095 #define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1 8096 #define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0 8097 #define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2 8098 #define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1 8099 #define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4 8100 #define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2 8101 #define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8 8102 #define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3 8103 #define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10 8104 #define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4 8105 #define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20 8106 #define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5 8107 #define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40 8108 #define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6 8109 #define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80 8110 #define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7 8111 #define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x100 8112 #define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8 8113 #define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200 8114 #define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9 8115 #define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400 8116 #define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa 8117 #define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800 8118 #define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb 8119 #define PB0_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000 8120 #define PB0_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc 8121 #define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000 8122 #define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd 8123 #define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000 8124 #define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe 8125 #define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000 8126 #define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf 8127 #define PB0_PIF_CNTL__TXGND_TIME_MASK 0x10000 8128 #define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x10 8129 #define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000 8130 #define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11 8131 #define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000 8132 #define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14 8133 #define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000 8134 #define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17 8135 #define PB0_PIF_CNTL__RXEN_GATER_MASK 0xf000000 8136 #define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x18 8137 #define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000 8138 #define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c 8139 #define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000 8140 #define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d 8141 #define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000 8142 #define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e 8143 #define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x1 8144 #define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0 8145 #define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x2 8146 #define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1 8147 #define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x4 8148 #define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2 8149 #define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x8 8150 #define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3 8151 #define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x10 8152 #define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4 8153 #define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x20 8154 #define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5 8155 #define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x40 8156 #define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6 8157 #define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x80 8158 #define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7 8159 #define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x100 8160 #define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8 8161 #define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x200 8162 #define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9 8163 #define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x400 8164 #define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa 8165 #define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x800 8166 #define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb 8167 #define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000 8168 #define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10 8169 #define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000 8170 #define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11 8171 #define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000 8172 #define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14 8173 #define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x2000000 8174 #define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x19 8175 #define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7 8176 #define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0 8177 #define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8 8178 #define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3 8179 #define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70 8180 #define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4 8181 #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380 8182 #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7 8183 #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00 8184 #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa 8185 #define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000 8186 #define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10 8187 #define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000 8188 #define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18 8189 #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000 8190 #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c 8191 #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000 8192 #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d 8193 #define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7 8194 #define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0 8195 #define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8 8196 #define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3 8197 #define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70 8198 #define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4 8199 #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380 8200 #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7 8201 #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00 8202 #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa 8203 #define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000 8204 #define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10 8205 #define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000 8206 #define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18 8207 #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000 8208 #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c 8209 #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000 8210 #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d 8211 #define PB0_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1 8212 #define PB0_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0 8213 #define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6 8214 #define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1 8215 #define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8 8216 #define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3 8217 #define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10 8218 #define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4 8219 #define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20 8220 #define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5 8221 #define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40 8222 #define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6 8223 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80 8224 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7 8225 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100 8226 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8 8227 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200 8228 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9 8229 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400 8230 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa 8231 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800 8232 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb 8233 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000 8234 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc 8235 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000 8236 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd 8237 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000 8238 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe 8239 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000 8240 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf 8241 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000 8242 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10 8243 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000 8244 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11 8245 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000 8246 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12 8247 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000 8248 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13 8249 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000 8250 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14 8251 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000 8252 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15 8253 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000 8254 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16 8255 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000 8256 #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17 8257 #define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000 8258 #define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18 8259 #define PB0_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000 8260 #define PB0_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b 8261 #define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000 8262 #define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c 8263 #define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000 8264 #define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d 8265 #define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000 8266 #define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e 8267 #define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000 8268 #define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f 8269 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1 8270 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0 8271 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2 8272 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1 8273 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4 8274 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2 8275 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8 8276 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3 8277 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10 8278 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4 8279 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20 8280 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5 8281 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40 8282 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6 8283 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80 8284 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7 8285 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100 8286 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8 8287 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200 8288 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9 8289 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400 8290 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa 8291 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800 8292 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb 8293 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000 8294 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc 8295 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000 8296 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd 8297 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000 8298 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe 8299 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000 8300 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf 8301 #define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1 8302 #define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0 8303 #define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x2 8304 #define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1 8305 #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4 8306 #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2 8307 #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8 8308 #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3 8309 #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10 8310 #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4 8311 #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20 8312 #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5 8313 #define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40 8314 #define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6 8315 #define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x100 8316 #define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8 8317 #define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x200 8318 #define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9 8319 #define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x400 8320 #define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa 8321 #define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x800 8322 #define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb 8323 #define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000 8324 #define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc 8325 #define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000 8326 #define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd 8327 #define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000 8328 #define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe 8329 #define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000 8330 #define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf 8331 #define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000 8332 #define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10 8333 #define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000 8334 #define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11 8335 #define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000 8336 #define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12 8337 #define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000 8338 #define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13 8339 #define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000 8340 #define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14 8341 #define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000 8342 #define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15 8343 #define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000 8344 #define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16 8345 #define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000 8346 #define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17 8347 #define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000 8348 #define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18 8349 #define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000 8350 #define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19 8351 #define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000 8352 #define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a 8353 #define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000 8354 #define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b 8355 #define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000 8356 #define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c 8357 #define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000 8358 #define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d 8359 #define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000 8360 #define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e 8361 #define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000 8362 #define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f 8363 #define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7 8364 #define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0 8365 #define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8 8366 #define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3 8367 #define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70 8368 #define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4 8369 #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380 8370 #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7 8371 #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00 8372 #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa 8373 #define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000 8374 #define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10 8375 #define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000 8376 #define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18 8377 #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000 8378 #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c 8379 #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000 8380 #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d 8381 #define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7 8382 #define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0 8383 #define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8 8384 #define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3 8385 #define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70 8386 #define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4 8387 #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380 8388 #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7 8389 #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00 8390 #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa 8391 #define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000 8392 #define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10 8393 #define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000 8394 #define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18 8395 #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000 8396 #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c 8397 #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000 8398 #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d 8399 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1 8400 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0 8401 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2 8402 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1 8403 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4 8404 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2 8405 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8 8406 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3 8407 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10 8408 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4 8409 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20 8410 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5 8411 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40 8412 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6 8413 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80 8414 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7 8415 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100 8416 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8 8417 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200 8418 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9 8419 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400 8420 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa 8421 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800 8422 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb 8423 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000 8424 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc 8425 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000 8426 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd 8427 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000 8428 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe 8429 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000 8430 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf 8431 #define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff 8432 #define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0 8433 #define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff 8434 #define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0 8435 #define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff 8436 #define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0 8437 #define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff 8438 #define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0 8439 #define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff 8440 #define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0 8441 #define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff 8442 #define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0 8443 #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1 8444 #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0 8445 #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe 8446 #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1 8447 #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10 8448 #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4 8449 #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0 8450 #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5 8451 #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100 8452 #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8 8453 #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200 8454 #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9 8455 #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400 8456 #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa 8457 #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800 8458 #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb 8459 #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000 8460 #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe 8461 #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000 8462 #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf 8463 #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1 8464 #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0 8465 #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe 8466 #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1 8467 #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10 8468 #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4 8469 #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0 8470 #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5 8471 #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100 8472 #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8 8473 #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200 8474 #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9 8475 #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400 8476 #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa 8477 #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800 8478 #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb 8479 #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000 8480 #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe 8481 #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000 8482 #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf 8483 #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1 8484 #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0 8485 #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe 8486 #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1 8487 #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10 8488 #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4 8489 #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0 8490 #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5 8491 #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100 8492 #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8 8493 #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200 8494 #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9 8495 #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400 8496 #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa 8497 #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800 8498 #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb 8499 #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000 8500 #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe 8501 #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000 8502 #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf 8503 #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1 8504 #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0 8505 #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe 8506 #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1 8507 #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10 8508 #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4 8509 #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0 8510 #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5 8511 #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100 8512 #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8 8513 #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200 8514 #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9 8515 #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400 8516 #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa 8517 #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800 8518 #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb 8519 #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000 8520 #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe 8521 #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000 8522 #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf 8523 #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1 8524 #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0 8525 #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe 8526 #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1 8527 #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10 8528 #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4 8529 #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0 8530 #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5 8531 #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100 8532 #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8 8533 #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200 8534 #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9 8535 #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400 8536 #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa 8537 #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800 8538 #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb 8539 #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000 8540 #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe 8541 #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000 8542 #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf 8543 #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1 8544 #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0 8545 #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe 8546 #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1 8547 #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10 8548 #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4 8549 #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0 8550 #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5 8551 #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100 8552 #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8 8553 #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200 8554 #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9 8555 #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400 8556 #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa 8557 #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800 8558 #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb 8559 #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000 8560 #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe 8561 #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000 8562 #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf 8563 #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1 8564 #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0 8565 #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe 8566 #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1 8567 #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10 8568 #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4 8569 #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0 8570 #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5 8571 #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100 8572 #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8 8573 #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200 8574 #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9 8575 #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400 8576 #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa 8577 #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800 8578 #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb 8579 #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000 8580 #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe 8581 #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000 8582 #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf 8583 #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1 8584 #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0 8585 #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe 8586 #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1 8587 #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10 8588 #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4 8589 #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0 8590 #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5 8591 #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100 8592 #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8 8593 #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200 8594 #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9 8595 #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400 8596 #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa 8597 #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800 8598 #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb 8599 #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000 8600 #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe 8601 #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000 8602 #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf 8603 #define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1 8604 #define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0 8605 #define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2 8606 #define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1 8607 #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4 8608 #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2 8609 #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8 8610 #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3 8611 #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10 8612 #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4 8613 #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20 8614 #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5 8615 #define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40 8616 #define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6 8617 #define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700 8618 #define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8 8619 #define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1 8620 #define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0 8621 #define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2 8622 #define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1 8623 #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4 8624 #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2 8625 #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8 8626 #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3 8627 #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10 8628 #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4 8629 #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20 8630 #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5 8631 #define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40 8632 #define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6 8633 #define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700 8634 #define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8 8635 #define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1 8636 #define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0 8637 #define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2 8638 #define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1 8639 #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4 8640 #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2 8641 #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8 8642 #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3 8643 #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10 8644 #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4 8645 #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20 8646 #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5 8647 #define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40 8648 #define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6 8649 #define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700 8650 #define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8 8651 #define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1 8652 #define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0 8653 #define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2 8654 #define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1 8655 #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4 8656 #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2 8657 #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8 8658 #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3 8659 #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10 8660 #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4 8661 #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20 8662 #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5 8663 #define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40 8664 #define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6 8665 #define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700 8666 #define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8 8667 #define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1 8668 #define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0 8669 #define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2 8670 #define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1 8671 #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4 8672 #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2 8673 #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8 8674 #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3 8675 #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10 8676 #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4 8677 #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20 8678 #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5 8679 #define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40 8680 #define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6 8681 #define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700 8682 #define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8 8683 #define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1 8684 #define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0 8685 #define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2 8686 #define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1 8687 #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4 8688 #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2 8689 #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8 8690 #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3 8691 #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10 8692 #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4 8693 #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20 8694 #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5 8695 #define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40 8696 #define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6 8697 #define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700 8698 #define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8 8699 #define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1 8700 #define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0 8701 #define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2 8702 #define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1 8703 #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4 8704 #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2 8705 #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8 8706 #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3 8707 #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10 8708 #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4 8709 #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20 8710 #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5 8711 #define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40 8712 #define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6 8713 #define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700 8714 #define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8 8715 #define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1 8716 #define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0 8717 #define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2 8718 #define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1 8719 #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4 8720 #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2 8721 #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8 8722 #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3 8723 #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10 8724 #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4 8725 #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20 8726 #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5 8727 #define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40 8728 #define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6 8729 #define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700 8730 #define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8 8731 #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1 8732 #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0 8733 #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe 8734 #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1 8735 #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10 8736 #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4 8737 #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0 8738 #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5 8739 #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100 8740 #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8 8741 #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200 8742 #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9 8743 #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400 8744 #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa 8745 #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800 8746 #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb 8747 #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000 8748 #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe 8749 #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000 8750 #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf 8751 #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1 8752 #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0 8753 #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe 8754 #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1 8755 #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10 8756 #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4 8757 #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0 8758 #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5 8759 #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100 8760 #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8 8761 #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200 8762 #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9 8763 #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400 8764 #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa 8765 #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800 8766 #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb 8767 #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000 8768 #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe 8769 #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000 8770 #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf 8771 #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1 8772 #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0 8773 #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe 8774 #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1 8775 #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10 8776 #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4 8777 #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0 8778 #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5 8779 #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100 8780 #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8 8781 #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200 8782 #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9 8783 #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400 8784 #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa 8785 #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800 8786 #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb 8787 #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000 8788 #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe 8789 #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000 8790 #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf 8791 #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1 8792 #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0 8793 #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe 8794 #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1 8795 #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10 8796 #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4 8797 #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0 8798 #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5 8799 #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100 8800 #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8 8801 #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200 8802 #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9 8803 #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400 8804 #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa 8805 #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800 8806 #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb 8807 #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000 8808 #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe 8809 #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000 8810 #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf 8811 #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1 8812 #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0 8813 #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe 8814 #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1 8815 #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10 8816 #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4 8817 #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0 8818 #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5 8819 #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100 8820 #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8 8821 #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200 8822 #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9 8823 #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400 8824 #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa 8825 #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800 8826 #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb 8827 #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000 8828 #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe 8829 #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000 8830 #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf 8831 #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1 8832 #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0 8833 #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe 8834 #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1 8835 #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10 8836 #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4 8837 #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0 8838 #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5 8839 #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100 8840 #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8 8841 #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200 8842 #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9 8843 #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400 8844 #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa 8845 #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800 8846 #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb 8847 #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000 8848 #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe 8849 #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000 8850 #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf 8851 #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1 8852 #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0 8853 #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe 8854 #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1 8855 #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10 8856 #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4 8857 #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0 8858 #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5 8859 #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100 8860 #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8 8861 #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200 8862 #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9 8863 #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400 8864 #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa 8865 #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800 8866 #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb 8867 #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000 8868 #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe 8869 #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000 8870 #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf 8871 #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1 8872 #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0 8873 #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe 8874 #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1 8875 #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10 8876 #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4 8877 #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0 8878 #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5 8879 #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100 8880 #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8 8881 #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200 8882 #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9 8883 #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400 8884 #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa 8885 #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800 8886 #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb 8887 #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000 8888 #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe 8889 #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000 8890 #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf 8891 #define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1 8892 #define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0 8893 #define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2 8894 #define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1 8895 #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4 8896 #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2 8897 #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8 8898 #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3 8899 #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10 8900 #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4 8901 #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20 8902 #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5 8903 #define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40 8904 #define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6 8905 #define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700 8906 #define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8 8907 #define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1 8908 #define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0 8909 #define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2 8910 #define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1 8911 #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4 8912 #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2 8913 #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8 8914 #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3 8915 #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10 8916 #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4 8917 #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20 8918 #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5 8919 #define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40 8920 #define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6 8921 #define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700 8922 #define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8 8923 #define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1 8924 #define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0 8925 #define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2 8926 #define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1 8927 #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4 8928 #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2 8929 #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8 8930 #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3 8931 #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10 8932 #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4 8933 #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20 8934 #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5 8935 #define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40 8936 #define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6 8937 #define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700 8938 #define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8 8939 #define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1 8940 #define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0 8941 #define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2 8942 #define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1 8943 #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4 8944 #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2 8945 #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8 8946 #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3 8947 #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10 8948 #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4 8949 #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20 8950 #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5 8951 #define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40 8952 #define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6 8953 #define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700 8954 #define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8 8955 #define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1 8956 #define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0 8957 #define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2 8958 #define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1 8959 #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4 8960 #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2 8961 #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8 8962 #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3 8963 #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10 8964 #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4 8965 #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20 8966 #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5 8967 #define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40 8968 #define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6 8969 #define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700 8970 #define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8 8971 #define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1 8972 #define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0 8973 #define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2 8974 #define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1 8975 #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4 8976 #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2 8977 #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8 8978 #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3 8979 #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10 8980 #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4 8981 #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20 8982 #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5 8983 #define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40 8984 #define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6 8985 #define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700 8986 #define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8 8987 #define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1 8988 #define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0 8989 #define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2 8990 #define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1 8991 #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4 8992 #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2 8993 #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8 8994 #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3 8995 #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10 8996 #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4 8997 #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20 8998 #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5 8999 #define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40 9000 #define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6 9001 #define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700 9002 #define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8 9003 #define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1 9004 #define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0 9005 #define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2 9006 #define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1 9007 #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4 9008 #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2 9009 #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8 9010 #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3 9011 #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10 9012 #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4 9013 #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20 9014 #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5 9015 #define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40 9016 #define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6 9017 #define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700 9018 #define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8 9019 #define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff 9020 #define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 9021 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x1 9022 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x0 9023 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x2 9024 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x1 9025 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x4 9026 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x2 9027 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x8 9028 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x3 9029 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x10 9030 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x4 9031 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x20 9032 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x5 9033 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x40 9034 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x6 9035 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x80 9036 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x7 9037 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x100 9038 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x8 9039 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x200 9040 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x9 9041 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x400 9042 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0xa 9043 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x800 9044 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0xb 9045 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x1000 9046 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0xc 9047 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x2000 9048 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0xd 9049 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x4000 9050 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0xe 9051 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x8000 9052 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0xf 9053 #define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff 9054 #define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0 9055 #define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff 9056 #define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0 9057 #define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1 9058 #define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0 9059 #define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2 9060 #define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1 9061 #define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4 9062 #define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2 9063 #define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8 9064 #define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3 9065 #define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10 9066 #define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4 9067 #define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20 9068 #define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5 9069 #define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40 9070 #define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6 9071 #define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80 9072 #define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7 9073 #define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x100 9074 #define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8 9075 #define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200 9076 #define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9 9077 #define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400 9078 #define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa 9079 #define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800 9080 #define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb 9081 #define PB1_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000 9082 #define PB1_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc 9083 #define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000 9084 #define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd 9085 #define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000 9086 #define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe 9087 #define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000 9088 #define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf 9089 #define PB1_PIF_CNTL__TXGND_TIME_MASK 0x10000 9090 #define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x10 9091 #define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000 9092 #define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11 9093 #define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000 9094 #define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14 9095 #define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000 9096 #define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17 9097 #define PB1_PIF_CNTL__RXEN_GATER_MASK 0xf000000 9098 #define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x18 9099 #define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000 9100 #define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c 9101 #define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000 9102 #define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d 9103 #define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000 9104 #define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e 9105 #define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x1 9106 #define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0 9107 #define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x2 9108 #define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1 9109 #define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x4 9110 #define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2 9111 #define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x8 9112 #define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3 9113 #define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x10 9114 #define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4 9115 #define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x20 9116 #define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5 9117 #define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x40 9118 #define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6 9119 #define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x80 9120 #define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7 9121 #define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x100 9122 #define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8 9123 #define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x200 9124 #define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9 9125 #define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x400 9126 #define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa 9127 #define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x800 9128 #define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb 9129 #define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000 9130 #define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10 9131 #define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000 9132 #define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11 9133 #define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000 9134 #define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14 9135 #define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x2000000 9136 #define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x19 9137 #define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7 9138 #define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0 9139 #define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8 9140 #define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3 9141 #define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70 9142 #define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4 9143 #define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380 9144 #define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7 9145 #define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00 9146 #define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa 9147 #define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000 9148 #define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10 9149 #define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000 9150 #define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18 9151 #define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000 9152 #define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c 9153 #define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000 9154 #define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d 9155 #define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7 9156 #define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0 9157 #define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8 9158 #define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3 9159 #define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70 9160 #define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4 9161 #define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380 9162 #define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7 9163 #define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00 9164 #define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa 9165 #define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000 9166 #define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10 9167 #define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000 9168 #define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18 9169 #define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000 9170 #define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c 9171 #define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000 9172 #define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d 9173 #define PB1_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1 9174 #define PB1_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0 9175 #define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6 9176 #define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1 9177 #define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8 9178 #define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3 9179 #define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10 9180 #define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4 9181 #define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20 9182 #define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5 9183 #define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40 9184 #define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6 9185 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80 9186 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7 9187 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100 9188 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8 9189 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200 9190 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9 9191 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400 9192 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa 9193 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800 9194 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb 9195 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000 9196 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc 9197 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000 9198 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd 9199 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000 9200 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe 9201 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000 9202 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf 9203 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000 9204 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10 9205 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000 9206 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11 9207 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000 9208 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12 9209 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000 9210 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13 9211 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000 9212 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14 9213 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000 9214 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15 9215 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000 9216 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16 9217 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000 9218 #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17 9219 #define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000 9220 #define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18 9221 #define PB1_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000 9222 #define PB1_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b 9223 #define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000 9224 #define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c 9225 #define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000 9226 #define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d 9227 #define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000 9228 #define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e 9229 #define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000 9230 #define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f 9231 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1 9232 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0 9233 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2 9234 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1 9235 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4 9236 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2 9237 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8 9238 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3 9239 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10 9240 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4 9241 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20 9242 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5 9243 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40 9244 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6 9245 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80 9246 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7 9247 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100 9248 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8 9249 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200 9250 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9 9251 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400 9252 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa 9253 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800 9254 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb 9255 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000 9256 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc 9257 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000 9258 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd 9259 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000 9260 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe 9261 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000 9262 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf 9263 #define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1 9264 #define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0 9265 #define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x2 9266 #define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1 9267 #define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4 9268 #define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2 9269 #define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8 9270 #define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3 9271 #define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10 9272 #define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4 9273 #define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20 9274 #define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5 9275 #define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40 9276 #define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6 9277 #define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x100 9278 #define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8 9279 #define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x200 9280 #define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9 9281 #define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x400 9282 #define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa 9283 #define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x800 9284 #define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb 9285 #define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000 9286 #define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc 9287 #define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000 9288 #define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd 9289 #define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000 9290 #define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe 9291 #define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000 9292 #define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf 9293 #define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000 9294 #define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10 9295 #define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000 9296 #define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11 9297 #define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000 9298 #define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12 9299 #define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000 9300 #define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13 9301 #define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000 9302 #define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14 9303 #define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000 9304 #define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15 9305 #define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000 9306 #define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16 9307 #define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000 9308 #define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17 9309 #define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000 9310 #define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18 9311 #define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000 9312 #define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19 9313 #define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000 9314 #define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a 9315 #define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000 9316 #define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b 9317 #define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000 9318 #define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c 9319 #define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000 9320 #define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d 9321 #define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000 9322 #define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e 9323 #define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000 9324 #define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f 9325 #define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7 9326 #define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0 9327 #define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8 9328 #define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3 9329 #define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70 9330 #define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4 9331 #define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380 9332 #define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7 9333 #define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00 9334 #define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa 9335 #define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000 9336 #define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10 9337 #define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000 9338 #define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18 9339 #define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000 9340 #define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c 9341 #define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000 9342 #define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d 9343 #define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7 9344 #define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0 9345 #define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8 9346 #define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3 9347 #define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70 9348 #define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4 9349 #define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380 9350 #define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7 9351 #define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00 9352 #define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa 9353 #define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000 9354 #define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10 9355 #define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000 9356 #define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18 9357 #define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000 9358 #define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c 9359 #define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000 9360 #define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d 9361 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1 9362 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0 9363 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2 9364 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1 9365 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4 9366 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2 9367 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8 9368 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3 9369 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10 9370 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4 9371 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20 9372 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5 9373 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40 9374 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6 9375 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80 9376 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7 9377 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100 9378 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8 9379 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200 9380 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9 9381 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400 9382 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa 9383 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800 9384 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb 9385 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000 9386 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc 9387 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000 9388 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd 9389 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000 9390 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe 9391 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000 9392 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf 9393 #define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff 9394 #define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0 9395 #define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff 9396 #define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0 9397 #define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff 9398 #define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0 9399 #define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff 9400 #define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0 9401 #define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff 9402 #define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0 9403 #define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff 9404 #define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0 9405 #define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1 9406 #define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0 9407 #define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe 9408 #define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1 9409 #define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10 9410 #define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4 9411 #define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0 9412 #define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5 9413 #define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100 9414 #define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8 9415 #define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200 9416 #define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9 9417 #define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400 9418 #define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa 9419 #define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800 9420 #define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb 9421 #define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000 9422 #define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe 9423 #define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000 9424 #define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf 9425 #define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1 9426 #define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0 9427 #define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe 9428 #define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1 9429 #define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10 9430 #define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4 9431 #define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0 9432 #define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5 9433 #define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100 9434 #define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8 9435 #define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200 9436 #define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9 9437 #define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400 9438 #define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa 9439 #define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800 9440 #define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb 9441 #define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000 9442 #define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe 9443 #define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000 9444 #define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf 9445 #define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1 9446 #define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0 9447 #define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe 9448 #define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1 9449 #define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10 9450 #define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4 9451 #define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0 9452 #define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5 9453 #define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100 9454 #define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8 9455 #define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200 9456 #define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9 9457 #define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400 9458 #define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa 9459 #define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800 9460 #define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb 9461 #define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000 9462 #define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe 9463 #define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000 9464 #define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf 9465 #define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1 9466 #define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0 9467 #define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe 9468 #define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1 9469 #define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10 9470 #define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4 9471 #define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0 9472 #define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5 9473 #define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100 9474 #define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8 9475 #define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200 9476 #define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9 9477 #define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400 9478 #define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa 9479 #define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800 9480 #define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb 9481 #define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000 9482 #define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe 9483 #define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000 9484 #define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf 9485 #define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1 9486 #define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0 9487 #define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe 9488 #define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1 9489 #define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10 9490 #define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4 9491 #define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0 9492 #define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5 9493 #define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100 9494 #define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8 9495 #define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200 9496 #define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9 9497 #define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400 9498 #define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa 9499 #define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800 9500 #define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb 9501 #define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000 9502 #define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe 9503 #define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000 9504 #define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf 9505 #define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1 9506 #define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0 9507 #define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe 9508 #define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1 9509 #define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10 9510 #define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4 9511 #define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0 9512 #define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5 9513 #define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100 9514 #define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8 9515 #define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200 9516 #define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9 9517 #define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400 9518 #define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa 9519 #define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800 9520 #define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb 9521 #define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000 9522 #define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe 9523 #define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000 9524 #define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf 9525 #define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1 9526 #define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0 9527 #define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe 9528 #define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1 9529 #define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10 9530 #define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4 9531 #define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0 9532 #define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5 9533 #define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100 9534 #define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8 9535 #define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200 9536 #define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9 9537 #define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400 9538 #define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa 9539 #define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800 9540 #define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb 9541 #define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000 9542 #define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe 9543 #define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000 9544 #define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf 9545 #define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1 9546 #define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0 9547 #define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe 9548 #define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1 9549 #define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10 9550 #define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4 9551 #define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0 9552 #define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5 9553 #define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100 9554 #define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8 9555 #define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200 9556 #define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9 9557 #define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400 9558 #define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa 9559 #define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800 9560 #define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb 9561 #define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000 9562 #define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe 9563 #define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000 9564 #define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf 9565 #define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1 9566 #define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0 9567 #define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2 9568 #define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1 9569 #define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4 9570 #define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2 9571 #define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8 9572 #define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3 9573 #define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10 9574 #define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4 9575 #define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20 9576 #define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5 9577 #define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40 9578 #define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6 9579 #define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700 9580 #define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8 9581 #define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1 9582 #define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0 9583 #define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2 9584 #define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1 9585 #define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4 9586 #define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2 9587 #define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8 9588 #define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3 9589 #define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10 9590 #define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4 9591 #define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20 9592 #define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5 9593 #define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40 9594 #define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6 9595 #define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700 9596 #define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8 9597 #define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1 9598 #define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0 9599 #define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2 9600 #define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1 9601 #define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4 9602 #define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2 9603 #define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8 9604 #define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3 9605 #define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10 9606 #define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4 9607 #define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20 9608 #define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5 9609 #define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40 9610 #define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6 9611 #define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700 9612 #define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8 9613 #define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1 9614 #define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0 9615 #define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2 9616 #define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1 9617 #define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4 9618 #define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2 9619 #define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8 9620 #define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3 9621 #define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10 9622 #define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4 9623 #define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20 9624 #define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5 9625 #define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40 9626 #define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6 9627 #define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700 9628 #define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8 9629 #define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1 9630 #define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0 9631 #define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2 9632 #define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1 9633 #define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4 9634 #define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2 9635 #define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8 9636 #define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3 9637 #define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10 9638 #define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4 9639 #define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20 9640 #define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5 9641 #define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40 9642 #define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6 9643 #define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700 9644 #define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8 9645 #define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1 9646 #define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0 9647 #define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2 9648 #define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1 9649 #define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4 9650 #define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2 9651 #define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8 9652 #define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3 9653 #define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10 9654 #define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4 9655 #define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20 9656 #define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5 9657 #define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40 9658 #define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6 9659 #define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700 9660 #define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8 9661 #define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1 9662 #define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0 9663 #define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2 9664 #define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1 9665 #define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4 9666 #define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2 9667 #define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8 9668 #define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3 9669 #define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10 9670 #define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4 9671 #define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20 9672 #define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5 9673 #define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40 9674 #define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6 9675 #define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700 9676 #define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8 9677 #define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1 9678 #define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0 9679 #define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2 9680 #define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1 9681 #define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4 9682 #define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2 9683 #define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8 9684 #define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3 9685 #define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10 9686 #define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4 9687 #define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20 9688 #define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5 9689 #define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40 9690 #define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6 9691 #define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700 9692 #define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8 9693 #define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1 9694 #define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0 9695 #define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe 9696 #define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1 9697 #define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10 9698 #define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4 9699 #define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0 9700 #define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5 9701 #define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100 9702 #define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8 9703 #define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200 9704 #define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9 9705 #define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400 9706 #define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa 9707 #define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800 9708 #define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb 9709 #define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000 9710 #define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe 9711 #define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000 9712 #define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf 9713 #define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1 9714 #define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0 9715 #define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe 9716 #define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1 9717 #define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10 9718 #define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4 9719 #define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0 9720 #define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5 9721 #define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100 9722 #define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8 9723 #define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200 9724 #define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9 9725 #define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400 9726 #define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa 9727 #define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800 9728 #define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb 9729 #define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000 9730 #define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe 9731 #define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000 9732 #define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf 9733 #define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1 9734 #define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0 9735 #define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe 9736 #define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1 9737 #define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10 9738 #define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4 9739 #define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0 9740 #define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5 9741 #define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100 9742 #define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8 9743 #define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200 9744 #define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9 9745 #define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400 9746 #define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa 9747 #define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800 9748 #define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb 9749 #define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000 9750 #define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe 9751 #define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000 9752 #define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf 9753 #define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1 9754 #define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0 9755 #define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe 9756 #define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1 9757 #define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10 9758 #define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4 9759 #define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0 9760 #define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5 9761 #define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100 9762 #define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8 9763 #define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200 9764 #define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9 9765 #define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400 9766 #define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa 9767 #define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800 9768 #define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb 9769 #define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000 9770 #define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe 9771 #define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000 9772 #define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf 9773 #define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1 9774 #define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0 9775 #define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe 9776 #define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1 9777 #define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10 9778 #define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4 9779 #define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0 9780 #define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5 9781 #define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100 9782 #define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8 9783 #define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200 9784 #define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9 9785 #define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400 9786 #define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa 9787 #define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800 9788 #define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb 9789 #define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000 9790 #define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe 9791 #define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000 9792 #define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf 9793 #define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1 9794 #define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0 9795 #define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe 9796 #define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1 9797 #define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10 9798 #define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4 9799 #define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0 9800 #define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5 9801 #define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100 9802 #define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8 9803 #define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200 9804 #define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9 9805 #define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400 9806 #define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa 9807 #define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800 9808 #define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb 9809 #define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000 9810 #define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe 9811 #define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000 9812 #define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf 9813 #define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1 9814 #define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0 9815 #define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe 9816 #define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1 9817 #define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10 9818 #define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4 9819 #define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0 9820 #define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5 9821 #define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100 9822 #define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8 9823 #define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200 9824 #define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9 9825 #define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400 9826 #define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa 9827 #define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800 9828 #define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb 9829 #define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000 9830 #define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe 9831 #define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000 9832 #define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf 9833 #define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1 9834 #define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0 9835 #define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe 9836 #define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1 9837 #define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10 9838 #define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4 9839 #define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0 9840 #define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5 9841 #define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100 9842 #define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8 9843 #define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200 9844 #define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9 9845 #define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400 9846 #define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa 9847 #define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800 9848 #define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb 9849 #define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000 9850 #define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe 9851 #define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000 9852 #define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf 9853 #define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1 9854 #define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0 9855 #define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2 9856 #define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1 9857 #define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4 9858 #define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2 9859 #define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8 9860 #define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3 9861 #define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10 9862 #define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4 9863 #define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20 9864 #define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5 9865 #define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40 9866 #define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6 9867 #define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700 9868 #define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8 9869 #define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1 9870 #define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0 9871 #define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2 9872 #define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1 9873 #define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4 9874 #define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2 9875 #define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8 9876 #define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3 9877 #define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10 9878 #define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4 9879 #define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20 9880 #define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5 9881 #define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40 9882 #define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6 9883 #define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700 9884 #define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8 9885 #define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1 9886 #define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0 9887 #define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2 9888 #define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1 9889 #define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4 9890 #define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2 9891 #define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8 9892 #define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3 9893 #define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10 9894 #define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4 9895 #define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20 9896 #define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5 9897 #define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40 9898 #define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6 9899 #define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700 9900 #define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8 9901 #define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1 9902 #define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0 9903 #define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2 9904 #define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1 9905 #define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4 9906 #define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2 9907 #define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8 9908 #define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3 9909 #define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10 9910 #define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4 9911 #define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20 9912 #define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5 9913 #define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40 9914 #define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6 9915 #define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700 9916 #define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8 9917 #define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1 9918 #define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0 9919 #define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2 9920 #define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1 9921 #define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4 9922 #define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2 9923 #define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8 9924 #define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3 9925 #define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10 9926 #define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4 9927 #define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20 9928 #define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5 9929 #define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40 9930 #define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6 9931 #define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700 9932 #define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8 9933 #define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1 9934 #define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0 9935 #define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2 9936 #define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1 9937 #define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4 9938 #define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2 9939 #define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8 9940 #define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3 9941 #define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10 9942 #define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4 9943 #define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20 9944 #define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5 9945 #define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40 9946 #define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6 9947 #define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700 9948 #define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8 9949 #define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1 9950 #define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0 9951 #define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2 9952 #define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1 9953 #define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4 9954 #define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2 9955 #define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8 9956 #define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3 9957 #define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10 9958 #define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4 9959 #define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20 9960 #define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5 9961 #define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40 9962 #define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6 9963 #define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700 9964 #define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8 9965 #define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1 9966 #define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0 9967 #define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2 9968 #define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1 9969 #define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4 9970 #define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2 9971 #define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8 9972 #define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3 9973 #define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10 9974 #define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4 9975 #define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20 9976 #define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5 9977 #define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40 9978 #define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6 9979 #define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700 9980 #define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8 9981 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1 9982 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0 9983 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2 9984 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1 9985 #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 9986 #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 9987 #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2 9988 #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1 9989 #define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff 9990 #define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 9991 #define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 9992 #define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e 9993 #define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 9994 #define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f 9995 #define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1 9996 #define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0 9997 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1 9998 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0 9999 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2 10000 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1 10001 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1 10002 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0 10003 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2 10004 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1 10005 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4 10006 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2 10007 #define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1 10008 #define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0 10009 #define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2 10010 #define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1 10011 #define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4 10012 #define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2 10013 #define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1 10014 #define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0 10015 #define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2 10016 #define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1 10017 #define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4 10018 #define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2 10019 #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff 10020 #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0 10021 #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00 10022 #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8 10023 #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000 10024 #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10 10025 #define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000 10026 #define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18 10027 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff 10028 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0 10029 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00 10030 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8 10031 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000 10032 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10 10033 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000 10034 #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18 10035 #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff 10036 #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0 10037 #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00 10038 #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8 10039 #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000 10040 #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10 10041 #define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000 10042 #define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18 10043 #define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 10044 #define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 10045 #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1 10046 #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0 10047 #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe 10048 #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1 10049 #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10 10050 #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4 10051 #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0 10052 #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5 10053 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e 10054 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1 10055 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20 10056 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5 10057 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0 10058 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6 10059 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400 10060 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa 10061 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800 10062 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb 10063 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000 10064 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf 10065 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000 10066 #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10 10067 #define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1 10068 #define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0 10069 #define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2 10070 #define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1 10071 #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4 10072 #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2 10073 #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8 10074 #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3 10075 #define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00 10076 #define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8 10077 #define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000 10078 #define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd 10079 #define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000 10080 #define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe 10081 #define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000 10082 #define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf 10083 #define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000 10084 #define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14 10085 #define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000 10086 #define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a 10087 #define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7 10088 #define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0 10089 #define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8 10090 #define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3 10091 #define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10 10092 #define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4 10093 #define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40 10094 #define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6 10095 #define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80 10096 #define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7 10097 #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00 10098 #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8 10099 #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000 10100 #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc 10101 #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000 10102 #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd 10103 #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000 10104 #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11 10105 #define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000 10106 #define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12 10107 #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000 10108 #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13 10109 #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000 10110 #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14 10111 #define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000 10112 #define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c 10113 #define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000 10114 #define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d 10115 #define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7 10116 #define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0 10117 #define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8 10118 #define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3 10119 #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00 10120 #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8 10121 #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000 10122 #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc 10123 #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000 10124 #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd 10125 #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000 10126 #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11 10127 #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000 10128 #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12 10129 #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000 10130 #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13 10131 #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000 10132 #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14 10133 #define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000 10134 #define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c 10135 #define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7 10136 #define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0 10137 #define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8 10138 #define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3 10139 #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00 10140 #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8 10141 #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000 10142 #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc 10143 #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000 10144 #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd 10145 #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000 10146 #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11 10147 #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000 10148 #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12 10149 #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000 10150 #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13 10151 #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000 10152 #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14 10153 #define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000 10154 #define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c 10155 #define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff 10156 #define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0 10157 #define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1 10158 #define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0 10159 #define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1 10160 #define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0 10161 #define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1 10162 #define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0 10163 #define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6 10164 #define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1 10165 #define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1 10166 #define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0 10167 #define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe 10168 #define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1 10169 #define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000 10170 #define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15 10171 #define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff 10172 #define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0 10173 #define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400 10174 #define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa 10175 #define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff 10176 #define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0 10177 #define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2 10178 #define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1 10179 #define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4 10180 #define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2 10181 #define BIF_RESET_EN__COR_RESET_EN_MASK 0x8 10182 #define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3 10183 #define BIF_RESET_EN__REG_RESET_EN_MASK 0x10 10184 #define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4 10185 #define BIF_RESET_EN__STY_RESET_EN_MASK 0x20 10186 #define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5 10187 #define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40 10188 #define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6 10189 #define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80 10190 #define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7 10191 #define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100 10192 #define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8 10193 #define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200 10194 #define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9 10195 #define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400 10196 #define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa 10197 #define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800 10198 #define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb 10199 #define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000 10200 #define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc 10201 #define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000 10202 #define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12 10203 #define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000 10204 #define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14 10205 #define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000 10206 #define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15 10207 #define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000 10208 #define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16 10209 #define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000 10210 #define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17 10211 #define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000 10212 #define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18 10213 #define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000 10214 #define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19 10215 #define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000 10216 #define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a 10217 #define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000 10218 #define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c 10219 #define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000 10220 #define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e 10221 #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7 10222 #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0 10223 #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38 10224 #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3 10225 #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0 10226 #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6 10227 #define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1 10228 #define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0 10229 #define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6 10230 #define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1 10231 #define BIF_RESET_CNTL__STRAP_EN_MASK 0x1 10232 #define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0 10233 #define BIF_RESET_CNTL__RST_DONE_MASK 0x2 10234 #define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1 10235 #define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4 10236 #define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2 10237 #define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8 10238 #define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3 10239 #define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100 10240 #define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8 10241 #define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200 10242 #define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9 10243 #define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1 10244 #define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0 10245 #define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2 10246 #define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1 10247 #define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4 10248 #define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2 10249 #define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8 10250 #define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3 10251 10252 #endif /* BIF_4_1_SH_MASK_H */ 10253