1 /* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef DCE_6_0_SH_MASK_H 24 #define DCE_6_0_SH_MASK_H 25 26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL 27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL 29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L 33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L 35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 36 #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L 37 #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008 38 #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L 39 #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014 40 #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L 41 #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c 42 #define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L 43 #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002 44 #define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L 45 #define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003 46 #define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L 47 #define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006 48 #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L 49 #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018 50 #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L 51 #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010 52 #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L 53 #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014 54 #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L 55 #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004 56 #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL 57 #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000 58 #define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L 59 #define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010 60 #define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L 61 #define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012 62 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 63 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 64 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 65 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 66 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L 67 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008 68 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L 69 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c 70 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L 71 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010 72 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L 73 #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014 74 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L 75 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c 76 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L 77 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004 78 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L 79 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010 80 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L 81 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000 82 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L 83 #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008 84 #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L 85 #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000 86 #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L 87 #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008 88 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L 89 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008 90 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L 91 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010 92 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L 93 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c 94 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L 95 #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000 96 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L 97 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008 98 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL 99 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L 100 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010 101 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000 102 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L 103 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b 104 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L 105 #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018 106 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL 107 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000 108 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L 109 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f 110 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L 111 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010 112 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L 113 #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b 114 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L 115 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c 116 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L 117 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008 118 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L 119 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000 120 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L 121 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001 122 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L 123 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010 124 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L 125 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018 126 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L 127 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a 128 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L 129 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018 130 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L 131 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017 132 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L 133 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000 134 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L 135 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c 136 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L 137 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e 138 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L 139 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e 140 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L 141 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f 142 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L 143 #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b 144 #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L 145 #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000 146 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L 147 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c 148 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L 149 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a 150 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL 151 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000 152 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L 153 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016 154 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L 155 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c 156 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L 157 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f 158 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L 159 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014 160 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L 161 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f 162 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L 163 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a 164 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L 165 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010 166 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L 167 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018 168 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L 169 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008 170 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L 171 #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d 172 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L 173 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c 174 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L 175 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007 176 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L 177 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008 178 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L 179 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010 180 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL 181 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000 182 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L 183 #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e 184 #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL 185 #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000 186 #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L 187 #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010 188 #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL 189 #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000 190 #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L 191 #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018 192 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL 193 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000 194 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L 195 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008 196 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L 197 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010 198 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L 199 #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018 200 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL 201 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000 202 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L 203 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008 204 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L 205 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010 206 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L 207 #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018 208 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L 209 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010 210 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L 211 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018 212 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL 213 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000 214 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L 215 #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008 216 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL 217 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000 218 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L 219 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008 220 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L 221 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010 222 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L 223 #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018 224 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL 225 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000 226 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L 227 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008 228 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L 229 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010 230 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L 231 #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018 232 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL 233 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000 234 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L 235 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008 236 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L 237 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010 238 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L 239 #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018 240 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL 241 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000 242 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L 243 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008 244 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L 245 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010 246 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L 247 #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018 248 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL 249 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000 250 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L 251 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008 252 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L 253 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010 254 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L 255 #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018 256 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL 257 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000 258 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L 259 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008 260 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L 261 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010 262 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L 263 #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018 264 #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L 265 #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006 266 #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L 267 #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007 268 #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L 269 #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a 270 #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L 271 #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006 272 #define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L 273 #define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000 274 #define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L 275 #define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007 276 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL 277 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000 278 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L 279 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008 280 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L 281 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010 282 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L 283 #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018 284 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL 285 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000 286 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L 287 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008 288 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L 289 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010 290 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L 291 #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018 292 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L 293 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010 294 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L 295 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018 296 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL 297 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000 298 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L 299 #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008 300 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL 301 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000 302 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L 303 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008 304 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L 305 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010 306 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L 307 #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018 308 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL 309 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000 310 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L 311 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008 312 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L 313 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010 314 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L 315 #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018 316 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL 317 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000 318 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L 319 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008 320 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L 321 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010 322 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L 323 #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018 324 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL 325 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000 326 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L 327 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008 328 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L 329 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010 330 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L 331 #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018 332 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL 333 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000 334 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L 335 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008 336 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L 337 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010 338 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L 339 #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018 340 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL 341 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000 342 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L 343 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008 344 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L 345 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010 346 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L 347 #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018 348 #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L 349 #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c 350 #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL 351 #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000 352 #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L 353 #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008 354 #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L 355 #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f 356 #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL 357 #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000 358 #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L 359 #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018 360 #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL 361 #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000 362 #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL 363 #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000 364 #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL 365 #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000 366 #define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L 367 #define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004 368 #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L 369 #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018 370 #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L 371 #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e 372 #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L 373 #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008 374 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L 375 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002 376 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L 377 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003 378 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L 379 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e 380 #define ATTR00__ATTR_PAL_MASK 0x0000003fL 381 #define ATTR00__ATTR_PAL__SHIFT 0x00000000 382 #define ATTR01__ATTR_PAL_MASK 0x0000003fL 383 #define ATTR01__ATTR_PAL__SHIFT 0x00000000 384 #define ATTR02__ATTR_PAL_MASK 0x0000003fL 385 #define ATTR02__ATTR_PAL__SHIFT 0x00000000 386 #define ATTR03__ATTR_PAL_MASK 0x0000003fL 387 #define ATTR03__ATTR_PAL__SHIFT 0x00000000 388 #define ATTR04__ATTR_PAL_MASK 0x0000003fL 389 #define ATTR04__ATTR_PAL__SHIFT 0x00000000 390 #define ATTR05__ATTR_PAL_MASK 0x0000003fL 391 #define ATTR05__ATTR_PAL__SHIFT 0x00000000 392 #define ATTR06__ATTR_PAL_MASK 0x0000003fL 393 #define ATTR06__ATTR_PAL__SHIFT 0x00000000 394 #define ATTR07__ATTR_PAL_MASK 0x0000003fL 395 #define ATTR07__ATTR_PAL__SHIFT 0x00000000 396 #define ATTR08__ATTR_PAL_MASK 0x0000003fL 397 #define ATTR08__ATTR_PAL__SHIFT 0x00000000 398 #define ATTR09__ATTR_PAL_MASK 0x0000003fL 399 #define ATTR09__ATTR_PAL__SHIFT 0x00000000 400 #define ATTR0A__ATTR_PAL_MASK 0x0000003fL 401 #define ATTR0A__ATTR_PAL__SHIFT 0x00000000 402 #define ATTR0B__ATTR_PAL_MASK 0x0000003fL 403 #define ATTR0B__ATTR_PAL__SHIFT 0x00000000 404 #define ATTR0C__ATTR_PAL_MASK 0x0000003fL 405 #define ATTR0C__ATTR_PAL__SHIFT 0x00000000 406 #define ATTR0D__ATTR_PAL_MASK 0x0000003fL 407 #define ATTR0D__ATTR_PAL__SHIFT 0x00000000 408 #define ATTR0E__ATTR_PAL_MASK 0x0000003fL 409 #define ATTR0E__ATTR_PAL__SHIFT 0x00000000 410 #define ATTR0F__ATTR_PAL_MASK 0x0000003fL 411 #define ATTR0F__ATTR_PAL__SHIFT 0x00000000 412 #define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L 413 #define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003 414 #define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L 415 #define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007 416 #define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L 417 #define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000 418 #define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L 419 #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002 420 #define ATTR10__ATTR_MONO_EN_MASK 0x00000002L 421 #define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001 422 #define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L 423 #define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005 424 #define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L 425 #define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006 426 #define ATTR11__ATTR_OVSC_MASK 0x000000ffL 427 #define ATTR11__ATTR_OVSC__SHIFT 0x00000000 428 #define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL 429 #define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000 430 #define ATTR12__ATTR_VSMUX_MASK 0x00000030L 431 #define ATTR12__ATTR_VSMUX__SHIFT 0x00000004 432 #define ATTR13__ATTR_PPAN_MASK 0x0000000fL 433 #define ATTR13__ATTR_PPAN__SHIFT 0x00000000 434 #define ATTR14__ATTR_CSEL1_MASK 0x00000003L 435 #define ATTR14__ATTR_CSEL1__SHIFT 0x00000000 436 #define ATTR14__ATTR_CSEL2_MASK 0x0000000cL 437 #define ATTR14__ATTR_CSEL2__SHIFT 0x00000002 438 #define ATTRDR__ATTR_DATA_MASK 0x000000ffL 439 #define ATTRDR__ATTR_DATA__SHIFT 0x00000000 440 #define ATTRDW__ATTR_DATA_MASK 0x000000ffL 441 #define ATTRDW__ATTR_DATA__SHIFT 0x00000000 442 #define ATTRX__ATTR_IDX_MASK 0x0000001fL 443 #define ATTRX__ATTR_IDX__SHIFT 0x00000000 444 #define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L 445 #define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005 446 #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 447 #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 448 #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L 449 #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 450 #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 451 #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 452 #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 453 #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 454 #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 455 #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 456 #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L 457 #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 458 #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 459 #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 460 #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 461 #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 462 #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 463 #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 464 #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L 465 #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 466 #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 467 #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 468 #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 469 #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 470 #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 471 #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 472 #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L 473 #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 474 #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 475 #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 476 #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 477 #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 478 #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 479 #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 480 #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L 481 #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 482 #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 483 #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 484 #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 485 #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 486 #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 487 #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 488 #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L 489 #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 490 #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 491 #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 492 #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 493 #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 494 #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 495 #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 496 #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L 497 #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 498 #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 499 #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 500 #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 501 #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 502 #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 503 #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 504 #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L 505 #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 506 #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 507 #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 508 #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 509 #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 510 #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 511 #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 512 #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L 513 #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 514 #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 515 #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 516 #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 517 #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 518 #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 519 #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 520 #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L 521 #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 522 #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 523 #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 524 #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 525 #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 526 #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 527 #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 528 #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L 529 #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 530 #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 531 #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 532 #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 533 #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 534 #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 535 #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 536 #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L 537 #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 538 #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 539 #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 540 #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 541 #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 542 #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 543 #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 544 #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L 545 #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 546 #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 547 #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 548 #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 549 #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 550 #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 551 #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 552 #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L 553 #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 554 #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 555 #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 556 #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 557 #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 558 #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L 559 #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000 560 #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L 561 #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019 562 #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L 563 #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018 564 #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L 565 #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018 566 #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L 567 #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a 568 #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L 569 #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008 570 #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL 571 #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002 572 #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L 573 #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011 574 #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L 575 #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010 576 #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L 577 #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010 578 #define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L 579 #define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d 580 #define AUX_CONTROL__AUX_EN_MASK 0x00000001L 581 #define AUX_CONTROL__AUX_EN__SHIFT 0x00000000 582 #define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L 583 #define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014 584 #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L 585 #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010 586 #define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L 587 #define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018 588 #define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L 589 #define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008 590 #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L 591 #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c 592 #define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L 593 #define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012 594 #define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L 595 #define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c 596 #define AUX_CONTROL__SPARE_0_MASK 0x40000000L 597 #define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e 598 #define AUX_CONTROL__SPARE_1_MASK 0x80000000L 599 #define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f 600 #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L 601 #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011 602 #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L 603 #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012 604 #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L 605 #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013 606 #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L 607 #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c 608 #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L 609 #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c 610 #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L 611 #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014 612 #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L 613 #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008 614 #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L 615 #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004 616 #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L 617 #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018 618 #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L 619 #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010 620 #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL 621 #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000 622 #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L 623 #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010 624 #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L 625 #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015 626 #define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L 627 #define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000 628 #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L 629 #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008 630 #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L 631 #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000 632 #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L 633 #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008 634 #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L 635 #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004 636 #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L 637 #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010 638 #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L 639 #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000 640 #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L 641 #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000 642 #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L 643 #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010 644 #define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L 645 #define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004 646 #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L 647 #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000 648 #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L 649 #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005 650 #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L 651 #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004 652 #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L 653 #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006 654 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L 655 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001 656 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L 657 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000 658 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L 659 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002 660 #define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L 661 #define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008 662 #define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L 663 #define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010 664 #define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L 665 #define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d 666 #define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L 667 #define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000 668 #define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L 669 #define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009 670 #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L 671 #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b 672 #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L 673 #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018 674 #define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L 675 #define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001 676 #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L 677 #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013 678 #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L 679 #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e 680 #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L 681 #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c 682 #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L 683 #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008 684 #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L 685 #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a 686 #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L 687 #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016 688 #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L 689 #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017 690 #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L 691 #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014 692 #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L 693 #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012 694 #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L 695 #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011 696 #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L 697 #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007 698 #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L 699 #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004 700 #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L 701 #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f 702 #define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L 703 #define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e 704 #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L 705 #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a 706 #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L 707 #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009 708 #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L 709 #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008 710 #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L 711 #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000 712 #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L 713 #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c 714 #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L 715 #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018 716 #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L 717 #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014 718 #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L 719 #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010 720 #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L 721 #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a 722 #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L 723 #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009 724 #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L 725 #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008 726 #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L 727 #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000 728 #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L 729 #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c 730 #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L 731 #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018 732 #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L 733 #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014 734 #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L 735 #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010 736 #define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L 737 #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002 738 #define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L 739 #define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000 740 #define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L 741 #define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004 742 #define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L 743 #define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010 744 #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L 745 #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f 746 #define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L 747 #define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L 748 #define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000 749 #define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008 750 #define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L 751 #define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010 752 #define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L 753 #define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e 754 #define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L 755 #define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000 756 #define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L 757 #define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009 758 #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L 759 #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b 760 #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L 761 #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018 762 #define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L 763 #define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001 764 #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L 765 #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013 766 #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L 767 #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e 768 #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L 769 #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c 770 #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L 771 #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008 772 #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L 773 #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a 774 #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L 775 #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016 776 #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L 777 #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017 778 #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L 779 #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014 780 #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L 781 #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012 782 #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L 783 #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011 784 #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L 785 #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007 786 #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L 787 #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004 788 #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL 789 #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000 790 #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L 791 #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010 792 #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL 793 #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000 794 #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L 795 #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008 796 #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L 797 #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004 798 #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L 799 #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000 800 #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL 801 #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000 802 #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L 803 #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004 804 #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L 805 #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000 806 #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL 807 #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000 808 #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL 809 #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000 810 #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L 811 #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000 812 #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L 813 #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010 814 #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L 815 #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011 816 #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L 817 #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004 818 #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L 819 #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000 820 #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L 821 #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004 822 #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L 823 #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000 824 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL 825 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 826 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L 827 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 828 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L 829 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 830 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL 831 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 832 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L 833 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 834 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L 835 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b 836 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L 837 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e 838 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L 839 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f 840 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L 841 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 842 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L 843 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 844 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L 845 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 846 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L 847 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 848 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L 849 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 850 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L 851 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 852 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L 853 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 854 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L 855 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 856 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L 857 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 858 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L 859 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 860 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L 861 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000 862 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL 863 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 864 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 865 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 866 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 867 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 868 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 869 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 870 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 871 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 872 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 873 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 874 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L 875 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 876 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 877 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 878 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 879 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 880 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 881 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 882 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 883 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 884 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 885 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 886 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 887 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 888 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 889 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 890 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 891 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 892 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL 893 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 894 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 895 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 896 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 897 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 898 #define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000 899 #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L 900 #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 901 #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L 902 #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 903 #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL 904 #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000 905 #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL 906 #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 907 #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL 908 #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 909 #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK 0x00000100L 910 #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT 0x00000008 911 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL 912 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 913 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L 914 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 915 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L 916 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 917 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL 918 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 919 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L 920 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a 921 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L 922 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 923 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL 924 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 925 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L 926 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 927 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L 928 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 929 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L 930 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 931 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL 932 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 933 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL 934 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 935 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L 936 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e 937 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L 938 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f 939 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL 940 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 941 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 942 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 943 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 944 #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 945 #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL 946 #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 947 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 948 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 949 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L 950 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 951 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 952 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 953 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 954 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 955 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 956 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 957 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L 958 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 959 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 960 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 961 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 962 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 963 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L 964 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 965 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 966 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 967 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 968 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 969 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L 970 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 971 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 972 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 973 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 974 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 975 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L 976 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 977 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 978 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 979 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 980 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 981 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L 982 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 983 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 984 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 985 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 986 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 987 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L 988 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 989 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 990 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 991 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 992 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 993 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L 994 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 995 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 996 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 997 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 998 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 999 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L 1000 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 1001 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1002 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1003 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1004 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1005 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L 1006 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 1007 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1008 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1009 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1010 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1011 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L 1012 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 1013 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1014 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1015 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1016 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1017 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L 1018 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 1019 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1020 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1021 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1022 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1023 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L 1024 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 1025 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1026 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1027 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1028 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1029 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L 1030 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 1031 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1032 #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1033 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L 1034 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008 1035 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L 1036 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f 1037 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L 1038 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011 1039 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L 1040 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012 1041 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L 1042 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010 1043 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L 1044 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b 1045 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL 1046 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000 1047 #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L 1048 #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f 1049 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L 1050 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 1051 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L 1052 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 1053 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L 1054 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001 1055 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L 1056 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c 1057 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L 1058 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008 1059 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L 1060 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009 1061 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L 1062 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014 1063 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L 1064 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010 1065 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L 1066 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011 1067 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L 1068 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c 1069 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L 1070 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018 1071 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L 1072 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019 1073 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L 1074 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 1075 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L 1076 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 1077 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L 1078 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 1079 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L 1080 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c 1081 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L 1082 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008 1083 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L 1084 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009 1085 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L 1086 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014 1087 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L 1088 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010 1089 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L 1090 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011 1091 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L 1092 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c 1093 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L 1094 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018 1095 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L 1096 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019 1097 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L 1098 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 1099 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L 1100 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c 1101 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L 1102 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 1103 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L 1104 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 1105 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L 1106 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 1107 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L 1108 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 1109 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L 1110 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 1111 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L 1112 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e 1113 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL 1114 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 1115 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L 1116 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000 1117 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L 1118 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004 1119 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L 1120 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 1121 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL 1122 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 1123 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL 1124 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 1125 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL 1126 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000 1127 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L 1128 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010 1129 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL 1130 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 1131 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL 1132 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000 1133 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL 1134 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000 1135 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL 1136 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000 1137 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L 1138 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008 1139 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L 1140 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010 1141 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L 1142 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018 1143 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL 1144 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000 1145 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L 1146 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008 1147 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L 1148 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010 1149 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L 1150 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018 1151 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L 1152 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010 1153 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L 1154 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018 1155 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL 1156 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000 1157 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L 1158 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008 1159 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL 1160 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000 1161 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L 1162 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008 1163 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L 1164 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010 1165 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L 1166 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018 1167 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL 1168 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000 1169 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L 1170 #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008 1171 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L 1172 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 1173 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L 1174 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c 1175 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL 1176 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000 1177 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL 1178 #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 1179 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L 1180 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 1181 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1182 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1183 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1184 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1185 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1186 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1187 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1188 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1189 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1190 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1191 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1192 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1193 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1194 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1195 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1196 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1197 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1198 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1199 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1200 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1201 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1202 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1203 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1204 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1205 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1206 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1207 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L 1208 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 1209 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L 1210 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 1211 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L 1212 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 1213 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L 1214 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 1215 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L 1216 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 1217 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L 1218 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 1219 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L 1220 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 1221 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L 1222 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 1223 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L 1224 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 1225 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L 1226 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 1227 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L 1228 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 1229 #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL 1230 #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000 1231 #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL 1232 #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 1233 #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL 1234 #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 1235 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L 1236 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 1237 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL 1238 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 1239 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L 1240 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L 1241 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 1242 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 1243 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L 1244 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L 1245 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 1246 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 1247 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL 1248 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L 1249 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 1250 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 1251 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL 1252 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L 1253 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 1254 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 1255 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L 1256 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 1257 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L 1258 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 1259 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L 1260 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 1261 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL 1262 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 1263 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL 1264 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 1265 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L 1266 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 1267 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 1268 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 1269 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 1270 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 1271 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL 1272 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 1273 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L 1274 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 1275 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL 1276 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 1277 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L 1278 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 1279 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL 1280 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 1281 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L 1282 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 1283 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L 1284 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 1285 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL 1286 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 1287 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L 1288 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 1289 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L 1290 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b 1291 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L 1292 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e 1293 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L 1294 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L 1295 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f 1296 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f 1297 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL 1298 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000 1299 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L 1300 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007 1301 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L 1302 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 1303 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L 1304 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 1305 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L 1306 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 1307 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L 1308 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 1309 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L 1310 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 1311 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L 1312 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 1313 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L 1314 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 1315 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L 1316 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 1317 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L 1318 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 1319 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L 1320 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 1321 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL 1322 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 1323 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1324 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1325 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1326 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1327 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1328 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1329 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1330 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1331 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1332 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1333 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L 1334 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 1335 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1336 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1337 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1338 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1339 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1340 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1341 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1342 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1343 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1344 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1345 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1346 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1347 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1348 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1349 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1350 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1351 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL 1352 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 1353 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 1354 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 1355 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 1356 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 1357 #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L 1358 #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 1359 #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L 1360 #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 1361 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL 1362 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 1363 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L 1364 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 1365 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L 1366 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 1367 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL 1368 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 1369 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L 1370 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a 1371 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L 1372 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 1373 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL 1374 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000 1375 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL 1376 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000 1377 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL 1378 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000 1379 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL 1380 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 1381 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L 1382 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 1383 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L 1384 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 1385 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L 1386 #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 1387 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL 1388 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 1389 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL 1390 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 1391 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L 1392 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e 1393 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L 1394 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f 1395 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL 1396 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 1397 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL 1398 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 1399 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 1400 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 1401 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 1402 #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 1403 #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL 1404 #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 1405 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL 1406 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000 1407 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1408 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1409 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L 1410 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003 1411 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L 1412 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000 1413 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1414 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1415 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 1416 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 1417 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL 1418 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000 1419 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL 1420 #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000 1421 #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL 1422 #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000 1423 #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L 1424 #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007 1425 #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L 1426 #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003 1427 #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L 1428 #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000 1429 #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L 1430 #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004 1431 #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L 1432 #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 1433 #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL 1434 #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 1435 #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL 1436 #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000 1437 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L 1438 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 1439 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L 1440 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 1441 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L 1442 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 1443 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L 1444 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 1445 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L 1446 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 1447 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L 1448 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001 1449 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L 1450 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004 1451 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L 1452 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000 1453 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L 1454 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001 1455 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L 1456 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004 1457 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L 1458 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000 1459 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L 1460 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001 1461 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L 1462 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004 1463 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L 1464 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000 1465 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L 1466 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001 1467 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L 1468 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004 1469 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L 1470 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000 1471 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L 1472 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001 1473 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L 1474 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004 1475 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L 1476 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000 1477 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L 1478 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001 1479 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L 1480 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004 1481 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L 1482 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000 1483 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L 1484 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001 1485 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L 1486 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 1487 #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL 1488 #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000 1489 #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL 1490 #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000 1491 #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL 1492 #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000 1493 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L 1494 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004 1495 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL 1496 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000 1497 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL 1498 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000 1499 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L 1500 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004 1501 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL 1502 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000 1503 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L 1504 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006 1505 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L 1506 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c 1507 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L 1508 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 1509 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L 1510 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 1511 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L 1512 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 1513 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L 1514 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 1515 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L 1516 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 1517 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L 1518 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e 1519 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL 1520 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 1521 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL 1522 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000 1523 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL 1524 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 1525 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L 1526 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f 1527 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L 1528 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009 1529 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L 1530 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a 1531 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L 1532 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008 1533 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL 1534 #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000 1535 #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL 1536 #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 1537 #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L 1538 #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 1539 #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL 1540 #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 1541 #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L 1542 #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 1543 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1544 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1545 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1546 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1547 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1548 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1549 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1550 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1551 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1552 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1553 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1554 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1555 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1556 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1557 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1558 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1559 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1560 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1561 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1562 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1563 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1564 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1565 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1566 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1567 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1568 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1569 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L 1570 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 1571 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L 1572 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 1573 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L 1574 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 1575 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L 1576 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 1577 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L 1578 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 1579 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L 1580 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 1581 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L 1582 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 1583 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L 1584 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 1585 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L 1586 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 1587 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L 1588 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 1589 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L 1590 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 1591 #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL 1592 #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000 1593 #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL 1594 #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 1595 #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL 1596 #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 1597 #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL 1598 #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 1599 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L 1600 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 1601 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL 1602 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 1603 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L 1604 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L 1605 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 1606 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 1607 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L 1608 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L 1609 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 1610 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 1611 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL 1612 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L 1613 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 1614 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 1615 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL 1616 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L 1617 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 1618 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 1619 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L 1620 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 1621 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L 1622 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 1623 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L 1624 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 1625 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL 1626 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 1627 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL 1628 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 1629 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L 1630 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 1631 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 1632 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 1633 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 1634 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 1635 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL 1636 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 1637 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L 1638 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 1639 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL 1640 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 1641 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L 1642 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 1643 #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L 1644 #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008 1645 #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L 1646 #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010 1647 #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL 1648 #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000 1649 #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L 1650 #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001 1651 #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L 1652 #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000 1653 #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL 1654 #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000 1655 #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L 1656 #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010 1657 #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL 1658 #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000 1659 #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L 1660 #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008 1661 #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L 1662 #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004 1663 #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L 1664 #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000 1665 #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L 1666 #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004 1667 #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL 1668 #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000 1669 #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL 1670 #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000 1671 #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL 1672 #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000 1673 #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L 1674 #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008 1675 #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL 1676 #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000 1677 #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL 1678 #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000 1679 #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL 1680 #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000 1681 #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL 1682 #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000 1683 #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 1684 #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 1685 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L 1686 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003 1687 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L 1688 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002 1689 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L 1690 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010 1691 #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L 1692 #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000 1693 #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L 1694 #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001 1695 #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL 1696 #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000 1697 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 1698 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 1699 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 1700 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 1701 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 1702 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 1703 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 1704 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 1705 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 1706 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 1707 #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL 1708 #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000 1709 #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL 1710 #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000 1711 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L 1712 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011 1713 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L 1714 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f 1715 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L 1716 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 1717 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L 1718 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000 1719 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L 1720 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008 1721 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L 1722 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010 1723 #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL 1724 #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000 1725 #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL 1726 #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000 1727 #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL 1728 #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000 1729 #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L 1730 #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e 1731 #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L 1732 #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f 1733 #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL 1734 #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000 1735 #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L 1736 #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c 1737 #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL 1738 #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000 1739 #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L 1740 #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f 1741 #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L 1742 #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e 1743 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L 1744 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011 1745 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L 1746 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f 1747 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L 1748 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 1749 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L 1750 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000 1751 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L 1752 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008 1753 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L 1754 #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010 1755 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L 1756 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010 1757 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL 1758 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000 1759 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L 1760 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c 1761 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L 1762 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002 1763 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L 1764 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001 1765 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L 1766 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000 1767 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L 1768 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014 1769 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L 1770 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004 1771 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L 1772 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018 1773 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L 1774 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010 1775 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L 1776 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c 1777 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L 1778 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008 1779 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L 1780 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000 1781 #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL 1782 #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001 1783 #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L 1784 #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L 1785 #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004 1786 #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000 1787 #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL 1788 #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000 1789 #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L 1790 #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010 1791 #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL 1792 #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000 1793 #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L 1794 #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010 1795 #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL 1796 #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000 1797 #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L 1798 #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010 1799 #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL 1800 #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000 1801 #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L 1802 #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010 1803 #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL 1804 #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000 1805 #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L 1806 #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010 1807 #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL 1808 #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000 1809 #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L 1810 #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010 1811 #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL 1812 #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000 1813 #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L 1814 #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010 1815 #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL 1816 #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000 1817 #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L 1818 #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010 1819 #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL 1820 #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000 1821 #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L 1822 #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010 1823 #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL 1824 #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000 1825 #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L 1826 #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010 1827 #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL 1828 #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000 1829 #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L 1830 #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010 1831 #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL 1832 #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000 1833 #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L 1834 #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010 1835 #define CRT00__H_TOTAL_MASK 0x000000ffL 1836 #define CRT00__H_TOTAL__SHIFT 0x00000000 1837 #define CRT01__H_DISP_END_MASK 0x000000ffL 1838 #define CRT01__H_DISP_END__SHIFT 0x00000000 1839 #define CRT02__H_BLANK_START_MASK 0x000000ffL 1840 #define CRT02__H_BLANK_START__SHIFT 0x00000000 1841 #define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L 1842 #define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007 1843 #define CRT03__H_BLANK_END_MASK 0x0000001fL 1844 #define CRT03__H_BLANK_END__SHIFT 0x00000000 1845 #define CRT03__H_DE_SKEW_MASK 0x00000060L 1846 #define CRT03__H_DE_SKEW__SHIFT 0x00000005 1847 #define CRT04__H_SYNC_START_MASK 0x000000ffL 1848 #define CRT04__H_SYNC_START__SHIFT 0x00000000 1849 #define CRT05__H_BLANK_END_B5_MASK 0x00000080L 1850 #define CRT05__H_BLANK_END_B5__SHIFT 0x00000007 1851 #define CRT05__H_SYNC_END_MASK 0x0000001fL 1852 #define CRT05__H_SYNC_END__SHIFT 0x00000000 1853 #define CRT05__H_SYNC_SKEW_MASK 0x00000060L 1854 #define CRT05__H_SYNC_SKEW__SHIFT 0x00000005 1855 #define CRT06__V_TOTAL_MASK 0x000000ffL 1856 #define CRT06__V_TOTAL__SHIFT 0x00000000 1857 #define CRT07__LINE_CMP_B8_MASK 0x00000010L 1858 #define CRT07__LINE_CMP_B8__SHIFT 0x00000004 1859 #define CRT07__V_BLANK_START_B8_MASK 0x00000008L 1860 #define CRT07__V_BLANK_START_B8__SHIFT 0x00000003 1861 #define CRT07__V_DISP_END_B8_MASK 0x00000002L 1862 #define CRT07__V_DISP_END_B8__SHIFT 0x00000001 1863 #define CRT07__V_DISP_END_B9_MASK 0x00000040L 1864 #define CRT07__V_DISP_END_B9__SHIFT 0x00000006 1865 #define CRT07__V_SYNC_START_B8_MASK 0x00000004L 1866 #define CRT07__V_SYNC_START_B8__SHIFT 0x00000002 1867 #define CRT07__V_SYNC_START_B9_MASK 0x00000080L 1868 #define CRT07__V_SYNC_START_B9__SHIFT 0x00000007 1869 #define CRT07__V_TOTAL_B8_MASK 0x00000001L 1870 #define CRT07__V_TOTAL_B8__SHIFT 0x00000000 1871 #define CRT07__V_TOTAL_B9_MASK 0x00000020L 1872 #define CRT07__V_TOTAL_B9__SHIFT 0x00000005 1873 #define CRT08__BYTE_PAN_MASK 0x00000060L 1874 #define CRT08__BYTE_PAN__SHIFT 0x00000005 1875 #define CRT08__ROW_SCAN_START_MASK 0x0000001fL 1876 #define CRT08__ROW_SCAN_START__SHIFT 0x00000000 1877 #define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L 1878 #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007 1879 #define CRT09__LINE_CMP_B9_MASK 0x00000040L 1880 #define CRT09__LINE_CMP_B9__SHIFT 0x00000006 1881 #define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL 1882 #define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000 1883 #define CRT09__V_BLANK_START_B9_MASK 0x00000020L 1884 #define CRT09__V_BLANK_START_B9__SHIFT 0x00000005 1885 #define CRT0A__CURSOR_DISABLE_MASK 0x00000020L 1886 #define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005 1887 #define CRT0A__CURSOR_START_MASK 0x0000001fL 1888 #define CRT0A__CURSOR_START__SHIFT 0x00000000 1889 #define CRT0B__CURSOR_END_MASK 0x0000001fL 1890 #define CRT0B__CURSOR_END__SHIFT 0x00000000 1891 #define CRT0B__CURSOR_SKEW_MASK 0x00000060L 1892 #define CRT0B__CURSOR_SKEW__SHIFT 0x00000005 1893 #define CRT0C__DISP_START_MASK 0x000000ffL 1894 #define CRT0C__DISP_START__SHIFT 0x00000000 1895 #define CRT0D__DISP_START_MASK 0x000000ffL 1896 #define CRT0D__DISP_START__SHIFT 0x00000000 1897 #define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL 1898 #define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000 1899 #define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL 1900 #define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000 1901 #define CRT10__V_SYNC_START_MASK 0x000000ffL 1902 #define CRT10__V_SYNC_START__SHIFT 0x00000000 1903 #define CRT11__C0T7_WR_ONLY_MASK 0x00000080L 1904 #define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007 1905 #define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L 1906 #define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006 1907 #define CRT11__V_INTR_CLR_MASK 0x00000010L 1908 #define CRT11__V_INTR_CLR__SHIFT 0x00000004 1909 #define CRT11__V_INTR_EN_MASK 0x00000020L 1910 #define CRT11__V_INTR_EN__SHIFT 0x00000005 1911 #define CRT11__V_SYNC_END_MASK 0x0000000fL 1912 #define CRT11__V_SYNC_END__SHIFT 0x00000000 1913 #define CRT12__V_DISP_END_MASK 0x000000ffL 1914 #define CRT12__V_DISP_END__SHIFT 0x00000000 1915 #define CRT13__DISP_PITCH_MASK 0x000000ffL 1916 #define CRT13__DISP_PITCH__SHIFT 0x00000000 1917 #define CRT14__ADDR_CNT_BY4_MASK 0x00000020L 1918 #define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005 1919 #define CRT14__DOUBLE_WORD_MASK 0x00000040L 1920 #define CRT14__DOUBLE_WORD__SHIFT 0x00000006 1921 #define CRT14__UNDRLN_LOC_MASK 0x0000001fL 1922 #define CRT14__UNDRLN_LOC__SHIFT 0x00000000 1923 #define CRT15__V_BLANK_START_MASK 0x000000ffL 1924 #define CRT15__V_BLANK_START__SHIFT 0x00000000 1925 #define CRT16__V_BLANK_END_MASK 0x000000ffL 1926 #define CRT16__V_BLANK_END__SHIFT 0x00000000 1927 #define CRT17__ADDR_CNT_BY2_MASK 0x00000008L 1928 #define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003 1929 #define CRT17__BYTE_MODE_MASK 0x00000040L 1930 #define CRT17__BYTE_MODE__SHIFT 0x00000006 1931 #define CRT17__CRTC_SYNC_EN_MASK 0x00000080L 1932 #define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007 1933 #define CRT17__RA0_AS_A13B_MASK 0x00000001L 1934 #define CRT17__RA0_AS_A13B__SHIFT 0x00000000 1935 #define CRT17__RA1_AS_A14B_MASK 0x00000002L 1936 #define CRT17__RA1_AS_A14B__SHIFT 0x00000001 1937 #define CRT17__VCOUNT_BY2_MASK 0x00000004L 1938 #define CRT17__VCOUNT_BY2__SHIFT 0x00000002 1939 #define CRT17__WRAP_A15TOA0_MASK 0x00000020L 1940 #define CRT17__WRAP_A15TOA0__SHIFT 0x00000005 1941 #define CRT18__LINE_CMP_MASK 0x000000ffL 1942 #define CRT18__LINE_CMP__SHIFT 0x00000000 1943 #define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L 1944 #define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001 1945 #define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL 1946 #define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000 1947 #define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL 1948 #define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000 1949 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L 1950 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008 1951 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1952 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1953 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1954 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1955 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L 1956 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009 1957 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L 1958 #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1959 #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L 1960 #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004 1961 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L 1962 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008 1963 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1964 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1965 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1966 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1967 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L 1968 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009 1969 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L 1970 #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1971 #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L 1972 #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004 1973 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L 1974 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008 1975 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1976 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1977 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1978 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1979 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L 1980 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009 1981 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L 1982 #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1983 #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L 1984 #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004 1985 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L 1986 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004 1987 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L 1988 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000 1989 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L 1990 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L 1991 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L 1992 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011 1993 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010 1994 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012 1995 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L 1996 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c 1997 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L 1998 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008 1999 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L 2000 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008 2001 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2002 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2003 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2004 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2005 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L 2006 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009 2007 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L 2008 #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2009 #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L 2010 #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004 2011 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L 2012 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008 2013 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2014 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2015 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2016 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2017 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L 2018 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009 2019 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L 2020 #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2021 #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L 2022 #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004 2023 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L 2024 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008 2025 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2026 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2027 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2028 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2029 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L 2030 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009 2031 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L 2032 #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2033 #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L 2034 #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004 2035 #define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL 2036 #define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000 2037 #define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL 2038 #define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000 2039 #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL 2040 #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000 2041 #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L 2042 #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010 2043 #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL 2044 #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000 2045 #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L 2046 #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a 2047 #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L 2048 #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014 2049 #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L 2050 #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008 2051 #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L 2052 #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010 2053 #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L 2054 #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000 2055 #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL 2056 #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000 2057 #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L 2058 #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a 2059 #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L 2060 #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014 2061 #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L 2062 #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010 2063 #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L 2064 #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008 2065 #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L 2066 #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018 2067 #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L 2068 #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d 2069 #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L 2070 #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014 2071 #define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L 2072 #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000 2073 #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L 2074 #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d 2075 #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L 2076 #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c 2077 #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L 2078 #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 2079 #define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000L 2080 #define CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x0000001c 2081 #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L 2082 #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 2083 #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL 2084 #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001 2085 #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L 2086 #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000 2087 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L 2088 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f 2089 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L 2090 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018 2091 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L 2092 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008 2093 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L 2094 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c 2095 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L 2096 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004 2097 #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L 2098 #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010 2099 #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L 2100 #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008 2101 #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L 2102 #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000 2103 #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL 2104 #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001 2105 #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L 2106 #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000 2107 #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L 2108 #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010 2109 #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL 2110 #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000 2111 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L 2112 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010 2113 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L 2114 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018 2115 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L 2116 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008 2117 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL 2118 #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000 2119 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L 2120 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004 2121 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L 2122 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018 2123 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L 2124 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000 2125 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L 2126 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010 2127 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L 2128 #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008 2129 #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L 2130 #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c 2131 #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL 2132 #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000 2133 #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L 2134 #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010 2135 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L 2136 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013 2137 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L 2138 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008 2139 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL 2140 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000 2141 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L 2142 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L 2143 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017 2144 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L 2145 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011 2146 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L 2147 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014 2148 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018 2149 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L 2150 #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010 2151 #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L 2152 #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010 2153 #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL 2154 #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000 2155 #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L 2156 #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010 2157 #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL 2158 #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000 2159 #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L 2160 #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010 2161 #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL 2162 #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000 2163 #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L 2164 #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010 2165 #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L 2166 #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011 2167 #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L 2168 #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000 2169 #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L 2170 #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010 2171 #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL 2172 #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000 2173 #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L 2174 #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010 2175 #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L 2176 #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011 2177 #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L 2178 #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000 2179 #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L 2180 #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010 2181 #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL 2182 #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000 2183 #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL 2184 #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000 2185 #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L 2186 #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000 2187 #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L 2188 #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010 2189 #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L 2190 #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000 2191 #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L 2192 #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001 2193 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L 2194 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008 2195 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L 2196 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009 2197 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L 2198 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010 2199 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L 2200 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011 2201 #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L 2202 #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e 2203 #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L 2204 #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f 2205 #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L 2206 #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000 2207 #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L 2208 #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001 2209 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L 2210 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018 2211 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L 2212 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a 2213 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L 2214 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019 2215 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L 2216 #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b 2217 #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L 2218 #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c 2219 #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L 2220 #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d 2221 #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L 2222 #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004 2223 #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L 2224 #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005 2225 #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L 2226 #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000 2227 #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L 2228 #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000 2229 #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L 2230 #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008 2231 #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L 2232 #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000 2233 #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL 2234 #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000 2235 #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L 2236 #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014 2237 #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L 2238 #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004 2239 #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L 2240 #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010 2241 #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L 2242 #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000 2243 #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL 2244 #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000 2245 #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL 2246 #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000 2247 #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L 2248 #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a 2249 #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L 2250 #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014 2251 #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L 2252 #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000 2253 #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL 2254 #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000 2255 #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L 2256 #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010 2257 #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL 2258 #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000 2259 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L 2260 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001 2261 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L 2262 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002 2263 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L 2264 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000 2265 #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L 2266 #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010 2267 #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L 2268 #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008 2269 #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L 2270 #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000 2271 #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L 2272 #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011 2273 #define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L 2274 #define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010 2275 #define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L 2276 #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012 2277 #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L 2278 #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001 2279 #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L 2280 #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005 2281 #define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L 2282 #define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000 2283 #define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L 2284 #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004 2285 #define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L 2286 #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002 2287 #define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L 2288 #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003 2289 #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL 2290 #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000 2291 #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL 2292 #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000 2293 #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L 2294 #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010 2295 #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL 2296 #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000 2297 #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL 2298 #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000 2299 #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L 2300 #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018 2301 #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL 2302 #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000 2303 #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L 2304 #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f 2305 #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L 2306 #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010 2307 #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L 2308 #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000 2309 #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L 2310 #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000 2311 #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L 2312 #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018 2313 #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L 2314 #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008 2315 #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L 2316 #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010 2317 #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL 2318 #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000 2319 #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL 2320 #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000 2321 #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 2322 #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 2323 #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL 2324 #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000 2325 #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L 2326 #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010 2327 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L 2328 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018 2329 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L 2330 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010 2331 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L 2332 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000 2333 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L 2334 #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008 2335 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L 2336 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c 2337 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL 2338 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000 2339 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L 2340 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004 2341 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L 2342 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010 2343 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L 2344 #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008 2345 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L 2346 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f 2347 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L 2348 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018 2349 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L 2350 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 2351 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L 2352 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014 2353 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L 2354 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009 2355 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L 2356 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b 2357 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L 2358 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005 2359 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L 2360 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a 2361 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L 2362 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008 2363 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L 2364 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c 2365 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL 2366 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000 2367 #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L 2368 #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000 2369 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L 2370 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f 2371 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L 2372 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018 2373 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L 2374 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 2375 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L 2376 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014 2377 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L 2378 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009 2379 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L 2380 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b 2381 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L 2382 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005 2383 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L 2384 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a 2385 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L 2386 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008 2387 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L 2388 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c 2389 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL 2390 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000 2391 #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L 2392 #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000 2393 #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L 2394 #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000 2395 #define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L 2396 #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010 2397 #define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL 2398 #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000 2399 #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L 2400 #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010 2401 #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL 2402 #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000 2403 #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L 2404 #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010 2405 #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L 2406 #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008 2407 #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L 2408 #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000 2409 #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L 2410 #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000 2411 #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L 2412 #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000 2413 #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L 2414 #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010 2415 #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL 2416 #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000 2417 #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L 2418 #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000 2419 #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L 2420 #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010 2421 #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL 2422 #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000 2423 #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L 2424 #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004 2425 #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L 2426 #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000 2427 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L 2428 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008 2429 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L 2430 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c 2431 #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L 2432 #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010 2433 #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L 2434 #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004 2435 #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L 2436 #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000 2437 #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL 2438 #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000 2439 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L 2440 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008 2441 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L 2442 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004 2443 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L 2444 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L 2445 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c 2446 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000 2447 #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L 2448 #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010 2449 #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL 2450 #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000 2451 #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL 2452 #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000 2453 #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L 2454 #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008 2455 #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L 2456 #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000 2457 #define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL 2458 #define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000 2459 #define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L 2460 #define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008 2461 #define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L 2462 #define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010 2463 #define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL 2464 #define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000 2465 #define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L 2466 #define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008 2467 #define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L 2468 #define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010 2469 #define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L 2470 #define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004 2471 #define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L 2472 #define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010 2473 #define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L 2474 #define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000 2475 #define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L 2476 #define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014 2477 #define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L 2478 #define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008 2479 #define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L 2480 #define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018 2481 #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L 2482 #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010 2483 #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL 2484 #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000 2485 #define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L 2486 #define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010 2487 #define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL 2488 #define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000 2489 #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L 2490 #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000 2491 #define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL 2492 #define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000 2493 #define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L 2494 #define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010 2495 #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL 2496 #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000 2497 #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 2498 #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 2499 #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 2500 #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 2501 #define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L 2502 #define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010 2503 #define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L 2504 #define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000 2505 #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L 2506 #define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001 2507 #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L 2508 #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000 2509 #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2510 #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2511 #define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L 2512 #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018 2513 #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2514 #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2515 #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L 2516 #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008 2517 #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L 2518 #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000 2519 #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2520 #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2521 #define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L 2522 #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018 2523 #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2524 #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2525 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L 2526 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008 2527 #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L 2528 #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000 2529 #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2530 #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2531 #define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L 2532 #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018 2533 #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2534 #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2535 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L 2536 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 2537 #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L 2538 #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000 2539 #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2540 #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2541 #define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L 2542 #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018 2543 #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2544 #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2545 #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L 2546 #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008 2547 #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L 2548 #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000 2549 #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2550 #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2551 #define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L 2552 #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018 2553 #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2554 #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2555 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L 2556 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008 2557 #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L 2558 #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000 2559 #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2560 #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2561 #define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L 2562 #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018 2563 #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2564 #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2565 #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L 2566 #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008 2567 #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL 2568 #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000 2569 #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L 2570 #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008 2571 #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL 2572 #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000 2573 #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L 2574 #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008 2575 #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L 2576 #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010 2577 #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L 2578 #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008 2579 #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L 2580 #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000 2581 #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L 2582 #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000 2583 #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L 2584 #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010 2585 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L 2586 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018 2587 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L 2588 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004 2589 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L 2590 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010 2591 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L 2592 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008 2593 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L 2594 #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000 2595 #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L 2596 #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000 2597 #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L 2598 #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004 2599 #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L 2600 #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012 2601 #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L 2602 #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000 2603 #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L 2604 #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008 2605 #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L 2606 #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011 2607 #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L 2608 #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010 2609 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L 2610 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001 2611 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L 2612 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002 2613 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L 2614 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L 2615 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003 2616 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000 2617 #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L 2618 #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000 2619 #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L 2620 #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008 2621 #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L 2622 #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010 2623 #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L 2624 #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000 2625 #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L 2626 #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008 2627 #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L 2628 #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010 2629 #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L 2630 #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000 2631 #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL 2632 #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000 2633 #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL 2634 #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000 2635 #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL 2636 #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000 2637 #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L 2638 #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a 2639 #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L 2640 #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014 2641 #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL 2642 #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 2643 #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L 2644 #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a 2645 #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L 2646 #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014 2647 #define DAC_DATA__DAC_DATA_MASK 0x0000003fL 2648 #define DAC_DATA__DAC_DATA__SHIFT 0x00000000 2649 #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL 2650 #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000 2651 #define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L 2652 #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000 2653 #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L 2654 #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001 2655 #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L 2656 #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005 2657 #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L 2658 #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004 2659 #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL 2660 #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002 2661 #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L 2662 #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008 2663 #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 2664 #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 2665 #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L 2666 #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d 2667 #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 2668 #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 2669 #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 2670 #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 2671 #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L 2672 #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 2673 #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 2674 #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 2675 #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 2676 #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 2677 #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 2678 #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 2679 #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL 2680 #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000 2681 #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L 2682 #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000 2683 #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L 2684 #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018 2685 #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L 2686 #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008 2687 #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2688 #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2689 #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2690 #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2691 #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2692 #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2693 #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2694 #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2695 #define DAC_MASK__DAC_MASK_MASK 0x000000ffL 2696 #define DAC_MASK__DAC_MASK__SHIFT 0x00000000 2697 #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L 2698 #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008 2699 #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L 2700 #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010 2701 #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L 2702 #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L 2703 #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018 2704 #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000 2705 #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L 2706 #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000 2707 #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L 2708 #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010 2709 #define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL 2710 #define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000 2711 #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L 2712 #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000 2713 #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L 2714 #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003 2715 #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L 2716 #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000 2717 #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L 2718 #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000 2719 #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L 2720 #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010 2721 #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L 2722 #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008 2723 #define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL 2724 #define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000 2725 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L 2726 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008 2727 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L 2728 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000 2729 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L 2730 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f 2731 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L 2732 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010 2733 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL 2734 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000 2735 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L 2736 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f 2737 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L 2738 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010 2739 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL 2740 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000 2741 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L 2742 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f 2743 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L 2744 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010 2745 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL 2746 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000 2747 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L 2748 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f 2749 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L 2750 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010 2751 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL 2752 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000 2753 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L 2754 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f 2755 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L 2756 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010 2757 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL 2758 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000 2759 #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L 2760 #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f 2761 #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL 2762 #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000 2763 #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L 2764 #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010 2765 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L 2766 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e 2767 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L 2768 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c 2769 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L 2770 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f 2771 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L 2772 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d 2773 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL 2774 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000 2775 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L 2776 #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010 2777 #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L 2778 #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f 2779 #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L 2780 #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f 2781 #define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L 2782 #define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000 2783 #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L 2784 #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008 2785 #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L 2786 #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010 2787 #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L 2788 #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000 2789 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L 2790 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008 2791 #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL 2792 #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000 2793 #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL 2794 #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000 2795 #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL 2796 #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000 2797 #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL 2798 #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000 2799 #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL 2800 #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000 2801 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L 2802 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002 2803 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L 2804 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f 2805 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L 2806 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a 2807 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L 2808 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000 2809 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L 2810 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010 2811 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L 2812 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008 2813 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L 2814 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001 2815 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L 2816 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018 2817 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L 2818 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009 2819 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L 2820 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017 2821 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L 2822 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018 2823 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L 2824 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c 2825 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L 2826 #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e 2827 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L 2828 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010 2829 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L 2830 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c 2831 #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L 2832 #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d 2833 #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2834 #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2835 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L 2836 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000 2837 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L 2838 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008 2839 #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L 2840 #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014 2841 #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL 2842 #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000 2843 #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL 2844 #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000 2845 #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL 2846 #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000 2847 #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL 2848 #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000 2849 #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL 2850 #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000 2851 #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL 2852 #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000 2853 #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL 2854 #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000 2855 #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL 2856 #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000 2857 #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL 2858 #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000 2859 #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL 2860 #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000 2861 #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL 2862 #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000 2863 #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL 2864 #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000 2865 #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL 2866 #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000 2867 #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL 2868 #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000 2869 #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL 2870 #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000 2871 #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL 2872 #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000 2873 #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL 2874 #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000 2875 #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL 2876 #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000 2877 #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL 2878 #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000 2879 #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL 2880 #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000 2881 #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL 2882 #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000 2883 #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL 2884 #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000 2885 #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL 2886 #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000 2887 #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL 2888 #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000 2889 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 2890 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 2891 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2892 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2893 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 2894 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 2895 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 2896 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 2897 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 2898 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 2899 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2900 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2901 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL 2902 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000 2903 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L 2904 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008 2905 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L 2906 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010 2907 #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L 2908 #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010 2909 #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL 2910 #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000 2911 #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL 2912 #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000 2913 #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L 2914 #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010 2915 #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL 2916 #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000 2917 #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2918 #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2919 #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L 2920 #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010 2921 #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL 2922 #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000 2923 #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL 2924 #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000 2925 #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL 2926 #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000 2927 #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL 2928 #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000 2929 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2930 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2931 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 2932 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 2933 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 2934 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 2935 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 2936 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 2937 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 2938 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 2939 #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL 2940 #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000 2941 #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L 2942 #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014 2943 #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L 2944 #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a 2945 #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL 2946 #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000 2947 #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL 2948 #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000 2949 #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL 2950 #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000 2951 #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL 2952 #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000 2953 #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL 2954 #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000 2955 #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L 2956 #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000 2957 #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L 2958 #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004 2959 #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL 2960 #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000 2961 #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L 2962 #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004 2963 #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L 2964 #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005 2965 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L 2966 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000 2967 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L 2968 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018 2969 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L 2970 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001 2971 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L 2972 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014 2973 #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L 2974 #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006 2975 #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L 2976 #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010 2977 #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L 2978 #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002 2979 #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L 2980 #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c 2981 #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L 2982 #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008 2983 #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L 2984 #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009 2985 #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L 2986 #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a 2987 #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L 2988 #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b 2989 #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L 2990 #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c 2991 #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L 2992 #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d 2993 #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L 2994 #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000 2995 #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL 2996 #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000 2997 #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL 2998 #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000 2999 #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L 3000 #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008 3001 #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L 3002 #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000 3003 #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L 3004 #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001 3005 #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L 3006 #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007 3007 #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L 3008 #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006 3009 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L 3010 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004 3011 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L 3012 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002 3013 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L 3014 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003 3015 #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L 3016 #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005 3017 #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L 3018 #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000 3019 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L 3020 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010 3021 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL 3022 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000 3023 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L 3024 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018 3025 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L 3026 #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008 3027 #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL 3028 #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000 3029 #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L 3030 #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c 3031 #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL 3032 #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000 3033 #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3034 #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 3035 #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L 3036 #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002 3037 #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L 3038 #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a 3039 #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L 3040 #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000 3041 #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L 3042 #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003 3043 #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L 3044 #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 3045 #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L 3046 #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008 3047 #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L 3048 #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 3049 #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L 3050 #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009 3051 #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L 3052 #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 3053 #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L 3054 #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a 3055 #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L 3056 #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 3057 #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L 3058 #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b 3059 #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L 3060 #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017 3061 #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L 3062 #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c 3063 #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L 3064 #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018 3065 #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L 3066 #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d 3067 #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L 3068 #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019 3069 #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L 3070 #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005 3071 #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L 3072 #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012 3073 #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L 3074 #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e 3075 #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L 3076 #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 3077 #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L 3078 #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004 3079 #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L 3080 #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011 3081 #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L 3082 #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001 3083 #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L 3084 #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f 3085 #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL 3086 #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000 3087 #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL 3088 #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000 3089 #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL 3090 #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000 3091 #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL 3092 #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000 3093 #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL 3094 #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000 3095 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L 3096 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005 3097 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L 3098 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006 3099 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L 3100 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014 3101 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L 3102 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007 3103 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L 3104 #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008 3105 #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL 3106 #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000 3107 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L 3108 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c 3109 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL 3110 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000 3111 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L 3112 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004 3113 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L 3114 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c 3115 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L 3116 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010 3117 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L 3118 #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014 3119 #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL 3120 #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000 3121 #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L 3122 #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015 3123 #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L 3124 #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014 3125 #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L 3126 #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013 3127 #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L 3128 #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004 3129 #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3130 #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3131 #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L 3132 #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001 3133 #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L 3134 #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002 3135 #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L 3136 #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003 3137 #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L 3138 #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004 3139 #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3140 #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3141 #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L 3142 #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001 3143 #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L 3144 #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002 3145 #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L 3146 #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003 3147 #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L 3148 #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004 3149 #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3150 #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3151 #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L 3152 #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001 3153 #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L 3154 #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002 3155 #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L 3156 #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003 3157 #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L 3158 #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004 3159 #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3160 #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3161 #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L 3162 #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001 3163 #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L 3164 #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002 3165 #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L 3166 #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003 3167 #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L 3168 #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004 3169 #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3170 #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3171 #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L 3172 #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001 3173 #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L 3174 #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002 3175 #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L 3176 #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003 3177 #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L 3178 #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004 3179 #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3180 #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3181 #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L 3182 #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001 3183 #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L 3184 #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002 3185 #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L 3186 #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003 3187 #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL 3188 #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000 3189 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L 3190 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000 3191 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L 3192 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008 3193 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L 3194 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002 3195 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L 3196 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c 3197 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L 3198 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d 3199 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L 3200 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e 3201 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L 3202 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 3203 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L 3204 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010 3205 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L 3206 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016 3207 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L 3208 #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018 3209 #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L 3210 #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003 3211 #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L 3212 #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e 3213 #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L 3214 #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c 3215 #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L 3216 #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006 3217 #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L 3218 #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014 3219 #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L 3220 #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005 3221 #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L 3222 #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012 3223 #define DC_GENERICA__GENERICA_EN_MASK 0x00000001L 3224 #define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000 3225 #define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L 3226 #define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008 3227 #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L 3228 #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 3229 #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L 3230 #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 3231 #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L 3232 #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 3233 #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L 3234 #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c 3235 #define DC_GENERICB__GENERICB_EN_MASK 0x00000001L 3236 #define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000 3237 #define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L 3238 #define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008 3239 #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L 3240 #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 3241 #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L 3242 #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 3243 #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L 3244 #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 3245 #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L 3246 #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c 3247 #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L 3248 #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000 3249 #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L 3250 #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008 3251 #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L 3252 #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000 3253 #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L 3254 #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008 3255 #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L 3256 #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016 3257 #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L 3258 #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014 3259 #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L 3260 #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010 3261 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L 3262 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000 3263 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L 3264 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004 3265 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L 3266 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006 3267 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L 3268 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018 3269 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L 3270 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008 3271 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L 3272 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c 3273 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L 3274 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e 3275 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L 3276 #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c 3277 #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L 3278 #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000 3279 #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L 3280 #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008 3281 #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L 3282 #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000 3283 #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L 3284 #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008 3285 #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L 3286 #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000 3287 #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L 3288 #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008 3289 #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L 3290 #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016 3291 #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L 3292 #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014 3293 #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L 3294 #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010 3295 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L 3296 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000 3297 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L 3298 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004 3299 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L 3300 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006 3301 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L 3302 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018 3303 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L 3304 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008 3305 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L 3306 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c 3307 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L 3308 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e 3309 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L 3310 #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c 3311 #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L 3312 #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000 3313 #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L 3314 #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008 3315 #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L 3316 #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000 3317 #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L 3318 #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008 3319 #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L 3320 #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000 3321 #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L 3322 #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008 3323 #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L 3324 #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016 3325 #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L 3326 #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014 3327 #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L 3328 #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010 3329 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L 3330 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000 3331 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L 3332 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004 3333 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L 3334 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006 3335 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L 3336 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018 3337 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L 3338 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008 3339 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L 3340 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c 3341 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L 3342 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e 3343 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L 3344 #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c 3345 #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L 3346 #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000 3347 #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L 3348 #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008 3349 #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L 3350 #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000 3351 #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L 3352 #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008 3353 #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L 3354 #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000 3355 #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L 3356 #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008 3357 #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L 3358 #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016 3359 #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L 3360 #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014 3361 #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L 3362 #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010 3363 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L 3364 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000 3365 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L 3366 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004 3367 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L 3368 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006 3369 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L 3370 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018 3371 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L 3372 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008 3373 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L 3374 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c 3375 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L 3376 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e 3377 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L 3378 #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c 3379 #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L 3380 #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000 3381 #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L 3382 #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008 3383 #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L 3384 #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000 3385 #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L 3386 #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008 3387 #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L 3388 #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000 3389 #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L 3390 #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008 3391 #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L 3392 #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016 3393 #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L 3394 #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014 3395 #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L 3396 #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010 3397 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L 3398 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000 3399 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L 3400 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004 3401 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L 3402 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006 3403 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L 3404 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018 3405 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L 3406 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008 3407 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L 3408 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c 3409 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L 3410 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e 3411 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L 3412 #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c 3413 #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L 3414 #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000 3415 #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L 3416 #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008 3417 #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L 3418 #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000 3419 #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L 3420 #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008 3421 #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L 3422 #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000 3423 #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L 3424 #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008 3425 #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L 3426 #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016 3427 #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L 3428 #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014 3429 #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L 3430 #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010 3431 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L 3432 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000 3433 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L 3434 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004 3435 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L 3436 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006 3437 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L 3438 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018 3439 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L 3440 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008 3441 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L 3442 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c 3443 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L 3444 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e 3445 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L 3446 #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c 3447 #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L 3448 #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000 3449 #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L 3450 #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008 3451 #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L 3452 #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000 3453 #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L 3454 #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008 3455 #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L 3456 #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000 3457 #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L 3458 #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008 3459 #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L 3460 #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016 3461 #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L 3462 #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010 3463 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L 3464 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 3465 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L 3466 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000 3467 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L 3468 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006 3469 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L 3470 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018 3471 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L 3472 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008 3473 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L 3474 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c 3475 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L 3476 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e 3477 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L 3478 #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c 3479 #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L 3480 #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000 3481 #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L 3482 #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008 3483 #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L 3484 #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010 3485 #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L 3486 #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008 3487 #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L 3488 #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000 3489 #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L 3490 #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c 3491 #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L 3492 #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018 3493 #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL 3494 #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000 3495 #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L 3496 #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e 3497 #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L 3498 #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c 3499 #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L 3500 #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018 3501 #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL 3502 #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000 3503 #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L 3504 #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e 3505 #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L 3506 #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c 3507 #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L 3508 #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018 3509 #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL 3510 #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000 3511 #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L 3512 #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e 3513 #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L 3514 #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c 3515 #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L 3516 #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018 3517 #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL 3518 #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000 3519 #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L 3520 #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e 3521 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L 3522 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000 3523 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L 3524 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008 3525 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L 3526 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010 3527 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L 3528 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014 3529 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L 3530 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015 3531 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L 3532 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016 3533 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L 3534 #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017 3535 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L 3536 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000 3537 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L 3538 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008 3539 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L 3540 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010 3541 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L 3542 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014 3543 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L 3544 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015 3545 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L 3546 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016 3547 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L 3548 #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017 3549 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L 3550 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000 3551 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L 3552 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001 3553 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L 3554 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002 3555 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L 3556 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004 3557 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L 3558 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005 3559 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L 3560 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006 3561 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L 3562 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008 3563 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L 3564 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009 3565 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L 3566 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a 3567 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L 3568 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c 3569 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L 3570 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d 3571 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L 3572 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e 3573 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L 3574 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010 3575 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L 3576 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011 3577 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L 3578 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012 3579 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L 3580 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014 3581 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L 3582 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015 3583 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L 3584 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016 3585 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L 3586 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018 3587 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L 3588 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019 3589 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L 3590 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a 3591 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L 3592 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000 3593 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L 3594 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008 3595 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L 3596 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010 3597 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L 3598 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014 3599 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L 3600 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015 3601 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L 3602 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016 3603 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L 3604 #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017 3605 #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L 3606 #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000 3607 #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L 3608 #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008 3609 #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L 3610 #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010 3611 #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L 3612 #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018 3613 #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L 3614 #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000 3615 #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L 3616 #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008 3617 #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L 3618 #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010 3619 #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L 3620 #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018 3621 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L 3622 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000 3623 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L 3624 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001 3625 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L 3626 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003 3627 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L 3628 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002 3629 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L 3630 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008 3631 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L 3632 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009 3633 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L 3634 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b 3635 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L 3636 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a 3637 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L 3638 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010 3639 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L 3640 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011 3641 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L 3642 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013 3643 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L 3644 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012 3645 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L 3646 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018 3647 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L 3648 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019 3649 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L 3650 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b 3651 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L 3652 #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a 3653 #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L 3654 #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000 3655 #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L 3656 #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008 3657 #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L 3658 #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010 3659 #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L 3660 #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018 3661 #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L 3662 #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000 3663 #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L 3664 #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008 3665 #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L 3666 #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010 3667 #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L 3668 #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018 3669 #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L 3670 #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a 3671 #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L 3672 #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c 3673 #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L 3674 #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000 3675 #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L 3676 #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008 3677 #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L 3678 #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010 3679 #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L 3680 #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018 3681 #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L 3682 #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a 3683 #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L 3684 #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c 3685 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L 3686 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000 3687 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L 3688 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004 3689 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L 3690 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006 3691 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L 3692 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008 3693 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L 3694 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009 3695 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L 3696 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a 3697 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L 3698 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010 3699 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L 3700 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011 3701 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L 3702 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012 3703 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L 3704 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014 3705 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L 3706 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015 3707 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L 3708 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016 3709 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L 3710 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018 3711 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L 3712 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019 3713 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L 3714 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a 3715 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L 3716 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c 3717 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L 3718 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d 3719 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L 3720 #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e 3721 #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L 3722 #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000 3723 #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L 3724 #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008 3725 #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L 3726 #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010 3727 #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L 3728 #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018 3729 #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L 3730 #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a 3731 #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L 3732 #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c 3733 #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L 3734 #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000 3735 #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L 3736 #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001 3737 #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L 3738 #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000 3739 #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L 3740 #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001 3741 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L 3742 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000 3743 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L 3744 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001 3745 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L 3746 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002 3747 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L 3748 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004 3749 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L 3750 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005 3751 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L 3752 #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006 3753 #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL 3754 #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000 3755 #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L 3756 #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004 3757 #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L 3758 #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000 3759 #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L 3760 #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001 3761 #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL 3762 #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000 3763 #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L 3764 #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004 3765 #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L 3766 #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018 3767 #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L 3768 #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c 3769 #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L 3770 #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010 3771 #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L 3772 #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014 3773 #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL 3774 #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000 3775 #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L 3776 #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004 3777 #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L 3778 #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000 3779 #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L 3780 #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008 3781 #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L 3782 #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010 3783 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L 3784 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000 3785 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L 3786 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008 3787 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L 3788 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010 3789 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L 3790 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001 3791 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L 3792 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000 3793 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L 3794 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004 3795 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L 3796 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006 3797 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L 3798 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008 3799 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L 3800 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c 3801 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L 3802 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e 3803 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L 3804 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010 3805 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L 3806 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014 3807 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L 3808 #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016 3809 #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L 3810 #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000 3811 #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L 3812 #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008 3813 #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L 3814 #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010 3815 #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L 3816 #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000 3817 #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L 3818 #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008 3819 #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L 3820 #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000 3821 #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L 3822 #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008 3823 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L 3824 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018 3825 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L 3826 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000 3827 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L 3828 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004 3829 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L 3830 #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006 3831 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L 3832 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c 3833 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L 3834 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008 3835 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L 3836 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c 3837 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L 3838 #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e 3839 #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L 3840 #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000 3841 #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L 3842 #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008 3843 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL 3844 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000 3845 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L 3846 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008 3847 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L 3848 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b 3849 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L 3850 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e 3851 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L 3852 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011 3853 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L 3854 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014 3855 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L 3856 #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017 3857 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL 3858 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 3859 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L 3860 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000 3861 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L 3862 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004 3863 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L 3864 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008 3865 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L 3866 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c 3867 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L 3868 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010 3869 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L 3870 #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014 3871 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L 3872 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000 3873 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L 3874 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004 3875 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L 3876 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008 3877 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L 3878 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c 3879 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L 3880 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010 3881 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L 3882 #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014 3883 #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL 3884 #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000 3885 #define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L 3886 #define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c 3887 #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L 3888 #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010 3889 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3890 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3891 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L 3892 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3893 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3894 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3895 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3896 #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3897 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L 3898 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000 3899 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L 3900 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010 3901 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L 3902 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008 3903 #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L 3904 #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014 3905 #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L 3906 #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018 3907 #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L 3908 #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000 3909 #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L 3910 #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008 3911 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L 3912 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004 3913 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L 3914 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001 3915 #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3916 #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3917 #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3918 #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3919 #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL 3920 #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000 3921 #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 3922 #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014 3923 #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL 3924 #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000 3925 #define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L 3926 #define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c 3927 #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L 3928 #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010 3929 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3930 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3931 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L 3932 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3933 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3934 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3935 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3936 #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3937 #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L 3938 #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000 3939 #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L 3940 #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010 3941 #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L 3942 #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008 3943 #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L 3944 #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014 3945 #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L 3946 #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018 3947 #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L 3948 #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000 3949 #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L 3950 #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008 3951 #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L 3952 #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004 3953 #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L 3954 #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001 3955 #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3956 #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3957 #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3958 #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3959 #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL 3960 #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000 3961 #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 3962 #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014 3963 #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL 3964 #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000 3965 #define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L 3966 #define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c 3967 #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L 3968 #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010 3969 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3970 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3971 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L 3972 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3973 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3974 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3975 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3976 #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3977 #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L 3978 #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000 3979 #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L 3980 #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010 3981 #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L 3982 #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008 3983 #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L 3984 #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014 3985 #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L 3986 #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018 3987 #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L 3988 #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000 3989 #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L 3990 #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008 3991 #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L 3992 #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004 3993 #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L 3994 #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001 3995 #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3996 #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3997 #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3998 #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3999 #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL 4000 #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000 4001 #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4002 #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4003 #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL 4004 #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000 4005 #define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L 4006 #define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c 4007 #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L 4008 #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010 4009 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4010 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4011 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L 4012 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4013 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4014 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4015 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4016 #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4017 #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L 4018 #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000 4019 #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L 4020 #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010 4021 #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L 4022 #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008 4023 #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L 4024 #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014 4025 #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L 4026 #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018 4027 #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L 4028 #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000 4029 #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L 4030 #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008 4031 #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L 4032 #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004 4033 #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L 4034 #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001 4035 #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4036 #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4037 #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4038 #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4039 #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL 4040 #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000 4041 #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4042 #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4043 #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL 4044 #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000 4045 #define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L 4046 #define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c 4047 #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L 4048 #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010 4049 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4050 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4051 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L 4052 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4053 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4054 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4055 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4056 #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4057 #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L 4058 #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000 4059 #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L 4060 #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010 4061 #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L 4062 #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008 4063 #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L 4064 #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014 4065 #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L 4066 #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018 4067 #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L 4068 #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000 4069 #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L 4070 #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008 4071 #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L 4072 #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004 4073 #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L 4074 #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001 4075 #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4076 #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4077 #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4078 #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4079 #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL 4080 #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000 4081 #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4082 #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4083 #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL 4084 #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000 4085 #define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L 4086 #define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c 4087 #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L 4088 #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010 4089 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4090 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4091 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L 4092 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4093 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4094 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4095 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4096 #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4097 #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L 4098 #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000 4099 #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L 4100 #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010 4101 #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L 4102 #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008 4103 #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L 4104 #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014 4105 #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L 4106 #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018 4107 #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L 4108 #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000 4109 #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L 4110 #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008 4111 #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L 4112 #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004 4113 #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L 4114 #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001 4115 #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4116 #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4117 #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4118 #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4119 #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL 4120 #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000 4121 #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4122 #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4123 #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L 4124 #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008 4125 #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L 4126 #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c 4127 #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L 4128 #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019 4129 #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L 4130 #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018 4131 #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L 4132 #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004 4133 #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL 4134 #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002 4135 #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L 4136 #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015 4137 #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L 4138 #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000 4139 #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L 4140 #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014 4141 #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L 4142 #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f 4143 #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L 4144 #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008 4145 #define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L 4146 #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000 4147 #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L 4148 #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002 4149 #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L 4150 #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001 4151 #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L 4152 #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003 4153 #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L 4154 #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014 4155 #define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L 4156 #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L 4157 #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000 4158 #define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008 4159 #define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L 4160 #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010 4161 #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L 4162 #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f 4163 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4164 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4165 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L 4166 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c 4167 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L 4168 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014 4169 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L 4170 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003 4171 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L 4172 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010 4173 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L 4174 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000 4175 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L 4176 #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011 4177 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L 4178 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007 4179 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L 4180 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000 4181 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L 4182 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001 4183 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L 4184 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004 4185 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L 4186 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005 4187 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L 4188 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006 4189 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4190 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008 4191 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4192 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4193 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L 4194 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018 4195 #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4196 #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4197 #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L 4198 #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010 4199 #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L 4200 #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000 4201 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4202 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4203 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L 4204 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c 4205 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L 4206 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014 4207 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L 4208 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003 4209 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L 4210 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010 4211 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L 4212 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000 4213 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L 4214 #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011 4215 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L 4216 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007 4217 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L 4218 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000 4219 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L 4220 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001 4221 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L 4222 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004 4223 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L 4224 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005 4225 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L 4226 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006 4227 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4228 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008 4229 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4230 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4231 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L 4232 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018 4233 #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4234 #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4235 #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L 4236 #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010 4237 #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L 4238 #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000 4239 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4240 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4241 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L 4242 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c 4243 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L 4244 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014 4245 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L 4246 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003 4247 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L 4248 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010 4249 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L 4250 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000 4251 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L 4252 #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011 4253 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L 4254 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007 4255 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L 4256 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000 4257 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L 4258 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001 4259 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L 4260 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004 4261 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L 4262 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005 4263 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L 4264 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006 4265 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4266 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008 4267 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4268 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4269 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L 4270 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018 4271 #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4272 #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4273 #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L 4274 #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010 4275 #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L 4276 #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000 4277 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4278 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4279 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L 4280 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c 4281 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L 4282 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014 4283 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L 4284 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003 4285 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L 4286 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010 4287 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L 4288 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000 4289 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L 4290 #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011 4291 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L 4292 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007 4293 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L 4294 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000 4295 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L 4296 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001 4297 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L 4298 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004 4299 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L 4300 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005 4301 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L 4302 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006 4303 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4304 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008 4305 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4306 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4307 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L 4308 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018 4309 #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4310 #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4311 #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L 4312 #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010 4313 #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L 4314 #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000 4315 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4316 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4317 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L 4318 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c 4319 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L 4320 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014 4321 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L 4322 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003 4323 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L 4324 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010 4325 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L 4326 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000 4327 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L 4328 #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011 4329 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L 4330 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007 4331 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L 4332 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000 4333 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L 4334 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001 4335 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L 4336 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004 4337 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L 4338 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005 4339 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L 4340 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006 4341 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4342 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008 4343 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4344 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4345 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L 4346 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 4347 #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4348 #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4349 #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L 4350 #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010 4351 #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L 4352 #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000 4353 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4354 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4355 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L 4356 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c 4357 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L 4358 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014 4359 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L 4360 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003 4361 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L 4362 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010 4363 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L 4364 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000 4365 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L 4366 #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011 4367 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L 4368 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007 4369 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L 4370 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000 4371 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L 4372 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001 4373 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L 4374 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004 4375 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L 4376 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005 4377 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L 4378 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006 4379 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4380 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008 4381 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4382 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4383 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L 4384 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018 4385 #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4386 #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4387 #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L 4388 #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010 4389 #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L 4390 #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000 4391 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4392 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4393 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L 4394 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c 4395 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L 4396 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014 4397 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L 4398 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003 4399 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L 4400 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010 4401 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L 4402 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000 4403 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L 4404 #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011 4405 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L 4406 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007 4407 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L 4408 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000 4409 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L 4410 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001 4411 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L 4412 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004 4413 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L 4414 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005 4415 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L 4416 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006 4417 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4418 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008 4419 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4420 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4421 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L 4422 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018 4423 #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4424 #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4425 #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L 4426 #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010 4427 #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L 4428 #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000 4429 #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L 4430 #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014 4431 #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L 4432 #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c 4433 #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL 4434 #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000 4435 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L 4436 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005 4437 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L 4438 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004 4439 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L 4440 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006 4441 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L 4442 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009 4443 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L 4444 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008 4445 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L 4446 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a 4447 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L 4448 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d 4449 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L 4450 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c 4451 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L 4452 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e 4453 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L 4454 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011 4455 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L 4456 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010 4457 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L 4458 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012 4459 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L 4460 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015 4461 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L 4462 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014 4463 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L 4464 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016 4465 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L 4466 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019 4467 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L 4468 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018 4469 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L 4470 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a 4471 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L 4472 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c 4473 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L 4474 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b 4475 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L 4476 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d 4477 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L 4478 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001 4479 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L 4480 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000 4481 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L 4482 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002 4483 #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L 4484 #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004 4485 #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L 4486 #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007 4487 #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L 4488 #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002 4489 #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L 4490 #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006 4491 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L 4492 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c 4493 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L 4494 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d 4495 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L 4496 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e 4497 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L 4498 #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f 4499 #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L 4500 #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012 4501 #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L 4502 #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000 4503 #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L 4504 #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008 4505 #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L 4506 #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005 4507 #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L 4508 #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010 4509 #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L 4510 #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000 4511 #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L 4512 #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c 4513 #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L 4514 #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d 4515 #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L 4516 #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008 4517 #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L 4518 #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010 4519 #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L 4520 #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000 4521 #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L 4522 #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c 4523 #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L 4524 #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d 4525 #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L 4526 #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008 4527 #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L 4528 #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010 4529 #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L 4530 #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000 4531 #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L 4532 #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c 4533 #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L 4534 #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d 4535 #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L 4536 #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008 4537 #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L 4538 #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010 4539 #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L 4540 #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000 4541 #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L 4542 #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c 4543 #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L 4544 #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d 4545 #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L 4546 #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008 4547 #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L 4548 #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b 4549 #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL 4550 #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000 4551 #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L 4552 #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f 4553 #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L 4554 #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010 4555 #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L 4556 #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011 4557 #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L 4558 #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012 4559 #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L 4560 #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013 4561 #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L 4562 #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014 4563 #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L 4564 #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015 4565 #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L 4566 #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009 4567 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L 4568 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b 4569 #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L 4570 #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d 4571 #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L 4572 #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006 4573 #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L 4574 #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005 4575 #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L 4576 #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e 4577 #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L 4578 #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a 4579 #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L 4580 #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c 4581 #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L 4582 #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016 4583 #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L 4584 #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017 4585 #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L 4586 #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008 4587 #define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL 4588 #define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000 4589 #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L 4590 #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000 4591 #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L 4592 #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c 4593 #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L 4594 #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006 4595 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L 4596 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001 4597 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L 4598 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e 4599 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L 4600 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007 4601 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L 4602 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002 4603 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L 4604 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010 4605 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L 4606 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 4607 #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L 4608 #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003 4609 #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L 4610 #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012 4611 #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L 4612 #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009 4613 #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L 4614 #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004 4615 #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L 4616 #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014 4617 #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L 4618 #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a 4619 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L 4620 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 4621 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L 4622 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016 4623 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L 4624 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b 4625 #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L 4626 #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000 4627 #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL 4628 #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002 4629 #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L 4630 #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004 4631 #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L 4632 #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016 4633 #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L 4634 #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c 4635 #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L 4636 #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000 4637 #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL 4638 #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002 4639 #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L 4640 #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004 4641 #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L 4642 #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006 4643 #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L 4644 #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008 4645 #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L 4646 #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a 4647 #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L 4648 #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c 4649 #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L 4650 #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a 4651 #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L 4652 #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018 4653 #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L 4654 #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010 4655 #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L 4656 #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012 4657 #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L 4658 #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e 4659 #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L 4660 #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014 4661 #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL 4662 #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000 4663 #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL 4664 #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000 4665 #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL 4666 #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000 4667 #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL 4668 #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000 4669 #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L 4670 #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012 4671 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L 4672 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L 4673 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e 4674 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L 4675 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d 4676 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f 4677 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L 4678 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L 4679 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013 4680 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L 4681 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010 4682 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014 4683 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L 4684 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016 4685 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L 4686 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015 4687 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L 4688 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L 4689 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a 4690 #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b 4691 #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L 4692 #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017 4693 #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L 4694 #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011 4695 #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L 4696 #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019 4697 #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L 4698 #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018 4699 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L 4700 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c 4701 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L 4702 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L 4703 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000 4704 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006 4705 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L 4706 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L 4707 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004 4708 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a 4709 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL 4710 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002 4711 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L 4712 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008 4713 #define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL 4714 #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000 4715 #define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL 4716 #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000 4717 #define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL 4718 #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000 4719 #define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL 4720 #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000 4721 #define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL 4722 #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000 4723 #define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL 4724 #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000 4725 #define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL 4726 #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000 4727 #define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL 4728 #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000 4729 #define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL 4730 #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000 4731 #define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL 4732 #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000 4733 #define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL 4734 #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000 4735 #define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL 4736 #define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000 4737 #define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL 4738 #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000 4739 #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL 4740 #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000 4741 #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL 4742 #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000 4743 #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL 4744 #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000 4745 #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4746 #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4747 #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L 4748 #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008 4749 #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L 4750 #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000 4751 #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4752 #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4753 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L 4754 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 4755 #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L 4756 #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000 4757 #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4758 #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4759 #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L 4760 #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008 4761 #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L 4762 #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000 4763 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L 4764 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 4765 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L 4766 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008 4767 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L 4768 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 4769 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L 4770 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 4771 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L 4772 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018 4773 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L 4774 #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 4775 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L 4776 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 4777 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L 4778 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008 4779 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L 4780 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 4781 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L 4782 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 4783 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L 4784 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018 4785 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L 4786 #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 4787 #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4788 #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4789 #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L 4790 #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4791 #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L 4792 #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4793 #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L 4794 #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008 4795 #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4796 #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4797 #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L 4798 #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4799 #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L 4800 #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4801 #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L 4802 #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008 4803 #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4804 #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4805 #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L 4806 #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4807 #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L 4808 #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4809 #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L 4810 #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008 4811 #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL 4812 #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000 4813 #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL 4814 #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000 4815 #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4816 #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 4817 #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L 4818 #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004 4819 #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L 4820 #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005 4821 #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L 4822 #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006 4823 #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L 4824 #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007 4825 #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L 4826 #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008 4827 #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L 4828 #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009 4829 #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L 4830 #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c 4831 #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L 4832 #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003 4833 #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L 4834 #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002 4835 #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L 4836 #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000 4837 #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L 4838 #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001 4839 #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL 4840 #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000 4841 #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL 4842 #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000 4843 #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4844 #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 4845 #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL 4846 #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000 4847 #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L 4848 #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a 4849 #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L 4850 #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014 4851 #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L 4852 #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001 4853 #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L 4854 #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000 4855 #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL 4856 #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000 4857 #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL 4858 #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000 4859 #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL 4860 #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000 4861 #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L 4862 #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005 4863 #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L 4864 #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006 4865 #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L 4866 #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004 4867 #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L 4868 #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d 4869 #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L 4870 #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e 4871 #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L 4872 #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c 4873 #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L 4874 #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015 4875 #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L 4876 #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016 4877 #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L 4878 #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014 4879 #define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL 4880 #define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000 4881 #define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L 4882 #define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008 4883 #define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L 4884 #define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010 4885 #define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL 4886 #define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000 4887 #define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L 4888 #define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010 4889 #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL 4890 #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000 4891 #define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L 4892 #define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000 4893 #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL 4894 #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000 4895 #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L 4896 #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000 4897 #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL 4898 #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000 4899 #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL 4900 #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000 4901 #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL 4902 #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000 4903 #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L 4904 #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000 4905 #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L 4906 #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f 4907 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L 4908 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c 4909 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L 4910 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c 4911 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L 4912 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010 4913 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L 4914 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008 4915 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L 4916 #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014 4917 #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L 4918 #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000 4919 #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL 4920 #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000 4921 #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L 4922 #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006 4923 #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L 4924 #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008 4925 #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L 4926 #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009 4927 #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L 4928 #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018 4929 #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L 4930 #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019 4931 #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L 4932 #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a 4933 #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L 4934 #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b 4935 #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L 4936 #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c 4937 #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L 4938 #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d 4939 #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L 4940 #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007 4941 #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L 4942 #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010 4943 #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L 4944 #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011 4945 #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L 4946 #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012 4947 #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L 4948 #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013 4949 #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L 4950 #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014 4951 #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L 4952 #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015 4953 #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L 4954 #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c 4955 #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L 4956 #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005 4957 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L 4958 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006 4959 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L 4960 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008 4961 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L 4962 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009 4963 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L 4964 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018 4965 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L 4966 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019 4967 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L 4968 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a 4969 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L 4970 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b 4971 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L 4972 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c 4973 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L 4974 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d 4975 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L 4976 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007 4977 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L 4978 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010 4979 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L 4980 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011 4981 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L 4982 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012 4983 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L 4984 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013 4985 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L 4986 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014 4987 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L 4988 #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015 4989 #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L 4990 #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c 4991 #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L 4992 #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005 4993 #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L 4994 #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003 4995 #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L 4996 #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011 4997 #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L 4998 #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 4999 #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L 5000 #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012 5001 #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L 5002 #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 5003 #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L 5004 #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 5005 #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L 5006 #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006 5007 #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L 5008 #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 5009 #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L 5010 #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007 5011 #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L 5012 #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 5013 #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L 5014 #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008 5015 #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L 5016 #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 5017 #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L 5018 #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009 5019 #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L 5020 #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a 5021 #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L 5022 #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b 5023 #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L 5024 #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c 5025 #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L 5026 #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d 5027 #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L 5028 #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e 5029 #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L 5030 #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001 5031 #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L 5032 #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002 5033 #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L 5034 #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 5035 #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L 5036 #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000 5037 #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L 5038 #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006 5039 #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L 5040 #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008 5041 #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L 5042 #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a 5043 #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L 5044 #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c 5045 #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L 5046 #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e 5047 #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L 5048 #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010 5049 #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L 5050 #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012 5051 #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L 5052 #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014 5053 #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L 5054 #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016 5055 #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L 5056 #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018 5057 #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L 5058 #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a 5059 #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L 5060 #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c 5061 #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL 5062 #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002 5063 #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L 5064 #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004 5065 #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L 5066 #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000 5067 #define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L 5068 #define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019 5069 #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L 5070 #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d 5071 #define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L 5072 #define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000 5073 #define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L 5074 #define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001 5075 #define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L 5076 #define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003 5077 #define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L 5078 #define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b 5079 #define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L 5080 #define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010 5081 #define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L 5082 #define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011 5083 #define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L 5084 #define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012 5085 #define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L 5086 #define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013 5087 #define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L 5088 #define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014 5089 #define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L 5090 #define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015 5091 #define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L 5092 #define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018 5093 #define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L 5094 #define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002 5095 #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L 5096 #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c 5097 #define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L 5098 #define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a 5099 #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL 5100 #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000 5101 #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L 5102 #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004 5103 #define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L 5104 #define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000 5105 #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L 5106 #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008 5107 #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL 5108 #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002 5109 #define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL 5110 #define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000 5111 #define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL 5112 #define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000 5113 #define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL 5114 #define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000 5115 #define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL 5116 #define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000 5117 #define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL 5118 #define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000 5119 #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL 5120 #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000 5121 #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L 5122 #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014 5123 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L 5124 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010 5125 #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L 5126 #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002 5127 #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L 5128 #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000 5129 #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L 5130 #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001 5131 #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL 5132 #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000 5133 #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL 5134 #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000 5135 #define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L 5136 #define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000 5137 #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L 5138 #define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001 5139 #define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L 5140 #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002 5141 #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L 5142 #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b 5143 #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L 5144 #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c 5145 #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L 5146 #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c 5147 #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L 5148 #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010 5149 #define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L 5150 #define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008 5151 #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L 5152 #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018 5153 #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL 5154 #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000 5155 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL 5156 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 5157 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5158 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5159 #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L 5160 #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e 5161 #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L 5162 #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a 5163 #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L 5164 #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010 5165 #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L 5166 #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d 5167 #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L 5168 #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b 5169 #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL 5170 #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000 5171 #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L 5172 #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004 5173 #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L 5174 #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010 5175 #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L 5176 #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008 5177 #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL 5178 #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000 5179 #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L 5180 #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008 5181 #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L 5182 #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a 5183 #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L 5184 #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009 5185 #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L 5186 #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006 5187 #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L 5188 #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000 5189 #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L 5190 #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004 5191 #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL 5192 #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000 5193 #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL 5194 #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000 5195 #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5196 #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5197 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L 5198 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000 5199 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L 5200 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 5201 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L 5202 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004 5203 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L 5204 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 5205 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L 5206 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008 5207 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L 5208 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b 5209 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L 5210 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c 5211 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L 5212 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f 5213 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L 5214 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010 5215 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L 5216 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013 5217 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L 5218 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000 5219 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L 5220 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 5221 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L 5222 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004 5223 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L 5224 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 5225 #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L 5226 #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008 5227 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L 5228 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 5229 #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L 5230 #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016 5231 #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L 5232 #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010 5233 #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L 5234 #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014 5235 #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL 5236 #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000 5237 #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L 5238 #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008 5239 #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L 5240 #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015 5241 #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L 5242 #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c 5243 #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L 5244 #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 5245 #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L 5246 #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 5247 #define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L 5248 #define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000 5249 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L 5250 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013 5251 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L 5252 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f 5253 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L 5254 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011 5255 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L 5256 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012 5257 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L 5258 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008 5259 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL 5260 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000 5261 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L 5262 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014 5263 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L 5264 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015 5265 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L 5266 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016 5267 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L 5268 #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018 5269 #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L 5270 #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008 5271 #define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L 5272 #define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c 5273 #define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L 5274 #define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010 5275 #define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L 5276 #define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000 5277 #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L 5278 #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008 5279 #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL 5280 #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000 5281 #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L 5282 #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000 5283 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L 5284 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008 5285 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L 5286 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L 5287 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c 5288 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004 5289 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L 5290 #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000 5291 #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L 5292 #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010 5293 #define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L 5294 #define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014 5295 #define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L 5296 #define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000 5297 #define DIG_FE_CNTL__DIG_START_MASK 0x00000400L 5298 #define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a 5299 #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L 5300 #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008 5301 #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L 5302 #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004 5303 #define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L 5304 #define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012 5305 #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L 5306 #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018 5307 #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 5308 #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 5309 #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L 5310 #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d 5311 #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L 5312 #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008 5313 #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 5314 #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 5315 #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 5316 #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 5317 #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L 5318 #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000 5319 #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L 5320 #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 5321 #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 5322 #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 5323 #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 5324 #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 5325 #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 5326 #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 5327 #define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L 5328 #define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008 5329 #define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L 5330 #define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000 5331 #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L 5332 #define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001 5333 #define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L 5334 #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002 5335 #define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L 5336 #define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003 5337 #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L 5338 #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008 5339 #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L 5340 #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000 5341 #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L 5342 #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004 5343 #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL 5344 #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000 5345 #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL 5346 #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000 5347 #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L 5348 #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018 5349 #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L 5350 #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001 5351 #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L 5352 #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000 5353 #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L 5354 #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005 5355 #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L 5356 #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004 5357 #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L 5358 #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009 5359 #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L 5360 #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008 5361 #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L 5362 #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d 5363 #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L 5364 #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c 5365 #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L 5366 #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011 5367 #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L 5368 #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010 5369 #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L 5370 #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015 5371 #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L 5372 #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014 5373 #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L 5374 #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001 5375 #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L 5376 #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004 5377 #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L 5378 #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005 5379 #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L 5380 #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010 5381 #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L 5382 #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006 5383 #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L 5384 #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000 5385 #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L 5386 #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008 5387 #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L 5388 #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002 5389 #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 5390 #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004 5391 #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL 5392 #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000 5393 #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L 5394 #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e 5395 #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L 5396 #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c 5397 #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L 5398 #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d 5399 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L 5400 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f 5401 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L 5402 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014 5403 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L 5404 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019 5405 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL 5406 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000 5407 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L 5408 #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010 5409 #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L 5410 #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e 5411 #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L 5412 #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c 5413 #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L 5414 #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d 5415 #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L 5416 #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014 5417 #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L 5418 #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013 5419 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L 5420 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014 5421 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L 5422 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013 5423 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5424 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5425 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5426 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5427 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5428 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5429 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5430 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5431 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L 5432 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007 5433 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L 5434 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008 5435 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5436 #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5437 #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L 5438 #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011 5439 #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L 5440 #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012 5441 #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5442 #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5443 #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5444 #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5445 #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L 5446 #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f 5447 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L 5448 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003 5449 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L 5450 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002 5451 #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5452 #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5453 #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L 5454 #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014 5455 #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L 5456 #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013 5457 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5458 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5459 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5460 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5461 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5462 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5463 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5464 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5465 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L 5466 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007 5467 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L 5468 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008 5469 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5470 #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5471 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L 5472 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011 5473 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L 5474 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012 5475 #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5476 #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5477 #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5478 #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5479 #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L 5480 #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f 5481 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L 5482 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003 5483 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L 5484 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002 5485 #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5486 #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5487 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L 5488 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014 5489 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L 5490 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013 5491 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5492 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5493 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5494 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5495 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5496 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5497 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5498 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5499 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L 5500 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007 5501 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L 5502 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008 5503 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5504 #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5505 #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L 5506 #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011 5507 #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L 5508 #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012 5509 #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5510 #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5511 #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5512 #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5513 #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L 5514 #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f 5515 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L 5516 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003 5517 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L 5518 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002 5519 #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5520 #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5521 #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L 5522 #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014 5523 #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L 5524 #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013 5525 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5526 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5527 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5528 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5529 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5530 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5531 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5532 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5533 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L 5534 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007 5535 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L 5536 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008 5537 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5538 #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5539 #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L 5540 #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011 5541 #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L 5542 #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012 5543 #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5544 #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5545 #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5546 #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5547 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L 5548 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003 5549 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L 5550 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002 5551 #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5552 #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5553 #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L 5554 #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014 5555 #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L 5556 #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013 5557 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5558 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5559 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5560 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5561 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5562 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5563 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5564 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5565 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L 5566 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007 5567 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L 5568 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008 5569 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5570 #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5571 #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L 5572 #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011 5573 #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L 5574 #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012 5575 #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5576 #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5577 #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5578 #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5579 #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L 5580 #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f 5581 #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L 5582 #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018 5583 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L 5584 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003 5585 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L 5586 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002 5587 #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5588 #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5589 #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5590 #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5591 #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5592 #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5593 #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5594 #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5595 #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5596 #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5597 #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L 5598 #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007 5599 #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L 5600 #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008 5601 #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5602 #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5603 #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L 5604 #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016 5605 #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L 5606 #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017 5607 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L 5608 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011 5609 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L 5610 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 5611 #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L 5612 #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019 5613 #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L 5614 #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018 5615 #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L 5616 #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015 5617 #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5618 #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5619 #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5620 #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5621 #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L 5622 #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f 5623 #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L 5624 #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b 5625 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L 5626 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a 5627 #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L 5628 #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003 5629 #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L 5630 #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002 5631 #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5632 #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5633 #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L 5634 #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000 5635 #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L 5636 #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010 5637 #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L 5638 #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004 5639 #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L 5640 #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000 5641 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL 5642 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000 5643 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 5644 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019 5645 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L 5646 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L 5647 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b 5648 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L 5649 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a 5650 #define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e 5651 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L 5652 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d 5653 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L 5654 #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c 5655 #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L 5656 #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002 5657 #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L 5658 #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003 5659 #define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L 5660 #define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004 5661 #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L 5662 #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001 5663 #define DMCU_CTRL__RESET_UC_MASK 0x00000001L 5664 #define DMCU_CTRL__RESET_UC__SHIFT 0x00000000 5665 #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L 5666 #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016 5667 #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL 5668 #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000 5669 #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L 5670 #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010 5671 #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L 5672 #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014 5673 #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL 5674 #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000 5675 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL 5676 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000 5677 #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L 5678 #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010 5679 #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L 5680 #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014 5681 #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL 5682 #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000 5683 #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L 5684 #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000 5685 #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L 5686 #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017 5687 #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L 5688 #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010 5689 #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL 5690 #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002 5691 #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L 5692 #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000 5693 #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL 5694 #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000 5695 #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL 5696 #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000 5697 #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL 5698 #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000 5699 #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L 5700 #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008 5701 #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL 5702 #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000 5703 #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L 5704 #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008 5705 #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL 5706 #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000 5707 #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L 5708 #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008 5709 #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L 5710 #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010 5711 #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL 5712 #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000 5713 #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L 5714 #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008 5715 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L 5716 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002 5717 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L 5718 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002 5719 #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L 5720 #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000 5721 #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L 5722 #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000 5723 #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L 5724 #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001 5725 #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L 5726 #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001 5727 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L 5728 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012 5729 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L 5730 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012 5731 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L 5732 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c 5733 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L 5734 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c 5735 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L 5736 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013 5737 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L 5738 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013 5739 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L 5740 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d 5741 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L 5742 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d 5743 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L 5744 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014 5745 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L 5746 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014 5747 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L 5748 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e 5749 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L 5750 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e 5751 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L 5752 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015 5753 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L 5754 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015 5755 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L 5756 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f 5757 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L 5758 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f 5759 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L 5760 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016 5761 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L 5762 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016 5763 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L 5764 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010 5765 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L 5766 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010 5767 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L 5768 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017 5769 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L 5770 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017 5771 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L 5772 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011 5773 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L 5774 #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011 5775 #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L 5776 #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008 5777 #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L 5778 #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008 5779 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L 5780 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003 5781 #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L 5782 #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009 5783 #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L 5784 #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a 5785 #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L 5786 #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a 5787 #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L 5788 #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b 5789 #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L 5790 #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b 5791 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L 5792 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018 5793 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L 5794 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018 5795 #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L 5796 #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019 5797 #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L 5798 #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019 5799 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L 5800 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a 5801 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L 5802 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a 5803 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L 5804 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b 5805 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L 5806 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b 5807 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L 5808 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c 5809 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L 5810 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c 5811 #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L 5812 #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d 5813 #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L 5814 #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d 5815 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L 5816 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002 5817 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L 5818 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000 5819 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L 5820 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001 5821 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L 5822 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012 5823 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L 5824 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c 5825 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L 5826 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013 5827 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L 5828 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d 5829 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L 5830 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014 5831 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L 5832 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e 5833 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L 5834 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015 5835 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L 5836 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f 5837 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L 5838 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016 5839 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L 5840 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010 5841 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L 5842 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017 5843 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L 5844 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011 5845 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L 5846 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009 5847 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L 5848 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a 5849 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L 5850 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b 5851 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L 5852 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002 5853 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L 5854 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000 5855 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L 5856 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001 5857 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L 5858 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012 5859 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L 5860 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c 5861 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L 5862 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013 5863 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L 5864 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d 5865 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L 5866 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014 5867 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L 5868 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e 5869 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L 5870 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015 5871 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L 5872 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f 5873 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L 5874 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016 5875 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L 5876 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010 5877 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L 5878 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017 5879 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L 5880 #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011 5881 #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L 5882 #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008 5883 #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L 5884 #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003 5885 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L 5886 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018 5887 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L 5888 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019 5889 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L 5890 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a 5891 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L 5892 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b 5893 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L 5894 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c 5895 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L 5896 #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d 5897 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L 5898 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002 5899 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L 5900 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000 5901 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L 5902 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001 5903 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L 5904 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012 5905 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L 5906 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c 5907 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L 5908 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013 5909 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L 5910 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d 5911 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L 5912 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014 5913 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L 5914 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e 5915 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L 5916 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015 5917 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L 5918 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f 5919 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L 5920 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016 5921 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L 5922 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010 5923 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L 5924 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017 5925 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L 5926 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011 5927 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L 5928 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008 5929 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L 5930 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003 5931 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L 5932 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018 5933 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L 5934 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019 5935 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L 5936 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a 5937 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L 5938 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b 5939 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L 5940 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c 5941 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L 5942 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d 5943 #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL 5944 #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000 5945 #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL 5946 #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000 5947 #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL 5948 #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000 5949 #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL 5950 #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000 5951 #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL 5952 #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000 5953 #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L 5954 #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008 5955 #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L 5956 #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004 5957 #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L 5958 #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001 5959 #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L 5960 #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000 5961 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L 5962 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005 5963 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L 5964 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003 5965 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L 5966 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002 5967 #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L 5968 #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008 5969 #define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L 5970 #define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000 5971 #define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L 5972 #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002 5973 #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L 5974 #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001 5975 #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL 5976 #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000 5977 #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL 5978 #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000 5979 #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5980 #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5981 #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L 5982 #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008 5983 #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L 5984 #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000 5985 #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L 5986 #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010 5987 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L 5988 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003 5989 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L 5990 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000 5991 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L 5992 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e 5993 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L 5994 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f 5995 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L 5996 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009 5997 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L 5998 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002 5999 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L 6000 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d 6001 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L 6002 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c 6003 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L 6004 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b 6005 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L 6006 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a 6007 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L 6008 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007 6009 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L 6010 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006 6011 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L 6012 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005 6013 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L 6014 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004 6015 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L 6016 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008 6017 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L 6018 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001 6019 #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6020 #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 6021 #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L 6022 #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c 6023 #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 6024 #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 6025 #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 6026 #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e 6027 #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 6028 #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 6029 #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L 6030 #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c 6031 #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6032 #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 6033 #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 6034 #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c 6035 #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 6036 #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 6037 #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL 6038 #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000 6039 #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L 6040 #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010 6041 #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L 6042 #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000 6043 #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L 6044 #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d 6045 #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L 6046 #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018 6047 #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L 6048 #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004 6049 #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L 6050 #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c 6051 #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L 6052 #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002 6053 #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L 6054 #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010 6055 #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L 6056 #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008 6057 #define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL 6058 #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000 6059 #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L 6060 #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010 6061 #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L 6062 #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011 6063 #define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL 6064 #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000 6065 #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L 6066 #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010 6067 #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L 6068 #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011 6069 #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL 6070 #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000 6071 #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L 6072 #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008 6073 #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L 6074 #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009 6075 #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L 6076 #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000 6077 #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L 6078 #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001 6079 #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L 6080 #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002 6081 #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L 6082 #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003 6083 #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L 6084 #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004 6085 #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L 6086 #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005 6087 #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L 6088 #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008 6089 #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L 6090 #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010 6091 #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L 6092 #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014 6093 #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L 6094 #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011 6095 #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL 6096 #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000 6097 #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L 6098 #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018 6099 #define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L 6100 #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c 6101 #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL 6102 #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000 6103 #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL 6104 #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 6105 #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6106 #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6107 #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L 6108 #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004 6109 #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L 6110 #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000 6111 #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L 6112 #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008 6113 #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L 6114 #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000 6115 #define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL 6116 #define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000 6117 #define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL 6118 #define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000 6119 #define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL 6120 #define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000 6121 #define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL 6122 #define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000 6123 #define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL 6124 #define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000 6125 #define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL 6126 #define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000 6127 #define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL 6128 #define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000 6129 #define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL 6130 #define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000 6131 #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL 6132 #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000 6133 #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL 6134 #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000 6135 #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6136 #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6137 #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL 6138 #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000 6139 #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL 6140 #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000 6141 #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL 6142 #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000 6143 #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL 6144 #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000 6145 #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL 6146 #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000 6147 #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL 6148 #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000 6149 #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL 6150 #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000 6151 #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL 6152 #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000 6153 #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL 6154 #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000 6155 #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL 6156 #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000 6157 #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL 6158 #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000 6159 #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL 6160 #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000 6161 #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL 6162 #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000 6163 #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL 6164 #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000 6165 #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL 6166 #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000 6167 #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL 6168 #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000 6169 #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL 6170 #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000 6171 #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL 6172 #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000 6173 #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL 6174 #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000 6175 #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL 6176 #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000 6177 #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL 6178 #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000 6179 #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL 6180 #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000 6181 #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL 6182 #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000 6183 #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL 6184 #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000 6185 #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL 6186 #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000 6187 #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL 6188 #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000 6189 #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL 6190 #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000 6191 #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL 6192 #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000 6193 #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL 6194 #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000 6195 #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL 6196 #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000 6197 #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL 6198 #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000 6199 #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL 6200 #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000 6201 #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL 6202 #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000 6203 #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL 6204 #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000 6205 #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL 6206 #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000 6207 #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL 6208 #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000 6209 #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL 6210 #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000 6211 #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL 6212 #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000 6213 #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL 6214 #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000 6215 #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL 6216 #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000 6217 #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL 6218 #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000 6219 #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL 6220 #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000 6221 #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL 6222 #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000 6223 #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL 6224 #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000 6225 #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL 6226 #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000 6227 #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL 6228 #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000 6229 #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL 6230 #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000 6231 #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL 6232 #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000 6233 #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL 6234 #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000 6235 #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL 6236 #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000 6237 #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL 6238 #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000 6239 #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL 6240 #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000 6241 #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL 6242 #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000 6243 #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL 6244 #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000 6245 #define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L 6246 #define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000 6247 #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L 6248 #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018 6249 #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L 6250 #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010 6251 #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L 6252 #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008 6253 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L 6254 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000 6255 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L 6256 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001 6257 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L 6258 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002 6259 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L 6260 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003 6261 #define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L 6262 #define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010 6263 #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L 6264 #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018 6265 #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L 6266 #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000 6267 #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L 6268 #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010 6269 #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L 6270 #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004 6271 #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L 6272 #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004 6273 #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L 6274 #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000 6275 #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L 6276 #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008 6277 #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL 6278 #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000 6279 #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L 6280 #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008 6281 #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L 6282 #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010 6283 #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L 6284 #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008 6285 #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L 6286 #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000 6287 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L 6288 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008 6289 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L 6290 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010 6291 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L 6292 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018 6293 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL 6294 #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000 6295 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L 6296 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008 6297 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L 6298 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014 6299 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L 6300 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002 6301 #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L 6302 #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000 6303 #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L 6304 #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001 6305 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L 6306 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c 6307 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L 6308 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008 6309 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L 6310 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004 6311 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L 6312 #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000 6313 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L 6314 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000 6315 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L 6316 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008 6317 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L 6318 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004 6319 #define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL 6320 #define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000 6321 #define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L 6322 #define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a 6323 #define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L 6324 #define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014 6325 #define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL 6326 #define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000 6327 #define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L 6328 #define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a 6329 #define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L 6330 #define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014 6331 #define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL 6332 #define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000 6333 #define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L 6334 #define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a 6335 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L 6336 #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 6337 #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL 6338 #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000 6339 #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL 6340 #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000 6341 #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL 6342 #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000 6343 #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL 6344 #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000 6345 #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL 6346 #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000 6347 #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL 6348 #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000 6349 #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL 6350 #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000 6351 #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL 6352 #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000 6353 #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL 6354 #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000 6355 #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL 6356 #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000 6357 #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL 6358 #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000 6359 #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL 6360 #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000 6361 #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L 6362 #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010 6363 #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL 6364 #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000 6365 #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL 6366 #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 6367 #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L 6368 #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 6369 #define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK_MASK 0x00030000L 6370 #define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT 0x00000010 6371 #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L 6372 #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 6373 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L 6374 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004 6375 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L 6376 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008 6377 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L 6378 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L 6379 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c 6380 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010 6381 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L 6382 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a 6383 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L 6384 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000 6385 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L 6386 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009 6387 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L 6388 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 6389 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L 6390 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 6391 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00003000L 6392 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c 6393 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L 6394 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 6395 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L 6396 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000 6397 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L 6398 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004 6399 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L 6400 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007 6401 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L 6402 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005 6403 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L 6404 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006 6405 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L 6406 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b 6407 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L 6408 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a 6409 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L 6410 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009 6411 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L 6412 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 6413 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L 6414 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 6415 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00003000L 6416 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0000000c 6417 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L 6418 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 6419 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L 6420 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004 6421 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L 6422 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007 6423 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L 6424 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005 6425 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L 6426 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006 6427 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L 6428 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b 6429 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L 6430 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a 6431 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L 6432 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009 6433 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L 6434 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008 6435 #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L 6436 #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010 6437 #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL 6438 #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000 6439 #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL 6440 #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000 6441 #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL 6442 #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 6443 #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6444 #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6445 #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L 6446 #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000 6447 #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L 6448 #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011 6449 #define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L 6450 #define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008 6451 #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L 6452 #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004 6453 #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL 6454 #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000 6455 #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L 6456 #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018 6457 #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L 6458 #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c 6459 #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L 6460 #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008 6461 #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL 6462 #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000 6463 #define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L 6464 #define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003 6465 #define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L 6466 #define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008 6467 #define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L 6468 #define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010 6469 #define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L 6470 #define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018 6471 #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L 6472 #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000 6473 #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L 6474 #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004 6475 #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L 6476 #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010 6477 #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL 6478 #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000 6479 #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL 6480 #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000 6481 #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L 6482 #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010 6483 #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L 6484 #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000 6485 #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L 6486 #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004 6487 #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L 6488 #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008 6489 #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L 6490 #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a 6491 #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL 6492 #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000 6493 #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L 6494 #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000 6495 #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L 6496 #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008 6497 #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L 6498 #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018 6499 #define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L 6500 #define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000 6501 #define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L 6502 #define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010 6503 #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L 6504 #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008 6505 #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L 6506 #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018 6507 #define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L 6508 #define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000 6509 #define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L 6510 #define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010 6511 #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L 6512 #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008 6513 #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L 6514 #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018 6515 #define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L 6516 #define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000 6517 #define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L 6518 #define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010 6519 #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L 6520 #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008 6521 #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L 6522 #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000 6523 #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L 6524 #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018 6525 #define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L 6526 #define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008 6527 #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L 6528 #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000 6529 #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L 6530 #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010 6531 #define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL 6532 #define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000 6533 #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL 6534 #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000 6535 #define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL 6536 #define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000 6537 #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL 6538 #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000 6539 #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L 6540 #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000 6541 #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L 6542 #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010 6543 #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L 6544 #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c 6545 #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L 6546 #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004 6547 #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L 6548 #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008 6549 #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L 6550 #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018 6551 #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L 6552 #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014 6553 #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L 6554 #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015 6555 #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L 6556 #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016 6557 #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L 6558 #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017 6559 #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L 6560 #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c 6561 #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L 6562 #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000 6563 #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL 6564 #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000 6565 #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L 6566 #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 6567 #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L 6568 #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 6569 #define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL 6570 #define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000 6571 #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL 6572 #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000 6573 #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L 6574 #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010 6575 #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L 6576 #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c 6577 #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L 6578 #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d 6579 #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L 6580 #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018 6581 #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L 6582 #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014 6583 #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L 6584 #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010 6585 #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL 6586 #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001 6587 #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L 6588 #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004 6589 #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L 6590 #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008 6591 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L 6592 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000 6593 #define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L 6594 #define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000 6595 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L 6596 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006 6597 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L 6598 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004 6599 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L 6600 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005 6601 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L 6602 #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007 6603 #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L 6604 #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c 6605 #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L 6606 #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008 6607 #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL 6608 #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000 6609 #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL 6610 #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000 6611 #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6612 #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6613 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L 6614 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001 6615 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L 6616 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000 6617 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L 6618 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002 6619 #define DP_VID_M__DP_VID_M_MASK 0x00ffffffL 6620 #define DP_VID_M__DP_VID_M__SHIFT 0x00000000 6621 #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL 6622 #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000 6623 #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L 6624 #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010 6625 #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L 6626 #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018 6627 #define DP_VID_N__DP_VID_N_MASK 0x00ffffffL 6628 #define DP_VID_N__DP_VID_N__SHIFT 0x00000000 6629 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L 6630 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014 6631 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L 6632 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008 6633 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L 6634 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000 6635 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L 6636 #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010 6637 #define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L 6638 #define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008 6639 #define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L 6640 #define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018 6641 #define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L 6642 #define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000 6643 #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L 6644 #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011 6645 #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L 6646 #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008 6647 #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L 6648 #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010 6649 #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L 6650 #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000 6651 #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L 6652 #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012 6653 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L 6654 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011 6655 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L 6656 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008 6657 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L 6658 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010 6659 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L 6660 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000 6661 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L 6662 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012 6663 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L 6664 #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014 6665 #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L 6666 #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018 6667 #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L 6668 #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c 6669 #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L 6670 #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011 6671 #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L 6672 #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008 6673 #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L 6674 #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010 6675 #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L 6676 #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000 6677 #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L 6678 #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012 6679 #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L 6680 #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000 6681 #define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L 6682 #define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018 6683 #define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L 6684 #define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f 6685 #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L 6686 #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008 6687 #define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L 6688 #define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012 6689 #define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L 6690 #define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000 6691 #define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L 6692 #define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010 6693 #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L 6694 #define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001 6695 #define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L 6696 #define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011 6697 #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL 6698 #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000 6699 #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL 6700 #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000 6701 #define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L 6702 #define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010 6703 #define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L 6704 #define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000 6705 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 6706 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 6707 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L 6708 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d 6709 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L 6710 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008 6711 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 6712 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 6713 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 6714 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 6715 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L 6716 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000 6717 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L 6718 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 6719 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 6720 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 6721 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 6722 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 6723 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 6724 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 6725 #define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L 6726 #define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008 6727 #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L 6728 #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000 6729 #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL 6730 #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000 6731 #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L 6732 #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000 6733 #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L 6734 #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010 6735 #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L 6736 #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c 6737 #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L 6738 #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008 6739 #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L 6740 #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c 6741 #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L 6742 #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d 6743 #define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L 6744 #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004 6745 #define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL 6746 #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000 6747 #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L 6748 #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004 6749 #define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L 6750 #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000 6751 #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L 6752 #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001 6753 #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L 6754 #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 6755 #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL 6756 #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 6757 #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL 6758 #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 6759 #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L 6760 #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 6761 #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L 6762 #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010 6763 #define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L 6764 #define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010 6765 #define FBC_CNTL__FBC_EN_MASK 0x80000000L 6766 #define FBC_CNTL__FBC_EN__SHIFT 0x0000001f 6767 #define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L 6768 #define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000 6769 #define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L 6770 #define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019 6771 #define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL 6772 #define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001 6773 #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L 6774 #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010 6775 #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L 6776 #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011 6777 #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L 6778 #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012 6779 #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L 6780 #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013 6781 #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L 6782 #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014 6783 #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL 6784 #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000 6785 #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L 6786 #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008 6787 #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L 6788 #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a 6789 #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L 6790 #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009 6791 #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L 6792 #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b 6793 #define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L 6794 #define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010 6795 #define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L 6796 #define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000 6797 #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL 6798 #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000 6799 #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L 6800 #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010 6801 #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL 6802 #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000 6803 #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L 6804 #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010 6805 #define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L 6806 #define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010 6807 #define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L 6808 #define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011 6809 #define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L 6810 #define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018 6811 #define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL 6812 #define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000 6813 #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L 6814 #define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008 6815 #define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL 6816 #define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000 6817 #define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL 6818 #define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000 6819 #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L 6820 #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b 6821 #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L 6822 #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004 6823 #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L 6824 #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008 6825 #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L 6826 #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a 6827 #define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L 6828 #define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003 6829 #define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L 6830 #define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000 6831 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL 6832 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000 6833 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L 6834 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f 6835 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L 6836 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011 6837 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L 6838 #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010 6839 #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL 6840 #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000 6841 #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL 6842 #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000 6843 #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL 6844 #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000 6845 #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL 6846 #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000 6847 #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL 6848 #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000 6849 #define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL 6850 #define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000 6851 #define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL 6852 #define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000 6853 #define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL 6854 #define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000 6855 #define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL 6856 #define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000 6857 #define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL 6858 #define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000 6859 #define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL 6860 #define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000 6861 #define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL 6862 #define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000 6863 #define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL 6864 #define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000 6865 #define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL 6866 #define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000 6867 #define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL 6868 #define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000 6869 #define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL 6870 #define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000 6871 #define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL 6872 #define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000 6873 #define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL 6874 #define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000 6875 #define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL 6876 #define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000 6877 #define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL 6878 #define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000 6879 #define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL 6880 #define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000 6881 #define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL 6882 #define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000 6883 #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L 6884 #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010 6885 #define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L 6886 #define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000 6887 #define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L 6888 #define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008 6889 #define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L 6890 #define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a 6891 #define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L 6892 #define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004 6893 #define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L 6894 #define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003 6895 #define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L 6896 #define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015 6897 #define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L 6898 #define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014 6899 #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L 6900 #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c 6901 #define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L 6902 #define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b 6903 #define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L 6904 #define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c 6905 #define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L 6906 #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002 6907 #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L 6908 #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008 6909 #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL 6910 #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000 6911 #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L 6912 #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007 6913 #define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L 6914 #define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000 6915 #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL 6916 #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000 6917 #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL 6918 #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000 6919 #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6920 #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6921 #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L 6922 #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a 6923 #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L 6924 #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c 6925 #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L 6926 #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e 6927 #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L 6928 #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d 6929 #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L 6930 #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f 6931 #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L 6932 #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e 6933 #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L 6934 #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c 6935 #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L 6936 #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 6937 #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L 6938 #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 6939 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L 6940 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014 6941 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L 6942 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010 6943 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L 6944 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015 6945 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L 6946 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019 6947 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L 6948 #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018 6949 #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L 6950 #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004 6951 #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L 6952 #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000 6953 #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L 6954 #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 6955 #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L 6956 #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000 6957 #define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L 6958 #define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010 6959 #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L 6960 #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000 6961 #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L 6962 #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004 6963 #define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L 6964 #define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004 6965 #define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L 6966 #define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000 6967 #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L 6968 #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014 6969 #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L 6970 #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018 6971 #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L 6972 #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c 6973 #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L 6974 #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008 6975 #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L 6976 #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010 6977 #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL 6978 #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000 6979 #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L 6980 #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010 6981 #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL 6982 #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 6983 #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L 6984 #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010 6985 #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L 6986 #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010 6987 #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL 6988 #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000 6989 #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L 6990 #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010 6991 #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL 6992 #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000 6993 #define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL 6994 #define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000 6995 #define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL 6996 #define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000 6997 #define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL 6998 #define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000 6999 #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L 7000 #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 7001 #define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL 7002 #define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000 7003 #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL 7004 #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000 7005 #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL 7006 #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000 7007 #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL 7008 #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000 7009 #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L 7010 #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 7011 #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L 7012 #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 7013 #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL 7014 #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000 7015 #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L 7016 #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010 7017 #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL 7018 #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000 7019 #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L 7020 #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010 7021 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L 7022 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000 7023 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L 7024 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010 7025 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L 7026 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008 7027 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L 7028 #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c 7029 #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L 7030 #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004 7031 #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L 7032 #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000 7033 #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL 7034 #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000 7035 #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL 7036 #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000 7037 #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL 7038 #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000 7039 #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL 7040 #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 7041 #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7042 #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7043 #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL 7044 #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000 7045 #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L 7046 #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010 7047 #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL 7048 #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000 7049 #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L 7050 #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010 7051 #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL 7052 #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000 7053 #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L 7054 #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010 7055 #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL 7056 #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000 7057 #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L 7058 #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010 7059 #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL 7060 #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000 7061 #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L 7062 #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010 7063 #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL 7064 #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000 7065 #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L 7066 #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010 7067 #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L 7068 #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000 7069 #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L 7070 #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004 7071 #define GENENB__BLK_IO_BASE_MASK 0x000000ffL 7072 #define GENENB__BLK_IO_BASE__SHIFT 0x00000000 7073 #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L 7074 #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f 7075 #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L 7076 #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003 7077 #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L 7078 #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000 7079 #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L 7080 #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002 7081 #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L 7082 #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001 7083 #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L 7084 #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L 7085 #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000 7086 #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008 7087 #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L 7088 #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010 7089 #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L 7090 #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f 7091 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L 7092 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001 7093 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L 7094 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000 7095 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L 7096 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002 7097 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L 7098 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002 7099 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L 7100 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001 7101 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L 7102 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000 7103 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L 7104 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006 7105 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L 7106 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005 7107 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L 7108 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004 7109 #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL 7110 #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000 7111 #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L 7112 #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008 7113 #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L 7114 #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007 7115 #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L 7116 #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000 7117 #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L 7118 #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001 7119 #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L 7120 #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008 7121 #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L 7122 #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018 7123 #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 7124 #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 7125 #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L 7126 #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010 7127 #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L 7128 #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000 7129 #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L 7130 #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005 7131 #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L 7132 #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004 7133 #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L 7134 #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a 7135 #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL 7136 #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000 7137 #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L 7138 #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009 7139 #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L 7140 #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006 7141 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L 7142 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009 7143 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L 7144 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010 7145 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L 7146 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000 7147 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L 7148 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c 7149 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L 7150 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L 7151 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008 7152 #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d 7153 #define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L 7154 #define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003 7155 #define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L 7156 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 7157 #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L 7158 #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 7159 #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L 7160 #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 7161 #define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL 7162 #define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002 7163 #define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L 7164 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 7165 #define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L 7166 #define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001 7167 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L 7168 #define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007 7169 #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L 7170 #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 7171 #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L 7172 #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 7173 #define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL 7174 #define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002 7175 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L 7176 #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 7177 #define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L 7178 #define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001 7179 #define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L 7180 #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 7181 #define GENS0__CRT_INTR_MASK 0x00000080L 7182 #define GENS0__CRT_INTR__SHIFT 0x00000007 7183 #define GENS0__SENSE_SWITCH_MASK 0x00000010L 7184 #define GENS0__SENSE_SWITCH__SHIFT 0x00000004 7185 #define GENS1__NO_DISPLAY_MASK 0x00000001L 7186 #define GENS1__NO_DISPLAY__SHIFT 0x00000000 7187 #define GENS1__PIXEL_READ_BACK_MASK 0x00000030L 7188 #define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004 7189 #define GENS1__VGA_VSTATUS_MASK 0x00000008L 7190 #define GENS1__VGA_VSTATUS__SHIFT 0x00000003 7191 #define GRA00__GRPH_SET_RESET0_MASK 0x00000001L 7192 #define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000 7193 #define GRA00__GRPH_SET_RESET1_MASK 0x00000002L 7194 #define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001 7195 #define GRA00__GRPH_SET_RESET2_MASK 0x00000004L 7196 #define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002 7197 #define GRA00__GRPH_SET_RESET3_MASK 0x00000008L 7198 #define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003 7199 #define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L 7200 #define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000 7201 #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L 7202 #define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001 7203 #define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L 7204 #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002 7205 #define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L 7206 #define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003 7207 #define GRA02__GRPH_CCOMP_MASK 0x0000000fL 7208 #define GRA02__GRPH_CCOMP__SHIFT 0x00000000 7209 #define GRA03__GRPH_FN_SEL_MASK 0x00000018L 7210 #define GRA03__GRPH_FN_SEL__SHIFT 0x00000003 7211 #define GRA03__GRPH_ROTATE_MASK 0x00000007L 7212 #define GRA03__GRPH_ROTATE__SHIFT 0x00000000 7213 #define GRA04__GRPH_RMAP_MASK 0x00000003L 7214 #define GRA04__GRPH_RMAP__SHIFT 0x00000000 7215 #define GRA05__CGA_ODDEVEN_MASK 0x00000010L 7216 #define GRA05__CGA_ODDEVEN__SHIFT 0x00000004 7217 #define GRA05__GRPH_OES_MASK 0x00000020L 7218 #define GRA05__GRPH_OES__SHIFT 0x00000005 7219 #define GRA05__GRPH_PACK_MASK 0x00000040L 7220 #define GRA05__GRPH_PACK__SHIFT 0x00000006 7221 #define GRA05__GRPH_READ1_MASK 0x00000008L 7222 #define GRA05__GRPH_READ1__SHIFT 0x00000003 7223 #define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L 7224 #define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000 7225 #define GRA06__GRPH_ADRSEL_MASK 0x0000000cL 7226 #define GRA06__GRPH_ADRSEL__SHIFT 0x00000002 7227 #define GRA06__GRPH_GRAPHICS_MASK 0x00000001L 7228 #define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000 7229 #define GRA06__GRPH_ODDEVEN_MASK 0x00000002L 7230 #define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001 7231 #define GRA07__GRPH_XCARE0_MASK 0x00000001L 7232 #define GRA07__GRPH_XCARE0__SHIFT 0x00000000 7233 #define GRA07__GRPH_XCARE1_MASK 0x00000002L 7234 #define GRA07__GRPH_XCARE1__SHIFT 0x00000001 7235 #define GRA07__GRPH_XCARE2_MASK 0x00000004L 7236 #define GRA07__GRPH_XCARE2__SHIFT 0x00000002 7237 #define GRA07__GRPH_XCARE3_MASK 0x00000008L 7238 #define GRA07__GRPH_XCARE3__SHIFT 0x00000003 7239 #define GRA08__GRPH_BMSK_MASK 0x000000ffL 7240 #define GRA08__GRPH_BMSK__SHIFT 0x00000000 7241 #define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL 7242 #define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000 7243 #define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL 7244 #define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000 7245 #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L 7246 #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006 7247 #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L 7248 #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008 7249 #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7250 #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7251 #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L 7252 #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 7253 #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L 7254 #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 7255 #define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L 7256 #define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b 7257 #define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L 7258 #define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006 7259 #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L 7260 #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f 7261 #define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L 7262 #define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000 7263 #define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L 7264 #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 7265 #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L 7266 #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 7267 #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L 7268 #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 7269 #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL 7270 #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 7271 #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L 7272 #define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018 7273 #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L 7274 #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 7275 #define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L 7276 #define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d 7277 #define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L 7278 #define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004 7279 #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L 7280 #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 7281 #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L 7282 #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000 7283 #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L 7284 #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004 7285 #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L 7286 #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009 7287 #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L 7288 #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008 7289 #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL 7290 #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000 7291 #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L 7292 #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 7293 #define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L 7294 #define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000 7295 #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L 7296 #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000 7297 #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L 7298 #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000 7299 #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L 7300 #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008 7301 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L 7302 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008 7303 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L 7304 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000 7305 #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L 7306 #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010 7307 #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L 7308 #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008 7309 #define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL 7310 #define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000 7311 #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L 7312 #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000 7313 #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L 7314 #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008 7315 #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7316 #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7317 #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L 7318 #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 7319 #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L 7320 #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 7321 #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7322 #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7323 #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L 7324 #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 7325 #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L 7326 #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 7327 #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L 7328 #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 7329 #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L 7330 #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 7331 #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L 7332 #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c 7333 #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL 7334 #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 7335 #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L 7336 #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 7337 #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL 7338 #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000 7339 #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL 7340 #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000 7341 #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L 7342 #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a 7343 #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L 7344 #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008 7345 #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L 7346 #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000 7347 #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L 7348 #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006 7349 #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L 7350 #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004 7351 #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 7352 #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 7353 #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L 7354 #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000 7355 #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L 7356 #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001 7357 #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L 7358 #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c 7359 #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L 7360 #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002 7361 #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L 7362 #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003 7363 #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L 7364 #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008 7365 #define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L 7366 #define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010 7367 #define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL 7368 #define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000 7369 #define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL 7370 #define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000 7371 #define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL 7372 #define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000 7373 #define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL 7374 #define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000 7375 #define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L 7376 #define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c 7377 #define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL 7378 #define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000 7379 #define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L 7380 #define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c 7381 #define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL 7382 #define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000 7383 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L 7384 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c 7385 #define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL 7386 #define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000 7387 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L 7388 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f 7389 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L 7390 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c 7391 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L 7392 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001 7393 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L 7394 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010 7395 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L 7396 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004 7397 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L 7398 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000 7399 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L 7400 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008 7401 #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L 7402 #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c 7403 #define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL 7404 #define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000 7405 #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L 7406 #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004 7407 #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L 7408 #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010 7409 #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L 7410 #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008 7411 #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L 7412 #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c 7413 #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L 7414 #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018 7415 #define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L 7416 #define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008 7417 #define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L 7418 #define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009 7419 #define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L 7420 #define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000 7421 #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L 7422 #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004 7423 #define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L 7424 #define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004 7425 #define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L 7426 #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002 7427 #define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L 7428 #define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000 7429 #define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L 7430 #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L 7431 #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c 7432 #define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008 7433 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L 7434 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001 7435 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L 7436 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010 7437 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L 7438 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000 7439 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L 7440 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005 7441 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L 7442 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018 7443 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L 7444 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004 7445 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L 7446 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001 7447 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L 7448 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010 7449 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L 7450 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000 7451 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L 7452 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005 7453 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L 7454 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018 7455 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L 7456 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004 7457 #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L 7458 #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005 7459 #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L 7460 #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004 7461 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L 7462 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001 7463 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L 7464 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000 7465 #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L 7466 #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009 7467 #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L 7468 #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008 7469 #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L 7470 #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008 7471 #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL 7472 #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000 7473 #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L 7474 #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010 7475 #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L 7476 #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000 7477 #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L 7478 #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010 7479 #define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L 7480 #define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b 7481 #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L 7482 #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014 7483 #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 7484 #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005 7485 #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 7486 #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 7487 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 7488 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 7489 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L 7490 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 7491 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 7492 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008 7493 #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 7494 #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000 7495 #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL 7496 #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 7497 #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL 7498 #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000 7499 #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL 7500 #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000 7501 #define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL 7502 #define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000 7503 #define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L 7504 #define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010 7505 #define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL 7506 #define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000 7507 #define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L 7508 #define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010 7509 #define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL 7510 #define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000 7511 #define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L 7512 #define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010 7513 #define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL 7514 #define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000 7515 #define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L 7516 #define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010 7517 #define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL 7518 #define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000 7519 #define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L 7520 #define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010 7521 #define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL 7522 #define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000 7523 #define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L 7524 #define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010 7525 #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L 7526 #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000 7527 #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L 7528 #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004 7529 #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L 7530 #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000 7531 #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L 7532 #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004 7533 #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L 7534 #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c 7535 #define KEY_CONTROL__KEY_MODE_MASK 0x00000006L 7536 #define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001 7537 #define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L 7538 #define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000 7539 #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L 7540 #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010 7541 #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL 7542 #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000 7543 #define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L 7544 #define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010 7545 #define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL 7546 #define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000 7547 #define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L 7548 #define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010 7549 #define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL 7550 #define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000 7551 #define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L 7552 #define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010 7553 #define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL 7554 #define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000 7555 #define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL 7556 #define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000 7557 #define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL 7558 #define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000 7559 #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L 7560 #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000 7561 #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L 7562 #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004 7563 #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L 7564 #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000 7565 #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL 7566 #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000 7567 #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL 7568 #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000 7569 #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7570 #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7571 #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L 7572 #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000 7573 #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L 7574 #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008 7575 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L 7576 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000 7577 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L 7578 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003 7579 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L 7580 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008 7581 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L 7582 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005 7583 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L 7584 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b 7585 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L 7586 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c 7587 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L 7588 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010 7589 #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L 7590 #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000 7591 #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L 7592 #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004 7593 #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L 7594 #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008 7595 #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L 7596 #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a 7597 #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L 7598 #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009 7599 #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L 7600 #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c 7601 #define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L 7602 #define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012 7603 #define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L 7604 #define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010 7605 #define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L 7606 #define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011 7607 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L 7608 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L 7609 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 7610 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L 7611 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a 7612 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 7613 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L 7614 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L 7615 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 7616 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L 7617 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 7618 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 7619 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L 7620 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001 7621 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L 7622 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000 7623 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L 7624 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004 7625 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L 7626 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L 7627 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009 7628 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L 7629 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a 7630 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 7631 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L 7632 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010 7633 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L 7634 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018 7635 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL 7636 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000 7637 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L 7638 #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008 7639 #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L 7640 #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010 7641 #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL 7642 #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000 7643 #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L 7644 #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008 7645 #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L 7646 #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018 7647 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L 7648 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 7649 #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL 7650 #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000 7651 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L 7652 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003 7653 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L 7654 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001 7655 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L 7656 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004 7657 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L 7658 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 7659 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L 7660 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002 7661 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L 7662 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000 7663 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL 7664 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 7665 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L 7666 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 7667 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L 7668 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 7669 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L 7670 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 7671 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 7672 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 7673 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL 7674 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 7675 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L 7676 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 7677 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L 7678 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 7679 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L 7680 #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 7681 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL 7682 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 7683 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L 7684 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 7685 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L 7686 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 7687 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L 7688 #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 7689 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL 7690 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 7691 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L 7692 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 7693 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L 7694 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 7695 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L 7696 #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 7697 #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L 7698 #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008 7699 #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L 7700 #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000 7701 #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L 7702 #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010 7703 #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L 7704 #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000 7705 #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L 7706 #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004 7707 #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L 7708 #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000 7709 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L 7710 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014 7711 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L 7712 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010 7713 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L 7714 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c 7715 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L 7716 #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018 7717 #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L 7718 #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c 7719 #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L 7720 #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008 7721 #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L 7722 #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004 7723 #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L 7724 #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010 7725 #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L 7726 #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018 7727 #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L 7728 #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000 7729 #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L 7730 #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e 7731 #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L 7732 #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f 7733 #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L 7734 #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c 7735 #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L 7736 #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008 7737 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L 7738 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000 7739 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L 7740 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004 7741 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L 7742 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010 7743 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L 7744 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008 7745 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L 7746 #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013 7747 #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL 7748 #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000 7749 #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL 7750 #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 7751 #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7752 #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7753 #define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL 7754 #define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000 7755 #define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L 7756 #define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004 7757 #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL 7758 #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000 7759 #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L 7760 #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008 7761 #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L 7762 #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 7763 #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL 7764 #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000 7765 #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L 7766 #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011 7767 #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L 7768 #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008 7769 #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L 7770 #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010 7771 #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L 7772 #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 7773 #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL 7774 #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000 7775 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL 7776 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000 7777 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L 7778 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c 7779 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L 7780 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008 7781 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L 7782 #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004 7783 #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L 7784 #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000 7785 #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L 7786 #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014 7787 #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L 7788 #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a 7789 #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL 7790 #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000 7791 #define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L 7792 #define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c 7793 #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L 7794 #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a 7795 #define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L 7796 #define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010 7797 #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L 7798 #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018 7799 #define MVP_CONTROL1__MVP_EN_MASK 0x00000001L 7800 #define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000 7801 #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L 7802 #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014 7803 #define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L 7804 #define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004 7805 #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L 7806 #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009 7807 #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L 7808 #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008 7809 #define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L 7810 #define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c 7811 #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L 7812 #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e 7813 #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L 7814 #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f 7815 #define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L 7816 #define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010 7817 #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L 7818 #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014 7819 #define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L 7820 #define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008 7821 #define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L 7822 #define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c 7823 #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L 7824 #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000 7825 #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L 7826 #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004 7827 #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L 7828 #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c 7829 #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L 7830 #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018 7831 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L 7832 #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 7833 #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L 7834 #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008 7835 #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L 7836 #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014 7837 #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L 7838 #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c 7839 #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L 7840 #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c 7841 #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L 7842 #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010 7843 #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L 7844 #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000 7845 #define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L 7846 #define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018 7847 #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL 7848 #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000 7849 #define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L 7850 #define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d 7851 #define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L 7852 #define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c 7853 #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L 7854 #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008 7855 #define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L 7856 #define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010 7857 #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L 7858 #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e 7859 #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL 7860 #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000 7861 #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L 7862 #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010 7863 #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL 7864 #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000 7865 #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L 7866 #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 7867 #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L 7868 #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 7869 #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L 7870 #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000 7871 #define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL 7872 #define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001 7873 #define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L 7874 #define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000 7875 #define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL 7876 #define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001 7877 #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L 7878 #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a 7879 #define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L 7880 #define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019 7881 #define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L 7882 #define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b 7883 #define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L 7884 #define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014 7885 #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L 7886 #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013 7887 #define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L 7888 #define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000 7889 #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L 7890 #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011 7891 #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L 7892 #define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010 7893 #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L 7894 #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012 7895 #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L 7896 #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f 7897 #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L 7898 #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e 7899 #define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L 7900 #define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b 7901 #define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L 7902 #define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c 7903 #define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L 7904 #define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a 7905 #define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L 7906 #define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009 7907 #define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L 7908 #define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d 7909 #define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L 7910 #define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003 7911 #define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L 7912 #define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006 7913 #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L 7914 #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004 7915 #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L 7916 #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000 7917 #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L 7918 #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003 7919 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L 7920 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002 7921 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L 7922 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001 7923 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L 7924 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004 7925 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L 7926 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c 7927 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L 7928 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 7929 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L 7930 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d 7931 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L 7932 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010 7933 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L 7934 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018 7935 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L 7936 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 7937 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL 7938 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002 7939 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L 7940 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 7941 #define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L 7942 #define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008 7943 #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L 7944 #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005 7945 #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L 7946 #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004 7947 #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L 7948 #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007 7949 #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L 7950 #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006 7951 #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L 7952 #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001 7953 #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L 7954 #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003 7955 #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L 7956 #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000 7957 #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L 7958 #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002 7959 #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L 7960 #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010 7961 #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L 7962 #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008 7963 #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL 7964 #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000 7965 #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L 7966 #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f 7967 #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L 7968 #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e 7969 #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL 7970 #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000 7971 #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L 7972 #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010 7973 #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L 7974 #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L 7975 #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c 7976 #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008 7977 #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L 7978 #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c 7979 #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L 7980 #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L 7981 #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018 7982 #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014 7983 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L 7984 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e 7985 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L 7986 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L 7987 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000 7988 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008 7989 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L 7990 #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018 7991 #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L 7992 #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000 7993 #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L 7994 #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008 7995 #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L 7996 #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004 7997 #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L 7998 #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f 7999 #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L 8000 #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010 8001 #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL 8002 #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000 8003 #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL 8004 #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L 8005 #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f 8006 #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000 8007 #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L 8008 #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010 8009 #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL 8010 #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000 8011 #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL 8012 #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000 8013 #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL 8014 #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000 8015 #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 8016 #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 8017 #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL 8018 #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000 8019 #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L 8020 #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010 8021 #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL 8022 #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000 8023 #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L 8024 #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010 8025 #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL 8026 #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000 8027 #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L 8028 #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010 8029 #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL 8030 #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000 8031 #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L 8032 #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010 8033 #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL 8034 #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000 8035 #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L 8036 #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010 8037 #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL 8038 #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000 8039 #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L 8040 #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010 8041 #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L 8042 #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000 8043 #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L 8044 #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004 8045 #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL 8046 #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000 8047 #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L 8048 #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 8049 #define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L 8050 #define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014 8051 #define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L 8052 #define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b 8053 #define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L 8054 #define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006 8055 #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L 8056 #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018 8057 #define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L 8058 #define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000 8059 #define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L 8060 #define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008 8061 #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L 8062 #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012 8063 #define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL 8064 #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002 8065 #define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L 8066 #define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019 8067 #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L 8068 #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 8069 #define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L 8070 #define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d 8071 #define OVL_CONTROL1__OVL_Z_MASK 0x00000030L 8072 #define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004 8073 #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L 8074 #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000 8075 #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L 8076 #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 8077 #define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L 8078 #define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000 8079 #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L 8080 #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004 8081 #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL 8082 #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000 8083 #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L 8084 #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009 8085 #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L 8086 #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008 8087 #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L 8088 #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 8089 #define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L 8090 #define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000 8091 #define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L 8092 #define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008 8093 #define OVL_END__OVL_X_END_MASK 0x7fff0000L 8094 #define OVL_END__OVL_X_END__SHIFT 0x00000010 8095 #define OVL_END__OVL_Y_END_MASK 0x00007fffL 8096 #define OVL_END__OVL_Y_END__SHIFT 0x00000000 8097 #define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL 8098 #define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000 8099 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL 8100 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000 8101 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L 8102 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a 8103 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L 8104 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014 8105 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L 8106 #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f 8107 #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 8108 #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 8109 #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L 8110 #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 8111 #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L 8112 #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 8113 #define OVL_START__OVL_X_START_MASK 0x3fff0000L 8114 #define OVL_START__OVL_X_START__SHIFT 0x00000010 8115 #define OVL_START__OVL_Y_START_MASK 0x00003fffL 8116 #define OVL_START__OVL_Y_START__SHIFT 0x00000000 8117 #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L 8118 #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 8119 #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L 8120 #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 8121 #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L 8122 #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 8123 #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L 8124 #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 8125 #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L 8126 #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c 8127 #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL 8128 #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 8129 #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 8130 #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 8131 #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L 8132 #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 8133 #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L 8134 #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000 8135 #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L 8136 #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008 8137 #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL 8138 #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000 8139 #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL 8140 #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000 8141 #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L 8142 #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a 8143 #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L 8144 #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008 8145 #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L 8146 #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000 8147 #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L 8148 #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006 8149 #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L 8150 #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004 8151 #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 8152 #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 8153 #define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L 8154 #define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010 8155 #define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L 8156 #define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000 8157 #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L 8158 #define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001 8159 #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L 8160 #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010 8161 #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L 8162 #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c 8163 #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L 8164 #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e 8165 #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8166 #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8167 #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8168 #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8169 #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8170 #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8171 #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8172 #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8173 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L 8174 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000 8175 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L 8176 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000 8177 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L 8178 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c 8179 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L 8180 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8181 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL 8182 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000 8183 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L 8184 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8185 #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8186 #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8187 #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8188 #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8189 #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8190 #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8191 #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8192 #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8193 #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L 8194 #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000 8195 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L 8196 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000 8197 #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L 8198 #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c 8199 #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L 8200 #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8201 #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL 8202 #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000 8203 #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L 8204 #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8205 #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8206 #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8207 #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8208 #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8209 #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8210 #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8211 #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8212 #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8213 #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L 8214 #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000 8215 #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L 8216 #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000 8217 #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L 8218 #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c 8219 #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L 8220 #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8221 #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL 8222 #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000 8223 #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L 8224 #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8225 #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8226 #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8227 #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8228 #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8229 #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8230 #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8231 #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8232 #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8233 #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L 8234 #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000 8235 #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L 8236 #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000 8237 #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L 8238 #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c 8239 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L 8240 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8241 #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL 8242 #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000 8243 #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L 8244 #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8245 #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8246 #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8247 #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8248 #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8249 #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8250 #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8251 #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8252 #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8253 #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L 8254 #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000 8255 #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L 8256 #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000 8257 #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L 8258 #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c 8259 #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L 8260 #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8261 #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL 8262 #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000 8263 #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L 8264 #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8265 #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8266 #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8267 #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8268 #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8269 #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8270 #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8271 #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8272 #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8273 #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L 8274 #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000 8275 #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L 8276 #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000 8277 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L 8278 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c 8279 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L 8280 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8281 #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL 8282 #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000 8283 #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L 8284 #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8285 #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L 8286 #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004 8287 #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L 8288 #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000 8289 #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L 8290 #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004 8291 #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L 8292 #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000 8293 #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L 8294 #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004 8295 #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L 8296 #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000 8297 #define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL 8298 #define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000 8299 #define PLL_ANALOG__PLL_CP_MASK 0x00000f00L 8300 #define PLL_ANALOG__PLL_CP__SHIFT 0x00000008 8301 #define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L 8302 #define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018 8303 #define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L 8304 #define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c 8305 #define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L 8306 #define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005 8307 #define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L 8308 #define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007 8309 #define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L 8310 #define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d 8311 #define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L 8312 #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002 8313 #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L 8314 #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a 8315 #define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L 8316 #define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014 8317 #define PLL_CNTL__PLL_CALREF_MASK 0x00000300L 8318 #define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008 8319 #define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L 8320 #define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a 8321 #define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L 8322 #define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015 8323 #define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L 8324 #define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013 8325 #define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L 8326 #define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006 8327 #define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L 8328 #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 8329 #define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L 8330 #define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001 8331 #define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L 8332 #define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b 8333 #define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L 8334 #define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010 8335 #define PLL_CNTL__PLL_RESET_MASK 0x00000001L 8336 #define PLL_CNTL__PLL_RESET__SHIFT 0x00000000 8337 #define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L 8338 #define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018 8339 #define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L 8340 #define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004 8341 #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L 8342 #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008 8343 #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L 8344 #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004 8345 #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L 8346 #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000 8347 #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL 8348 #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000 8349 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L 8350 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018 8351 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L 8352 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010 8353 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL 8354 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000 8355 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L 8356 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016 8357 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L 8358 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011 8359 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L 8360 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014 8361 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L 8362 #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015 8363 #define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL 8364 #define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000 8365 #define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L 8366 #define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012 8367 #define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L 8368 #define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010 8369 #define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L 8370 #define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013 8371 #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 8372 #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 8373 #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL 8374 #define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000 8375 #define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L 8376 #define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010 8377 #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L 8378 #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L 8379 #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008 8380 #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L 8381 #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c 8382 #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010 8383 #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L 8384 #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001 8385 #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L 8386 #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000 8387 #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L 8388 #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003 8389 #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L 8390 #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002 8391 #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L 8392 #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004 8393 #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L 8394 #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 8395 #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L 8396 #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f 8397 #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L 8398 #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008 8399 #define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L 8400 #define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010 8401 #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL 8402 #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000 8403 #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L 8404 #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c 8405 #define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL 8406 #define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000 8407 #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL 8408 #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000 8409 #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL 8410 #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000 8411 #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L 8412 #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008 8413 #define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L 8414 #define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c 8415 #define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L 8416 #define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d 8417 #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L 8418 #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010 8419 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L 8420 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004 8421 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L 8422 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000 8423 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L 8424 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001 8425 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L 8426 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003 8427 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L 8428 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002 8429 #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L 8430 #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010 8431 #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L 8432 #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000 8433 #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L 8434 #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008 8435 #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L 8436 #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000 8437 #define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L 8438 #define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a 8439 #define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L 8440 #define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c 8441 #define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL 8442 #define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000 8443 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L 8444 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003 8445 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L 8446 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004 8447 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L 8448 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002 8449 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L 8450 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001 8451 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L 8452 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000 8453 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L 8454 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004 8455 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L 8456 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001 8457 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L 8458 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003 8459 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L 8460 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000 8461 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L 8462 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002 8463 #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL 8464 #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000 8465 #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L 8466 #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010 8467 #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL 8468 #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000 8469 #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L 8470 #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010 8471 #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL 8472 #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000 8473 #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L 8474 #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010 8475 #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL 8476 #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000 8477 #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L 8478 #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010 8479 #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL 8480 #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000 8481 #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L 8482 #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010 8483 #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL 8484 #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000 8485 #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L 8486 #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010 8487 #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL 8488 #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000 8489 #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L 8490 #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010 8491 #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL 8492 #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000 8493 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL 8494 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 8495 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 8496 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c 8497 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L 8498 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 8499 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 8500 #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c 8501 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL 8502 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 8503 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 8504 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c 8505 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L 8506 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 8507 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 8508 #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c 8509 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL 8510 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 8511 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 8512 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c 8513 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L 8514 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 8515 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 8516 #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c 8517 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL 8518 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 8519 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 8520 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c 8521 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L 8522 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 8523 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 8524 #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c 8525 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL 8526 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 8527 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 8528 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c 8529 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L 8530 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 8531 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 8532 #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c 8533 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL 8534 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 8535 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 8536 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c 8537 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L 8538 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 8539 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 8540 #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c 8541 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL 8542 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 8543 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 8544 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c 8545 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L 8546 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 8547 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 8548 #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c 8549 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL 8550 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 8551 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 8552 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c 8553 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L 8554 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 8555 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 8556 #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c 8557 #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL 8558 #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 8559 #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL 8560 #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L 8561 #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 8562 #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000 8563 #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL 8564 #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000 8565 #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L 8566 #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010 8567 #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL 8568 #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000 8569 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL 8570 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 8571 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 8572 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c 8573 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L 8574 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 8575 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 8576 #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c 8577 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL 8578 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 8579 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 8580 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c 8581 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L 8582 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 8583 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 8584 #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c 8585 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL 8586 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 8587 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 8588 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c 8589 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L 8590 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 8591 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 8592 #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c 8593 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL 8594 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 8595 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 8596 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c 8597 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L 8598 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 8599 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 8600 #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c 8601 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL 8602 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 8603 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 8604 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c 8605 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L 8606 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 8607 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 8608 #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c 8609 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL 8610 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 8611 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 8612 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c 8613 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L 8614 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 8615 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 8616 #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c 8617 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL 8618 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 8619 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 8620 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c 8621 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L 8622 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 8623 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 8624 #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c 8625 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL 8626 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 8627 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 8628 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c 8629 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L 8630 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 8631 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 8632 #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c 8633 #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL 8634 #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 8635 #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL 8636 #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L 8637 #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 8638 #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000 8639 #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L 8640 #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000 8641 #define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L 8642 #define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004 8643 #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL 8644 #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000 8645 #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL 8646 #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 8647 #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L 8648 #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 8649 #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L 8650 #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 8651 #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L 8652 #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000 8653 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L 8654 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008 8655 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L 8656 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000 8657 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L 8658 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010 8659 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L 8660 #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c 8661 #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L 8662 #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010 8663 #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L 8664 #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008 8665 #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL 8666 #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 8667 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L 8668 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f 8669 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL 8670 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 8671 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L 8672 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f 8673 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L 8674 #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010 8675 #define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL 8676 #define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000 8677 #define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL 8678 #define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 8679 #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L 8680 #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004 8681 #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L 8682 #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000 8683 #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L 8684 #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c 8685 #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L 8686 #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008 8687 #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L 8688 #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000 8689 #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL 8690 #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 8691 #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 8692 #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 8693 #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL 8694 #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000 8695 #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L 8696 #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 8697 #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL 8698 #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 8699 #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L 8700 #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007 8701 #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L 8702 #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004 8703 #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L 8704 #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000 8705 #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL 8706 #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000 8707 #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL 8708 #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000 8709 #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L 8710 #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010 8711 #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L 8712 #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000 8713 #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL 8714 #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 8715 #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL 8716 #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 8717 #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 8718 #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 8719 #define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L 8720 #define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010 8721 #define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L 8722 #define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 8723 #define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L 8724 #define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008 8725 #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L 8726 #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000 8727 #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL 8728 #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 8729 #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L 8730 #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010 8731 #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL 8732 #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 8733 #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L 8734 #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010 8735 #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL 8736 #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 8737 #define SEQ00__SEQ_RST0B_MASK 0x00000001L 8738 #define SEQ00__SEQ_RST0B__SHIFT 0x00000000 8739 #define SEQ00__SEQ_RST1B_MASK 0x00000002L 8740 #define SEQ00__SEQ_RST1B__SHIFT 0x00000001 8741 #define SEQ01__SEQ_DOT8_MASK 0x00000001L 8742 #define SEQ01__SEQ_DOT8__SHIFT 0x00000000 8743 #define SEQ01__SEQ_MAXBW_MASK 0x00000020L 8744 #define SEQ01__SEQ_MAXBW__SHIFT 0x00000005 8745 #define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L 8746 #define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003 8747 #define SEQ01__SEQ_SHIFT2_MASK 0x00000004L 8748 #define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002 8749 #define SEQ01__SEQ_SHIFT4_MASK 0x00000010L 8750 #define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004 8751 #define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L 8752 #define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000 8753 #define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L 8754 #define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001 8755 #define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L 8756 #define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002 8757 #define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L 8758 #define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003 8759 #define SEQ03__SEQ_FONT_A0_MASK 0x00000020L 8760 #define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005 8761 #define SEQ03__SEQ_FONT_A1_MASK 0x00000004L 8762 #define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002 8763 #define SEQ03__SEQ_FONT_A2_MASK 0x00000008L 8764 #define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003 8765 #define SEQ03__SEQ_FONT_B0_MASK 0x00000010L 8766 #define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004 8767 #define SEQ03__SEQ_FONT_B1_MASK 0x00000001L 8768 #define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000 8769 #define SEQ03__SEQ_FONT_B2_MASK 0x00000002L 8770 #define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001 8771 #define SEQ04__SEQ_256K_MASK 0x00000002L 8772 #define SEQ04__SEQ_256K__SHIFT 0x00000001 8773 #define SEQ04__SEQ_CHAIN_MASK 0x00000008L 8774 #define SEQ04__SEQ_CHAIN__SHIFT 0x00000003 8775 #define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L 8776 #define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002 8777 #define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL 8778 #define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000 8779 #define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L 8780 #define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000 8781 #define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL 8782 #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000 8783 #define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL 8784 #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000 8785 #define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL 8786 #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000 8787 #define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL 8788 #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000 8789 #define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL 8790 #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000 8791 #define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL 8792 #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000 8793 #define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL 8794 #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000 8795 #define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL 8796 #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000 8797 #define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL 8798 #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000 8799 #define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL 8800 #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000 8801 #define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL 8802 #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000 8803 #define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL 8804 #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000 8805 #define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL 8806 #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000 8807 #define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL 8808 #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000 8809 #define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL 8810 #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000 8811 #define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL 8812 #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000 8813 #define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL 8814 #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000 8815 #define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL 8816 #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000 8817 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL 8818 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 8819 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L 8820 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 8821 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L 8822 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 8823 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L 8824 #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 8825 #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L 8826 #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008 8827 #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L 8828 #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000 8829 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL 8830 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 8831 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L 8832 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 8833 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L 8834 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 8835 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L 8836 #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 8837 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL 8838 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 8839 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L 8840 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 8841 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L 8842 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 8843 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L 8844 #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 8845 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL 8846 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 8847 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L 8848 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 8849 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L 8850 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 8851 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L 8852 #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 8853 #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L 8854 #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000 8855 #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L 8856 #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004 8857 #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L 8858 #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008 8859 #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L 8860 #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000 8861 #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L 8862 #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004 8863 #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L 8864 #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008 8865 #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L 8866 #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000 8867 #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L 8868 #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004 8869 #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L 8870 #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008 8871 #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L 8872 #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000 8873 #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L 8874 #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004 8875 #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L 8876 #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008 8877 #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L 8878 #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000 8879 #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L 8880 #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004 8881 #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L 8882 #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008 8883 #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L 8884 #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000 8885 #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L 8886 #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004 8887 #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L 8888 #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008 8889 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 8890 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 8891 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 8892 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 8893 #define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L 8894 #define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000 8895 #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L 8896 #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008 8897 #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L 8898 #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000 8899 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L 8900 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000 8901 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L 8902 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001 8903 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L 8904 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002 8905 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L 8906 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003 8907 #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L 8908 #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f 8909 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L 8910 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004 8911 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L 8912 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007 8913 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L 8914 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008 8915 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL 8916 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000 8917 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L 8918 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b 8919 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L 8920 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c 8921 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L 8922 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a 8923 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L 8924 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014 8925 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L 8926 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017 8927 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L 8928 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018 8929 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L 8930 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010 8931 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L 8932 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b 8933 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L 8934 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c 8935 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L 8936 #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a 8937 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L 8938 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004 8939 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L 8940 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007 8941 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L 8942 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008 8943 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL 8944 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000 8945 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L 8946 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b 8947 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L 8948 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c 8949 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L 8950 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a 8951 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L 8952 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014 8953 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L 8954 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017 8955 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L 8956 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018 8957 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L 8958 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010 8959 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L 8960 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b 8961 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L 8962 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c 8963 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L 8964 #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a 8965 #define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L 8966 #define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000 8967 #define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L 8968 #define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008 8969 #define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L 8970 #define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010 8971 #define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L 8972 #define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018 8973 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L 8974 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000 8975 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L 8976 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018 8977 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L 8978 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008 8979 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L 8980 #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010 8981 #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L 8982 #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004 8983 #define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L 8984 #define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019 8985 #define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L 8986 #define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018 8987 #define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L 8988 #define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000 8989 #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L 8990 #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009 8991 #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L 8992 #define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008 8993 #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L 8994 #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011 8995 #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L 8996 #define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010 8997 #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L 8998 #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000 8999 #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL 9000 #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000 9001 #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L 9002 #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010 9003 #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL 9004 #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000 9005 #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L 9006 #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010 9007 #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL 9008 #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000 9009 #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L 9010 #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010 9011 #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L 9012 #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011 9013 #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL 9014 #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000 9015 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L 9016 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010 9017 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L 9018 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001 9019 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L 9020 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018 9021 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L 9022 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008 9023 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L 9024 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000 9025 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL 9026 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000 9027 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L 9028 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010 9029 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L 9030 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 9031 #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL 9032 #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000 9033 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L 9034 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000 9035 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L 9036 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008 9037 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L 9038 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010 9039 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L 9040 #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018 9041 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L 9042 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006 9043 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L 9044 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004 9045 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L 9046 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000 9047 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L 9048 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010 9049 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L 9050 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c 9051 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L 9052 #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008 9053 #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL 9054 #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000 9055 #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L 9056 #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010 9057 #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L 9058 #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011 9059 #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL 9060 #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000 9061 #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L 9062 #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a 9063 #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L 9064 #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009 9065 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L 9066 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008 9067 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L 9068 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000 9069 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L 9070 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c 9071 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L 9072 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018 9073 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L 9074 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e 9075 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L 9076 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014 9077 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L 9078 #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010 9079 #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L 9080 #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a 9081 #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L 9082 #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009 9083 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L 9084 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008 9085 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L 9086 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000 9087 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L 9088 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c 9089 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L 9090 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018 9091 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L 9092 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e 9093 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L 9094 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014 9095 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L 9096 #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010 9097 #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L 9098 #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a 9099 #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L 9100 #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009 9101 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L 9102 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008 9103 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L 9104 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000 9105 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L 9106 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c 9107 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L 9108 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018 9109 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L 9110 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e 9111 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L 9112 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014 9113 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L 9114 #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010 9115 #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L 9116 #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a 9117 #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L 9118 #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009 9119 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L 9120 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008 9121 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L 9122 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000 9123 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L 9124 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c 9125 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L 9126 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018 9127 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L 9128 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e 9129 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L 9130 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014 9131 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L 9132 #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010 9133 #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L 9134 #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a 9135 #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L 9136 #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009 9137 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L 9138 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008 9139 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L 9140 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000 9141 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L 9142 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c 9143 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L 9144 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018 9145 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L 9146 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e 9147 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L 9148 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014 9149 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L 9150 #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010 9151 #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L 9152 #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a 9153 #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L 9154 #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009 9155 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L 9156 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008 9157 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L 9158 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000 9159 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L 9160 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c 9161 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L 9162 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018 9163 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L 9164 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e 9165 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L 9166 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014 9167 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L 9168 #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010 9169 #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL 9170 #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000 9171 #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL 9172 #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000 9173 #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L 9174 #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010 9175 #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL 9176 #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000 9177 #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L 9178 #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010 9179 #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL 9180 #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000 9181 #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L 9182 #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010 9183 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L 9184 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c 9185 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L 9186 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d 9187 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L 9188 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e 9189 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L 9190 #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f 9191 #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L 9192 #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014 9193 #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L 9194 #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010 9195 #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L 9196 #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008 9197 #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L 9198 #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000 9199 #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L 9200 #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004 9201 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L 9202 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010 9203 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L 9204 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003 9205 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L 9206 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004 9207 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L 9208 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000 9209 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L 9210 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002 9211 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L 9212 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008 9213 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L 9214 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001 9215 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L 9216 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019 9217 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L 9218 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018 9219 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L 9220 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a 9221 #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L 9222 #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c 9223 #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L 9224 #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d 9225 #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL 9226 #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002 9227 #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L 9228 #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c 9229 #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L 9230 #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004 9231 #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L 9232 #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005 9233 #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L 9234 #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006 9235 #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L 9236 #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b 9237 #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L 9238 #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014 9239 #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L 9240 #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d 9241 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L 9242 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000 9243 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L 9244 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008 9245 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L 9246 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018 9247 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L 9248 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013 9249 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L 9250 #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010 9251 #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL 9252 #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002 9253 #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L 9254 #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010 9255 #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L 9256 #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c 9257 #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L 9258 #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d 9259 #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL 9260 #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000 9261 #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL 9262 #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000 9263 #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L 9264 #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010 9265 #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L 9266 #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008 9267 #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L 9268 #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c 9269 #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L 9270 #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000 9271 #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L 9272 #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002 9273 #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L 9274 #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001 9275 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L 9276 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014 9277 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L 9278 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f 9279 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L 9280 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010 9281 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L 9282 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d 9283 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L 9284 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c 9285 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L 9286 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019 9287 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL 9288 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 9289 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L 9290 #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011 9291 #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L 9292 #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000 9293 #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L 9294 #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001 9295 #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L 9296 #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002 9297 #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L 9298 #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003 9299 #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L 9300 #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004 9301 #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L 9302 #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005 9303 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L 9304 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000 9305 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L 9306 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004 9307 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L 9308 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008 9309 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L 9310 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c 9311 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L 9312 #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010 9313 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L 9314 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014 9315 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L 9316 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016 9317 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L 9318 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018 9319 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L 9320 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a 9321 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L 9322 #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c 9323 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L 9324 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000 9325 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L 9326 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004 9327 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L 9328 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008 9329 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L 9330 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c 9331 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L 9332 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010 9333 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L 9334 #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014 9335 #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L 9336 #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015 9337 #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L 9338 #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017 9339 #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L 9340 #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019 9341 #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L 9342 #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b 9343 #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L 9344 #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d 9345 #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L 9346 #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f 9347 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L 9348 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014 9349 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L 9350 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015 9351 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L 9352 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016 9353 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L 9354 #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017 9355 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L 9356 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004 9357 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L 9358 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008 9359 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L 9360 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000 9361 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL 9362 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002 9363 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L 9364 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c 9365 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L 9366 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010 9367 #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L 9368 #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018 9369 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL 9370 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000 9371 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L 9372 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005 9373 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L 9374 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018 9375 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L 9376 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c 9377 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L 9378 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c 9379 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L 9380 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011 9381 #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL 9382 #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000 9383 #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L 9384 #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008 9385 #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L 9386 #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018 9387 #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L 9388 #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c 9389 #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9390 #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9391 #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9392 #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9393 #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9394 #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9395 #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L 9396 #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010 9397 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9398 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9399 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9400 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9401 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9402 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9403 #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL 9404 #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000 9405 #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL 9406 #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000 9407 #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L 9408 #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008 9409 #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L 9410 #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018 9411 #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L 9412 #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c 9413 #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9414 #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9415 #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9416 #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9417 #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9418 #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9419 #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L 9420 #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010 9421 #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9422 #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9423 #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9424 #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9425 #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9426 #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9427 #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL 9428 #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000 9429 #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL 9430 #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000 9431 #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L 9432 #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008 9433 #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L 9434 #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018 9435 #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L 9436 #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c 9437 #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9438 #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9439 #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9440 #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9441 #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9442 #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9443 #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L 9444 #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010 9445 #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9446 #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9447 #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9448 #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9449 #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9450 #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9451 #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL 9452 #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000 9453 #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L 9454 #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014 9455 #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L 9456 #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018 9457 #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L 9458 #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010 9459 #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L 9460 #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008 9461 #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L 9462 #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000 9463 #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL 9464 #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 9465 #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL 9466 #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000 9467 #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL 9468 #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000 9469 #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL 9470 #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000 9471 #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL 9472 #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000 9473 #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L 9474 #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004 9475 #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L 9476 #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000 9477 #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L 9478 #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008 9479 #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L 9480 #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010 9481 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L 9482 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018 9483 #define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL 9484 #define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000 9485 #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L 9486 #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010 9487 #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L 9488 #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000 9489 #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L 9490 #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018 9491 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L 9492 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008 9493 #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L 9494 #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002 9495 #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L 9496 #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000 9497 #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L 9498 #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003 9499 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L 9500 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001 9501 #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L 9502 #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000 9503 #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L 9504 #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d 9505 #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L 9506 #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f 9507 #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L 9508 #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018 9509 #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L 9510 #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010 9511 #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L 9512 #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a 9513 #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L 9514 #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008 9515 #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L 9516 #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b 9517 #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L 9518 #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003 9519 #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L 9520 #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005 9521 #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L 9522 #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c 9523 #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL 9524 #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000 9525 #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL 9526 #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000 9527 #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL 9528 #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000 9529 #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L 9530 #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010 9531 #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL 9532 #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000 9533 #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L 9534 #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010 9535 #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L 9536 #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008 9537 #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L 9538 #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000 9539 #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L 9540 #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004 9541 #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L 9542 #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010 9543 #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L 9544 #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005 9545 #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL 9546 #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000 9547 #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L 9548 #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007 9549 #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L 9550 #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008 9551 #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L 9552 #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018 9553 #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L 9554 #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019 9555 #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L 9556 #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010 9557 #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L 9558 #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000 9559 #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L 9560 #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008 9561 #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L 9562 #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001 9563 #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L 9564 #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009 9565 #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L 9566 #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002 9567 #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L 9568 #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a 9569 #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L 9570 #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003 9571 #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L 9572 #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b 9573 #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L 9574 #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004 9575 #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L 9576 #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c 9577 #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L 9578 #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005 9579 #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L 9580 #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d 9581 #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L 9582 #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010 9583 #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L 9584 #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012 9585 #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L 9586 #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011 9587 #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L 9588 #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000 9589 #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L 9590 #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008 9591 #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L 9592 #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010 9593 #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L 9594 #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000 9595 #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L 9596 #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018 9597 #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L 9598 #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008 9599 #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L 9600 #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002 9601 #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L 9602 #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000 9603 #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L 9604 #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003 9605 #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L 9606 #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001 9607 #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L 9608 #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008 9609 #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L 9610 #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000 9611 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L 9612 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000 9613 #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L 9614 #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018 9615 #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L 9616 #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010 9617 #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L 9618 #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008 9619 #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL 9620 #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000 9621 #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL 9622 #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9623 #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9624 #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9625 #define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL 9626 #define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000 9627 #define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L 9628 #define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010 9629 #define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L 9630 #define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010 9631 #define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL 9632 #define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000 9633 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L 9634 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f 9635 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L 9636 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013 9637 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L 9638 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012 9639 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L 9640 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014 9641 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L 9642 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010 9643 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 9644 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 9645 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL 9646 #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000 9647 #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L 9648 #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008 9649 #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL 9650 #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000 9651 #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L 9652 #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a 9653 #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L 9654 #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009 9655 #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L 9656 #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008 9657 #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L 9658 #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e 9659 #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L 9660 #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d 9661 #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L 9662 #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c 9663 #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L 9664 #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012 9665 #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L 9666 #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011 9667 #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L 9668 #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010 9669 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL 9670 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000 9671 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L 9672 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a 9673 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L 9674 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008 9675 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L 9676 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c 9677 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L 9678 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014 9679 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L 9680 #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004 9681 #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L 9682 #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016 9683 #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L 9684 #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b 9685 #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L 9686 #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000 9687 #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L 9688 #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010 9689 #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L 9690 #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008 9691 #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L 9692 #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c 9693 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L 9694 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000 9695 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L 9696 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010 9697 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L 9698 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e 9699 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L 9700 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 9701 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L 9702 #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018 9703 #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L 9704 #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008 9705 #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L 9706 #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012 9707 #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L 9708 #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010 9709 #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L 9710 #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009 9711 #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L 9712 #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014 9713 #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL 9714 #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000 9715 #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L 9716 #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010 9717 #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL 9718 #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000 9719 #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL 9720 #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000 9721 #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL 9722 #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000 9723 #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L 9724 #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010 9725 #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L 9726 #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008 9727 #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L 9728 #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c 9729 #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L 9730 #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010 9731 #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L 9732 #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c 9733 #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL 9734 #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000 9735 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L 9736 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000 9737 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L 9738 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c 9739 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L 9740 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008 9741 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L 9742 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004 9743 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L 9744 #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010 9745 #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L 9746 #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010 9747 #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L 9748 #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c 9749 #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL 9750 #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000 9751 #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L 9752 #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010 9753 #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL 9754 #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000 9755 #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL 9756 #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 9757 #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL 9758 #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 9759 #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL 9760 #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000 9761 #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL 9762 #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000 9763 #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL 9764 #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000 9765 #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L 9766 #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010 9767 #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L 9768 #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000 9769 #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L 9770 #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 9771 #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L 9772 #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f 9773 #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L 9774 #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008 9775 #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L 9776 #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010 9777 #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L 9778 #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009 9779 #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L 9780 #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013 9781 #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L 9782 #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014 9783 #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L 9784 #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000 9785 #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L 9786 #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010 9787 #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L 9788 #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008 9789 #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L 9790 #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c 9791 #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L 9792 #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f 9793 #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L 9794 #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010 9795 #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL 9796 #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000 9797 #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L 9798 #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010 9799 #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L 9800 #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c 9801 #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL 9802 #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000 9803 #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL 9804 #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000 9805 #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L 9806 #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014 9807 #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L 9808 #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010 9809 #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL 9810 #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000 9811 #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL 9812 #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000 9813 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L 9814 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000 9815 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L 9816 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c 9817 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L 9818 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008 9819 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L 9820 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004 9821 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L 9822 #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010 9823 #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL 9824 #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 9825 #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL 9826 #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 9827 #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL 9828 #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000 9829 #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L 9830 #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010 9831 #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L 9832 #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010 9833 #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL 9834 #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000 9835 #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L 9836 #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c 9837 #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L 9838 #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000 9839 #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L 9840 #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008 9841 #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL 9842 #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000 9843 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL 9844 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9845 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9846 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9847 9848 // DATA_FORMAT 9849 #define DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L 9850 #define DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x00000000 9851 #define DATA_FORMAT__RESET_REQ_AT_EOL_MASK 0x00000010L 9852 #define DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT 0x00000004 9853 #define DATA_FORMAT__PREFETCH_MASK 0x00001000L 9854 #define DATA_FORMAT__PREFETCH__SHIFT 0x0000000c 9855 #define DATA_FORMAT__SOF_READ_PT_MASK 0x001f0000L 9856 #define DATA_FORMAT__SOF_READ_PT__SHIFT 0x00000010 9857 #define DATA_FORMAT__REQUEST_MODE_MASK 0x03000000L 9858 #define DATA_FORMAT__REQUEST_MODE__SHIFT 0x00000018 9859 #define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK 0x10000000L 9860 #define DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT 0x0000001c 9861 9862 9863 // DC_LB_MEMORY_SPLIT 9864 #define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK 0x000f0000L 9865 #define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT 0x00000010 9866 #define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG_MASK 0x00300000L 9867 #define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT 0x00000014 9868 9869 // DC_LB_MEM_SIZE 9870 #define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK 0x000007ffL 9871 #define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT 0x00000000 9872 9873 // SCL_TAP_CONTROL 9874 #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L 9875 #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x00000000 9876 #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000f00L 9877 #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x00000008 9878 9879 // INT_MASK 9880 #define INT_MASK__VBLANK_INT_MASK 0x00000001L 9881 #define INT_MASK__VBLANK_INT__SHIFT 0x00000000 9882 #define INT_MASK__VLINE_INT_MASK 0x00000010L 9883 #define INT_MASK__VLINE_INT__SHIFT 0x00000004 9884 9885 // PRIORITY_A_CNT 9886 #define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK 0x00007fffL 9887 #define PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT 0x00000000 9888 #define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK 0x00010000L 9889 #define PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT 0x00000010 9890 #define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK 0x00100000L 9891 #define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT 0x00000014 9892 #define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK 0x01000000L 9893 #define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT 0x00000018 9894 9895 // PRIORITY_B_CNT 9896 #define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK 0x00007fffL 9897 #define PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT 0x00000000 9898 #define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK 0x00010000L 9899 #define PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT 0x00000010 9900 #define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK 0x00100000L 9901 #define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT 0x00000014 9902 #define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK 0x01000000L 9903 #define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT 0x00000018 9904 9905 // VLINE_STATUS 9906 #define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L 9907 #define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000 9908 #define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L 9909 #define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004 9910 #define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L 9911 #define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c 9912 #define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L 9913 #define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010 9914 #define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L 9915 #define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011 9916 9917 // VBLANK_STATUS 9918 #define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L 9919 #define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000 9920 #define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L 9921 #define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004 9922 #define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L 9923 #define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c 9924 #define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L 9925 #define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010 9926 #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L 9927 #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011 9928 9929 // SCL_HORZ_FILTER_INIT_RGB_LUMA 9930 #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK 0x0000ffffL 9931 #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT 0x00000000 9932 #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK 0x000f0000L 9933 #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT 0x00000010 9934 9935 // SCL_HORZ_FILTER_INIT_CHROMA 9936 #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK 0x0000ffffL 9937 #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT 0x00000000 9938 #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK 0x00070000L 9939 #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT 0x00000010 9940 9941 9942 #endif 9943