1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright (C) 2021 Advanced Micro Devices, Inc.
4  *
5  * Authors: AMD
6  */
7 
8 #ifndef _dpcs_3_0_3_OFFSET_HEADER
9 #define _dpcs_3_0_3_OFFSET_HEADER
10 
11 
12 
13 // addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
14 // base address: 0x0
15 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
16 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
17 #define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
18 #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
19 #define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
20 #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
21 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
22 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
23 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
24 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
25 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
26 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
27 
28 
29 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
30 // base address: 0x0
31 #define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
32 #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
33 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
34 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
35 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
36 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
37 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
38 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
39 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
40 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
41 #define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
42 #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
43 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
44 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
45 #define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
46 #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
47 #define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
48 #define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
49 #define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
50 #define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
51 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
52 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
53 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
54 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
55 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
56 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
57 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
58 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
59 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
60 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
61 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
62 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
63 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
64 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
65 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
66 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
67 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
68 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
69 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
70 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
71 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
72 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
73 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
74 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
75 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
76 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
77 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
78 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
79 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
80 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
81 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
82 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
83 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
84 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
85 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
86 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
87 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
88 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
89 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
90 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
91 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
92 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
93 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
94 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
95 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
96 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
97 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
98 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
99 
100 
101 // addressBlock: dpcssys_dpcssys_cr0_dispdec
102 // base address: 0x0
103 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
104 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
105 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
106 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
107 
108 
109 // addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
110 // base address: 0x360
111 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
112 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
113 #define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
114 #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
115 #define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
116 #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
117 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
118 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
119 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
120 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
121 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
122 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
123 
124 
125 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
126 // base address: 0x360
127 #define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
128 #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
129 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
130 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
131 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
132 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
133 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
134 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
135 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
136 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
137 #define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
138 #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
139 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
140 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
141 #define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
142 #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
143 #define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
144 #define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
145 #define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
146 #define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
147 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
148 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
149 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
150 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
151 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
152 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
153 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
154 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
155 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
156 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
157 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
158 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
159 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
160 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
161 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
162 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
163 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
164 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
165 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
166 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
167 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
168 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
169 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
170 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
171 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
172 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
173 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
174 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
175 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
176 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
177 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
178 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
179 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
180 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
181 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
182 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
183 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
184 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
185 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
186 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
187 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
188 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
189 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
190 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
191 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
192 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
193 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
194 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
195 
196 
197 // addressBlock: dpcssys_dpcssys_cr1_dispdec
198 // base address: 0x360
199 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
200 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
201 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
202 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
203 
204 #endif
205