1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 
25 #ifndef _dpcs_4_2_3_OFFSET_HEADER
26 #define _dpcs_4_2_3_OFFSET_HEADER
27 
28 
29 
30 // addressBlock: dpcssys_dpcssys_cr0_dispdec
31 // base address: 0x0
32 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
33 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
34 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
35 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
36 
37 
38 // addressBlock: dpcssys_dpcssys_cr1_dispdec
39 // base address: 0x360
40 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
41 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
42 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
43 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
44 
45 
46 // addressBlock: dpcssys_dpcssys_cr2_dispdec
47 // base address: 0x6c0
48 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
49 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
50 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
51 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
52 
53 
54 // addressBlock: dpcssys_dpcssys_cr3_dispdec
55 // base address: 0xa20
56 #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
57 #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
58 #define regDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
59 #define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
60 
61 
62 // addressBlock: dpcssys_dpcssys_cr4_dispdec
63 // base address: 0xd80
64 #define regDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
65 #define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
66 #define regDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
67 #define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
68 
69 
70 // addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
71 // base address: 0x0
72 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10
73 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
74 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11
75 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
76 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12
77 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
78 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13
79 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
80 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14
81 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
82 #define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15
83 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
84 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16
85 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
86 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17
87 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
88 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18
89 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
90 #define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19
91 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2
92 #define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a
93 #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2
94 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b
95 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
96 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c
97 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
98 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d
99 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
100 #define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21
101 #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2
102 
103 
104 // addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
105 // base address: 0x1b0
106 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c
107 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
108 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d
109 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
110 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e
111 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
112 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f
113 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
114 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80
115 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
116 #define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81
117 #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
118 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82
119 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
120 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83
121 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
122 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84
123 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
124 #define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85
125 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2
126 #define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86
127 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2
128 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87
129 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
130 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88
131 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
132 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89
133 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
134 #define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d
135 #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2
136 
137 
138 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
139 // base address: 0x0
140 #define regRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
141 #define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
142 #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
143 #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
144 #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
145 #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
146 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2933
147 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
148 #define regRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
149 #define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
150 #define regRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
151 #define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
152 #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
153 #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
154 #define regRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
155 #define regRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
156 #define regRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
157 #define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
158 #define regRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
159 #define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
160 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
161 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
162 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d
163 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
164 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
165 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
166 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
167 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
168 #define regRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
169 #define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
170 #define regRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
171 #define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
172 #define regRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
173 #define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
174 #define regRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
175 #define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
176 #define regRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
177 #define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
178 #define regRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
179 #define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
180 #define regRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
181 #define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
182 #define regRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
183 #define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
184 #define regRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
185 #define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
186 #define regRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
187 #define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
188 #define regRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
189 #define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
190 #define regRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
191 #define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
192 #define regRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
193 #define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
194 #define regRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
195 #define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
196 #define regRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
197 #define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
198 #define regRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
199 #define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
200 #define regRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
201 #define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
202 #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
203 #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
204 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
205 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
206 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
207 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
208 #define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
209 #define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
210 #define regRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958
211 #define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
212 #define regRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959
213 #define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
214 #define regRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a
215 #define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
216 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2                                                               0x295b
217 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
218 #define regRDPCSTX0_RDPCS_CNTL3                                                                         0x295c
219 #define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX                                                                2
220 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x295d
221 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
222 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x295e
223 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
224 
225 
226 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
227 // base address: 0x360
228 #define regRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
229 #define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
230 #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
231 #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
232 #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
233 #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
234 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2a0b
235 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
236 #define regRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
237 #define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
238 #define regRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
239 #define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
240 #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
241 #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
242 #define regRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
243 #define regRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
244 #define regRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
245 #define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
246 #define regRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
247 #define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
248 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
249 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
250 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15
251 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
252 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
253 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
254 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
255 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
256 #define regRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
257 #define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
258 #define regRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
259 #define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
260 #define regRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
261 #define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
262 #define regRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
263 #define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
264 #define regRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
265 #define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
266 #define regRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
267 #define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
268 #define regRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
269 #define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
270 #define regRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
271 #define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
272 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
273 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
274 #define regRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
275 #define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
276 #define regRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
277 #define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
278 #define regRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
279 #define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
280 #define regRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
281 #define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
282 #define regRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
283 #define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
284 #define regRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
285 #define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
286 #define regRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
287 #define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
288 #define regRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
289 #define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
290 #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
291 #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
292 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
293 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
294 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
295 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
296 #define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
297 #define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
298 #define regRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30
299 #define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
300 #define regRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31
301 #define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
302 #define regRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32
303 #define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
304 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2                                                               0x2a33
305 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
306 #define regRDPCSTX1_RDPCS_CNTL3                                                                         0x2a34
307 #define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX                                                                2
308 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2a35
309 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
310 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2a36
311 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
312 
313 
314 // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
315 // base address: 0x6c0
316 #define regRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
317 #define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
318 #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
319 #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
320 #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
321 #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
322 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2ae3
323 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
324 #define regRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
325 #define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
326 #define regRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
327 #define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
328 #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
329 #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
330 #define regRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
331 #define regRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
332 #define regRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
333 #define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
334 #define regRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
335 #define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
336 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
337 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
338 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed
339 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
340 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
341 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
342 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
343 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
344 #define regRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
345 #define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
346 #define regRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
347 #define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
348 #define regRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
349 #define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
350 #define regRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
351 #define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
352 #define regRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
353 #define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
354 #define regRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
355 #define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
356 #define regRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
357 #define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
358 #define regRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
359 #define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
360 #define regRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
361 #define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
362 #define regRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
363 #define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
364 #define regRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
365 #define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
366 #define regRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
367 #define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
368 #define regRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
369 #define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
370 #define regRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
371 #define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
372 #define regRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
373 #define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
374 #define regRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
375 #define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
376 #define regRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
377 #define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
378 #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
379 #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
380 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
381 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
382 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
383 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
384 #define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
385 #define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
386 #define regRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08
387 #define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
388 #define regRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09
389 #define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
390 #define regRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a
391 #define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
392 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2                                                               0x2b0b
393 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
394 #define regRDPCSTX2_RDPCS_CNTL3                                                                         0x2b0c
395 #define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX                                                                2
396 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2b0d
397 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
398 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2b0e
399 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
400 
401 
402 // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
403 // base address: 0xa20
404 #define regRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
405 #define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
406 #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
407 #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
408 #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
409 #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
410 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2bbb
411 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
412 #define regRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
413 #define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
414 #define regRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
415 #define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
416 #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
417 #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
418 #define regRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
419 #define regRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
420 #define regRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
421 #define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
422 #define regRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
423 #define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
424 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
425 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
426 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5
427 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
428 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
429 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
430 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
431 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
432 #define regRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
433 #define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
434 #define regRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
435 #define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
436 #define regRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
437 #define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
438 #define regRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
439 #define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
440 #define regRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
441 #define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
442 #define regRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
443 #define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
444 #define regRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
445 #define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
446 #define regRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
447 #define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
448 #define regRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
449 #define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
450 #define regRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
451 #define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
452 #define regRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
453 #define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
454 #define regRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
455 #define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
456 #define regRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
457 #define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
458 #define regRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
459 #define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
460 #define regRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
461 #define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
462 #define regRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
463 #define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
464 #define regRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
465 #define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
466 #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
467 #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
468 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
469 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
470 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
471 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
472 #define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
473 #define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
474 #define regRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0
475 #define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
476 #define regRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1
477 #define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
478 #define regRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2
479 #define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
480 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2                                                               0x2be3
481 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
482 #define regRDPCSTX3_RDPCS_CNTL3                                                                         0x2be4
483 #define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX                                                                2
484 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2be5
485 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
486 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2be6
487 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
488 
489 
490 // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
491 // base address: 0xd80
492 #define regRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
493 #define regRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
494 #define regRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
495 #define regRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
496 #define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
497 #define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
498 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2c93
499 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
500 #define regRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
501 #define regRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
502 #define regRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
503 #define regRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
504 #define regRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
505 #define regRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
506 #define regRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
507 #define regRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
508 #define regRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
509 #define regRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
510 #define regRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
511 #define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
512 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
513 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
514 #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG                                                                0x2c9d
515 #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
516 #define regRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
517 #define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
518 #define regRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
519 #define regRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
520 #define regRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
521 #define regRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
522 #define regRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
523 #define regRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
524 #define regRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
525 #define regRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
526 #define regRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
527 #define regRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
528 #define regRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
529 #define regRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
530 #define regRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
531 #define regRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
532 #define regRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
533 #define regRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
534 #define regRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
535 #define regRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
536 #define regRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
537 #define regRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
538 #define regRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
539 #define regRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
540 #define regRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
541 #define regRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
542 #define regRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
543 #define regRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
544 #define regRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
545 #define regRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
546 #define regRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
547 #define regRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
548 #define regRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
549 #define regRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
550 #define regRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
551 #define regRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
552 #define regRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
553 #define regRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
554 #define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
555 #define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
556 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
557 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
558 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
559 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
560 #define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
561 #define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
562 #define regRDPCSTX4_RDPCSTX_PHY_CNTL15                                                                  0x2cb8
563 #define regRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
564 #define regRDPCSTX4_RDPCSTX_PHY_CNTL16                                                                  0x2cb9
565 #define regRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
566 #define regRDPCSTX4_RDPCSTX_PHY_CNTL17                                                                  0x2cba
567 #define regRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
568 #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG2                                                               0x2cbb
569 #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
570 #define regRDPCSTX4_RDPCS_CNTL3                                                                         0x2cbc
571 #define regRDPCSTX4_RDPCS_CNTL3_BASE_IDX                                                                2
572 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2cbd
573 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
574 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2cbe
575 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
576 
577 
578 // addressBlock: dpcssys_dpcs0_rdpcspipe0_dispdec
579 // base address: 0x10e0
580 #define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6                                                               0x2d73
581 #define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
582 
583 
584 // addressBlock: dpcssys_dpcs0_rdpcspipe1_dispdec
585 // base address: 0x1440
586 #define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6                                                               0x2e4b
587 #define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
588 
589 // Hack to be cleaned up after bring up, driver should not need rdpcs registers
590 #define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6                                                              0x2d73
591 #define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                     2
592 #define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6                                                              0x2e4b
593 #define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                     2
594 #define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6                                                              0x2d73
595 #define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                     2
596 
597 // addressBlock: dpcssys_dcio_dcio_dispdec
598 // base address: 0x0
599 #define regDC_GENERICA                                                                                  0x2868
600 #define regDC_GENERICA_BASE_IDX                                                                         2
601 #define regDC_GENERICB                                                                                  0x2869
602 #define regDC_GENERICB_BASE_IDX                                                                         2
603 #define regDCIO_CLOCK_CNTL                                                                              0x286a
604 #define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
605 #define regDC_REF_CLK_CNTL                                                                              0x286b
606 #define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
607 #define regUNIPHYA_LINK_CNTL                                                                            0x286d
608 #define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
609 #define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
610 #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
611 #define regUNIPHYB_LINK_CNTL                                                                            0x286f
612 #define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
613 #define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
614 #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
615 #define regUNIPHYC_LINK_CNTL                                                                            0x2871
616 #define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
617 #define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
618 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
619 #define regUNIPHYD_LINK_CNTL                                                                            0x2873
620 #define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
621 #define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
622 #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
623 #define regUNIPHYE_LINK_CNTL                                                                            0x2875
624 #define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
625 #define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
626 #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
627 #define regDCIO_WRCMD_DELAY                                                                             0x287e
628 #define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
629 #define regDC_PINSTRAPS                                                                                 0x2880
630 #define regDC_PINSTRAPS_BASE_IDX                                                                        2
631 #define regINTERCEPT_STATE                                                                              0x2884
632 #define regINTERCEPT_STATE_BASE_IDX                                                                     2
633 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
634 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
635 #define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
636 #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
637 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
638 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
639 #define regDCIO_SOFT_RESET                                                                              0x289e
640 #define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
641 
642 
643 // addressBlock: dpcssys_dcio_dcio_chip_dispdec
644 // base address: 0x0
645 #define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
646 #define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
647 #define regDC_GPIO_GENERIC_A                                                                            0x28c9
648 #define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
649 #define regDC_GPIO_GENERIC_EN                                                                           0x28ca
650 #define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
651 #define regDC_GPIO_GENERIC_Y                                                                            0x28cb
652 #define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
653 #define regDC_GPIO_DDC1_MASK                                                                            0x28d0
654 #define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
655 #define regDC_GPIO_DDC1_A                                                                               0x28d1
656 #define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
657 #define regDC_GPIO_DDC1_EN                                                                              0x28d2
658 #define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
659 #define regDC_GPIO_DDC1_Y                                                                               0x28d3
660 #define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
661 #define regDC_GPIO_DDC2_MASK                                                                            0x28d4
662 #define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
663 #define regDC_GPIO_DDC2_A                                                                               0x28d5
664 #define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
665 #define regDC_GPIO_DDC2_EN                                                                              0x28d6
666 #define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
667 #define regDC_GPIO_DDC2_Y                                                                               0x28d7
668 #define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
669 #define regDC_GPIO_DDC3_MASK                                                                            0x28d8
670 #define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
671 #define regDC_GPIO_DDC3_A                                                                               0x28d9
672 #define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
673 #define regDC_GPIO_DDC3_EN                                                                              0x28da
674 #define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
675 #define regDC_GPIO_DDC3_Y                                                                               0x28db
676 #define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
677 #define regDC_GPIO_DDC4_MASK                                                                            0x28dc
678 #define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
679 #define regDC_GPIO_DDC4_A                                                                               0x28dd
680 #define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
681 #define regDC_GPIO_DDC4_EN                                                                              0x28de
682 #define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
683 #define regDC_GPIO_DDC4_Y                                                                               0x28df
684 #define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
685 #define regDC_GPIO_DDC5_MASK                                                                            0x28e0
686 #define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
687 #define regDC_GPIO_DDC5_A                                                                               0x28e1
688 #define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
689 #define regDC_GPIO_DDC5_EN                                                                              0x28e2
690 #define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
691 #define regDC_GPIO_DDC5_Y                                                                               0x28e3
692 #define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
693 #define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
694 #define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
695 #define regDC_GPIO_DDCVGA_A                                                                             0x28e9
696 #define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
697 #define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
698 #define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
699 #define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
700 #define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
701 #define regDC_GPIO_GENLK_MASK                                                                           0x28f0
702 #define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
703 #define regDC_GPIO_GENLK_A                                                                              0x28f1
704 #define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
705 #define regDC_GPIO_GENLK_EN                                                                             0x28f2
706 #define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
707 #define regDC_GPIO_GENLK_Y                                                                              0x28f3
708 #define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
709 #define regDC_GPIO_HPD_MASK                                                                             0x28f4
710 #define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
711 #define regDC_GPIO_HPD_A                                                                                0x28f5
712 #define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
713 #define regDC_GPIO_HPD_EN                                                                               0x28f6
714 #define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
715 #define regDC_GPIO_HPD_Y                                                                                0x28f7
716 #define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
717 #define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
718 #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
719 #define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
720 #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
721 #define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
722 #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
723 #define regPHY_AUX_CNTL                                                                                 0x28ff
724 #define regPHY_AUX_CNTL_BASE_IDX                                                                        2
725 #define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902
726 #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
727 #define regDC_GPIO_TX12_EN                                                                              0x2915
728 #define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
729 #define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
730 #define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
731 #define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
732 #define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
733 #define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
734 #define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
735 #define regDC_GPIO_RXEN                                                                                 0x2919
736 #define regDC_GPIO_RXEN_BASE_IDX                                                                        2
737 #define regDC_GPIO_PULLUPEN                                                                             0x291a
738 #define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
739 #define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
740 #define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
741 #define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
742 #define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
743 #define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
744 #define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
745 #define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
746 #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
747 
748 
749 // addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec
750 // base address: 0x360
751 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
752 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
753 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
754 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
755 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
756 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
757 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
758 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
759 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
760 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
761 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
762 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
763 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
764 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
765 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
766 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
767 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
768 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
769 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
770 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
771 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
772 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
773 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
774 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
775 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
776 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
777 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
778 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
779 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
780 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
781 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
782 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
783 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
784 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
785 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
786 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
787 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
788 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
789 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
790 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
791 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
792 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
793 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
794 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
795 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
796 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
797 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
798 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
799 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
800 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
801 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
802 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
803 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
804 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
805 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
806 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
807 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
808 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
809 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
810 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
811 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
812 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
813 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
814 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
815 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
816 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
817 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
818 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
819 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
820 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
821 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
822 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
823 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
824 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
825 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
826 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
827 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
828 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
829 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
830 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
831 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
832 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
833 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
834 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
835 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
836 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
837 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
838 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
839 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
840 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
841 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
842 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
843 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
844 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
845 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
846 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
847 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
848 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
849 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
850 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
851 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
852 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
853 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
854 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
855 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
856 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
857 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
858 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
859 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
860 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
861 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
862 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
863 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
864 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
865 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
866 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
867 
868 
869 // addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec
870 // base address: 0x6c0
871 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
872 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
873 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
874 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
875 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
876 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
877 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
878 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
879 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
880 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
881 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
882 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
883 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
884 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
885 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
886 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
887 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
888 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
889 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
890 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
891 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
892 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
893 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
894 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
895 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
896 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
897 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
898 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
899 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
900 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
901 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
902 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
903 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
904 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
905 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
906 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
907 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
908 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
909 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
910 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
911 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
912 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
913 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
914 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
915 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
916 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
917 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
918 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
919 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
920 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
921 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
922 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
923 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
924 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
925 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
926 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
927 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
928 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
929 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
930 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
931 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
932 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
933 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
934 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
935 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
936 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
937 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
938 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
939 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
940 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
941 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
942 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
943 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
944 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
945 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
946 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
947 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
948 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
949 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
950 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
951 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
952 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
953 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
954 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
955 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
956 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
957 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
958 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
959 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
960 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
961 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
962 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
963 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
964 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
965 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
966 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
967 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
968 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
969 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
970 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
971 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
972 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
973 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
974 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
975 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
976 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
977 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
978 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
979 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
980 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
981 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
982 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
983 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
984 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
985 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
986 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
987 
988 
989 // addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec
990 // base address: 0xa20
991 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
992 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
993 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
994 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
995 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
996 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
997 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
998 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
999 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
1000 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
1001 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
1002 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
1003 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
1004 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
1005 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
1006 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
1007 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
1008 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
1009 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
1010 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
1011 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
1012 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
1013 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
1014 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
1015 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
1016 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
1017 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
1018 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
1019 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
1020 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
1021 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
1022 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
1023 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
1024 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
1025 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
1026 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
1027 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
1028 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
1029 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
1030 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
1031 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
1032 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
1033 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
1034 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
1035 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
1036 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
1037 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
1038 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
1039 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
1040 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
1041 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
1042 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
1043 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
1044 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
1045 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
1046 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
1047 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
1048 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
1049 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
1050 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
1051 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
1052 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
1053 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
1054 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
1055 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
1056 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
1057 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
1058 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
1059 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
1060 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
1061 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
1062 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
1063 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
1064 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
1065 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
1066 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
1067 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
1068 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
1069 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
1070 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
1071 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
1072 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
1073 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
1074 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
1075 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
1076 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
1077 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
1078 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
1079 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
1080 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
1081 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
1082 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
1083 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
1084 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
1085 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
1086 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
1087 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
1088 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
1089 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
1090 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
1091 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
1092 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
1093 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
1094 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
1095 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
1096 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
1097 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
1098 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
1099 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
1100 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
1101 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
1102 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
1103 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
1104 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
1105 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
1106 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
1107 
1108 
1109 // addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec
1110 // base address: 0xd80
1111 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
1112 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
1113 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
1114 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
1115 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
1116 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
1117 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
1118 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
1119 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
1120 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
1121 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
1122 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
1123 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
1124 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
1125 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
1126 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
1127 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
1128 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
1129 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
1130 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
1131 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
1132 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
1133 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
1134 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
1135 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
1136 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
1137 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
1138 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
1139 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
1140 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
1141 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
1142 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
1143 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
1144 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
1145 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
1146 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
1147 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
1148 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
1149 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
1150 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
1151 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
1152 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
1153 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
1154 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
1155 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
1156 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
1157 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
1158 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
1159 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
1160 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
1161 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
1162 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
1163 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
1164 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
1165 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
1166 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
1167 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
1168 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
1169 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
1170 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
1171 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
1172 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
1173 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
1174 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
1175 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
1176 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
1177 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
1178 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
1179 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
1180 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
1181 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
1182 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
1183 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
1184 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
1185 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
1186 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
1187 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
1188 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
1189 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
1190 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
1191 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
1192 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
1193 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
1194 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
1195 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
1196 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
1197 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
1198 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
1199 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
1200 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
1201 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
1202 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
1203 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
1204 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
1205 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
1206 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
1207 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
1208 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
1209 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
1210 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
1211 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
1212 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
1213 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
1214 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
1215 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
1216 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
1217 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
1218 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
1219 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
1220 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
1221 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
1222 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
1223 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
1224 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
1225 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
1226 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
1227 
1228 
1229 // addressBlock: dpcssys_cr0_rdpcstxcrind
1230 // base address: 0x0
1231 #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO                                                                0x0000
1232 #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI                                                                0x0001
1233 #define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
1234 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
1235 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
1236 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
1237 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
1238 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
1239 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
1240 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
1241 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
1242 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
1243 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
1244 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
1245 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
1246 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
1247 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
1248 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
1249 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
1250 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
1251 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
1252 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
1253 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
1254 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
1255 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
1256 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
1257 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
1258 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
1259 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
1260 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
1261 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
1262 #define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN                                                              0x001f
1263 #define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
1264 #define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
1265 #define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN                                                              0x0022
1266 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
1267 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
1268 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
1269 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
1270 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
1271 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
1272 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
1273 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
1274 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
1275 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
1276 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
1277 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
1278 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
1279 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
1280 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
1281 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
1282 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
1283 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
1284 #define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN                                                                  0x0036
1285 #define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN                                                              0x0037
1286 #define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
1287 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
1288 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
1289 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
1290 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
1291 #define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL                                                           0x0040
1292 #define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL                                                               0x0041
1293 #define ixDPCSSYS_CR0_SUP_ANA_BG1                                                                      0x0042
1294 #define ixDPCSSYS_CR0_SUP_ANA_BG2                                                                      0x0043
1295 #define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
1296 #define ixDPCSSYS_CR0_SUP_ANA_BG3                                                                      0x0045
1297 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1                                                              0x0046
1298 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2                                                              0x0047
1299 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD                                                               0x0048
1300 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1                                                               0x0049
1301 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2                                                               0x004a
1302 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3                                                               0x004b
1303 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1                                                               0x004c
1304 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2                                                               0x004d
1305 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3                                                               0x004e
1306 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4                                                               0x004f
1307 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5                                                               0x0050
1308 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
1309 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
1310 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1                                                              0x0053
1311 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2                                                              0x0054
1312 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD                                                               0x0055
1313 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1                                                               0x0056
1314 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2                                                               0x0057
1315 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3                                                               0x0058
1316 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1                                                               0x0059
1317 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2                                                               0x005a
1318 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3                                                               0x005b
1319 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4                                                               0x005c
1320 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5                                                               0x005d
1321 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
1322 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
1323 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
1324 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
1325 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
1326 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
1327 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
1328 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
1329 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
1330 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
1331 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
1332 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
1333 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
1334 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
1335 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
1336 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
1337 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
1338 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
1339 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
1340 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
1341 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
1342 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
1343 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
1344 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
1345 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
1346 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
1347 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
1348 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG                                                             0x0081
1349 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT                                                               0x0082
1350 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
1351 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
1352 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
1353 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
1354 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
1355 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
1356 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
1357 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
1358 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
1359 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
1360 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
1361 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
1362 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
1363 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
1364 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
1365 #define ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
1366 #define ixDPCSSYS_CR0_SUP_DIG_ANA_STAT                                                                 0x0093
1367 #define ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
1368 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
1369 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
1370 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
1371 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
1372 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
1373 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
1374 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
1375 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
1376 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
1377 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
1378 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
1379 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
1380 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
1381 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
1382 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
1383 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
1384 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
1385 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
1386 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
1387 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
1388 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
1389 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
1390 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
1391 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
1392 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
1393 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
1394 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
1395 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
1396 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
1397 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
1398 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
1399 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
1400 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
1401 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
1402 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
1403 #define ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
1404 #define ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
1405 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
1406 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
1407 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
1408 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
1409 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
1410 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
1411 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
1412 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
1413 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
1414 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
1415 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
1416 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
1417 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
1418 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
1419 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
1420 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
1421 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
1422 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
1423 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
1424 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
1425 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
1426 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
1427 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
1428 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
1429 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
1430 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
1431 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
1432 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
1433 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
1434 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
1435 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
1436 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
1437 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
1438 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
1439 #define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
1440 #define ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
1441 #define ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
1442 #define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1                                                                0x10e3
1443 #define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2                                                                0x10e4
1444 #define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
1445 #define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
1446 #define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
1447 #define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
1448 #define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
1449 #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1                                                               0x10ea
1450 #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2                                                               0x10eb
1451 #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3                                                               0x10ec
1452 #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2                                                           0x10ed
1453 #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3                                                           0x10ee
1454 #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4                                                           0x10ef
1455 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
1456 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
1457 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
1458 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
1459 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
1460 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
1461 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
1462 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
1463 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
1464 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
1465 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
1466 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
1467 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
1468 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
1469 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
1470 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
1471 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
1472 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
1473 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
1474 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
1475 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
1476 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
1477 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
1478 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
1479 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
1480 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
1481 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
1482 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
1483 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
1484 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
1485 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
1486 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA                                                              0x111f
1487 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
1488 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
1489 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
1490 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
1491 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
1492 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
1493 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
1494 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
1495 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
1496 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
1497 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
1498 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
1499 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
1500 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
1501 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
1502 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
1503 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
1504 #define ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
1505 #define ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
1506 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
1507 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
1508 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
1509 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
1510 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
1511 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
1512 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
1513 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
1514 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
1515 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
1516 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
1517 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
1518 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
1519 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
1520 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
1521 #define ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
1522 #define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
1523 #define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
1524 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
1525 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
1526 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
1527 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
1528 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
1529 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT                                                            0x1158
1530 #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
1531 #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
1532 #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
1533 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
1534 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
1535 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
1536 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
1537 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
1538 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
1539 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
1540 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
1541 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
1542 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
1543 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
1544 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
1545 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
1546 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
1547 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
1548 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
1549 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
1550 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
1551 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
1552 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
1553 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
1554 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
1555 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
1556 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
1557 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
1558 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
1559 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
1560 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
1561 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
1562 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
1563 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
1564 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
1565 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
1566 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
1567 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
1568 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
1569 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
1570 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
1571 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
1572 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
1573 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
1574 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
1575 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
1576 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
1577 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
1578 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
1579 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
1580 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
1581 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
1582 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
1583 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
1584 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
1585 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
1586 #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
1587 #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
1588 #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
1589 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
1590 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
1591 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
1592 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
1593 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
1594 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
1595 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
1596 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
1597 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
1598 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
1599 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
1600 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
1601 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
1602 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
1603 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
1604 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
1605 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
1606 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
1607 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
1608 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
1609 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
1610 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
1611 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
1612 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
1613 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
1614 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
1615 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
1616 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
1617 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
1618 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
1619 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
1620 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
1621 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
1622 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
1623 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
1624 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
1625 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
1626 #define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
1627 #define ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
1628 #define ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
1629 #define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1                                                                0x11e3
1630 #define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2                                                                0x11e4
1631 #define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
1632 #define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
1633 #define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
1634 #define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
1635 #define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
1636 #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1                                                               0x11ea
1637 #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2                                                               0x11eb
1638 #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3                                                               0x11ec
1639 #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2                                                           0x11ed
1640 #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3                                                           0x11ee
1641 #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4                                                           0x11ef
1642 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1                                                               0x11f0
1643 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2                                                               0x11f1
1644 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES                                                             0x11f2
1645 #define ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
1646 #define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
1647 #define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
1648 #define ixDPCSSYS_CR0_LANE1_ANA_RX_SQ                                                                  0x11f6
1649 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1                                                                0x11f7
1650 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2                                                                0x11f8
1651 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
1652 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
1653 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
1654 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
1655 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
1656 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
1657 #define ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1                                                           0x11ff
1658 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
1659 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
1660 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
1661 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
1662 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
1663 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
1664 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
1665 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
1666 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
1667 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
1668 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
1669 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
1670 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
1671 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
1672 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
1673 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
1674 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
1675 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
1676 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
1677 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
1678 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
1679 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
1680 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
1681 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
1682 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
1683 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
1684 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
1685 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
1686 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
1687 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
1688 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
1689 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA                                                              0x121f
1690 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
1691 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
1692 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
1693 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
1694 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
1695 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
1696 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
1697 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
1698 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
1699 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
1700 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
1701 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
1702 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
1703 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
1704 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
1705 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
1706 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
1707 #define ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
1708 #define ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
1709 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
1710 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
1711 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
1712 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
1713 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
1714 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
1715 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
1716 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
1717 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
1718 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
1719 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
1720 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
1721 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
1722 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
1723 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
1724 #define ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
1725 #define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
1726 #define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
1727 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
1728 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
1729 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
1730 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
1731 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
1732 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT                                                            0x1258
1733 #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
1734 #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
1735 #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
1736 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
1737 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
1738 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
1739 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
1740 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
1741 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
1742 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
1743 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
1744 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
1745 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
1746 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
1747 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
1748 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
1749 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
1750 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
1751 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
1752 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
1753 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
1754 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
1755 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
1756 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
1757 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
1758 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
1759 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
1760 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
1761 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
1762 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
1763 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
1764 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
1765 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
1766 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
1767 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
1768 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
1769 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
1770 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
1771 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
1772 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
1773 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
1774 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
1775 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
1776 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
1777 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
1778 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
1779 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
1780 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
1781 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
1782 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
1783 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
1784 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
1785 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
1786 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
1787 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
1788 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
1789 #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
1790 #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
1791 #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
1792 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
1793 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
1794 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
1795 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
1796 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
1797 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
1798 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
1799 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
1800 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
1801 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
1802 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
1803 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
1804 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
1805 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
1806 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
1807 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
1808 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
1809 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
1810 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
1811 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
1812 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
1813 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
1814 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
1815 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
1816 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
1817 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
1818 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
1819 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
1820 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
1821 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
1822 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
1823 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
1824 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
1825 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
1826 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
1827 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
1828 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
1829 #define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
1830 #define ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
1831 #define ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
1832 #define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1                                                                0x12e3
1833 #define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2                                                                0x12e4
1834 #define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
1835 #define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
1836 #define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
1837 #define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
1838 #define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
1839 #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1                                                               0x12ea
1840 #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2                                                               0x12eb
1841 #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3                                                               0x12ec
1842 #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2                                                           0x12ed
1843 #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3                                                           0x12ee
1844 #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4                                                           0x12ef
1845 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1                                                               0x12f0
1846 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2                                                               0x12f1
1847 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES                                                             0x12f2
1848 #define ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
1849 #define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
1850 #define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
1851 #define ixDPCSSYS_CR0_LANE2_ANA_RX_SQ                                                                  0x12f6
1852 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1                                                                0x12f7
1853 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2                                                                0x12f8
1854 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
1855 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
1856 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
1857 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
1858 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
1859 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
1860 #define ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1                                                           0x12ff
1861 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
1862 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
1863 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
1864 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
1865 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
1866 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
1867 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
1868 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
1869 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
1870 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
1871 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
1872 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
1873 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
1874 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
1875 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
1876 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
1877 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
1878 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
1879 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
1880 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
1881 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
1882 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
1883 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
1884 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
1885 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
1886 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
1887 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
1888 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
1889 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
1890 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
1891 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
1892 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
1893 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
1894 #define ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
1895 #define ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
1896 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
1897 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
1898 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
1899 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
1900 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
1901 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
1902 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
1903 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
1904 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
1905 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
1906 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
1907 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
1908 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
1909 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
1910 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
1911 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
1912 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
1913 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
1914 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
1915 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
1916 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
1917 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
1918 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
1919 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
1920 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
1921 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
1922 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
1923 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
1924 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
1925 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
1926 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
1927 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
1928 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
1929 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
1930 #define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
1931 #define ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
1932 #define ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
1933 #define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1                                                                0x13e3
1934 #define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2                                                                0x13e4
1935 #define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
1936 #define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
1937 #define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
1938 #define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
1939 #define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
1940 #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1                                                               0x13ea
1941 #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2                                                               0x13eb
1942 #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3                                                               0x13ec
1943 #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2                                                           0x13ed
1944 #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3                                                           0x13ee
1945 #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4                                                           0x13ef
1946 #define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL                                                               0x2000
1947 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
1948 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
1949 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
1950 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
1951 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
1952 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
1953 #define ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
1954 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
1955 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
1956 #define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
1957 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
1958 #define ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
1959 #define ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
1960 #define ixDPCSSYS_CR0_RAWCMN_DIG_OCLA                                                                  0x200e
1961 #define ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
1962 #define ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
1963 #define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
1964 #define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
1965 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
1966 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
1967 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
1968 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
1969 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
1970 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
1971 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
1972 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
1973 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
1974 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
1975 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
1976 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
1977 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
1978 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
1979 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
1980 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
1981 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
1982 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
1983 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
1984 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
1985 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
1986 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
1987 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
1988 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
1989 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
1990 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
1991 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
1992 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
1993 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
1994 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
1995 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
1996 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
1997 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
1998 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
1999 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
2000 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
2001 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
2002 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
2003 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
2004 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
2005 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
2006 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
2007 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
2008 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
2009 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
2010 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
2011 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
2012 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
2013 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
2014 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
2015 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
2016 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
2017 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
2018 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
2019 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
2020 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
2021 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
2022 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
2023 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
2024 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
2025 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
2026 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
2027 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
2028 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
2029 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
2030 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
2031 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
2032 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
2033 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
2034 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
2035 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
2036 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
2037 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
2038 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
2039 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
2040 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
2041 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
2042 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
2043 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
2044 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
2045 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
2046 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
2047 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
2048 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
2049 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
2050 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
2051 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
2052 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
2053 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
2054 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
2055 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
2056 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
2057 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
2058 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
2059 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
2060 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
2061 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
2062 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
2063 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
2064 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
2065 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
2066 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
2067 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
2068 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
2069 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
2070 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
2071 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
2072 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
2073 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
2074 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
2075 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
2076 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
2077 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
2078 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
2079 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
2080 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
2081 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
2082 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
2083 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
2084 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
2085 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
2086 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
2087 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
2088 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
2089 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
2090 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
2091 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
2092 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
2093 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
2094 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
2095 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
2096 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
2097 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
2098 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
2099 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
2100 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
2101 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
2102 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
2103 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
2104 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
2105 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
2106 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
2107 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
2108 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
2109 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
2110 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
2111 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
2112 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
2113 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
2114 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
2115 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
2116 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
2117 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
2118 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
2119 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
2120 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
2121 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
2122 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
2123 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
2124 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
2125 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
2126 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
2127 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
2128 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
2129 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
2130 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
2131 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
2132 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
2133 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
2134 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
2135 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
2136 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
2137 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
2138 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
2139 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
2140 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
2141 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
2142 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
2143 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
2144 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
2145 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
2146 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
2147 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
2148 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
2149 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
2150 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
2151 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
2152 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
2153 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
2154 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
2155 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
2156 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
2157 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
2158 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
2159 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
2160 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
2161 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
2162 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
2163 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
2164 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
2165 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
2166 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
2167 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
2168 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
2169 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
2170 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
2171 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
2172 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
2173 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
2174 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
2175 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
2176 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
2177 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
2178 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
2179 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
2180 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
2181 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
2182 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
2183 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
2184 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
2185 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
2186 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
2187 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
2188 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
2189 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
2190 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
2191 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
2192 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
2193 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
2194 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
2195 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
2196 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
2197 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
2198 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
2199 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
2200 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
2201 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
2202 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
2203 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
2204 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
2205 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
2206 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
2207 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
2208 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
2209 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
2210 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
2211 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
2212 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
2213 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
2214 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
2215 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
2216 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
2217 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
2218 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
2219 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
2220 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
2221 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
2222 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
2223 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
2224 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
2225 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
2226 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
2227 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
2228 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
2229 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
2230 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
2231 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
2232 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
2233 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
2234 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
2235 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
2236 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
2237 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
2238 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
2239 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
2240 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
2241 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
2242 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
2243 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
2244 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
2245 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
2246 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
2247 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
2248 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
2249 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
2250 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
2251 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
2252 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
2253 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
2254 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
2255 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
2256 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
2257 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
2258 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
2259 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
2260 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
2261 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
2262 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
2263 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
2264 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
2265 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
2266 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
2267 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
2268 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
2269 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
2270 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
2271 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
2272 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
2273 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
2274 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
2275 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
2276 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
2277 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
2278 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
2279 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
2280 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
2281 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
2282 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
2283 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
2284 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
2285 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
2286 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
2287 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
2288 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
2289 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
2290 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
2291 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
2292 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
2293 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
2294 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
2295 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
2296 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
2297 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
2298 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
2299 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
2300 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
2301 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
2302 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
2303 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
2304 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
2305 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
2306 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
2307 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
2308 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
2309 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
2310 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
2311 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
2312 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
2313 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
2314 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
2315 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
2316 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
2317 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
2318 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
2319 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
2320 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
2321 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
2322 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
2323 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
2324 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
2325 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
2326 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
2327 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
2328 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
2329 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
2330 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
2331 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
2332 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
2333 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
2334 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
2335 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
2336 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
2337 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
2338 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
2339 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
2340 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
2341 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
2342 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
2343 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
2344 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
2345 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
2346 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
2347 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
2348 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
2349 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
2350 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
2351 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
2352 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
2353 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
2354 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
2355 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
2356 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
2357 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
2358 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
2359 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
2360 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
2361 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
2362 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
2363 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
2364 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
2365 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
2366 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
2367 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
2368 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
2369 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
2370 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
2371 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
2372 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
2373 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
2374 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
2375 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
2376 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
2377 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
2378 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
2379 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
2380 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
2381 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
2382 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
2383 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
2384 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
2385 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
2386 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
2387 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
2388 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
2389 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
2390 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
2391 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
2392 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
2393 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
2394 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
2395 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
2396 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
2397 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
2398 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
2399 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
2400 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
2401 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
2402 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
2403 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
2404 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
2405 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
2406 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
2407 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
2408 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
2409 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
2410 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
2411 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
2412 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
2413 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
2414 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
2415 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
2416 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
2417 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
2418 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
2419 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
2420 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
2421 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
2422 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
2423 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
2424 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
2425 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
2426 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
2427 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
2428 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
2429 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
2430 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
2431 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
2432 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
2433 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
2434 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
2435 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
2436 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
2437 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
2438 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
2439 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
2440 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
2441 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
2442 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
2443 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
2444 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
2445 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
2446 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
2447 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
2448 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
2449 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
2450 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
2451 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
2452 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
2453 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
2454 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
2455 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
2456 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
2457 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
2458 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
2459 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
2460 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
2461 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
2462 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
2463 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
2464 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
2465 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
2466 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
2467 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
2468 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
2469 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
2470 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
2471 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
2472 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
2473 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
2474 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
2475 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
2476 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
2477 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
2478 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
2479 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
2480 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
2481 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
2482 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
2483 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
2484 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
2485 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
2486 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
2487 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
2488 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
2489 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
2490 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
2491 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
2492 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
2493 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
2494 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
2495 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
2496 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
2497 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
2498 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
2499 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
2500 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
2501 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
2502 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
2503 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
2504 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
2505 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
2506 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
2507 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
2508 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
2509 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
2510 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
2511 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
2512 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
2513 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
2514 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
2515 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
2516 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
2517 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
2518 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
2519 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
2520 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
2521 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
2522 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
2523 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
2524 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
2525 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
2526 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
2527 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
2528 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
2529 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
2530 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
2531 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
2532 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
2533 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
2534 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
2535 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
2536 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
2537 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
2538 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
2539 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
2540 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
2541 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
2542 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
2543 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
2544 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
2545 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
2546 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
2547 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
2548 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS                                                            0x4032
2549 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
2550 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
2551 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
2552 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
2553 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
2554 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
2555 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
2556 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
2557 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
2558 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
2559 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
2560 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
2561 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
2562 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
2563 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
2564 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
2565 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
2566 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
2567 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
2568 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
2569 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
2570 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
2571 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
2572 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
2573 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
2574 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
2575 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
2576 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
2577 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
2578 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
2579 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
2580 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
2581 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
2582 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
2583 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
2584 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
2585 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
2586 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
2587 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
2588 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
2589 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
2590 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
2591 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
2592 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
2593 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
2594 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
2595 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
2596 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
2597 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
2598 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
2599 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
2600 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
2601 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
2602 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
2603 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
2604 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
2605 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
2606 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
2607 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
2608 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
2609 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
2610 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
2611 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
2612 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
2613 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
2614 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
2615 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
2616 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
2617 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
2618 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
2619 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
2620 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
2621 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
2622 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
2623 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
2624 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
2625 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
2626 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
2627 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
2628 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
2629 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
2630 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS                                                            0x4132
2631 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
2632 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
2633 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
2634 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
2635 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
2636 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
2637 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
2638 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
2639 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
2640 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
2641 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
2642 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
2643 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
2644 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
2645 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
2646 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
2647 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
2648 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
2649 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
2650 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
2651 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
2652 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
2653 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
2654 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
2655 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
2656 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
2657 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
2658 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
2659 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
2660 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
2661 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
2662 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
2663 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
2664 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
2665 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
2666 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
2667 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
2668 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
2669 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
2670 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
2671 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
2672 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
2673 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
2674 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
2675 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
2676 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
2677 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
2678 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
2679 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
2680 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
2681 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
2682 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
2683 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
2684 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
2685 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
2686 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
2687 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
2688 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
2689 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
2690 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
2691 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
2692 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
2693 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
2694 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
2695 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
2696 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
2697 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
2698 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
2699 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
2700 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
2701 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
2702 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
2703 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
2704 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
2705 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
2706 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
2707 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
2708 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
2709 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
2710 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
2711 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
2712 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS                                                            0x4232
2713 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
2714 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
2715 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
2716 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
2717 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
2718 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
2719 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
2720 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
2721 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
2722 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
2723 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
2724 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
2725 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
2726 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
2727 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
2728 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
2729 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
2730 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
2731 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
2732 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
2733 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
2734 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
2735 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
2736 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
2737 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
2738 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
2739 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
2740 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
2741 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
2742 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
2743 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
2744 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
2745 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
2746 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
2747 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
2748 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
2749 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
2750 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
2751 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
2752 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
2753 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
2754 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
2755 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
2756 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
2757 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
2758 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
2759 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
2760 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
2761 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
2762 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
2763 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
2764 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
2765 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
2766 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
2767 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
2768 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
2769 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
2770 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
2771 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
2772 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
2773 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
2774 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
2775 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
2776 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
2777 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
2778 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
2779 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
2780 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
2781 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
2782 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
2783 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
2784 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
2785 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
2786 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
2787 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
2788 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
2789 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
2790 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
2791 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
2792 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
2793 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
2794 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS                                                            0x4332
2795 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
2796 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
2797 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
2798 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
2799 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
2800 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
2801 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
2802 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
2803 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
2804 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
2805 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
2806 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
2807 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
2808 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
2809 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
2810 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
2811 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
2812 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
2813 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
2814 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
2815 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
2816 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
2817 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
2818 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
2819 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
2820 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
2821 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
2822 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
2823 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
2824 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
2825 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
2826 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
2827 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
2828 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
2829 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
2830 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
2831 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
2832 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
2833 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
2834 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
2835 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
2836 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
2837 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
2838 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
2839 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
2840 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
2841 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
2842 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
2843 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
2844 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
2845 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
2846 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
2847 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
2848 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
2849 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
2850 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
2851 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
2852 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
2853 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
2854 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
2855 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
2856 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
2857 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
2858 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
2859 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
2860 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
2861 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
2862 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
2863 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
2864 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
2865 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
2866 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
2867 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
2868 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
2869 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
2870 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
2871 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
2872 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
2873 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
2874 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
2875 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
2876 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS                                                            0x7032
2877 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
2878 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
2879 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
2880 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
2881 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
2882 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
2883 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
2884 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
2885 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
2886 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
2887 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
2888 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
2889 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
2890 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
2891 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
2892 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
2893 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
2894 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
2895 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
2896 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
2897 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
2898 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
2899 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
2900 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
2901 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
2902 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
2903 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
2904 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
2905 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
2906 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
2907 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
2908 #define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO                                                               0x8000
2909 #define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI                                                               0x8001
2910 #define ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
2911 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
2912 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
2913 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
2914 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
2915 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
2916 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
2917 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
2918 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
2919 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
2920 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
2921 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
2922 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
2923 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
2924 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
2925 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
2926 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
2927 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
2928 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
2929 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
2930 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
2931 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
2932 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
2933 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
2934 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
2935 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
2936 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
2937 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
2938 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
2939 #define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
2940 #define ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
2941 #define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
2942 #define ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
2943 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
2944 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
2945 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
2946 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
2947 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
2948 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
2949 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
2950 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
2951 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
2952 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
2953 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
2954 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
2955 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
2956 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
2957 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
2958 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
2959 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
2960 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
2961 #define ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN                                                                 0x8036
2962 #define ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
2963 #define ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
2964 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
2965 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
2966 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
2967 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
2968 #define ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
2969 #define ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL                                                              0x8041
2970 #define ixDPCSSYS_CR0_SUPX_ANA_BG1                                                                     0x8042
2971 #define ixDPCSSYS_CR0_SUPX_ANA_BG2                                                                     0x8043
2972 #define ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
2973 #define ixDPCSSYS_CR0_SUPX_ANA_BG3                                                                     0x8045
2974 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1                                                             0x8046
2975 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2                                                             0x8047
2976 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD                                                              0x8048
2977 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1                                                              0x8049
2978 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2                                                              0x804a
2979 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3                                                              0x804b
2980 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1                                                              0x804c
2981 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2                                                              0x804d
2982 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3                                                              0x804e
2983 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4                                                              0x804f
2984 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5                                                              0x8050
2985 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
2986 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
2987 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1                                                             0x8053
2988 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2                                                             0x8054
2989 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD                                                              0x8055
2990 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1                                                              0x8056
2991 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2                                                              0x8057
2992 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3                                                              0x8058
2993 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1                                                              0x8059
2994 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2                                                              0x805a
2995 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3                                                              0x805b
2996 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4                                                              0x805c
2997 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5                                                              0x805d
2998 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
2999 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
3000 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
3001 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
3002 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
3003 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
3004 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
3005 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
3006 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
3007 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
3008 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
3009 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
3010 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
3011 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
3012 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
3013 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
3014 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
3015 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
3016 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
3017 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
3018 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
3019 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
3020 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
3021 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
3022 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
3023 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
3024 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
3025 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
3026 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT                                                              0x8082
3027 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
3028 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
3029 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
3030 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
3031 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
3032 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
3033 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
3034 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
3035 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
3036 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
3037 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
3038 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
3039 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
3040 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
3041 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
3042 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
3043 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT                                                                0x8093
3044 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
3045 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
3046 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
3047 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
3048 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
3049 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
3050 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
3051 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
3052 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
3053 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
3054 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
3055 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
3056 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
3057 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
3058 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
3059 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
3060 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
3061 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
3062 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
3063 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
3064 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
3065 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
3066 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
3067 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
3068 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
3069 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
3070 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
3071 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
3072 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
3073 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
3074 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
3075 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
3076 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
3077 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
3078 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA                                                              0x901f
3079 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
3080 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
3081 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
3082 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
3083 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
3084 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
3085 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
3086 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
3087 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
3088 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
3089 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
3090 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
3091 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
3092 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
3093 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
3094 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
3095 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
3096 #define ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
3097 #define ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
3098 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
3099 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
3100 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
3101 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
3102 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
3103 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
3104 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
3105 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
3106 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
3107 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
3108 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
3109 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
3110 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
3111 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
3112 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
3113 #define ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
3114 #define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
3115 #define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
3116 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
3117 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
3118 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
3119 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
3120 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
3121 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT                                                            0x9058
3122 #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
3123 #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
3124 #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
3125 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
3126 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
3127 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
3128 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
3129 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
3130 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
3131 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
3132 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
3133 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
3134 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
3135 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
3136 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
3137 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
3138 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
3139 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
3140 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
3141 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
3142 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
3143 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
3144 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
3145 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
3146 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
3147 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
3148 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
3149 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
3150 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
3151 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
3152 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
3153 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
3154 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
3155 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
3156 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
3157 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
3158 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
3159 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
3160 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
3161 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
3162 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
3163 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
3164 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
3165 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
3166 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
3167 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
3168 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
3169 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
3170 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
3171 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
3172 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
3173 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
3174 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
3175 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
3176 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
3177 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
3178 #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
3179 #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
3180 #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
3181 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
3182 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
3183 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
3184 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
3185 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
3186 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
3187 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
3188 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
3189 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
3190 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
3191 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
3192 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
3193 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
3194 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
3195 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
3196 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
3197 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
3198 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
3199 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
3200 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
3201 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
3202 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
3203 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
3204 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
3205 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
3206 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
3207 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
3208 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
3209 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
3210 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
3211 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
3212 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
3213 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
3214 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
3215 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
3216 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
3217 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
3218 #define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
3219 #define ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
3220 #define ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
3221 #define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1                                                                0x90e3
3222 #define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2                                                                0x90e4
3223 #define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
3224 #define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
3225 #define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
3226 #define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
3227 #define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
3228 #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1                                                               0x90ea
3229 #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2                                                               0x90eb
3230 #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3                                                               0x90ec
3231 #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2                                                           0x90ed
3232 #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3                                                           0x90ee
3233 #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4                                                           0x90ef
3234 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1                                                               0x90f0
3235 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2                                                               0x90f1
3236 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES                                                             0x90f2
3237 #define ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
3238 #define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
3239 #define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
3240 #define ixDPCSSYS_CR0_LANEX_ANA_RX_SQ                                                                  0x90f6
3241 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1                                                                0x90f7
3242 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2                                                                0x90f8
3243 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
3244 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
3245 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
3246 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
3247 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
3248 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
3249 #define ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1                                                           0x90ff
3250 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
3251 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
3252 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
3253 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
3254 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
3255 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
3256 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
3257 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
3258 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
3259 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
3260 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
3261 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
3262 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
3263 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
3264 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
3265 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
3266 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
3267 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
3268 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
3269 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
3270 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
3271 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
3272 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
3273 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
3274 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
3275 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
3276 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
3277 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
3278 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
3279 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
3280 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
3281 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
3282 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
3283 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
3284 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
3285 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
3286 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
3287 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
3288 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
3289 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
3290 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
3291 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
3292 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
3293 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
3294 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
3295 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
3296 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
3297 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
3298 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
3299 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
3300 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
3301 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
3302 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
3303 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
3304 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
3305 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
3306 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
3307 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
3308 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
3309 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
3310 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
3311 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
3312 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
3313 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
3314 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
3315 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
3316 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
3317 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
3318 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
3319 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
3320 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
3321 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
3322 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
3323 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
3324 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
3325 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
3326 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
3327 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
3328 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
3329 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
3330 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
3331 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
3332 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
3333 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
3334 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
3335 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
3336 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
3337 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
3338 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
3339 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
3340 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
3341 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
3342 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
3343 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
3344 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
3345 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
3346 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
3347 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
3348 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
3349 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
3350 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
3351 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
3352 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
3353 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
3354 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
3355 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
3356 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
3357 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
3358 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
3359 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
3360 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
3361 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
3362 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
3363 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
3364 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
3365 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
3366 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
3367 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
3368 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
3369 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
3370 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
3371 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
3372 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
3373 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
3374 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
3375 
3376 
3377 // addressBlock: dpcssys_cr1_rdpcstxcrind
3378 // base address: 0x0
3379 #define ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO                                                                0x0000
3380 #define ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI                                                                0x0001
3381 #define ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
3382 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
3383 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
3384 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
3385 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
3386 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
3387 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
3388 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
3389 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
3390 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
3391 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
3392 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
3393 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
3394 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
3395 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
3396 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
3397 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
3398 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
3399 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
3400 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
3401 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
3402 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
3403 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
3404 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
3405 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
3406 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
3407 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
3408 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
3409 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
3410 #define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN                                                              0x001f
3411 #define ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
3412 #define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
3413 #define ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN                                                              0x0022
3414 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
3415 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
3416 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
3417 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
3418 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
3419 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
3420 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
3421 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
3422 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
3423 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
3424 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
3425 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
3426 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
3427 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
3428 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
3429 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
3430 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
3431 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
3432 #define ixDPCSSYS_CR1_SUP_DIG_ASIC_IN                                                                  0x0036
3433 #define ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN                                                              0x0037
3434 #define ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
3435 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
3436 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
3437 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
3438 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
3439 #define ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL                                                           0x0040
3440 #define ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL                                                               0x0041
3441 #define ixDPCSSYS_CR1_SUP_ANA_BG1                                                                      0x0042
3442 #define ixDPCSSYS_CR1_SUP_ANA_BG2                                                                      0x0043
3443 #define ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
3444 #define ixDPCSSYS_CR1_SUP_ANA_BG3                                                                      0x0045
3445 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1                                                              0x0046
3446 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2                                                              0x0047
3447 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD                                                               0x0048
3448 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1                                                               0x0049
3449 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2                                                               0x004a
3450 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3                                                               0x004b
3451 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1                                                               0x004c
3452 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2                                                               0x004d
3453 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3                                                               0x004e
3454 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4                                                               0x004f
3455 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5                                                               0x0050
3456 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
3457 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
3458 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1                                                              0x0053
3459 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2                                                              0x0054
3460 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD                                                               0x0055
3461 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1                                                               0x0056
3462 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2                                                               0x0057
3463 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3                                                               0x0058
3464 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1                                                               0x0059
3465 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2                                                               0x005a
3466 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3                                                               0x005b
3467 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4                                                               0x005c
3468 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5                                                               0x005d
3469 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
3470 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
3471 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
3472 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
3473 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
3474 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
3475 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
3476 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
3477 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
3478 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
3479 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
3480 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
3481 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
3482 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
3483 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
3484 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
3485 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
3486 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
3487 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
3488 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
3489 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
3490 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
3491 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
3492 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
3493 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
3494 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
3495 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
3496 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG                                                             0x0081
3497 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT                                                               0x0082
3498 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
3499 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
3500 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
3501 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
3502 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
3503 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
3504 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
3505 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
3506 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
3507 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
3508 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
3509 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
3510 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
3511 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
3512 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
3513 #define ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
3514 #define ixDPCSSYS_CR1_SUP_DIG_ANA_STAT                                                                 0x0093
3515 #define ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
3516 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
3517 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
3518 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
3519 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
3520 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
3521 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
3522 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
3523 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
3524 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
3525 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
3526 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
3527 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
3528 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
3529 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
3530 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
3531 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
3532 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
3533 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
3534 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
3535 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
3536 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
3537 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
3538 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
3539 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
3540 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
3541 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
3542 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
3543 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
3544 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
3545 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
3546 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
3547 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
3548 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
3549 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
3550 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
3551 #define ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
3552 #define ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
3553 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
3554 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
3555 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
3556 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
3557 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
3558 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
3559 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
3560 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
3561 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
3562 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
3563 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
3564 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
3565 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
3566 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
3567 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
3568 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
3569 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
3570 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
3571 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
3572 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
3573 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
3574 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
3575 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
3576 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
3577 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
3578 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
3579 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
3580 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
3581 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
3582 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
3583 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
3584 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
3585 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
3586 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
3587 #define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
3588 #define ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
3589 #define ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
3590 #define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1                                                                0x10e3
3591 #define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2                                                                0x10e4
3592 #define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
3593 #define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
3594 #define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
3595 #define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
3596 #define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
3597 #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1                                                               0x10ea
3598 #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2                                                               0x10eb
3599 #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3                                                               0x10ec
3600 #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2                                                           0x10ed
3601 #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3                                                           0x10ee
3602 #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4                                                           0x10ef
3603 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
3604 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
3605 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
3606 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
3607 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
3608 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
3609 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
3610 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
3611 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
3612 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
3613 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
3614 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
3615 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
3616 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
3617 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
3618 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
3619 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
3620 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
3621 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
3622 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
3623 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
3624 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
3625 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
3626 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
3627 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
3628 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
3629 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
3630 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
3631 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
3632 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
3633 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
3634 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA                                                              0x111f
3635 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
3636 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
3637 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
3638 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
3639 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
3640 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
3641 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
3642 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
3643 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
3644 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
3645 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
3646 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
3647 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
3648 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
3649 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
3650 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
3651 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
3652 #define ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
3653 #define ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
3654 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
3655 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
3656 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
3657 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
3658 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
3659 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
3660 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
3661 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
3662 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
3663 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
3664 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
3665 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
3666 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
3667 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
3668 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
3669 #define ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
3670 #define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
3671 #define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
3672 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
3673 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
3674 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
3675 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
3676 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
3677 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT                                                            0x1158
3678 #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
3679 #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
3680 #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
3681 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
3682 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
3683 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
3684 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
3685 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
3686 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
3687 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
3688 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
3689 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
3690 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
3691 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
3692 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
3693 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
3694 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
3695 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
3696 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
3697 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
3698 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
3699 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
3700 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
3701 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
3702 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
3703 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
3704 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
3705 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
3706 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
3707 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
3708 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
3709 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
3710 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
3711 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
3712 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
3713 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
3714 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
3715 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
3716 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
3717 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
3718 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
3719 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
3720 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
3721 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
3722 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
3723 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
3724 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
3725 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
3726 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
3727 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
3728 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
3729 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
3730 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
3731 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
3732 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
3733 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
3734 #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
3735 #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
3736 #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
3737 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
3738 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
3739 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
3740 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
3741 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
3742 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
3743 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
3744 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
3745 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
3746 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
3747 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
3748 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
3749 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
3750 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
3751 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
3752 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
3753 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
3754 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
3755 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
3756 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
3757 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
3758 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
3759 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
3760 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
3761 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
3762 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
3763 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
3764 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
3765 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
3766 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
3767 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
3768 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
3769 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
3770 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
3771 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
3772 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
3773 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
3774 #define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
3775 #define ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
3776 #define ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
3777 #define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1                                                                0x11e3
3778 #define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2                                                                0x11e4
3779 #define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
3780 #define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
3781 #define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
3782 #define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
3783 #define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
3784 #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1                                                               0x11ea
3785 #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2                                                               0x11eb
3786 #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3                                                               0x11ec
3787 #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2                                                           0x11ed
3788 #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3                                                           0x11ee
3789 #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4                                                           0x11ef
3790 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1                                                               0x11f0
3791 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2                                                               0x11f1
3792 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES                                                             0x11f2
3793 #define ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
3794 #define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
3795 #define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
3796 #define ixDPCSSYS_CR1_LANE1_ANA_RX_SQ                                                                  0x11f6
3797 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1                                                                0x11f7
3798 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2                                                                0x11f8
3799 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
3800 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
3801 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
3802 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
3803 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
3804 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
3805 #define ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1                                                           0x11ff
3806 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
3807 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
3808 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
3809 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
3810 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
3811 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
3812 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
3813 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
3814 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
3815 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
3816 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
3817 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
3818 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
3819 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
3820 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
3821 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
3822 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
3823 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
3824 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
3825 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
3826 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
3827 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
3828 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
3829 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
3830 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
3831 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
3832 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
3833 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
3834 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
3835 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
3836 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
3837 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA                                                              0x121f
3838 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
3839 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
3840 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
3841 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
3842 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
3843 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
3844 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
3845 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
3846 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
3847 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
3848 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
3849 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
3850 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
3851 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
3852 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
3853 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
3854 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
3855 #define ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
3856 #define ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
3857 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
3858 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
3859 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
3860 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
3861 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
3862 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
3863 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
3864 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
3865 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
3866 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
3867 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
3868 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
3869 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
3870 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
3871 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
3872 #define ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
3873 #define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
3874 #define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
3875 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
3876 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
3877 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
3878 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
3879 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
3880 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT                                                            0x1258
3881 #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
3882 #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
3883 #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
3884 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
3885 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
3886 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
3887 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
3888 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
3889 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
3890 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
3891 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
3892 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
3893 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
3894 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
3895 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
3896 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
3897 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
3898 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
3899 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
3900 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
3901 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
3902 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
3903 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
3904 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
3905 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
3906 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
3907 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
3908 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
3909 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
3910 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
3911 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
3912 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
3913 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
3914 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
3915 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
3916 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
3917 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
3918 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
3919 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
3920 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
3921 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
3922 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
3923 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
3924 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
3925 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
3926 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
3927 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
3928 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
3929 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
3930 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
3931 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
3932 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
3933 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
3934 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
3935 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
3936 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
3937 #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
3938 #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
3939 #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
3940 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
3941 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
3942 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
3943 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
3944 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
3945 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
3946 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
3947 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
3948 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
3949 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
3950 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
3951 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
3952 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
3953 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
3954 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
3955 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
3956 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
3957 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
3958 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
3959 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
3960 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
3961 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
3962 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
3963 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
3964 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
3965 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
3966 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
3967 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
3968 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
3969 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
3970 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
3971 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
3972 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
3973 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
3974 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
3975 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
3976 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
3977 #define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
3978 #define ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
3979 #define ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
3980 #define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1                                                                0x12e3
3981 #define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2                                                                0x12e4
3982 #define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
3983 #define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
3984 #define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
3985 #define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
3986 #define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
3987 #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1                                                               0x12ea
3988 #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2                                                               0x12eb
3989 #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3                                                               0x12ec
3990 #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2                                                           0x12ed
3991 #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3                                                           0x12ee
3992 #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4                                                           0x12ef
3993 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1                                                               0x12f0
3994 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2                                                               0x12f1
3995 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES                                                             0x12f2
3996 #define ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
3997 #define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
3998 #define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
3999 #define ixDPCSSYS_CR1_LANE2_ANA_RX_SQ                                                                  0x12f6
4000 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1                                                                0x12f7
4001 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2                                                                0x12f8
4002 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
4003 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
4004 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
4005 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
4006 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
4007 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
4008 #define ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1                                                           0x12ff
4009 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
4010 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
4011 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
4012 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
4013 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
4014 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
4015 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
4016 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
4017 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
4018 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
4019 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
4020 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
4021 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
4022 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
4023 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
4024 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
4025 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
4026 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
4027 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
4028 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
4029 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
4030 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
4031 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
4032 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
4033 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
4034 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
4035 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
4036 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
4037 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
4038 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
4039 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
4040 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
4041 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
4042 #define ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
4043 #define ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
4044 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
4045 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
4046 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
4047 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
4048 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
4049 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
4050 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
4051 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
4052 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
4053 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
4054 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
4055 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
4056 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
4057 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
4058 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
4059 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
4060 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
4061 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
4062 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
4063 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
4064 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
4065 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
4066 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
4067 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
4068 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
4069 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
4070 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
4071 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
4072 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
4073 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
4074 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
4075 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
4076 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
4077 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
4078 #define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
4079 #define ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
4080 #define ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
4081 #define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1                                                                0x13e3
4082 #define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2                                                                0x13e4
4083 #define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
4084 #define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
4085 #define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
4086 #define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
4087 #define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
4088 #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1                                                               0x13ea
4089 #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2                                                               0x13eb
4090 #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3                                                               0x13ec
4091 #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2                                                           0x13ed
4092 #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3                                                           0x13ee
4093 #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4                                                           0x13ef
4094 #define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL                                                               0x2000
4095 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
4096 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
4097 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
4098 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
4099 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
4100 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
4101 #define ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
4102 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
4103 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
4104 #define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
4105 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
4106 #define ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
4107 #define ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
4108 #define ixDPCSSYS_CR1_RAWCMN_DIG_OCLA                                                                  0x200e
4109 #define ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
4110 #define ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
4111 #define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
4112 #define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
4113 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
4114 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
4115 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
4116 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
4117 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
4118 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
4119 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
4120 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
4121 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
4122 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
4123 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
4124 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
4125 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
4126 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
4127 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
4128 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
4129 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
4130 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
4131 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
4132 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
4133 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
4134 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
4135 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
4136 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
4137 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
4138 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
4139 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
4140 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
4141 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
4142 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
4143 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
4144 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
4145 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
4146 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
4147 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
4148 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
4149 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
4150 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
4151 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
4152 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
4153 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
4154 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
4155 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
4156 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
4157 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
4158 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
4159 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
4160 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
4161 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
4162 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
4163 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
4164 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
4165 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
4166 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
4167 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
4168 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
4169 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
4170 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
4171 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
4172 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
4173 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
4174 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
4175 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
4176 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
4177 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
4178 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
4179 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
4180 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
4181 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
4182 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
4183 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
4184 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
4185 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
4186 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
4187 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
4188 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
4189 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
4190 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
4191 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
4192 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
4193 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
4194 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
4195 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
4196 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
4197 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
4198 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
4199 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
4200 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
4201 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
4202 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
4203 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
4204 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
4205 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
4206 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
4207 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
4208 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
4209 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
4210 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
4211 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
4212 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
4213 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
4214 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
4215 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
4216 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
4217 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
4218 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
4219 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
4220 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
4221 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
4222 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
4223 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
4224 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
4225 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
4226 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
4227 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
4228 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
4229 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
4230 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
4231 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
4232 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
4233 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
4234 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
4235 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
4236 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
4237 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
4238 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
4239 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
4240 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
4241 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
4242 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
4243 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
4244 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
4245 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
4246 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
4247 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
4248 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
4249 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
4250 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
4251 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
4252 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
4253 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
4254 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
4255 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
4256 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
4257 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
4258 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
4259 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
4260 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
4261 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
4262 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
4263 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
4264 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
4265 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
4266 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
4267 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
4268 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
4269 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
4270 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
4271 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
4272 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
4273 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
4274 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
4275 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
4276 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
4277 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
4278 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
4279 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
4280 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
4281 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
4282 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
4283 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
4284 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
4285 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
4286 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
4287 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
4288 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
4289 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
4290 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
4291 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
4292 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
4293 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
4294 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
4295 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
4296 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
4297 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
4298 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
4299 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
4300 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
4301 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
4302 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
4303 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
4304 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
4305 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
4306 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
4307 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
4308 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
4309 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
4310 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
4311 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
4312 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
4313 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
4314 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
4315 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
4316 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
4317 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
4318 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
4319 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
4320 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
4321 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
4322 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
4323 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
4324 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
4325 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
4326 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
4327 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
4328 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
4329 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
4330 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
4331 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
4332 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
4333 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
4334 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
4335 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
4336 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
4337 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
4338 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
4339 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
4340 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
4341 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
4342 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
4343 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
4344 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
4345 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
4346 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
4347 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
4348 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
4349 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
4350 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
4351 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
4352 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
4353 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
4354 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
4355 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
4356 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
4357 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
4358 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
4359 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
4360 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
4361 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
4362 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
4363 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
4364 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
4365 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
4366 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
4367 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
4368 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
4369 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
4370 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
4371 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
4372 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
4373 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
4374 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
4375 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
4376 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
4377 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
4378 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
4379 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
4380 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
4381 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
4382 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
4383 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
4384 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
4385 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
4386 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
4387 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
4388 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
4389 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
4390 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
4391 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
4392 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
4393 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
4394 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
4395 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
4396 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
4397 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
4398 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
4399 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
4400 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
4401 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
4402 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
4403 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
4404 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
4405 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
4406 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
4407 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
4408 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
4409 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
4410 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
4411 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
4412 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
4413 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
4414 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
4415 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
4416 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
4417 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
4418 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
4419 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
4420 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
4421 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
4422 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
4423 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
4424 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
4425 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
4426 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
4427 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
4428 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
4429 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
4430 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
4431 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
4432 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
4433 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
4434 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
4435 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
4436 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
4437 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
4438 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
4439 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
4440 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
4441 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
4442 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
4443 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
4444 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
4445 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
4446 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
4447 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
4448 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
4449 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
4450 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
4451 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
4452 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
4453 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
4454 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
4455 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
4456 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
4457 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
4458 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
4459 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
4460 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
4461 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
4462 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
4463 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
4464 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
4465 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
4466 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
4467 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
4468 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
4469 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
4470 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
4471 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
4472 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
4473 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
4474 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
4475 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
4476 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
4477 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
4478 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
4479 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
4480 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
4481 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
4482 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
4483 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
4484 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
4485 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
4486 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
4487 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
4488 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
4489 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
4490 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
4491 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
4492 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
4493 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
4494 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
4495 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
4496 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
4497 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
4498 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
4499 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
4500 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
4501 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
4502 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
4503 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
4504 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
4505 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
4506 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
4507 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
4508 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
4509 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
4510 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
4511 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
4512 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
4513 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
4514 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
4515 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
4516 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
4517 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
4518 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
4519 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
4520 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
4521 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
4522 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
4523 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
4524 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
4525 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
4526 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
4527 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
4528 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
4529 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
4530 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
4531 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
4532 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
4533 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
4534 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
4535 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
4536 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
4537 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
4538 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
4539 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
4540 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
4541 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
4542 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
4543 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
4544 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
4545 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
4546 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
4547 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
4548 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
4549 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
4550 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
4551 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
4552 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
4553 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
4554 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
4555 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
4556 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
4557 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
4558 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
4559 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
4560 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
4561 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
4562 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
4563 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
4564 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
4565 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
4566 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
4567 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
4568 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
4569 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
4570 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
4571 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
4572 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
4573 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
4574 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
4575 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
4576 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
4577 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
4578 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
4579 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
4580 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
4581 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
4582 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
4583 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
4584 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
4585 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
4586 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
4587 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
4588 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
4589 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
4590 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
4591 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
4592 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
4593 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
4594 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
4595 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
4596 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
4597 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
4598 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
4599 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
4600 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
4601 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
4602 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
4603 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
4604 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
4605 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
4606 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
4607 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
4608 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
4609 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
4610 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
4611 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
4612 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
4613 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
4614 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
4615 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
4616 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
4617 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
4618 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
4619 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
4620 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
4621 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
4622 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
4623 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
4624 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
4625 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
4626 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
4627 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
4628 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
4629 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
4630 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
4631 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
4632 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
4633 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
4634 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
4635 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
4636 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
4637 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
4638 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
4639 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
4640 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
4641 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
4642 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
4643 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
4644 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
4645 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
4646 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
4647 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
4648 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
4649 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
4650 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
4651 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
4652 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
4653 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
4654 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
4655 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
4656 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
4657 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
4658 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
4659 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
4660 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
4661 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
4662 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
4663 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
4664 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
4665 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
4666 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
4667 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
4668 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
4669 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
4670 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
4671 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
4672 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
4673 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
4674 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
4675 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
4676 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
4677 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
4678 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
4679 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
4680 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
4681 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
4682 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
4683 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
4684 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
4685 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
4686 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
4687 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
4688 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
4689 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
4690 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
4691 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
4692 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
4693 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
4694 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
4695 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
4696 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS                                                            0x4032
4697 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
4698 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
4699 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
4700 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
4701 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
4702 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
4703 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
4704 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
4705 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
4706 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
4707 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
4708 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
4709 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
4710 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
4711 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
4712 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
4713 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
4714 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
4715 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
4716 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
4717 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
4718 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
4719 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
4720 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
4721 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
4722 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
4723 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
4724 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
4725 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
4726 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
4727 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
4728 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
4729 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
4730 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
4731 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
4732 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
4733 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
4734 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
4735 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
4736 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
4737 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
4738 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
4739 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
4740 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
4741 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
4742 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
4743 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
4744 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
4745 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
4746 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
4747 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
4748 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
4749 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
4750 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
4751 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
4752 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
4753 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
4754 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
4755 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
4756 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
4757 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
4758 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
4759 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
4760 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
4761 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
4762 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
4763 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
4764 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
4765 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
4766 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
4767 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
4768 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
4769 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
4770 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
4771 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
4772 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
4773 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
4774 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
4775 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
4776 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
4777 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
4778 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS                                                            0x4132
4779 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
4780 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
4781 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
4782 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
4783 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
4784 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
4785 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
4786 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
4787 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
4788 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
4789 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
4790 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
4791 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
4792 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
4793 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
4794 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
4795 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
4796 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
4797 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
4798 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
4799 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
4800 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
4801 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
4802 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
4803 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
4804 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
4805 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
4806 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
4807 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
4808 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
4809 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
4810 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
4811 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
4812 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
4813 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
4814 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
4815 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
4816 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
4817 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
4818 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
4819 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
4820 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
4821 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
4822 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
4823 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
4824 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
4825 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
4826 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
4827 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
4828 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
4829 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
4830 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
4831 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
4832 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
4833 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
4834 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
4835 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
4836 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
4837 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
4838 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
4839 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
4840 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
4841 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
4842 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
4843 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
4844 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
4845 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
4846 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
4847 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
4848 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
4849 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
4850 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
4851 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
4852 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
4853 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
4854 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
4855 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
4856 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
4857 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
4858 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
4859 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
4860 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS                                                            0x4232
4861 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
4862 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
4863 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
4864 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
4865 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
4866 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
4867 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
4868 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
4869 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
4870 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
4871 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
4872 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
4873 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
4874 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
4875 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
4876 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
4877 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
4878 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
4879 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
4880 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
4881 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
4882 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
4883 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
4884 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
4885 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
4886 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
4887 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
4888 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
4889 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
4890 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
4891 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
4892 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
4893 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
4894 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
4895 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
4896 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
4897 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
4898 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
4899 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
4900 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
4901 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
4902 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
4903 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
4904 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
4905 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
4906 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
4907 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
4908 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
4909 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
4910 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
4911 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
4912 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
4913 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
4914 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
4915 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
4916 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
4917 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
4918 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
4919 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
4920 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
4921 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
4922 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
4923 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
4924 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
4925 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
4926 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
4927 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
4928 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
4929 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
4930 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
4931 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
4932 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
4933 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
4934 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
4935 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
4936 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
4937 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
4938 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
4939 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
4940 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
4941 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
4942 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS                                                            0x4332
4943 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
4944 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
4945 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
4946 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
4947 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
4948 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
4949 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
4950 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
4951 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
4952 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
4953 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
4954 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
4955 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
4956 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
4957 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
4958 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
4959 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
4960 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
4961 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
4962 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
4963 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
4964 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
4965 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
4966 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
4967 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
4968 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
4969 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
4970 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
4971 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
4972 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
4973 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
4974 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
4975 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
4976 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
4977 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
4978 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
4979 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
4980 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
4981 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
4982 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
4983 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
4984 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
4985 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
4986 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
4987 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
4988 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
4989 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
4990 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
4991 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
4992 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
4993 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
4994 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
4995 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
4996 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
4997 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
4998 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
4999 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
5000 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
5001 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
5002 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
5003 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
5004 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
5005 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
5006 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
5007 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
5008 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
5009 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
5010 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
5011 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
5012 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
5013 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
5014 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
5015 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
5016 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
5017 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
5018 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
5019 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
5020 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
5021 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
5022 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
5023 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
5024 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS                                                            0x7032
5025 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
5026 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
5027 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
5028 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
5029 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
5030 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
5031 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
5032 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
5033 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
5034 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
5035 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
5036 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
5037 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
5038 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
5039 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
5040 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
5041 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
5042 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
5043 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
5044 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
5045 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
5046 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
5047 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
5048 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
5049 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
5050 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
5051 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
5052 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
5053 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
5054 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
5055 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
5056 #define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO                                                               0x8000
5057 #define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI                                                               0x8001
5058 #define ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
5059 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
5060 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
5061 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
5062 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
5063 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
5064 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
5065 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
5066 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
5067 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
5068 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
5069 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
5070 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
5071 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
5072 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
5073 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
5074 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
5075 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
5076 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
5077 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
5078 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
5079 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
5080 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
5081 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
5082 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
5083 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
5084 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
5085 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
5086 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
5087 #define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
5088 #define ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
5089 #define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
5090 #define ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
5091 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
5092 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
5093 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
5094 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
5095 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
5096 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
5097 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
5098 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
5099 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
5100 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
5101 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
5102 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
5103 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
5104 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
5105 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
5106 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
5107 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
5108 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
5109 #define ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN                                                                 0x8036
5110 #define ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
5111 #define ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
5112 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
5113 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
5114 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
5115 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
5116 #define ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
5117 #define ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL                                                              0x8041
5118 #define ixDPCSSYS_CR1_SUPX_ANA_BG1                                                                     0x8042
5119 #define ixDPCSSYS_CR1_SUPX_ANA_BG2                                                                     0x8043
5120 #define ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
5121 #define ixDPCSSYS_CR1_SUPX_ANA_BG3                                                                     0x8045
5122 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1                                                             0x8046
5123 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2                                                             0x8047
5124 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD                                                              0x8048
5125 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1                                                              0x8049
5126 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2                                                              0x804a
5127 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3                                                              0x804b
5128 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1                                                              0x804c
5129 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2                                                              0x804d
5130 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3                                                              0x804e
5131 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4                                                              0x804f
5132 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5                                                              0x8050
5133 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
5134 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
5135 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1                                                             0x8053
5136 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2                                                             0x8054
5137 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD                                                              0x8055
5138 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1                                                              0x8056
5139 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2                                                              0x8057
5140 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3                                                              0x8058
5141 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1                                                              0x8059
5142 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2                                                              0x805a
5143 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3                                                              0x805b
5144 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4                                                              0x805c
5145 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5                                                              0x805d
5146 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
5147 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
5148 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
5149 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
5150 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
5151 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
5152 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
5153 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
5154 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
5155 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
5156 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
5157 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
5158 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
5159 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
5160 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
5161 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
5162 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
5163 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
5164 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
5165 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
5166 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
5167 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
5168 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
5169 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
5170 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
5171 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
5172 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
5173 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
5174 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT                                                              0x8082
5175 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
5176 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
5177 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
5178 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
5179 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
5180 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
5181 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
5182 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
5183 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
5184 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
5185 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
5186 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
5187 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
5188 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
5189 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
5190 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
5191 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT                                                                0x8093
5192 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
5193 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
5194 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
5195 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
5196 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
5197 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
5198 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
5199 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
5200 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
5201 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
5202 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
5203 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
5204 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
5205 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
5206 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
5207 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
5208 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
5209 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
5210 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
5211 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
5212 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
5213 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
5214 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
5215 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
5216 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
5217 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
5218 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
5219 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
5220 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
5221 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
5222 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
5223 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
5224 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
5225 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
5226 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA                                                              0x901f
5227 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
5228 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
5229 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
5230 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
5231 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
5232 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
5233 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
5234 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
5235 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
5236 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
5237 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
5238 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
5239 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
5240 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
5241 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
5242 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
5243 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
5244 #define ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
5245 #define ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
5246 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
5247 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
5248 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
5249 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
5250 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
5251 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
5252 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
5253 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
5254 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
5255 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
5256 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
5257 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
5258 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
5259 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
5260 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
5261 #define ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
5262 #define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
5263 #define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
5264 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
5265 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
5266 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
5267 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
5268 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
5269 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT                                                            0x9058
5270 #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
5271 #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
5272 #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
5273 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
5274 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
5275 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
5276 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
5277 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
5278 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
5279 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
5280 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
5281 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
5282 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
5283 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
5284 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
5285 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
5286 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
5287 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
5288 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
5289 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
5290 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
5291 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
5292 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
5293 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
5294 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
5295 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
5296 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
5297 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
5298 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
5299 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
5300 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
5301 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
5302 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
5303 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
5304 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
5305 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
5306 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
5307 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
5308 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
5309 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
5310 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
5311 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
5312 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
5313 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
5314 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
5315 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
5316 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
5317 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
5318 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
5319 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
5320 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
5321 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
5322 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
5323 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
5324 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
5325 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
5326 #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
5327 #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
5328 #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
5329 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
5330 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
5331 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
5332 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
5333 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
5334 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
5335 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
5336 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
5337 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
5338 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
5339 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
5340 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
5341 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
5342 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
5343 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
5344 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
5345 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
5346 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
5347 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
5348 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
5349 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
5350 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
5351 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
5352 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
5353 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
5354 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
5355 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
5356 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
5357 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
5358 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
5359 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
5360 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
5361 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
5362 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
5363 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
5364 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
5365 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
5366 #define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
5367 #define ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
5368 #define ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
5369 #define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1                                                                0x90e3
5370 #define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2                                                                0x90e4
5371 #define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
5372 #define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
5373 #define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
5374 #define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
5375 #define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
5376 #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1                                                               0x90ea
5377 #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2                                                               0x90eb
5378 #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3                                                               0x90ec
5379 #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2                                                           0x90ed
5380 #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3                                                           0x90ee
5381 #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4                                                           0x90ef
5382 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1                                                               0x90f0
5383 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2                                                               0x90f1
5384 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES                                                             0x90f2
5385 #define ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
5386 #define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
5387 #define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
5388 #define ixDPCSSYS_CR1_LANEX_ANA_RX_SQ                                                                  0x90f6
5389 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1                                                                0x90f7
5390 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2                                                                0x90f8
5391 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
5392 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
5393 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
5394 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
5395 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
5396 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
5397 #define ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1                                                           0x90ff
5398 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
5399 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
5400 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
5401 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
5402 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
5403 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
5404 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
5405 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
5406 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
5407 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
5408 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
5409 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
5410 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
5411 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
5412 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
5413 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
5414 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
5415 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
5416 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
5417 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
5418 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
5419 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
5420 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
5421 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
5422 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
5423 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
5424 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
5425 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
5426 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
5427 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
5428 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
5429 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
5430 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
5431 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
5432 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
5433 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
5434 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
5435 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
5436 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
5437 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
5438 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
5439 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
5440 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
5441 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
5442 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
5443 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
5444 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
5445 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
5446 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
5447 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
5448 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
5449 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
5450 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
5451 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
5452 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
5453 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
5454 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
5455 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
5456 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
5457 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
5458 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
5459 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
5460 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
5461 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
5462 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
5463 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
5464 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
5465 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
5466 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
5467 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
5468 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
5469 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
5470 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
5471 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
5472 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
5473 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
5474 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
5475 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
5476 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
5477 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
5478 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
5479 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
5480 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
5481 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
5482 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
5483 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
5484 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
5485 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
5486 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
5487 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
5488 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
5489 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
5490 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
5491 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
5492 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
5493 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
5494 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
5495 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
5496 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
5497 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
5498 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
5499 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
5500 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
5501 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
5502 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
5503 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
5504 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
5505 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
5506 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
5507 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
5508 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
5509 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
5510 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
5511 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
5512 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
5513 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
5514 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
5515 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
5516 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
5517 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
5518 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
5519 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
5520 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
5521 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
5522 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
5523 
5524 
5525 // addressBlock: dpcssys_cr2_rdpcstxcrind
5526 // base address: 0x0
5527 #define ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO                                                                0x0000
5528 #define ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI                                                                0x0001
5529 #define ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
5530 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
5531 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
5532 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
5533 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
5534 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
5535 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
5536 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
5537 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
5538 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
5539 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
5540 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
5541 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
5542 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
5543 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
5544 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
5545 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
5546 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
5547 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
5548 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
5549 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
5550 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
5551 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
5552 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
5553 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
5554 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
5555 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
5556 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
5557 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
5558 #define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN                                                              0x001f
5559 #define ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
5560 #define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
5561 #define ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN                                                              0x0022
5562 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
5563 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
5564 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
5565 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
5566 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
5567 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
5568 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
5569 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
5570 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
5571 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
5572 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
5573 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
5574 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
5575 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
5576 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
5577 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
5578 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
5579 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
5580 #define ixDPCSSYS_CR2_SUP_DIG_ASIC_IN                                                                  0x0036
5581 #define ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN                                                              0x0037
5582 #define ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
5583 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
5584 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
5585 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
5586 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
5587 #define ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL                                                           0x0040
5588 #define ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL                                                               0x0041
5589 #define ixDPCSSYS_CR2_SUP_ANA_BG1                                                                      0x0042
5590 #define ixDPCSSYS_CR2_SUP_ANA_BG2                                                                      0x0043
5591 #define ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
5592 #define ixDPCSSYS_CR2_SUP_ANA_BG3                                                                      0x0045
5593 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1                                                              0x0046
5594 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2                                                              0x0047
5595 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD                                                               0x0048
5596 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1                                                               0x0049
5597 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2                                                               0x004a
5598 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3                                                               0x004b
5599 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1                                                               0x004c
5600 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2                                                               0x004d
5601 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3                                                               0x004e
5602 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4                                                               0x004f
5603 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5                                                               0x0050
5604 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
5605 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
5606 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1                                                              0x0053
5607 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2                                                              0x0054
5608 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD                                                               0x0055
5609 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1                                                               0x0056
5610 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2                                                               0x0057
5611 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3                                                               0x0058
5612 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1                                                               0x0059
5613 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2                                                               0x005a
5614 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3                                                               0x005b
5615 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4                                                               0x005c
5616 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5                                                               0x005d
5617 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
5618 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
5619 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
5620 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
5621 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
5622 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
5623 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
5624 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
5625 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
5626 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
5627 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
5628 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
5629 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
5630 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
5631 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
5632 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
5633 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
5634 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
5635 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
5636 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
5637 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
5638 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
5639 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
5640 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
5641 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
5642 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
5643 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
5644 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG                                                             0x0081
5645 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT                                                               0x0082
5646 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
5647 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
5648 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
5649 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
5650 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
5651 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
5652 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
5653 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
5654 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
5655 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
5656 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
5657 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
5658 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
5659 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
5660 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
5661 #define ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
5662 #define ixDPCSSYS_CR2_SUP_DIG_ANA_STAT                                                                 0x0093
5663 #define ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
5664 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
5665 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
5666 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
5667 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
5668 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
5669 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
5670 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
5671 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
5672 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
5673 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
5674 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
5675 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
5676 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
5677 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
5678 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
5679 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
5680 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
5681 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
5682 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
5683 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
5684 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
5685 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
5686 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
5687 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
5688 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
5689 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
5690 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
5691 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
5692 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
5693 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
5694 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
5695 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
5696 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
5697 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
5698 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
5699 #define ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
5700 #define ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
5701 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
5702 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
5703 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
5704 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
5705 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
5706 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
5707 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
5708 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
5709 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
5710 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
5711 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
5712 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
5713 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
5714 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
5715 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
5716 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
5717 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
5718 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
5719 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
5720 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
5721 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
5722 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
5723 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
5724 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
5725 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
5726 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
5727 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
5728 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
5729 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
5730 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
5731 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
5732 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
5733 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
5734 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
5735 #define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
5736 #define ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
5737 #define ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
5738 #define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1                                                                0x10e3
5739 #define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2                                                                0x10e4
5740 #define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
5741 #define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
5742 #define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
5743 #define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
5744 #define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
5745 #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1                                                               0x10ea
5746 #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2                                                               0x10eb
5747 #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3                                                               0x10ec
5748 #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2                                                           0x10ed
5749 #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3                                                           0x10ee
5750 #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4                                                           0x10ef
5751 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
5752 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
5753 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
5754 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
5755 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
5756 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
5757 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
5758 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
5759 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
5760 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
5761 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
5762 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
5763 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
5764 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
5765 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
5766 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
5767 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
5768 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
5769 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
5770 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
5771 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
5772 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
5773 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
5774 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
5775 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
5776 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
5777 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
5778 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
5779 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
5780 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
5781 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
5782 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA                                                              0x111f
5783 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
5784 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
5785 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
5786 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
5787 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
5788 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
5789 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
5790 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
5791 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
5792 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
5793 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
5794 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
5795 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
5796 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
5797 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
5798 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
5799 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
5800 #define ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
5801 #define ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
5802 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
5803 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
5804 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
5805 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
5806 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
5807 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
5808 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
5809 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
5810 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
5811 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
5812 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
5813 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
5814 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
5815 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
5816 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
5817 #define ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
5818 #define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
5819 #define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
5820 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
5821 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
5822 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
5823 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
5824 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
5825 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT                                                            0x1158
5826 #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
5827 #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
5828 #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
5829 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
5830 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
5831 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
5832 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
5833 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
5834 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
5835 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
5836 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
5837 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
5838 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
5839 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
5840 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
5841 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
5842 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
5843 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
5844 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
5845 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
5846 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
5847 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
5848 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
5849 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
5850 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
5851 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
5852 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
5853 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
5854 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
5855 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
5856 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
5857 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
5858 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
5859 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
5860 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
5861 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
5862 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
5863 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
5864 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
5865 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
5866 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
5867 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
5868 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
5869 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
5870 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
5871 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
5872 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
5873 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
5874 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
5875 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
5876 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
5877 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
5878 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
5879 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
5880 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
5881 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
5882 #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
5883 #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
5884 #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
5885 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
5886 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
5887 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
5888 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
5889 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
5890 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
5891 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
5892 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
5893 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
5894 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
5895 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
5896 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
5897 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
5898 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
5899 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
5900 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
5901 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
5902 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
5903 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
5904 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
5905 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
5906 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
5907 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
5908 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
5909 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
5910 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
5911 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
5912 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
5913 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
5914 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
5915 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
5916 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
5917 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
5918 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
5919 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
5920 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
5921 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
5922 #define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
5923 #define ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
5924 #define ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
5925 #define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1                                                                0x11e3
5926 #define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2                                                                0x11e4
5927 #define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
5928 #define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
5929 #define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
5930 #define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
5931 #define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
5932 #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1                                                               0x11ea
5933 #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2                                                               0x11eb
5934 #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3                                                               0x11ec
5935 #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2                                                           0x11ed
5936 #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3                                                           0x11ee
5937 #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4                                                           0x11ef
5938 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1                                                               0x11f0
5939 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2                                                               0x11f1
5940 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES                                                             0x11f2
5941 #define ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
5942 #define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
5943 #define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
5944 #define ixDPCSSYS_CR2_LANE1_ANA_RX_SQ                                                                  0x11f6
5945 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1                                                                0x11f7
5946 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2                                                                0x11f8
5947 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
5948 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
5949 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
5950 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
5951 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
5952 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
5953 #define ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1                                                           0x11ff
5954 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
5955 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
5956 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
5957 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
5958 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
5959 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
5960 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
5961 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
5962 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
5963 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
5964 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
5965 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
5966 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
5967 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
5968 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
5969 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
5970 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
5971 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
5972 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
5973 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
5974 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
5975 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
5976 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
5977 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
5978 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
5979 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
5980 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
5981 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
5982 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
5983 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
5984 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
5985 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA                                                              0x121f
5986 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
5987 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
5988 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
5989 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
5990 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
5991 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
5992 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
5993 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
5994 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
5995 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
5996 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
5997 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
5998 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
5999 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
6000 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
6001 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
6002 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
6003 #define ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
6004 #define ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
6005 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
6006 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
6007 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
6008 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
6009 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
6010 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
6011 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
6012 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
6013 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
6014 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
6015 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
6016 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
6017 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
6018 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
6019 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
6020 #define ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
6021 #define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
6022 #define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
6023 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
6024 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
6025 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
6026 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
6027 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
6028 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT                                                            0x1258
6029 #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
6030 #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
6031 #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
6032 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
6033 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
6034 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
6035 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
6036 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
6037 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
6038 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
6039 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
6040 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
6041 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
6042 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
6043 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
6044 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
6045 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
6046 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
6047 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
6048 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
6049 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
6050 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
6051 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
6052 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
6053 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
6054 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
6055 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
6056 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
6057 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
6058 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
6059 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
6060 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
6061 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
6062 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
6063 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
6064 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
6065 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
6066 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
6067 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
6068 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
6069 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
6070 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
6071 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
6072 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
6073 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
6074 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
6075 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
6076 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
6077 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
6078 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
6079 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
6080 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
6081 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
6082 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
6083 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
6084 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
6085 #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
6086 #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
6087 #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
6088 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
6089 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
6090 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
6091 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
6092 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
6093 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
6094 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
6095 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
6096 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
6097 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
6098 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
6099 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
6100 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
6101 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
6102 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
6103 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
6104 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
6105 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
6106 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
6107 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
6108 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
6109 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
6110 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
6111 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
6112 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
6113 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
6114 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
6115 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
6116 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
6117 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
6118 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
6119 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
6120 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
6121 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
6122 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
6123 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
6124 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
6125 #define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
6126 #define ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
6127 #define ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
6128 #define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1                                                                0x12e3
6129 #define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2                                                                0x12e4
6130 #define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
6131 #define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
6132 #define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
6133 #define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
6134 #define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
6135 #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1                                                               0x12ea
6136 #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2                                                               0x12eb
6137 #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3                                                               0x12ec
6138 #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2                                                           0x12ed
6139 #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3                                                           0x12ee
6140 #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4                                                           0x12ef
6141 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1                                                               0x12f0
6142 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2                                                               0x12f1
6143 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES                                                             0x12f2
6144 #define ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
6145 #define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
6146 #define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
6147 #define ixDPCSSYS_CR2_LANE2_ANA_RX_SQ                                                                  0x12f6
6148 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1                                                                0x12f7
6149 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2                                                                0x12f8
6150 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
6151 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
6152 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
6153 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
6154 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
6155 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
6156 #define ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1                                                           0x12ff
6157 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
6158 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
6159 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
6160 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
6161 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
6162 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
6163 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
6164 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
6165 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
6166 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
6167 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
6168 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
6169 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
6170 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
6171 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
6172 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
6173 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
6174 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
6175 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
6176 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
6177 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
6178 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
6179 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
6180 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
6181 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
6182 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
6183 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
6184 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
6185 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
6186 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
6187 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
6188 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
6189 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
6190 #define ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
6191 #define ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
6192 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
6193 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
6194 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
6195 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
6196 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
6197 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
6198 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
6199 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
6200 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
6201 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
6202 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
6203 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
6204 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
6205 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
6206 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
6207 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
6208 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
6209 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
6210 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
6211 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
6212 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
6213 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
6214 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
6215 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
6216 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
6217 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
6218 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
6219 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
6220 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
6221 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
6222 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
6223 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
6224 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
6225 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
6226 #define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
6227 #define ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
6228 #define ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
6229 #define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1                                                                0x13e3
6230 #define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2                                                                0x13e4
6231 #define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
6232 #define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
6233 #define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
6234 #define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
6235 #define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
6236 #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1                                                               0x13ea
6237 #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2                                                               0x13eb
6238 #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3                                                               0x13ec
6239 #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2                                                           0x13ed
6240 #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3                                                           0x13ee
6241 #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4                                                           0x13ef
6242 #define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL                                                               0x2000
6243 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
6244 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
6245 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
6246 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
6247 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
6248 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
6249 #define ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
6250 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
6251 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
6252 #define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
6253 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
6254 #define ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
6255 #define ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
6256 #define ixDPCSSYS_CR2_RAWCMN_DIG_OCLA                                                                  0x200e
6257 #define ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
6258 #define ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
6259 #define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
6260 #define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
6261 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
6262 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
6263 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
6264 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
6265 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
6266 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
6267 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
6268 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
6269 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
6270 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
6271 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
6272 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
6273 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
6274 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
6275 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
6276 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
6277 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
6278 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
6279 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
6280 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
6281 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
6282 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
6283 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
6284 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
6285 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
6286 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
6287 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
6288 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
6289 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
6290 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
6291 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
6292 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
6293 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
6294 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
6295 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
6296 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
6297 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
6298 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
6299 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
6300 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
6301 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
6302 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
6303 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
6304 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
6305 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
6306 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
6307 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
6308 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
6309 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
6310 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
6311 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
6312 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
6313 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
6314 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
6315 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
6316 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
6317 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
6318 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
6319 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
6320 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
6321 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
6322 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
6323 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
6324 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
6325 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
6326 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
6327 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
6328 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
6329 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
6330 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
6331 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
6332 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
6333 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
6334 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
6335 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
6336 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
6337 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
6338 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
6339 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
6340 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
6341 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
6342 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
6343 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
6344 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
6345 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
6346 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
6347 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
6348 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
6349 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
6350 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
6351 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
6352 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
6353 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
6354 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
6355 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
6356 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
6357 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
6358 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
6359 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
6360 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
6361 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
6362 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
6363 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
6364 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
6365 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
6366 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
6367 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
6368 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
6369 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
6370 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
6371 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
6372 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
6373 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
6374 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
6375 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
6376 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
6377 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
6378 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
6379 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
6380 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
6381 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
6382 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
6383 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
6384 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
6385 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
6386 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
6387 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
6388 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
6389 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
6390 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
6391 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
6392 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
6393 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
6394 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
6395 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
6396 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
6397 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
6398 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
6399 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
6400 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
6401 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
6402 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
6403 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
6404 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
6405 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
6406 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
6407 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
6408 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
6409 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
6410 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
6411 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
6412 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
6413 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
6414 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
6415 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
6416 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
6417 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
6418 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
6419 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
6420 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
6421 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
6422 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
6423 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
6424 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
6425 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
6426 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
6427 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
6428 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
6429 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
6430 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
6431 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
6432 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
6433 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
6434 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
6435 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
6436 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
6437 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
6438 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
6439 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
6440 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
6441 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
6442 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
6443 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
6444 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
6445 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
6446 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
6447 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
6448 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
6449 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
6450 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
6451 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
6452 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
6453 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
6454 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
6455 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
6456 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
6457 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
6458 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
6459 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
6460 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
6461 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
6462 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
6463 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
6464 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
6465 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
6466 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
6467 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
6468 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
6469 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
6470 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
6471 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
6472 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
6473 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
6474 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
6475 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
6476 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
6477 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
6478 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
6479 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
6480 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
6481 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
6482 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
6483 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
6484 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
6485 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
6486 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
6487 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
6488 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
6489 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
6490 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
6491 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
6492 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
6493 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
6494 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
6495 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
6496 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
6497 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
6498 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
6499 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
6500 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
6501 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
6502 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
6503 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
6504 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
6505 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
6506 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
6507 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
6508 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
6509 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
6510 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
6511 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
6512 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
6513 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
6514 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
6515 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
6516 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
6517 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
6518 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
6519 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
6520 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
6521 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
6522 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
6523 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
6524 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
6525 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
6526 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
6527 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
6528 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
6529 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
6530 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
6531 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
6532 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
6533 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
6534 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
6535 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
6536 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
6537 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
6538 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
6539 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
6540 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
6541 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
6542 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
6543 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
6544 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
6545 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
6546 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
6547 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
6548 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
6549 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
6550 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
6551 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
6552 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
6553 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
6554 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
6555 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
6556 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
6557 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
6558 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
6559 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
6560 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
6561 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
6562 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
6563 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
6564 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
6565 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
6566 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
6567 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
6568 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
6569 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
6570 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
6571 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
6572 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
6573 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
6574 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
6575 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
6576 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
6577 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
6578 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
6579 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
6580 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
6581 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
6582 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
6583 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
6584 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
6585 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
6586 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
6587 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
6588 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
6589 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
6590 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
6591 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
6592 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
6593 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
6594 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
6595 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
6596 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
6597 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
6598 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
6599 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
6600 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
6601 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
6602 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
6603 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
6604 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
6605 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
6606 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
6607 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
6608 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
6609 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
6610 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
6611 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
6612 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
6613 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
6614 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
6615 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
6616 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
6617 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
6618 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
6619 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
6620 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
6621 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
6622 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
6623 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
6624 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
6625 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
6626 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
6627 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
6628 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
6629 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
6630 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
6631 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
6632 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
6633 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
6634 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
6635 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
6636 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
6637 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
6638 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
6639 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
6640 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
6641 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
6642 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
6643 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
6644 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
6645 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
6646 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
6647 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
6648 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
6649 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
6650 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
6651 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
6652 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
6653 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
6654 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
6655 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
6656 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
6657 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
6658 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
6659 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
6660 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
6661 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
6662 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
6663 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
6664 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
6665 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
6666 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
6667 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
6668 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
6669 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
6670 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
6671 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
6672 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
6673 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
6674 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
6675 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
6676 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
6677 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
6678 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
6679 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
6680 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
6681 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
6682 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
6683 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
6684 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
6685 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
6686 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
6687 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
6688 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
6689 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
6690 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
6691 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
6692 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
6693 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
6694 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
6695 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
6696 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
6697 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
6698 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
6699 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
6700 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
6701 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
6702 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
6703 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
6704 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
6705 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
6706 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
6707 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
6708 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
6709 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
6710 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
6711 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
6712 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
6713 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
6714 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
6715 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
6716 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
6717 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
6718 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
6719 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
6720 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
6721 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
6722 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
6723 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
6724 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
6725 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
6726 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
6727 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
6728 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
6729 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
6730 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
6731 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
6732 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
6733 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
6734 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
6735 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
6736 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
6737 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
6738 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
6739 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
6740 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
6741 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
6742 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
6743 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
6744 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
6745 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
6746 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
6747 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
6748 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
6749 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
6750 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
6751 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
6752 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
6753 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
6754 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
6755 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
6756 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
6757 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
6758 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
6759 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
6760 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
6761 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
6762 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
6763 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
6764 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
6765 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
6766 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
6767 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
6768 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
6769 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
6770 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
6771 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
6772 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
6773 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
6774 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
6775 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
6776 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
6777 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
6778 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
6779 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
6780 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
6781 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
6782 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
6783 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
6784 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
6785 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
6786 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
6787 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
6788 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
6789 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
6790 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
6791 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
6792 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
6793 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
6794 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
6795 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
6796 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
6797 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
6798 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
6799 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
6800 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
6801 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
6802 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
6803 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
6804 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
6805 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
6806 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
6807 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
6808 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
6809 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
6810 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
6811 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
6812 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
6813 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
6814 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
6815 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
6816 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
6817 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
6818 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
6819 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
6820 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
6821 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
6822 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
6823 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
6824 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
6825 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
6826 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
6827 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
6828 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
6829 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
6830 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
6831 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
6832 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
6833 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
6834 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
6835 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
6836 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
6837 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
6838 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
6839 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
6840 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
6841 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
6842 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
6843 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
6844 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS                                                            0x4032
6845 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
6846 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
6847 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
6848 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
6849 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
6850 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
6851 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
6852 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
6853 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
6854 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
6855 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
6856 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
6857 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
6858 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
6859 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
6860 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
6861 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
6862 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
6863 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
6864 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
6865 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
6866 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
6867 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
6868 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
6869 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
6870 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
6871 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
6872 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
6873 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
6874 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
6875 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
6876 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
6877 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
6878 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
6879 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
6880 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
6881 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
6882 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
6883 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
6884 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
6885 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
6886 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
6887 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
6888 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
6889 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
6890 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
6891 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
6892 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
6893 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
6894 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
6895 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
6896 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
6897 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
6898 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
6899 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
6900 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
6901 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
6902 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
6903 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
6904 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
6905 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
6906 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
6907 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
6908 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
6909 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
6910 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
6911 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
6912 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
6913 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
6914 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
6915 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
6916 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
6917 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
6918 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
6919 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
6920 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
6921 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
6922 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
6923 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
6924 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
6925 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
6926 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS                                                            0x4132
6927 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
6928 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
6929 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
6930 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
6931 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
6932 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
6933 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
6934 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
6935 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
6936 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
6937 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
6938 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
6939 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
6940 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
6941 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
6942 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
6943 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
6944 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
6945 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
6946 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
6947 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
6948 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
6949 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
6950 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
6951 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
6952 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
6953 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
6954 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
6955 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
6956 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
6957 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
6958 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
6959 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
6960 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
6961 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
6962 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
6963 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
6964 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
6965 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
6966 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
6967 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
6968 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
6969 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
6970 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
6971 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
6972 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
6973 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
6974 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
6975 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
6976 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
6977 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
6978 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
6979 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
6980 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
6981 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
6982 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
6983 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
6984 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
6985 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
6986 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
6987 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
6988 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
6989 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
6990 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
6991 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
6992 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
6993 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
6994 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
6995 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
6996 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
6997 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
6998 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
6999 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
7000 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
7001 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
7002 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
7003 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
7004 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
7005 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
7006 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
7007 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
7008 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS                                                            0x4232
7009 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
7010 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
7011 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
7012 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
7013 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
7014 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
7015 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
7016 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
7017 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
7018 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
7019 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
7020 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
7021 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
7022 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
7023 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
7024 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
7025 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
7026 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
7027 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
7028 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
7029 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
7030 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
7031 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
7032 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
7033 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
7034 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
7035 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
7036 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
7037 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
7038 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
7039 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
7040 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
7041 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
7042 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
7043 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
7044 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
7045 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
7046 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
7047 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
7048 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
7049 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
7050 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
7051 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
7052 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
7053 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
7054 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
7055 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
7056 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
7057 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
7058 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
7059 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
7060 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
7061 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
7062 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
7063 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
7064 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
7065 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
7066 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
7067 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
7068 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
7069 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
7070 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
7071 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
7072 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
7073 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
7074 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
7075 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
7076 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
7077 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
7078 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
7079 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
7080 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
7081 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
7082 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
7083 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
7084 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
7085 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
7086 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
7087 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
7088 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
7089 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
7090 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS                                                            0x4332
7091 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
7092 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
7093 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
7094 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
7095 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
7096 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
7097 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
7098 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
7099 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
7100 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
7101 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
7102 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
7103 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
7104 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
7105 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
7106 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
7107 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
7108 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
7109 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
7110 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
7111 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
7112 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
7113 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
7114 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
7115 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
7116 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
7117 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
7118 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
7119 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
7120 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
7121 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
7122 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
7123 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
7124 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
7125 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
7126 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
7127 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
7128 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
7129 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
7130 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
7131 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
7132 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
7133 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
7134 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
7135 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
7136 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
7137 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
7138 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
7139 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
7140 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
7141 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
7142 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
7143 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
7144 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
7145 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
7146 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
7147 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
7148 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
7149 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
7150 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
7151 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
7152 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
7153 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
7154 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
7155 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
7156 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
7157 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
7158 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
7159 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
7160 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
7161 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
7162 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
7163 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
7164 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
7165 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
7166 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
7167 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
7168 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
7169 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
7170 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
7171 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
7172 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS                                                            0x7032
7173 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
7174 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
7175 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
7176 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
7177 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
7178 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
7179 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
7180 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
7181 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
7182 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
7183 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
7184 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
7185 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
7186 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
7187 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
7188 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
7189 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
7190 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
7191 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
7192 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
7193 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
7194 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
7195 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
7196 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
7197 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
7198 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
7199 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
7200 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
7201 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
7202 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
7203 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
7204 #define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO                                                               0x8000
7205 #define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI                                                               0x8001
7206 #define ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
7207 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
7208 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
7209 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
7210 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
7211 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
7212 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
7213 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
7214 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
7215 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
7216 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
7217 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
7218 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
7219 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
7220 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
7221 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
7222 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
7223 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
7224 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
7225 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
7226 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
7227 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
7228 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
7229 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
7230 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
7231 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
7232 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
7233 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
7234 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
7235 #define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
7236 #define ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
7237 #define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
7238 #define ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
7239 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
7240 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
7241 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
7242 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
7243 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
7244 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
7245 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
7246 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
7247 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
7248 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
7249 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
7250 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
7251 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
7252 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
7253 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
7254 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
7255 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
7256 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
7257 #define ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN                                                                 0x8036
7258 #define ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
7259 #define ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
7260 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
7261 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
7262 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
7263 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
7264 #define ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
7265 #define ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL                                                              0x8041
7266 #define ixDPCSSYS_CR2_SUPX_ANA_BG1                                                                     0x8042
7267 #define ixDPCSSYS_CR2_SUPX_ANA_BG2                                                                     0x8043
7268 #define ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
7269 #define ixDPCSSYS_CR2_SUPX_ANA_BG3                                                                     0x8045
7270 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1                                                             0x8046
7271 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2                                                             0x8047
7272 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD                                                              0x8048
7273 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1                                                              0x8049
7274 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2                                                              0x804a
7275 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3                                                              0x804b
7276 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1                                                              0x804c
7277 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2                                                              0x804d
7278 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3                                                              0x804e
7279 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4                                                              0x804f
7280 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5                                                              0x8050
7281 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
7282 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
7283 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1                                                             0x8053
7284 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2                                                             0x8054
7285 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD                                                              0x8055
7286 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1                                                              0x8056
7287 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2                                                              0x8057
7288 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3                                                              0x8058
7289 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1                                                              0x8059
7290 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2                                                              0x805a
7291 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3                                                              0x805b
7292 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4                                                              0x805c
7293 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5                                                              0x805d
7294 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
7295 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
7296 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
7297 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
7298 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
7299 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
7300 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
7301 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
7302 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
7303 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
7304 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
7305 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
7306 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
7307 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
7308 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
7309 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
7310 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
7311 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
7312 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
7313 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
7314 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
7315 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
7316 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
7317 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
7318 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
7319 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
7320 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
7321 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
7322 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT                                                              0x8082
7323 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
7324 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
7325 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
7326 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
7327 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
7328 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
7329 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
7330 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
7331 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
7332 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
7333 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
7334 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
7335 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
7336 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
7337 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
7338 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
7339 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT                                                                0x8093
7340 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
7341 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
7342 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
7343 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
7344 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
7345 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
7346 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
7347 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
7348 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
7349 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
7350 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
7351 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
7352 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
7353 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
7354 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
7355 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
7356 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
7357 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
7358 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
7359 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
7360 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
7361 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
7362 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
7363 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
7364 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
7365 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
7366 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
7367 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
7368 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
7369 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
7370 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
7371 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
7372 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
7373 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
7374 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA                                                              0x901f
7375 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
7376 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
7377 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
7378 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
7379 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
7380 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
7381 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
7382 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
7383 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
7384 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
7385 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
7386 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
7387 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
7388 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
7389 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
7390 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
7391 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
7392 #define ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
7393 #define ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
7394 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
7395 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
7396 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
7397 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
7398 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
7399 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
7400 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
7401 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
7402 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
7403 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
7404 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
7405 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
7406 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
7407 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
7408 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
7409 #define ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
7410 #define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
7411 #define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
7412 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
7413 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
7414 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
7415 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
7416 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
7417 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT                                                            0x9058
7418 #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
7419 #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
7420 #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
7421 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
7422 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
7423 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
7424 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
7425 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
7426 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
7427 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
7428 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
7429 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
7430 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
7431 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
7432 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
7433 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
7434 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
7435 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
7436 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
7437 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
7438 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
7439 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
7440 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
7441 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
7442 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
7443 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
7444 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
7445 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
7446 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
7447 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
7448 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
7449 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
7450 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
7451 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
7452 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
7453 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
7454 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
7455 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
7456 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
7457 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
7458 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
7459 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
7460 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
7461 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
7462 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
7463 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
7464 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
7465 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
7466 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
7467 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
7468 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
7469 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
7470 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
7471 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
7472 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
7473 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
7474 #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
7475 #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
7476 #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
7477 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
7478 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
7479 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
7480 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
7481 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
7482 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
7483 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
7484 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
7485 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
7486 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
7487 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
7488 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
7489 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
7490 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
7491 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
7492 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
7493 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
7494 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
7495 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
7496 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
7497 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
7498 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
7499 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
7500 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
7501 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
7502 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
7503 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
7504 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
7505 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
7506 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
7507 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
7508 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
7509 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
7510 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
7511 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
7512 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
7513 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
7514 #define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
7515 #define ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
7516 #define ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
7517 #define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1                                                                0x90e3
7518 #define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2                                                                0x90e4
7519 #define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
7520 #define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
7521 #define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
7522 #define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
7523 #define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
7524 #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1                                                               0x90ea
7525 #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2                                                               0x90eb
7526 #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3                                                               0x90ec
7527 #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2                                                           0x90ed
7528 #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3                                                           0x90ee
7529 #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4                                                           0x90ef
7530 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1                                                               0x90f0
7531 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2                                                               0x90f1
7532 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES                                                             0x90f2
7533 #define ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
7534 #define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
7535 #define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
7536 #define ixDPCSSYS_CR2_LANEX_ANA_RX_SQ                                                                  0x90f6
7537 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1                                                                0x90f7
7538 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2                                                                0x90f8
7539 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
7540 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
7541 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
7542 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
7543 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
7544 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
7545 #define ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1                                                           0x90ff
7546 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
7547 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
7548 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
7549 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
7550 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
7551 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
7552 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
7553 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
7554 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
7555 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
7556 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
7557 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
7558 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
7559 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
7560 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
7561 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
7562 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
7563 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
7564 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
7565 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
7566 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
7567 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
7568 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
7569 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
7570 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
7571 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
7572 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
7573 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
7574 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
7575 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
7576 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
7577 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
7578 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
7579 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
7580 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
7581 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
7582 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
7583 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
7584 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
7585 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
7586 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
7587 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
7588 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
7589 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
7590 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
7591 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
7592 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
7593 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
7594 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
7595 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
7596 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
7597 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
7598 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
7599 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
7600 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
7601 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
7602 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
7603 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
7604 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
7605 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
7606 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
7607 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
7608 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
7609 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
7610 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
7611 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
7612 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
7613 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
7614 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
7615 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
7616 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
7617 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
7618 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
7619 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
7620 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
7621 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
7622 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
7623 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
7624 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
7625 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
7626 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
7627 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
7628 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
7629 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
7630 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
7631 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
7632 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
7633 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
7634 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
7635 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
7636 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
7637 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
7638 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
7639 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
7640 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
7641 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
7642 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
7643 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
7644 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
7645 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
7646 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
7647 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
7648 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
7649 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
7650 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
7651 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
7652 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
7653 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
7654 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
7655 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
7656 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
7657 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
7658 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
7659 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
7660 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
7661 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
7662 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
7663 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
7664 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
7665 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
7666 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
7667 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
7668 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
7669 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
7670 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
7671 
7672 
7673 // addressBlock: dpcssys_cr3_rdpcstxcrind
7674 // base address: 0x0
7675 #define ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO                                                                0x0000
7676 #define ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI                                                                0x0001
7677 #define ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
7678 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
7679 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
7680 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
7681 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
7682 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
7683 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
7684 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
7685 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
7686 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
7687 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
7688 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
7689 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
7690 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
7691 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
7692 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
7693 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
7694 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
7695 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
7696 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
7697 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
7698 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
7699 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
7700 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
7701 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
7702 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
7703 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
7704 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
7705 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
7706 #define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN                                                              0x001f
7707 #define ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
7708 #define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
7709 #define ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN                                                              0x0022
7710 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
7711 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
7712 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
7713 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
7714 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
7715 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
7716 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
7717 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
7718 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
7719 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
7720 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
7721 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
7722 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
7723 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
7724 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
7725 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
7726 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
7727 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
7728 #define ixDPCSSYS_CR3_SUP_DIG_ASIC_IN                                                                  0x0036
7729 #define ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN                                                              0x0037
7730 #define ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
7731 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
7732 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
7733 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
7734 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
7735 #define ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL                                                           0x0040
7736 #define ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL                                                               0x0041
7737 #define ixDPCSSYS_CR3_SUP_ANA_BG1                                                                      0x0042
7738 #define ixDPCSSYS_CR3_SUP_ANA_BG2                                                                      0x0043
7739 #define ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
7740 #define ixDPCSSYS_CR3_SUP_ANA_BG3                                                                      0x0045
7741 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1                                                              0x0046
7742 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2                                                              0x0047
7743 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD                                                               0x0048
7744 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1                                                               0x0049
7745 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2                                                               0x004a
7746 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3                                                               0x004b
7747 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1                                                               0x004c
7748 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2                                                               0x004d
7749 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3                                                               0x004e
7750 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4                                                               0x004f
7751 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5                                                               0x0050
7752 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
7753 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
7754 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1                                                              0x0053
7755 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2                                                              0x0054
7756 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD                                                               0x0055
7757 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1                                                               0x0056
7758 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2                                                               0x0057
7759 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3                                                               0x0058
7760 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1                                                               0x0059
7761 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2                                                               0x005a
7762 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3                                                               0x005b
7763 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4                                                               0x005c
7764 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5                                                               0x005d
7765 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
7766 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
7767 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
7768 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
7769 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
7770 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
7771 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
7772 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
7773 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
7774 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
7775 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
7776 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
7777 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
7778 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
7779 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
7780 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
7781 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
7782 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
7783 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
7784 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
7785 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
7786 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
7787 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
7788 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
7789 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
7790 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
7791 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
7792 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG                                                             0x0081
7793 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT                                                               0x0082
7794 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
7795 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
7796 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
7797 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
7798 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
7799 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
7800 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
7801 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
7802 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
7803 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
7804 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
7805 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
7806 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
7807 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
7808 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
7809 #define ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
7810 #define ixDPCSSYS_CR3_SUP_DIG_ANA_STAT                                                                 0x0093
7811 #define ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
7812 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
7813 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
7814 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
7815 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
7816 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
7817 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
7818 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
7819 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
7820 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
7821 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
7822 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
7823 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
7824 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
7825 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
7826 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
7827 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
7828 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
7829 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
7830 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
7831 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
7832 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
7833 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
7834 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
7835 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
7836 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
7837 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
7838 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
7839 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
7840 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
7841 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
7842 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
7843 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
7844 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
7845 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
7846 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
7847 #define ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
7848 #define ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
7849 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
7850 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
7851 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
7852 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
7853 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
7854 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
7855 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
7856 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
7857 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
7858 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
7859 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
7860 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
7861 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
7862 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
7863 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
7864 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
7865 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
7866 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
7867 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
7868 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
7869 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
7870 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
7871 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
7872 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
7873 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
7874 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
7875 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
7876 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
7877 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
7878 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
7879 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
7880 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
7881 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
7882 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
7883 #define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
7884 #define ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
7885 #define ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
7886 #define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1                                                                0x10e3
7887 #define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2                                                                0x10e4
7888 #define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
7889 #define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
7890 #define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
7891 #define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
7892 #define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
7893 #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1                                                               0x10ea
7894 #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2                                                               0x10eb
7895 #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3                                                               0x10ec
7896 #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2                                                           0x10ed
7897 #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3                                                           0x10ee
7898 #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4                                                           0x10ef
7899 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
7900 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
7901 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
7902 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
7903 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
7904 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
7905 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
7906 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
7907 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
7908 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
7909 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
7910 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
7911 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
7912 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
7913 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
7914 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
7915 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
7916 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
7917 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
7918 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
7919 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
7920 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
7921 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
7922 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
7923 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
7924 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
7925 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
7926 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
7927 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
7928 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
7929 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
7930 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA                                                              0x111f
7931 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
7932 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
7933 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
7934 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
7935 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
7936 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
7937 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
7938 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
7939 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
7940 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
7941 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
7942 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
7943 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
7944 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
7945 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
7946 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
7947 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
7948 #define ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
7949 #define ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
7950 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
7951 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
7952 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
7953 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
7954 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
7955 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
7956 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
7957 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
7958 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
7959 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
7960 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
7961 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
7962 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
7963 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
7964 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
7965 #define ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
7966 #define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
7967 #define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
7968 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
7969 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
7970 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
7971 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
7972 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
7973 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT                                                            0x1158
7974 #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
7975 #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
7976 #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
7977 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
7978 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
7979 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
7980 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
7981 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
7982 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
7983 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
7984 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
7985 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
7986 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
7987 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
7988 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
7989 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
7990 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
7991 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
7992 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
7993 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
7994 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
7995 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
7996 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
7997 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
7998 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
7999 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
8000 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
8001 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
8002 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
8003 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
8004 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
8005 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
8006 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
8007 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
8008 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
8009 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
8010 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
8011 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
8012 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
8013 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
8014 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
8015 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
8016 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
8017 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
8018 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
8019 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
8020 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
8021 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
8022 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
8023 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
8024 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
8025 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
8026 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
8027 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
8028 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
8029 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
8030 #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
8031 #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
8032 #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
8033 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
8034 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
8035 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
8036 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
8037 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
8038 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
8039 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
8040 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
8041 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
8042 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
8043 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
8044 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
8045 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
8046 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
8047 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
8048 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
8049 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
8050 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
8051 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
8052 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
8053 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
8054 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
8055 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
8056 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
8057 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
8058 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
8059 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
8060 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
8061 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
8062 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
8063 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
8064 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
8065 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
8066 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
8067 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
8068 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
8069 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
8070 #define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
8071 #define ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
8072 #define ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
8073 #define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1                                                                0x11e3
8074 #define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2                                                                0x11e4
8075 #define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
8076 #define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
8077 #define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
8078 #define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
8079 #define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
8080 #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1                                                               0x11ea
8081 #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2                                                               0x11eb
8082 #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3                                                               0x11ec
8083 #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2                                                           0x11ed
8084 #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3                                                           0x11ee
8085 #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4                                                           0x11ef
8086 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1                                                               0x11f0
8087 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2                                                               0x11f1
8088 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES                                                             0x11f2
8089 #define ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
8090 #define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
8091 #define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
8092 #define ixDPCSSYS_CR3_LANE1_ANA_RX_SQ                                                                  0x11f6
8093 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1                                                                0x11f7
8094 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2                                                                0x11f8
8095 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
8096 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
8097 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
8098 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
8099 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
8100 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
8101 #define ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1                                                           0x11ff
8102 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
8103 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
8104 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
8105 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
8106 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
8107 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
8108 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
8109 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
8110 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
8111 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
8112 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
8113 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
8114 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
8115 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
8116 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
8117 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
8118 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
8119 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
8120 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
8121 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
8122 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
8123 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
8124 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
8125 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
8126 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
8127 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
8128 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
8129 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
8130 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
8131 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
8132 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
8133 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA                                                              0x121f
8134 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
8135 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
8136 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
8137 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
8138 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
8139 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
8140 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
8141 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
8142 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
8143 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
8144 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
8145 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
8146 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
8147 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
8148 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
8149 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
8150 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
8151 #define ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
8152 #define ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
8153 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
8154 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
8155 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
8156 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
8157 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
8158 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
8159 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
8160 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
8161 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
8162 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
8163 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
8164 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
8165 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
8166 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
8167 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
8168 #define ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
8169 #define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
8170 #define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
8171 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
8172 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
8173 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
8174 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
8175 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
8176 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT                                                            0x1258
8177 #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
8178 #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
8179 #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
8180 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
8181 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
8182 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
8183 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
8184 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
8185 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
8186 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
8187 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
8188 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
8189 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
8190 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
8191 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
8192 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
8193 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
8194 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
8195 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
8196 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
8197 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
8198 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
8199 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
8200 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
8201 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
8202 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
8203 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
8204 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
8205 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
8206 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
8207 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
8208 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
8209 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
8210 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
8211 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
8212 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
8213 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
8214 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
8215 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
8216 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
8217 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
8218 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
8219 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
8220 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
8221 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
8222 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
8223 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
8224 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
8225 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
8226 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
8227 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
8228 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
8229 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
8230 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
8231 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
8232 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
8233 #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
8234 #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
8235 #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
8236 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
8237 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
8238 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
8239 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
8240 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
8241 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
8242 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
8243 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
8244 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
8245 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
8246 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
8247 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
8248 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
8249 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
8250 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
8251 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
8252 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
8253 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
8254 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
8255 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
8256 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
8257 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
8258 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
8259 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
8260 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
8261 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
8262 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
8263 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
8264 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
8265 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
8266 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
8267 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
8268 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
8269 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
8270 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
8271 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
8272 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
8273 #define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
8274 #define ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
8275 #define ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
8276 #define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1                                                                0x12e3
8277 #define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2                                                                0x12e4
8278 #define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
8279 #define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
8280 #define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
8281 #define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
8282 #define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
8283 #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1                                                               0x12ea
8284 #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2                                                               0x12eb
8285 #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3                                                               0x12ec
8286 #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2                                                           0x12ed
8287 #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3                                                           0x12ee
8288 #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4                                                           0x12ef
8289 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1                                                               0x12f0
8290 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2                                                               0x12f1
8291 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES                                                             0x12f2
8292 #define ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
8293 #define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
8294 #define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
8295 #define ixDPCSSYS_CR3_LANE2_ANA_RX_SQ                                                                  0x12f6
8296 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1                                                                0x12f7
8297 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2                                                                0x12f8
8298 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
8299 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
8300 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
8301 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
8302 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
8303 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
8304 #define ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1                                                           0x12ff
8305 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
8306 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
8307 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
8308 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
8309 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
8310 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
8311 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
8312 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
8313 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
8314 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
8315 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
8316 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
8317 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
8318 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
8319 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
8320 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
8321 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
8322 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
8323 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
8324 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
8325 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
8326 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
8327 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
8328 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
8329 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
8330 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
8331 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
8332 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
8333 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
8334 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
8335 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
8336 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
8337 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
8338 #define ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
8339 #define ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
8340 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
8341 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
8342 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
8343 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
8344 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
8345 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
8346 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
8347 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
8348 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
8349 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
8350 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
8351 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
8352 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
8353 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
8354 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
8355 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
8356 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
8357 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
8358 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
8359 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
8360 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
8361 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
8362 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
8363 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
8364 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
8365 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
8366 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
8367 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
8368 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
8369 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
8370 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
8371 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
8372 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
8373 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
8374 #define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
8375 #define ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
8376 #define ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
8377 #define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1                                                                0x13e3
8378 #define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2                                                                0x13e4
8379 #define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
8380 #define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
8381 #define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
8382 #define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
8383 #define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
8384 #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1                                                               0x13ea
8385 #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2                                                               0x13eb
8386 #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3                                                               0x13ec
8387 #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2                                                           0x13ed
8388 #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3                                                           0x13ee
8389 #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4                                                           0x13ef
8390 #define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL                                                               0x2000
8391 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
8392 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
8393 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
8394 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
8395 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
8396 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
8397 #define ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
8398 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
8399 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
8400 #define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
8401 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
8402 #define ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
8403 #define ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
8404 #define ixDPCSSYS_CR3_RAWCMN_DIG_OCLA                                                                  0x200e
8405 #define ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
8406 #define ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
8407 #define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
8408 #define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
8409 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
8410 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
8411 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
8412 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
8413 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
8414 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
8415 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
8416 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
8417 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
8418 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
8419 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
8420 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
8421 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
8422 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
8423 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
8424 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
8425 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
8426 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
8427 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
8428 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
8429 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
8430 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
8431 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
8432 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
8433 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
8434 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
8435 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
8436 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
8437 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
8438 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
8439 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
8440 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
8441 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
8442 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
8443 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
8444 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
8445 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
8446 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
8447 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
8448 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
8449 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
8450 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
8451 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
8452 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
8453 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
8454 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
8455 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
8456 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
8457 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
8458 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
8459 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
8460 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
8461 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
8462 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
8463 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
8464 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
8465 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
8466 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
8467 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
8468 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
8469 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
8470 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
8471 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
8472 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
8473 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
8474 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
8475 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
8476 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
8477 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
8478 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
8479 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
8480 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
8481 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
8482 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
8483 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
8484 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
8485 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
8486 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
8487 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
8488 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
8489 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
8490 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
8491 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
8492 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
8493 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
8494 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
8495 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
8496 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
8497 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
8498 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
8499 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
8500 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
8501 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
8502 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
8503 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
8504 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
8505 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
8506 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
8507 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
8508 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
8509 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
8510 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
8511 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
8512 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
8513 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
8514 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
8515 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
8516 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
8517 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
8518 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
8519 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
8520 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
8521 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
8522 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
8523 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
8524 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
8525 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
8526 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
8527 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
8528 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
8529 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
8530 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
8531 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
8532 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
8533 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
8534 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
8535 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
8536 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
8537 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
8538 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
8539 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
8540 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
8541 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
8542 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
8543 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
8544 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
8545 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
8546 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
8547 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
8548 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
8549 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
8550 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
8551 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
8552 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
8553 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
8554 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
8555 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
8556 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
8557 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
8558 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
8559 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
8560 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
8561 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
8562 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
8563 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
8564 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
8565 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
8566 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
8567 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
8568 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
8569 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
8570 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
8571 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
8572 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
8573 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
8574 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
8575 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
8576 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
8577 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
8578 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
8579 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
8580 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
8581 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
8582 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
8583 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
8584 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
8585 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
8586 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
8587 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
8588 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
8589 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
8590 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
8591 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
8592 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
8593 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
8594 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
8595 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
8596 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
8597 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
8598 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
8599 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
8600 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
8601 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
8602 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
8603 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
8604 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
8605 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
8606 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
8607 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
8608 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
8609 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
8610 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
8611 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
8612 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
8613 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
8614 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
8615 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
8616 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
8617 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
8618 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
8619 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
8620 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
8621 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
8622 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
8623 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
8624 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
8625 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
8626 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
8627 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
8628 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
8629 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
8630 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
8631 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
8632 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
8633 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
8634 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
8635 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
8636 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
8637 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
8638 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
8639 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
8640 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
8641 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
8642 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
8643 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
8644 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
8645 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
8646 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
8647 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
8648 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
8649 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
8650 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
8651 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
8652 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
8653 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
8654 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
8655 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
8656 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
8657 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
8658 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
8659 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
8660 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
8661 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
8662 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
8663 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
8664 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
8665 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
8666 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
8667 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
8668 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
8669 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
8670 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
8671 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
8672 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
8673 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
8674 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
8675 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
8676 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
8677 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
8678 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
8679 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
8680 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
8681 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
8682 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
8683 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
8684 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
8685 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
8686 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
8687 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
8688 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
8689 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
8690 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
8691 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
8692 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
8693 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
8694 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
8695 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
8696 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
8697 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
8698 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
8699 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
8700 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
8701 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
8702 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
8703 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
8704 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
8705 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
8706 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
8707 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
8708 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
8709 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
8710 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
8711 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
8712 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
8713 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
8714 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
8715 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
8716 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
8717 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
8718 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
8719 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
8720 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
8721 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
8722 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
8723 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
8724 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
8725 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
8726 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
8727 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
8728 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
8729 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
8730 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
8731 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
8732 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
8733 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
8734 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
8735 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
8736 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
8737 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
8738 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
8739 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
8740 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
8741 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
8742 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
8743 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
8744 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
8745 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
8746 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
8747 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
8748 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
8749 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
8750 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
8751 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
8752 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
8753 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
8754 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
8755 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
8756 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
8757 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
8758 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
8759 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
8760 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
8761 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
8762 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
8763 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
8764 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
8765 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
8766 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
8767 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
8768 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
8769 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
8770 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
8771 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
8772 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
8773 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
8774 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
8775 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
8776 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
8777 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
8778 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
8779 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
8780 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
8781 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
8782 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
8783 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
8784 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
8785 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
8786 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
8787 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
8788 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
8789 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
8790 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
8791 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
8792 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
8793 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
8794 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
8795 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
8796 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
8797 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
8798 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
8799 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
8800 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
8801 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
8802 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
8803 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
8804 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
8805 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
8806 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
8807 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
8808 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
8809 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
8810 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
8811 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
8812 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
8813 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
8814 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
8815 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
8816 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
8817 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
8818 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
8819 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
8820 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
8821 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
8822 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
8823 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
8824 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
8825 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
8826 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
8827 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
8828 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
8829 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
8830 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
8831 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
8832 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
8833 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
8834 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
8835 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
8836 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
8837 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
8838 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
8839 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
8840 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
8841 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
8842 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
8843 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
8844 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
8845 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
8846 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
8847 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
8848 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
8849 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
8850 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
8851 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
8852 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
8853 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
8854 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
8855 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
8856 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
8857 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
8858 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
8859 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
8860 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
8861 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
8862 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
8863 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
8864 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
8865 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
8866 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
8867 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
8868 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
8869 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
8870 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
8871 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
8872 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
8873 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
8874 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
8875 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
8876 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
8877 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
8878 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
8879 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
8880 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
8881 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
8882 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
8883 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
8884 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
8885 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
8886 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
8887 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
8888 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
8889 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
8890 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
8891 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
8892 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
8893 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
8894 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
8895 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
8896 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
8897 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
8898 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
8899 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
8900 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
8901 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
8902 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
8903 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
8904 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
8905 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
8906 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
8907 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
8908 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
8909 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
8910 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
8911 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
8912 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
8913 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
8914 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
8915 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
8916 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
8917 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
8918 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
8919 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
8920 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
8921 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
8922 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
8923 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
8924 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
8925 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
8926 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
8927 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
8928 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
8929 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
8930 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
8931 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
8932 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
8933 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
8934 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
8935 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
8936 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
8937 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
8938 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
8939 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
8940 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
8941 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
8942 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
8943 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
8944 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
8945 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
8946 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
8947 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
8948 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
8949 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
8950 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
8951 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
8952 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
8953 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
8954 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
8955 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
8956 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
8957 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
8958 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
8959 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
8960 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
8961 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
8962 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
8963 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
8964 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
8965 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
8966 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
8967 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
8968 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
8969 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
8970 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
8971 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
8972 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
8973 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
8974 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
8975 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
8976 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
8977 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
8978 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
8979 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
8980 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
8981 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
8982 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
8983 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
8984 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
8985 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
8986 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
8987 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
8988 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
8989 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
8990 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
8991 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
8992 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS                                                            0x4032
8993 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
8994 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
8995 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
8996 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
8997 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
8998 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
8999 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
9000 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
9001 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
9002 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
9003 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
9004 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
9005 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
9006 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
9007 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
9008 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
9009 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
9010 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
9011 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
9012 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
9013 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
9014 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
9015 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
9016 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
9017 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
9018 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
9019 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
9020 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
9021 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
9022 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
9023 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
9024 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
9025 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
9026 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
9027 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
9028 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
9029 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
9030 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
9031 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
9032 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
9033 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
9034 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
9035 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
9036 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
9037 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
9038 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
9039 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
9040 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
9041 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
9042 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
9043 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
9044 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
9045 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
9046 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
9047 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
9048 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
9049 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
9050 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
9051 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
9052 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
9053 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
9054 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
9055 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
9056 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
9057 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
9058 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
9059 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
9060 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
9061 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
9062 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
9063 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
9064 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
9065 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
9066 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
9067 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
9068 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
9069 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
9070 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
9071 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
9072 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
9073 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
9074 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS                                                            0x4132
9075 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
9076 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
9077 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
9078 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
9079 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
9080 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
9081 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
9082 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
9083 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
9084 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
9085 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
9086 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
9087 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
9088 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
9089 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
9090 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
9091 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
9092 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
9093 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
9094 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
9095 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
9096 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
9097 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
9098 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
9099 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
9100 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
9101 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
9102 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
9103 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
9104 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
9105 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
9106 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
9107 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
9108 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
9109 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
9110 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
9111 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
9112 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
9113 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
9114 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
9115 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
9116 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
9117 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
9118 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
9119 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
9120 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
9121 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
9122 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
9123 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
9124 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
9125 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
9126 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
9127 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
9128 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
9129 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
9130 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
9131 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
9132 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
9133 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
9134 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
9135 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
9136 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
9137 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
9138 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
9139 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
9140 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
9141 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
9142 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
9143 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
9144 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
9145 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
9146 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
9147 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
9148 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
9149 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
9150 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
9151 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
9152 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
9153 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
9154 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
9155 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
9156 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS                                                            0x4232
9157 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
9158 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
9159 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
9160 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
9161 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
9162 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
9163 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
9164 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
9165 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
9166 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
9167 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
9168 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
9169 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
9170 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
9171 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
9172 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
9173 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
9174 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
9175 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
9176 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
9177 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
9178 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
9179 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
9180 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
9181 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
9182 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
9183 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
9184 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
9185 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
9186 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
9187 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
9188 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
9189 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
9190 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
9191 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
9192 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
9193 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
9194 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
9195 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
9196 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
9197 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
9198 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
9199 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
9200 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
9201 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
9202 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
9203 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
9204 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
9205 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
9206 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
9207 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
9208 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
9209 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
9210 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
9211 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
9212 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
9213 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
9214 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
9215 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
9216 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
9217 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
9218 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
9219 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
9220 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
9221 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
9222 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
9223 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
9224 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
9225 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
9226 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
9227 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
9228 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
9229 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
9230 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
9231 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
9232 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
9233 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
9234 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
9235 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
9236 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
9237 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
9238 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS                                                            0x4332
9239 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
9240 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
9241 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
9242 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
9243 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
9244 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
9245 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
9246 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
9247 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
9248 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
9249 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
9250 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
9251 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
9252 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
9253 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
9254 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
9255 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
9256 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
9257 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
9258 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
9259 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
9260 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
9261 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
9262 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
9263 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
9264 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
9265 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
9266 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
9267 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
9268 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
9269 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
9270 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
9271 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
9272 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
9273 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
9274 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
9275 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
9276 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
9277 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
9278 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
9279 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
9280 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
9281 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
9282 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
9283 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
9284 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
9285 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
9286 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
9287 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
9288 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
9289 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
9290 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
9291 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
9292 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
9293 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
9294 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
9295 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
9296 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
9297 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
9298 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
9299 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
9300 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
9301 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
9302 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
9303 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
9304 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
9305 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
9306 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
9307 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
9308 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
9309 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
9310 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
9311 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
9312 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
9313 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
9314 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
9315 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
9316 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
9317 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
9318 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
9319 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
9320 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS                                                            0x7032
9321 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
9322 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
9323 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
9324 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
9325 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
9326 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
9327 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
9328 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
9329 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
9330 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
9331 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
9332 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
9333 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
9334 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
9335 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
9336 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
9337 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
9338 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
9339 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
9340 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
9341 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
9342 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
9343 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
9344 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
9345 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
9346 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
9347 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
9348 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
9349 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
9350 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
9351 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
9352 #define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO                                                               0x8000
9353 #define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI                                                               0x8001
9354 #define ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
9355 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
9356 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
9357 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
9358 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
9359 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
9360 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
9361 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
9362 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
9363 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
9364 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
9365 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
9366 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
9367 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
9368 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
9369 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
9370 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
9371 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
9372 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
9373 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
9374 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
9375 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
9376 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
9377 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
9378 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
9379 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
9380 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
9381 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
9382 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
9383 #define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
9384 #define ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
9385 #define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
9386 #define ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
9387 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
9388 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
9389 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
9390 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
9391 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
9392 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
9393 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
9394 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
9395 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
9396 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
9397 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
9398 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
9399 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
9400 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
9401 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
9402 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
9403 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
9404 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
9405 #define ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN                                                                 0x8036
9406 #define ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
9407 #define ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
9408 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
9409 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
9410 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
9411 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
9412 #define ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
9413 #define ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL                                                              0x8041
9414 #define ixDPCSSYS_CR3_SUPX_ANA_BG1                                                                     0x8042
9415 #define ixDPCSSYS_CR3_SUPX_ANA_BG2                                                                     0x8043
9416 #define ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
9417 #define ixDPCSSYS_CR3_SUPX_ANA_BG3                                                                     0x8045
9418 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1                                                             0x8046
9419 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2                                                             0x8047
9420 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD                                                              0x8048
9421 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1                                                              0x8049
9422 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2                                                              0x804a
9423 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3                                                              0x804b
9424 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1                                                              0x804c
9425 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2                                                              0x804d
9426 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3                                                              0x804e
9427 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4                                                              0x804f
9428 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5                                                              0x8050
9429 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
9430 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
9431 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1                                                             0x8053
9432 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2                                                             0x8054
9433 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD                                                              0x8055
9434 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1                                                              0x8056
9435 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2                                                              0x8057
9436 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3                                                              0x8058
9437 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1                                                              0x8059
9438 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2                                                              0x805a
9439 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3                                                              0x805b
9440 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4                                                              0x805c
9441 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5                                                              0x805d
9442 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
9443 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
9444 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
9445 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
9446 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
9447 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
9448 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
9449 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
9450 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
9451 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
9452 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
9453 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
9454 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
9455 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
9456 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
9457 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
9458 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
9459 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
9460 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
9461 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
9462 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
9463 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
9464 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
9465 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
9466 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
9467 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
9468 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
9469 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
9470 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT                                                              0x8082
9471 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
9472 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
9473 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
9474 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
9475 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
9476 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
9477 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
9478 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
9479 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
9480 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
9481 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
9482 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
9483 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
9484 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
9485 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
9486 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
9487 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT                                                                0x8093
9488 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
9489 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
9490 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
9491 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
9492 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
9493 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
9494 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
9495 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
9496 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
9497 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
9498 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
9499 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
9500 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
9501 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
9502 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
9503 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
9504 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
9505 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
9506 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
9507 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
9508 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
9509 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
9510 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
9511 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
9512 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
9513 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
9514 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
9515 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
9516 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
9517 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
9518 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
9519 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
9520 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
9521 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
9522 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA                                                              0x901f
9523 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
9524 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
9525 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
9526 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
9527 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
9528 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
9529 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
9530 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
9531 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
9532 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
9533 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
9534 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
9535 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
9536 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
9537 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
9538 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
9539 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
9540 #define ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
9541 #define ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
9542 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
9543 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
9544 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
9545 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
9546 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
9547 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
9548 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
9549 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
9550 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
9551 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
9552 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
9553 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
9554 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
9555 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
9556 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
9557 #define ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
9558 #define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
9559 #define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
9560 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
9561 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
9562 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
9563 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
9564 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
9565 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT                                                            0x9058
9566 #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
9567 #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
9568 #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
9569 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
9570 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
9571 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
9572 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
9573 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
9574 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
9575 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
9576 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
9577 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
9578 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
9579 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
9580 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
9581 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
9582 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
9583 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
9584 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
9585 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
9586 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
9587 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
9588 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
9589 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
9590 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
9591 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
9592 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
9593 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
9594 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
9595 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
9596 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
9597 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
9598 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
9599 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
9600 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
9601 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
9602 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
9603 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
9604 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
9605 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
9606 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
9607 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
9608 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
9609 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
9610 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
9611 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
9612 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
9613 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
9614 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
9615 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
9616 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
9617 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
9618 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
9619 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
9620 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
9621 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
9622 #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
9623 #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
9624 #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
9625 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
9626 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
9627 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
9628 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
9629 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
9630 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
9631 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
9632 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
9633 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
9634 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
9635 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
9636 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
9637 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
9638 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
9639 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
9640 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
9641 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
9642 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
9643 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
9644 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
9645 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
9646 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
9647 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
9648 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
9649 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
9650 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
9651 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
9652 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
9653 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
9654 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
9655 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
9656 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
9657 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
9658 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
9659 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
9660 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
9661 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
9662 #define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
9663 #define ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
9664 #define ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
9665 #define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1                                                                0x90e3
9666 #define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2                                                                0x90e4
9667 #define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
9668 #define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
9669 #define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
9670 #define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
9671 #define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
9672 #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1                                                               0x90ea
9673 #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2                                                               0x90eb
9674 #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3                                                               0x90ec
9675 #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2                                                           0x90ed
9676 #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3                                                           0x90ee
9677 #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4                                                           0x90ef
9678 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1                                                               0x90f0
9679 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2                                                               0x90f1
9680 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES                                                             0x90f2
9681 #define ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
9682 #define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
9683 #define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
9684 #define ixDPCSSYS_CR3_LANEX_ANA_RX_SQ                                                                  0x90f6
9685 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1                                                                0x90f7
9686 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2                                                                0x90f8
9687 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
9688 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
9689 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
9690 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
9691 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
9692 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
9693 #define ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1                                                           0x90ff
9694 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
9695 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
9696 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
9697 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
9698 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
9699 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
9700 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
9701 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
9702 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
9703 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
9704 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
9705 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
9706 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
9707 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
9708 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
9709 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
9710 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
9711 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
9712 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
9713 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
9714 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
9715 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
9716 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
9717 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
9718 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
9719 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
9720 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
9721 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
9722 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
9723 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
9724 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
9725 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
9726 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
9727 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
9728 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
9729 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
9730 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
9731 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
9732 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
9733 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
9734 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
9735 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
9736 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
9737 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
9738 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
9739 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
9740 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
9741 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
9742 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
9743 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
9744 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
9745 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
9746 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
9747 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
9748 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
9749 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
9750 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
9751 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
9752 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
9753 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
9754 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
9755 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
9756 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
9757 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
9758 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
9759 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
9760 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
9761 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
9762 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
9763 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
9764 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
9765 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
9766 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
9767 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
9768 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
9769 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
9770 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
9771 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
9772 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
9773 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
9774 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
9775 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
9776 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
9777 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
9778 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
9779 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
9780 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
9781 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
9782 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
9783 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
9784 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
9785 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
9786 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
9787 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
9788 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
9789 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
9790 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
9791 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
9792 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
9793 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
9794 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
9795 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
9796 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
9797 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
9798 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
9799 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
9800 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
9801 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
9802 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
9803 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
9804 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
9805 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
9806 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
9807 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
9808 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
9809 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
9810 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
9811 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
9812 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
9813 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
9814 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
9815 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
9816 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
9817 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
9818 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
9819 
9820 
9821 // addressBlock: dpcssys_cr4_rdpcstxcrind
9822 // base address: 0x0
9823 #define ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO                                                                0x0000
9824 #define ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI                                                                0x0001
9825 #define ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
9826 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
9827 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
9828 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
9829 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
9830 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
9831 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
9832 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
9833 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
9834 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
9835 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
9836 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
9837 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
9838 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
9839 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
9840 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
9841 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
9842 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
9843 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
9844 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
9845 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
9846 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
9847 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
9848 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
9849 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
9850 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
9851 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
9852 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
9853 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
9854 #define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN                                                              0x001f
9855 #define ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
9856 #define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
9857 #define ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN                                                              0x0022
9858 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
9859 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
9860 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
9861 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
9862 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
9863 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
9864 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
9865 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
9866 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
9867 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
9868 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
9869 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
9870 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
9871 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
9872 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
9873 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
9874 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
9875 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
9876 #define ixDPCSSYS_CR4_SUP_DIG_ASIC_IN                                                                  0x0036
9877 #define ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN                                                              0x0037
9878 #define ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
9879 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
9880 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
9881 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
9882 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
9883 #define ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL                                                           0x0040
9884 #define ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL                                                               0x0041
9885 #define ixDPCSSYS_CR4_SUP_ANA_BG1                                                                      0x0042
9886 #define ixDPCSSYS_CR4_SUP_ANA_BG2                                                                      0x0043
9887 #define ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
9888 #define ixDPCSSYS_CR4_SUP_ANA_BG3                                                                      0x0045
9889 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1                                                              0x0046
9890 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2                                                              0x0047
9891 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD                                                               0x0048
9892 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1                                                               0x0049
9893 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2                                                               0x004a
9894 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3                                                               0x004b
9895 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1                                                               0x004c
9896 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2                                                               0x004d
9897 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3                                                               0x004e
9898 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4                                                               0x004f
9899 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5                                                               0x0050
9900 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
9901 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
9902 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1                                                              0x0053
9903 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2                                                              0x0054
9904 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD                                                               0x0055
9905 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1                                                               0x0056
9906 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2                                                               0x0057
9907 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3                                                               0x0058
9908 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1                                                               0x0059
9909 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2                                                               0x005a
9910 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3                                                               0x005b
9911 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4                                                               0x005c
9912 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5                                                               0x005d
9913 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
9914 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
9915 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
9916 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
9917 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
9918 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
9919 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
9920 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
9921 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
9922 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
9923 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
9924 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
9925 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
9926 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
9927 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
9928 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
9929 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
9930 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
9931 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
9932 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
9933 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
9934 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
9935 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
9936 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
9937 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
9938 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
9939 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
9940 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG                                                             0x0081
9941 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT                                                               0x0082
9942 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
9943 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
9944 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
9945 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
9946 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
9947 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
9948 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
9949 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
9950 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
9951 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
9952 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
9953 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
9954 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
9955 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
9956 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
9957 #define ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
9958 #define ixDPCSSYS_CR4_SUP_DIG_ANA_STAT                                                                 0x0093
9959 #define ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
9960 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
9961 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
9962 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
9963 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
9964 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
9965 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
9966 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
9967 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
9968 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
9969 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
9970 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
9971 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
9972 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
9973 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
9974 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
9975 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
9976 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
9977 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
9978 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
9979 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
9980 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
9981 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
9982 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
9983 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
9984 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
9985 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
9986 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
9987 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
9988 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
9989 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
9990 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
9991 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
9992 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
9993 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
9994 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
9995 #define ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
9996 #define ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
9997 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
9998 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
9999 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
10000 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
10001 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
10002 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
10003 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
10004 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
10005 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
10006 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
10007 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
10008 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
10009 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
10010 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
10011 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
10012 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
10013 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
10014 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
10015 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
10016 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
10017 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
10018 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
10019 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
10020 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
10021 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
10022 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
10023 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
10024 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
10025 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
10026 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
10027 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
10028 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
10029 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
10030 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
10031 #define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
10032 #define ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
10033 #define ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
10034 #define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1                                                                0x10e3
10035 #define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2                                                                0x10e4
10036 #define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
10037 #define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
10038 #define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
10039 #define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
10040 #define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
10041 #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1                                                               0x10ea
10042 #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2                                                               0x10eb
10043 #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3                                                               0x10ec
10044 #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2                                                           0x10ed
10045 #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3                                                           0x10ee
10046 #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4                                                           0x10ef
10047 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
10048 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
10049 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
10050 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
10051 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
10052 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
10053 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
10054 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
10055 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
10056 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
10057 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
10058 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
10059 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
10060 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
10061 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
10062 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
10063 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
10064 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
10065 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
10066 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
10067 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
10068 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
10069 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
10070 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
10071 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
10072 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
10073 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
10074 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
10075 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
10076 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
10077 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
10078 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA                                                              0x111f
10079 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
10080 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
10081 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
10082 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
10083 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
10084 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
10085 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
10086 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
10087 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
10088 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
10089 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
10090 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
10091 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
10092 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
10093 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
10094 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
10095 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
10096 #define ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
10097 #define ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
10098 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
10099 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
10100 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
10101 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
10102 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
10103 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
10104 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
10105 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
10106 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
10107 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
10108 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
10109 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
10110 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
10111 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
10112 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
10113 #define ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
10114 #define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
10115 #define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
10116 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
10117 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
10118 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
10119 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
10120 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
10121 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT                                                            0x1158
10122 #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
10123 #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
10124 #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
10125 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
10126 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
10127 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
10128 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
10129 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
10130 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
10131 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
10132 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
10133 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
10134 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
10135 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
10136 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
10137 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
10138 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
10139 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
10140 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
10141 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
10142 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
10143 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
10144 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
10145 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
10146 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
10147 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
10148 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
10149 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
10150 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
10151 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
10152 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
10153 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
10154 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
10155 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
10156 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
10157 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
10158 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
10159 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
10160 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
10161 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
10162 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
10163 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
10164 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
10165 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
10166 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
10167 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
10168 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
10169 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
10170 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
10171 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
10172 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
10173 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
10174 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
10175 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
10176 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
10177 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
10178 #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
10179 #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
10180 #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
10181 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
10182 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
10183 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
10184 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
10185 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
10186 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
10187 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
10188 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
10189 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
10190 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
10191 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
10192 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
10193 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
10194 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
10195 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
10196 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
10197 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
10198 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
10199 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
10200 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
10201 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
10202 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
10203 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
10204 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
10205 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
10206 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
10207 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
10208 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
10209 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
10210 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
10211 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
10212 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
10213 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
10214 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
10215 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
10216 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
10217 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
10218 #define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
10219 #define ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
10220 #define ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
10221 #define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1                                                                0x11e3
10222 #define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2                                                                0x11e4
10223 #define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
10224 #define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
10225 #define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
10226 #define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
10227 #define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
10228 #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1                                                               0x11ea
10229 #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2                                                               0x11eb
10230 #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3                                                               0x11ec
10231 #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2                                                           0x11ed
10232 #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3                                                           0x11ee
10233 #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4                                                           0x11ef
10234 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1                                                               0x11f0
10235 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2                                                               0x11f1
10236 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES                                                             0x11f2
10237 #define ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
10238 #define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
10239 #define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
10240 #define ixDPCSSYS_CR4_LANE1_ANA_RX_SQ                                                                  0x11f6
10241 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1                                                                0x11f7
10242 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2                                                                0x11f8
10243 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
10244 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
10245 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
10246 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
10247 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
10248 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
10249 #define ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1                                                           0x11ff
10250 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
10251 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
10252 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
10253 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
10254 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
10255 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
10256 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
10257 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
10258 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
10259 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
10260 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
10261 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
10262 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
10263 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
10264 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
10265 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
10266 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
10267 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
10268 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
10269 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
10270 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
10271 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
10272 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
10273 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
10274 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
10275 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
10276 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
10277 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
10278 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
10279 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
10280 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
10281 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA                                                              0x121f
10282 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
10283 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
10284 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
10285 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
10286 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
10287 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
10288 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
10289 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
10290 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
10291 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
10292 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
10293 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
10294 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
10295 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
10296 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
10297 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
10298 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
10299 #define ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
10300 #define ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
10301 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
10302 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
10303 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
10304 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
10305 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
10306 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
10307 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
10308 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
10309 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
10310 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
10311 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
10312 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
10313 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
10314 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
10315 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
10316 #define ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
10317 #define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
10318 #define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
10319 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
10320 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
10321 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
10322 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
10323 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
10324 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT                                                            0x1258
10325 #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
10326 #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
10327 #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
10328 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
10329 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
10330 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
10331 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
10332 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
10333 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
10334 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
10335 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
10336 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
10337 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
10338 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
10339 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
10340 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
10341 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
10342 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
10343 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
10344 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
10345 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
10346 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
10347 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
10348 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
10349 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
10350 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
10351 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
10352 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
10353 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
10354 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
10355 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
10356 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
10357 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
10358 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
10359 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
10360 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
10361 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
10362 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
10363 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
10364 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
10365 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
10366 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
10367 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
10368 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
10369 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
10370 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
10371 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
10372 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
10373 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
10374 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
10375 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
10376 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
10377 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
10378 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
10379 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
10380 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
10381 #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
10382 #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
10383 #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
10384 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
10385 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
10386 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
10387 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
10388 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
10389 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
10390 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
10391 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
10392 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
10393 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
10394 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
10395 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
10396 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
10397 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
10398 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
10399 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
10400 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
10401 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
10402 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
10403 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
10404 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
10405 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
10406 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
10407 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
10408 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
10409 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
10410 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
10411 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
10412 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
10413 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
10414 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
10415 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
10416 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
10417 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
10418 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
10419 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
10420 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
10421 #define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
10422 #define ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
10423 #define ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
10424 #define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1                                                                0x12e3
10425 #define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2                                                                0x12e4
10426 #define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
10427 #define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
10428 #define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
10429 #define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
10430 #define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
10431 #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1                                                               0x12ea
10432 #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2                                                               0x12eb
10433 #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3                                                               0x12ec
10434 #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2                                                           0x12ed
10435 #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3                                                           0x12ee
10436 #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4                                                           0x12ef
10437 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1                                                               0x12f0
10438 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2                                                               0x12f1
10439 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES                                                             0x12f2
10440 #define ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
10441 #define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
10442 #define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
10443 #define ixDPCSSYS_CR4_LANE2_ANA_RX_SQ                                                                  0x12f6
10444 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1                                                                0x12f7
10445 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2                                                                0x12f8
10446 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
10447 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
10448 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
10449 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
10450 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
10451 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
10452 #define ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1                                                           0x12ff
10453 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
10454 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
10455 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
10456 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
10457 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
10458 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
10459 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
10460 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
10461 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
10462 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
10463 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
10464 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
10465 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
10466 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
10467 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
10468 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
10469 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
10470 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
10471 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
10472 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
10473 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
10474 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
10475 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
10476 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
10477 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
10478 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
10479 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
10480 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
10481 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
10482 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
10483 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
10484 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
10485 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
10486 #define ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
10487 #define ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
10488 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
10489 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
10490 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
10491 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
10492 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
10493 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
10494 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
10495 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
10496 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
10497 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
10498 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
10499 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
10500 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
10501 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
10502 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
10503 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
10504 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
10505 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
10506 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
10507 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
10508 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
10509 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
10510 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
10511 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
10512 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
10513 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
10514 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
10515 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
10516 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
10517 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
10518 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
10519 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
10520 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
10521 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
10522 #define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
10523 #define ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
10524 #define ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
10525 #define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1                                                                0x13e3
10526 #define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2                                                                0x13e4
10527 #define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
10528 #define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
10529 #define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
10530 #define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
10531 #define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
10532 #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1                                                               0x13ea
10533 #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2                                                               0x13eb
10534 #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3                                                               0x13ec
10535 #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2                                                           0x13ed
10536 #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3                                                           0x13ee
10537 #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4                                                           0x13ef
10538 #define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL                                                               0x2000
10539 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
10540 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
10541 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
10542 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
10543 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
10544 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
10545 #define ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
10546 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
10547 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
10548 #define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
10549 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
10550 #define ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
10551 #define ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
10552 #define ixDPCSSYS_CR4_RAWCMN_DIG_OCLA                                                                  0x200e
10553 #define ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
10554 #define ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
10555 #define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
10556 #define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
10557 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
10558 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
10559 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
10560 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
10561 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
10562 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
10563 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
10564 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
10565 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
10566 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
10567 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
10568 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
10569 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
10570 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
10571 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
10572 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
10573 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
10574 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
10575 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
10576 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
10577 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
10578 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
10579 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
10580 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
10581 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
10582 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
10583 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
10584 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
10585 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
10586 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
10587 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
10588 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
10589 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
10590 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
10591 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
10592 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
10593 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
10594 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
10595 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
10596 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
10597 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
10598 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
10599 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
10600 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
10601 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
10602 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
10603 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
10604 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
10605 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
10606 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
10607 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
10608 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
10609 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
10610 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
10611 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
10612 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
10613 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
10614 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
10615 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
10616 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
10617 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
10618 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
10619 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
10620 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
10621 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
10622 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
10623 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
10624 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
10625 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
10626 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
10627 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
10628 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
10629 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
10630 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
10631 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
10632 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
10633 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
10634 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
10635 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
10636 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
10637 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
10638 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
10639 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
10640 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
10641 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
10642 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
10643 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
10644 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
10645 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
10646 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
10647 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
10648 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
10649 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
10650 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
10651 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
10652 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
10653 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
10654 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
10655 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
10656 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
10657 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
10658 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
10659 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
10660 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
10661 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
10662 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
10663 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
10664 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
10665 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
10666 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
10667 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
10668 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
10669 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
10670 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
10671 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
10672 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
10673 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
10674 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
10675 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
10676 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
10677 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
10678 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
10679 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
10680 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
10681 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
10682 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
10683 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
10684 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
10685 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
10686 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
10687 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
10688 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
10689 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
10690 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
10691 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
10692 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
10693 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
10694 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
10695 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
10696 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
10697 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
10698 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
10699 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
10700 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
10701 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
10702 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
10703 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
10704 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
10705 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
10706 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
10707 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
10708 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
10709 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
10710 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
10711 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
10712 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
10713 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
10714 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
10715 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
10716 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
10717 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
10718 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
10719 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
10720 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
10721 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
10722 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
10723 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
10724 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
10725 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
10726 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
10727 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
10728 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
10729 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
10730 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
10731 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
10732 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
10733 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
10734 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
10735 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
10736 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
10737 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
10738 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
10739 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
10740 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
10741 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
10742 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
10743 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
10744 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
10745 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
10746 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
10747 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
10748 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
10749 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
10750 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
10751 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
10752 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
10753 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
10754 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
10755 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
10756 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
10757 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
10758 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
10759 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
10760 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
10761 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
10762 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
10763 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
10764 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
10765 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
10766 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
10767 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
10768 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
10769 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
10770 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
10771 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
10772 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
10773 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
10774 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
10775 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
10776 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
10777 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
10778 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
10779 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
10780 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
10781 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
10782 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
10783 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
10784 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
10785 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
10786 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
10787 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
10788 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
10789 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
10790 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
10791 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
10792 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
10793 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
10794 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
10795 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
10796 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
10797 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
10798 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
10799 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
10800 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
10801 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
10802 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
10803 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
10804 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
10805 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
10806 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
10807 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
10808 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
10809 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
10810 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
10811 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
10812 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
10813 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
10814 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
10815 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
10816 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
10817 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
10818 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
10819 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
10820 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
10821 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
10822 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
10823 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
10824 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
10825 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
10826 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
10827 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
10828 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
10829 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
10830 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
10831 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
10832 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
10833 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
10834 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
10835 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
10836 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
10837 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
10838 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
10839 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
10840 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
10841 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
10842 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
10843 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
10844 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
10845 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
10846 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
10847 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
10848 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
10849 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
10850 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
10851 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
10852 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
10853 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
10854 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
10855 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
10856 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
10857 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
10858 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
10859 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
10860 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
10861 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
10862 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
10863 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
10864 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
10865 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
10866 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
10867 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
10868 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
10869 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
10870 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
10871 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
10872 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
10873 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
10874 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
10875 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
10876 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
10877 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
10878 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
10879 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
10880 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
10881 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
10882 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
10883 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
10884 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
10885 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
10886 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
10887 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
10888 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
10889 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
10890 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
10891 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
10892 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
10893 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
10894 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
10895 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
10896 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
10897 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
10898 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
10899 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
10900 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
10901 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
10902 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
10903 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
10904 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
10905 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
10906 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
10907 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
10908 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
10909 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
10910 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
10911 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
10912 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
10913 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
10914 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
10915 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
10916 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
10917 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
10918 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
10919 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
10920 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
10921 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
10922 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
10923 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
10924 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
10925 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
10926 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
10927 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
10928 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
10929 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
10930 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
10931 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
10932 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
10933 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
10934 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
10935 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
10936 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
10937 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
10938 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
10939 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
10940 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
10941 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
10942 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
10943 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
10944 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
10945 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
10946 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
10947 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
10948 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
10949 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
10950 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
10951 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
10952 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
10953 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
10954 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
10955 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
10956 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
10957 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
10958 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
10959 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
10960 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
10961 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
10962 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
10963 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
10964 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
10965 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
10966 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
10967 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
10968 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
10969 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
10970 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
10971 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
10972 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
10973 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
10974 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
10975 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
10976 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
10977 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
10978 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
10979 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
10980 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
10981 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
10982 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
10983 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
10984 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
10985 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
10986 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
10987 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
10988 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
10989 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
10990 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
10991 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
10992 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
10993 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
10994 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
10995 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
10996 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
10997 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
10998 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
10999 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
11000 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
11001 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
11002 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
11003 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
11004 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
11005 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
11006 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
11007 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
11008 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
11009 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
11010 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
11011 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
11012 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
11013 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
11014 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
11015 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
11016 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
11017 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
11018 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
11019 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
11020 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
11021 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
11022 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
11023 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
11024 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
11025 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
11026 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
11027 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
11028 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
11029 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
11030 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
11031 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
11032 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
11033 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
11034 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
11035 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
11036 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
11037 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
11038 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
11039 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
11040 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
11041 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
11042 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
11043 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
11044 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
11045 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
11046 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
11047 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
11048 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
11049 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
11050 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
11051 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
11052 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
11053 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
11054 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
11055 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
11056 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
11057 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
11058 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
11059 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
11060 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
11061 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
11062 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
11063 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
11064 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
11065 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
11066 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
11067 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
11068 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
11069 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
11070 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
11071 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
11072 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
11073 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
11074 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
11075 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
11076 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
11077 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
11078 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
11079 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
11080 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
11081 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
11082 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
11083 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
11084 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
11085 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
11086 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
11087 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
11088 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
11089 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
11090 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
11091 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
11092 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
11093 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
11094 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
11095 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
11096 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
11097 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
11098 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
11099 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
11100 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
11101 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
11102 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
11103 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
11104 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
11105 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
11106 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
11107 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
11108 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
11109 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
11110 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
11111 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
11112 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
11113 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
11114 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
11115 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
11116 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
11117 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
11118 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
11119 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
11120 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
11121 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
11122 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
11123 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
11124 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
11125 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
11126 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
11127 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
11128 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
11129 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
11130 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
11131 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
11132 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
11133 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
11134 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
11135 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
11136 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
11137 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
11138 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
11139 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
11140 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS                                                            0x4032
11141 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
11142 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
11143 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
11144 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
11145 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
11146 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
11147 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
11148 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
11149 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
11150 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
11151 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
11152 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
11153 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
11154 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
11155 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
11156 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
11157 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
11158 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
11159 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
11160 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
11161 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
11162 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
11163 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
11164 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
11165 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
11166 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
11167 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
11168 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
11169 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
11170 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
11171 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
11172 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
11173 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
11174 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
11175 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
11176 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
11177 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
11178 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
11179 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
11180 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
11181 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
11182 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
11183 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
11184 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
11185 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
11186 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
11187 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
11188 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
11189 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
11190 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
11191 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
11192 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
11193 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
11194 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
11195 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
11196 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
11197 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
11198 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
11199 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
11200 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
11201 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
11202 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
11203 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
11204 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
11205 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
11206 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
11207 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
11208 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
11209 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
11210 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
11211 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
11212 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
11213 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
11214 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
11215 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
11216 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
11217 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
11218 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
11219 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
11220 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
11221 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
11222 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS                                                            0x4132
11223 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
11224 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
11225 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
11226 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
11227 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
11228 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
11229 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
11230 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
11231 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
11232 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
11233 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
11234 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
11235 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
11236 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
11237 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
11238 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
11239 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
11240 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
11241 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
11242 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
11243 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
11244 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
11245 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
11246 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
11247 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
11248 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
11249 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
11250 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
11251 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
11252 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
11253 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
11254 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
11255 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
11256 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
11257 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
11258 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
11259 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
11260 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
11261 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
11262 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
11263 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
11264 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
11265 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
11266 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
11267 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
11268 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
11269 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
11270 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
11271 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
11272 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
11273 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
11274 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
11275 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
11276 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
11277 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
11278 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
11279 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
11280 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
11281 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
11282 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
11283 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
11284 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
11285 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
11286 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
11287 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
11288 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
11289 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
11290 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
11291 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
11292 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
11293 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
11294 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
11295 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
11296 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
11297 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
11298 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
11299 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
11300 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
11301 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
11302 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
11303 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
11304 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS                                                            0x4232
11305 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
11306 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
11307 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
11308 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
11309 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
11310 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
11311 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
11312 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
11313 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
11314 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
11315 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
11316 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
11317 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
11318 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
11319 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
11320 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
11321 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
11322 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
11323 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
11324 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
11325 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
11326 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
11327 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
11328 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
11329 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
11330 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
11331 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
11332 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
11333 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
11334 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
11335 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
11336 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
11337 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
11338 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
11339 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
11340 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
11341 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
11342 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
11343 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
11344 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
11345 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
11346 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
11347 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
11348 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
11349 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
11350 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
11351 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
11352 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
11353 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
11354 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
11355 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
11356 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
11357 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
11358 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
11359 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
11360 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
11361 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
11362 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
11363 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
11364 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
11365 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
11366 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
11367 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
11368 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
11369 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
11370 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
11371 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
11372 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
11373 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
11374 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
11375 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
11376 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
11377 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
11378 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
11379 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
11380 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
11381 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
11382 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
11383 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
11384 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
11385 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
11386 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS                                                            0x4332
11387 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
11388 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
11389 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
11390 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
11391 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
11392 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
11393 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
11394 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
11395 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
11396 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
11397 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
11398 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
11399 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
11400 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
11401 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
11402 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
11403 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
11404 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
11405 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
11406 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
11407 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
11408 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
11409 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
11410 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
11411 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
11412 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
11413 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
11414 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
11415 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
11416 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
11417 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
11418 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
11419 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
11420 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
11421 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
11422 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
11423 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
11424 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
11425 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
11426 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
11427 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
11428 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
11429 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
11430 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
11431 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
11432 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
11433 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
11434 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
11435 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
11436 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
11437 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
11438 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
11439 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
11440 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
11441 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
11442 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
11443 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
11444 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
11445 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
11446 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
11447 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
11448 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
11449 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
11450 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
11451 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
11452 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
11453 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
11454 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
11455 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
11456 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
11457 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
11458 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
11459 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
11460 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
11461 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
11462 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
11463 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
11464 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
11465 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
11466 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
11467 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
11468 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS                                                            0x7032
11469 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
11470 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
11471 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
11472 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
11473 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
11474 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
11475 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
11476 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
11477 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
11478 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
11479 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
11480 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
11481 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
11482 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
11483 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
11484 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
11485 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
11486 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
11487 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
11488 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
11489 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
11490 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
11491 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
11492 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
11493 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
11494 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
11495 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
11496 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
11497 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
11498 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
11499 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
11500 #define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO                                                               0x8000
11501 #define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI                                                               0x8001
11502 #define ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
11503 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
11504 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
11505 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
11506 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
11507 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
11508 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
11509 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
11510 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
11511 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
11512 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
11513 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
11514 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
11515 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
11516 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
11517 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
11518 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
11519 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
11520 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
11521 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
11522 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
11523 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
11524 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
11525 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
11526 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
11527 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
11528 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
11529 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
11530 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
11531 #define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
11532 #define ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
11533 #define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
11534 #define ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
11535 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
11536 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
11537 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
11538 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
11539 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
11540 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
11541 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
11542 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
11543 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
11544 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
11545 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
11546 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
11547 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
11548 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
11549 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
11550 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
11551 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
11552 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
11553 #define ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN                                                                 0x8036
11554 #define ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
11555 #define ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
11556 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
11557 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
11558 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
11559 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
11560 #define ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
11561 #define ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL                                                              0x8041
11562 #define ixDPCSSYS_CR4_SUPX_ANA_BG1                                                                     0x8042
11563 #define ixDPCSSYS_CR4_SUPX_ANA_BG2                                                                     0x8043
11564 #define ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
11565 #define ixDPCSSYS_CR4_SUPX_ANA_BG3                                                                     0x8045
11566 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1                                                             0x8046
11567 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2                                                             0x8047
11568 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD                                                              0x8048
11569 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1                                                              0x8049
11570 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2                                                              0x804a
11571 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3                                                              0x804b
11572 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1                                                              0x804c
11573 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2                                                              0x804d
11574 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3                                                              0x804e
11575 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4                                                              0x804f
11576 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5                                                              0x8050
11577 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
11578 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
11579 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1                                                             0x8053
11580 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2                                                             0x8054
11581 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD                                                              0x8055
11582 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1                                                              0x8056
11583 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2                                                              0x8057
11584 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3                                                              0x8058
11585 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1                                                              0x8059
11586 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2                                                              0x805a
11587 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3                                                              0x805b
11588 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4                                                              0x805c
11589 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5                                                              0x805d
11590 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
11591 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
11592 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
11593 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
11594 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
11595 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
11596 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
11597 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
11598 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
11599 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
11600 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
11601 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
11602 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
11603 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
11604 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
11605 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
11606 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
11607 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
11608 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
11609 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
11610 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
11611 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
11612 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
11613 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
11614 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
11615 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
11616 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
11617 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
11618 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT                                                              0x8082
11619 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
11620 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
11621 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
11622 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
11623 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
11624 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
11625 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
11626 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
11627 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
11628 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
11629 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
11630 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
11631 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
11632 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
11633 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
11634 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
11635 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT                                                                0x8093
11636 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
11637 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
11638 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
11639 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
11640 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
11641 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
11642 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
11643 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
11644 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
11645 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
11646 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
11647 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
11648 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
11649 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
11650 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
11651 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
11652 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
11653 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
11654 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
11655 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
11656 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
11657 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
11658 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
11659 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
11660 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
11661 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
11662 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
11663 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
11664 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
11665 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
11666 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
11667 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
11668 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
11669 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
11670 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA                                                              0x901f
11671 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
11672 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
11673 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
11674 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
11675 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
11676 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
11677 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
11678 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
11679 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
11680 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
11681 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
11682 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
11683 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
11684 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
11685 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
11686 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
11687 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
11688 #define ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
11689 #define ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
11690 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
11691 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
11692 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
11693 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
11694 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
11695 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
11696 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
11697 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
11698 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
11699 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
11700 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
11701 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
11702 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
11703 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
11704 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
11705 #define ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
11706 #define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
11707 #define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
11708 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
11709 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
11710 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
11711 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
11712 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
11713 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT                                                            0x9058
11714 #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
11715 #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
11716 #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
11717 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
11718 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
11719 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
11720 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
11721 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
11722 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
11723 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
11724 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
11725 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
11726 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
11727 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
11728 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
11729 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
11730 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
11731 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
11732 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
11733 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
11734 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
11735 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
11736 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
11737 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
11738 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
11739 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
11740 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
11741 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
11742 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
11743 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
11744 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
11745 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
11746 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
11747 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
11748 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
11749 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
11750 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
11751 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
11752 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
11753 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
11754 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
11755 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
11756 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
11757 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
11758 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
11759 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
11760 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
11761 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
11762 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
11763 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
11764 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
11765 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
11766 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
11767 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
11768 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
11769 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
11770 #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
11771 #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
11772 #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
11773 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
11774 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
11775 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
11776 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
11777 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
11778 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
11779 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
11780 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
11781 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
11782 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
11783 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
11784 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
11785 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
11786 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
11787 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
11788 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
11789 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
11790 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
11791 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
11792 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
11793 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
11794 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
11795 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
11796 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
11797 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
11798 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
11799 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
11800 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
11801 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
11802 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
11803 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
11804 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
11805 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
11806 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
11807 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
11808 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
11809 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
11810 #define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
11811 #define ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
11812 #define ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
11813 #define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1                                                                0x90e3
11814 #define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2                                                                0x90e4
11815 #define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
11816 #define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
11817 #define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
11818 #define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
11819 #define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
11820 #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1                                                               0x90ea
11821 #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2                                                               0x90eb
11822 #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3                                                               0x90ec
11823 #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2                                                           0x90ed
11824 #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3                                                           0x90ee
11825 #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4                                                           0x90ef
11826 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1                                                               0x90f0
11827 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2                                                               0x90f1
11828 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES                                                             0x90f2
11829 #define ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
11830 #define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
11831 #define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
11832 #define ixDPCSSYS_CR4_LANEX_ANA_RX_SQ                                                                  0x90f6
11833 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1                                                                0x90f7
11834 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2                                                                0x90f8
11835 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
11836 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
11837 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
11838 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
11839 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
11840 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
11841 #define ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1                                                           0x90ff
11842 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
11843 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
11844 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
11845 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
11846 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
11847 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
11848 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
11849 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
11850 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
11851 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
11852 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
11853 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
11854 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
11855 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
11856 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
11857 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
11858 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
11859 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
11860 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
11861 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
11862 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
11863 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
11864 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
11865 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
11866 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
11867 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
11868 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
11869 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
11870 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
11871 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
11872 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
11873 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
11874 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
11875 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
11876 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
11877 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
11878 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
11879 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
11880 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
11881 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
11882 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
11883 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
11884 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
11885 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
11886 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
11887 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
11888 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
11889 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
11890 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
11891 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
11892 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
11893 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
11894 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
11895 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
11896 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
11897 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
11898 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
11899 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
11900 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
11901 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
11902 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
11903 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
11904 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
11905 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
11906 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
11907 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
11908 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
11909 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
11910 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
11911 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
11912 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
11913 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
11914 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
11915 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
11916 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
11917 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
11918 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
11919 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
11920 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
11921 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
11922 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
11923 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
11924 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
11925 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
11926 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
11927 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
11928 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
11929 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
11930 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
11931 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
11932 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
11933 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
11934 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
11935 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
11936 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
11937 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
11938 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
11939 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
11940 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
11941 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
11942 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
11943 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
11944 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
11945 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
11946 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
11947 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
11948 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
11949 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
11950 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
11951 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
11952 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
11953 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
11954 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
11955 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
11956 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
11957 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
11958 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
11959 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
11960 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
11961 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
11962 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
11963 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
11964 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
11965 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
11966 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
11967 
11968 
11969 #endif
11970