1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _gc_9_4_3_OFFSET_HEADER 24 #define _gc_9_4_3_OFFSET_HEADER 25 26 27 28 // addressBlock: xcd0_gc_grbmdec 29 // base address: 0x8000 30 #define regGRBM_CNTL 0x0000 31 #define regGRBM_CNTL_BASE_IDX 0 32 #define regGRBM_SKEW_CNTL 0x0001 33 #define regGRBM_SKEW_CNTL_BASE_IDX 0 34 #define regGRBM_STATUS2 0x0002 35 #define regGRBM_STATUS2_BASE_IDX 0 36 #define regGRBM_PWR_CNTL 0x0003 37 #define regGRBM_PWR_CNTL_BASE_IDX 0 38 #define regGRBM_STATUS 0x0004 39 #define regGRBM_STATUS_BASE_IDX 0 40 #define regGRBM_STATUS_SE0 0x0005 41 #define regGRBM_STATUS_SE0_BASE_IDX 0 42 #define regGRBM_STATUS_SE1 0x0006 43 #define regGRBM_STATUS_SE1_BASE_IDX 0 44 #define regGRBM_SOFT_RESET 0x0008 45 #define regGRBM_SOFT_RESET_BASE_IDX 0 46 #define regGRBM_GFX_CLKEN_CNTL 0x000c 47 #define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 48 #define regGRBM_WAIT_IDLE_CLOCKS 0x000d 49 #define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 50 #define regGRBM_STATUS_SE2 0x000e 51 #define regGRBM_STATUS_SE2_BASE_IDX 0 52 #define regGRBM_STATUS_SE3 0x000f 53 #define regGRBM_STATUS_SE3_BASE_IDX 0 54 #define regGRBM_READ_ERROR 0x0016 55 #define regGRBM_READ_ERROR_BASE_IDX 0 56 #define regGRBM_READ_ERROR2 0x0017 57 #define regGRBM_READ_ERROR2_BASE_IDX 0 58 #define regGRBM_INT_CNTL 0x0018 59 #define regGRBM_INT_CNTL_BASE_IDX 0 60 #define regGRBM_TRAP_OP 0x0019 61 #define regGRBM_TRAP_OP_BASE_IDX 0 62 #define regGRBM_TRAP_ADDR 0x001a 63 #define regGRBM_TRAP_ADDR_BASE_IDX 0 64 #define regGRBM_TRAP_ADDR_MSK 0x001b 65 #define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 66 #define regGRBM_TRAP_WD 0x001c 67 #define regGRBM_TRAP_WD_BASE_IDX 0 68 #define regGRBM_TRAP_WD_MSK 0x001d 69 #define regGRBM_TRAP_WD_MSK_BASE_IDX 0 70 #define regGRBM_WRITE_ERROR 0x001f 71 #define regGRBM_WRITE_ERROR_BASE_IDX 0 72 #define regGRBM_IOV_ERROR 0x0020 73 #define regGRBM_IOV_ERROR_BASE_IDX 0 74 #define regGRBM_CHIP_REVISION 0x0021 75 #define regGRBM_CHIP_REVISION_BASE_IDX 0 76 #define regGRBM_GFX_CNTL 0x0022 77 #define regGRBM_GFX_CNTL_BASE_IDX 0 78 #define regGRBM_RSMU_CFG 0x0023 79 #define regGRBM_RSMU_CFG_BASE_IDX 0 80 #define regGRBM_IH_CREDIT 0x0024 81 #define regGRBM_IH_CREDIT_BASE_IDX 0 82 #define regGRBM_PWR_CNTL2 0x0025 83 #define regGRBM_PWR_CNTL2_BASE_IDX 0 84 #define regGRBM_UTCL2_INVAL_RANGE_START 0x0026 85 #define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 86 #define regGRBM_UTCL2_INVAL_RANGE_END 0x0027 87 #define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 88 #define regGRBM_RSMU_READ_ERROR 0x0028 89 #define regGRBM_RSMU_READ_ERROR_BASE_IDX 0 90 #define regGRBM_CHICKEN_BITS 0x0029 91 #define regGRBM_CHICKEN_BITS_BASE_IDX 0 92 #define regGRBM_FENCE_RANGE0 0x002a 93 #define regGRBM_FENCE_RANGE0_BASE_IDX 0 94 #define regGRBM_FENCE_RANGE1 0x002b 95 #define regGRBM_FENCE_RANGE1_BASE_IDX 0 96 #define regGRBM_IOV_READ_ERROR 0x002c 97 #define regGRBM_IOV_READ_ERROR_BASE_IDX 0 98 #define regGRBM_NOWHERE 0x003f 99 #define regGRBM_NOWHERE_BASE_IDX 0 100 #define regGRBM_SCRATCH_REG0 0x0040 101 #define regGRBM_SCRATCH_REG0_BASE_IDX 0 102 #define regGRBM_SCRATCH_REG1 0x0041 103 #define regGRBM_SCRATCH_REG1_BASE_IDX 0 104 #define regGRBM_SCRATCH_REG2 0x0042 105 #define regGRBM_SCRATCH_REG2_BASE_IDX 0 106 #define regGRBM_SCRATCH_REG3 0x0043 107 #define regGRBM_SCRATCH_REG3_BASE_IDX 0 108 #define regGRBM_SCRATCH_REG4 0x0044 109 #define regGRBM_SCRATCH_REG4_BASE_IDX 0 110 #define regGRBM_SCRATCH_REG5 0x0045 111 #define regGRBM_SCRATCH_REG5_BASE_IDX 0 112 #define regGRBM_SCRATCH_REG6 0x0046 113 #define regGRBM_SCRATCH_REG6_BASE_IDX 0 114 #define regGRBM_SCRATCH_REG7 0x0047 115 #define regGRBM_SCRATCH_REG7_BASE_IDX 0 116 #define regVIOLATION_DATA_ASYNC_VF_PROG 0x0048 117 #define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 118 119 120 // addressBlock: xcd0_gc_cpdec 121 // base address: 0x8200 122 #define regCP_CPC_DEBUG_CNTL 0x0080 123 #define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 124 #define regCP_CPF_DEBUG_CNTL 0x0082 125 #define regCP_CPF_DEBUG_CNTL_BASE_IDX 0 126 #define regCP_CPC_STATUS 0x0084 127 #define regCP_CPC_STATUS_BASE_IDX 0 128 #define regCP_CPC_BUSY_STAT 0x0085 129 #define regCP_CPC_BUSY_STAT_BASE_IDX 0 130 #define regCP_CPC_STALLED_STAT1 0x0086 131 #define regCP_CPC_STALLED_STAT1_BASE_IDX 0 132 #define regCP_CPF_STATUS 0x0087 133 #define regCP_CPF_STATUS_BASE_IDX 0 134 #define regCP_CPF_BUSY_STAT 0x0088 135 #define regCP_CPF_BUSY_STAT_BASE_IDX 0 136 #define regCP_CPF_STALLED_STAT1 0x0089 137 #define regCP_CPF_STALLED_STAT1_BASE_IDX 0 138 #define regCP_CPC_GRBM_FREE_COUNT 0x008b 139 #define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 140 #define regCP_CPC_PRIV_VIOLATION_ADDR 0x008c 141 #define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 142 #define regCP_MEC_CNTL 0x008d 143 #define regCP_MEC_CNTL_BASE_IDX 0 144 #define regCP_MEC_ME1_HEADER_DUMP 0x008e 145 #define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 146 #define regCP_MEC_ME2_HEADER_DUMP 0x008f 147 #define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 148 #define regCP_CPC_SCRATCH_INDEX 0x0090 149 #define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 150 #define regCP_CPC_SCRATCH_DATA 0x0091 151 #define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 152 #define regCP_CPF_GRBM_FREE_COUNT 0x0092 153 #define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 154 #define regCP_CPC_HALT_HYST_COUNT 0x00a7 155 #define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 156 #define regCP_CE_COMPARE_COUNT 0x00c0 157 #define regCP_CE_COMPARE_COUNT_BASE_IDX 0 158 #define regCP_CE_DE_COUNT 0x00c1 159 #define regCP_CE_DE_COUNT_BASE_IDX 0 160 #define regCP_DE_CE_COUNT 0x00c2 161 #define regCP_DE_CE_COUNT_BASE_IDX 0 162 #define regCP_DE_LAST_INVAL_COUNT 0x00c3 163 #define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 164 #define regCP_DE_DE_COUNT 0x00c4 165 #define regCP_DE_DE_COUNT_BASE_IDX 0 166 #define regCP_STALLED_STAT3 0x019c 167 #define regCP_STALLED_STAT3_BASE_IDX 0 168 #define regCP_STALLED_STAT1 0x019d 169 #define regCP_STALLED_STAT1_BASE_IDX 0 170 #define regCP_STALLED_STAT2 0x019e 171 #define regCP_STALLED_STAT2_BASE_IDX 0 172 #define regCP_BUSY_STAT 0x019f 173 #define regCP_BUSY_STAT_BASE_IDX 0 174 #define regCP_STAT 0x01a0 175 #define regCP_STAT_BASE_IDX 0 176 #define regCP_ME_HEADER_DUMP 0x01a1 177 #define regCP_ME_HEADER_DUMP_BASE_IDX 0 178 #define regCP_PFP_HEADER_DUMP 0x01a2 179 #define regCP_PFP_HEADER_DUMP_BASE_IDX 0 180 #define regCP_GRBM_FREE_COUNT 0x01a3 181 #define regCP_GRBM_FREE_COUNT_BASE_IDX 0 182 #define regCP_CE_HEADER_DUMP 0x01a4 183 #define regCP_CE_HEADER_DUMP_BASE_IDX 0 184 #define regCP_PFP_INSTR_PNTR 0x01a5 185 #define regCP_PFP_INSTR_PNTR_BASE_IDX 0 186 #define regCP_ME_INSTR_PNTR 0x01a6 187 #define regCP_ME_INSTR_PNTR_BASE_IDX 0 188 #define regCP_CE_INSTR_PNTR 0x01a7 189 #define regCP_CE_INSTR_PNTR_BASE_IDX 0 190 #define regCP_MEC1_INSTR_PNTR 0x01a8 191 #define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 192 #define regCP_MEC2_INSTR_PNTR 0x01a9 193 #define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 194 #define regCP_CSF_STAT 0x01b4 195 #define regCP_CSF_STAT_BASE_IDX 0 196 #define regCP_ME_CNTL 0x01b6 197 #define regCP_ME_CNTL_BASE_IDX 0 198 #define regCP_CNTX_STAT 0x01b8 199 #define regCP_CNTX_STAT_BASE_IDX 0 200 #define regCP_ME_PREEMPTION 0x01b9 201 #define regCP_ME_PREEMPTION_BASE_IDX 0 202 #define regCP_ROQ_THRESHOLDS 0x01bc 203 #define regCP_ROQ_THRESHOLDS_BASE_IDX 0 204 #define regCP_MEQ_STQ_THRESHOLD 0x01bd 205 #define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 206 #define regCP_RB2_RPTR 0x01be 207 #define regCP_RB2_RPTR_BASE_IDX 0 208 #define regCP_RB1_RPTR 0x01bf 209 #define regCP_RB1_RPTR_BASE_IDX 0 210 #define regCP_RB0_RPTR 0x01c0 211 #define regCP_RB0_RPTR_BASE_IDX 0 212 #define regCP_RB_RPTR 0x01c0 213 #define regCP_RB_RPTR_BASE_IDX 0 214 #define regCP_RB_WPTR_DELAY 0x01c1 215 #define regCP_RB_WPTR_DELAY_BASE_IDX 0 216 #define regCP_RB_WPTR_POLL_CNTL 0x01c2 217 #define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 218 #define regCP_ROQ1_THRESHOLDS 0x01d5 219 #define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 220 #define regCP_ROQ2_THRESHOLDS 0x01d6 221 #define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 222 #define regCP_STQ_THRESHOLDS 0x01d7 223 #define regCP_STQ_THRESHOLDS_BASE_IDX 0 224 #define regCP_QUEUE_THRESHOLDS 0x01d8 225 #define regCP_QUEUE_THRESHOLDS_BASE_IDX 0 226 #define regCP_MEQ_THRESHOLDS 0x01d9 227 #define regCP_MEQ_THRESHOLDS_BASE_IDX 0 228 #define regCP_ROQ_AVAIL 0x01da 229 #define regCP_ROQ_AVAIL_BASE_IDX 0 230 #define regCP_STQ_AVAIL 0x01db 231 #define regCP_STQ_AVAIL_BASE_IDX 0 232 #define regCP_ROQ2_AVAIL 0x01dc 233 #define regCP_ROQ2_AVAIL_BASE_IDX 0 234 #define regCP_MEQ_AVAIL 0x01dd 235 #define regCP_MEQ_AVAIL_BASE_IDX 0 236 #define regCP_CMD_INDEX 0x01de 237 #define regCP_CMD_INDEX_BASE_IDX 0 238 #define regCP_CMD_DATA 0x01df 239 #define regCP_CMD_DATA_BASE_IDX 0 240 #define regCP_ROQ_RB_STAT 0x01e0 241 #define regCP_ROQ_RB_STAT_BASE_IDX 0 242 #define regCP_ROQ_IB1_STAT 0x01e1 243 #define regCP_ROQ_IB1_STAT_BASE_IDX 0 244 #define regCP_ROQ_IB2_STAT 0x01e2 245 #define regCP_ROQ_IB2_STAT_BASE_IDX 0 246 #define regCP_STQ_STAT 0x01e3 247 #define regCP_STQ_STAT_BASE_IDX 0 248 #define regCP_STQ_WR_STAT 0x01e4 249 #define regCP_STQ_WR_STAT_BASE_IDX 0 250 #define regCP_MEQ_STAT 0x01e5 251 #define regCP_MEQ_STAT_BASE_IDX 0 252 #define regCP_CEQ1_AVAIL 0x01e6 253 #define regCP_CEQ1_AVAIL_BASE_IDX 0 254 #define regCP_CEQ2_AVAIL 0x01e7 255 #define regCP_CEQ2_AVAIL_BASE_IDX 0 256 #define regCP_CE_ROQ_RB_STAT 0x01e8 257 #define regCP_CE_ROQ_RB_STAT_BASE_IDX 0 258 #define regCP_CE_ROQ_IB1_STAT 0x01e9 259 #define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0 260 #define regCP_CE_ROQ_IB2_STAT 0x01ea 261 #define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0 262 #define regCP_INT_STAT_DEBUG 0x01f7 263 #define regCP_INT_STAT_DEBUG_BASE_IDX 0 264 #define regCP_DEBUG_CNTL 0x01f8 265 #define regCP_DEBUG_CNTL_BASE_IDX 0 266 #define regCP_PRIV_VIOLATION_ADDR 0x01fa 267 #define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 268 269 270 // addressBlock: xcd0_gc_padec 271 // base address: 0x8800 272 #define regVGT_VTX_VECT_EJECT_REG 0x022c 273 #define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 274 #define regVGT_DMA_DATA_FIFO_DEPTH 0x022d 275 #define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 276 #define regVGT_DMA_REQ_FIFO_DEPTH 0x022e 277 #define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 278 #define regVGT_DRAW_INIT_FIFO_DEPTH 0x022f 279 #define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 280 #define regVGT_LAST_COPY_STATE 0x0230 281 #define regVGT_LAST_COPY_STATE_BASE_IDX 0 282 #define regVGT_CACHE_INVALIDATION 0x0231 283 #define regVGT_CACHE_INVALIDATION_BASE_IDX 0 284 #define regVGT_RESET_DEBUG 0x0232 285 #define regVGT_RESET_DEBUG_BASE_IDX 0 286 #define regVGT_STRMOUT_DELAY 0x0233 287 #define regVGT_STRMOUT_DELAY_BASE_IDX 0 288 #define regVGT_FIFO_DEPTHS 0x0234 289 #define regVGT_FIFO_DEPTHS_BASE_IDX 0 290 #define regVGT_GS_VERTEX_REUSE 0x0235 291 #define regVGT_GS_VERTEX_REUSE_BASE_IDX 0 292 #define regVGT_MC_LAT_CNTL 0x0236 293 #define regVGT_MC_LAT_CNTL_BASE_IDX 0 294 #define regIA_CNTL_STATUS 0x0237 295 #define regIA_CNTL_STATUS_BASE_IDX 0 296 #define regVGT_CNTL_STATUS 0x023c 297 #define regVGT_CNTL_STATUS_BASE_IDX 0 298 #define regWD_CNTL_STATUS 0x023f 299 #define regWD_CNTL_STATUS_BASE_IDX 0 300 #define regCC_GC_PRIM_CONFIG 0x0240 301 #define regCC_GC_PRIM_CONFIG_BASE_IDX 0 302 #define regGC_USER_PRIM_CONFIG 0x0241 303 #define regGC_USER_PRIM_CONFIG_BASE_IDX 0 304 #define regWD_QOS 0x0242 305 #define regWD_QOS_BASE_IDX 0 306 #define regWD_UTCL1_CNTL 0x0243 307 #define regWD_UTCL1_CNTL_BASE_IDX 0 308 #define regWD_UTCL1_STATUS 0x0244 309 #define regWD_UTCL1_STATUS_BASE_IDX 0 310 #define regIA_UTCL1_CNTL 0x0246 311 #define regIA_UTCL1_CNTL_BASE_IDX 0 312 #define regIA_UTCL1_STATUS 0x0247 313 #define regIA_UTCL1_STATUS_BASE_IDX 0 314 #define regVGT_SYS_CONFIG 0x0263 315 #define regVGT_SYS_CONFIG_BASE_IDX 0 316 #define regVGT_VS_MAX_WAVE_ID 0x0268 317 #define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0 318 #define regVGT_GS_MAX_WAVE_ID 0x0269 319 #define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 320 #define regGFX_PIPE_CONTROL 0x026d 321 #define regGFX_PIPE_CONTROL_BASE_IDX 0 322 #define regCC_GC_SHADER_ARRAY_CONFIG 0x026f 323 #define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 324 #define regGC_USER_SHADER_ARRAY_CONFIG 0x0270 325 #define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 326 #define regVGT_DMA_PRIMITIVE_TYPE 0x0271 327 #define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 328 #define regVGT_DMA_CONTROL 0x0272 329 #define regVGT_DMA_CONTROL_BASE_IDX 0 330 #define regVGT_DMA_LS_HS_CONFIG 0x0273 331 #define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 332 #define regWD_BUF_RESOURCE_1 0x0276 333 #define regWD_BUF_RESOURCE_1_BASE_IDX 0 334 #define regWD_BUF_RESOURCE_2 0x0277 335 #define regWD_BUF_RESOURCE_2_BASE_IDX 0 336 #define regPA_CL_CNTL_STATUS 0x0284 337 #define regPA_CL_CNTL_STATUS_BASE_IDX 0 338 #define regPA_CL_ENHANCE 0x0285 339 #define regPA_CL_ENHANCE_BASE_IDX 0 340 #define regPA_CL_RESET_DEBUG 0x0286 341 #define regPA_CL_RESET_DEBUG_BASE_IDX 0 342 #define regPA_SU_CNTL_STATUS 0x0294 343 #define regPA_SU_CNTL_STATUS_BASE_IDX 0 344 #define regPA_SC_FIFO_DEPTH_CNTL 0x0295 345 #define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 346 #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 347 #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 348 #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 349 #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 350 #define regPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 351 #define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 352 #define regPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 353 #define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 354 #define regPA_SC_BINNER_EVENT_CNTL_0 0x02cc 355 #define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 356 #define regPA_SC_BINNER_EVENT_CNTL_1 0x02cd 357 #define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 358 #define regPA_SC_BINNER_EVENT_CNTL_2 0x02ce 359 #define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 360 #define regPA_SC_BINNER_EVENT_CNTL_3 0x02cf 361 #define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 362 #define regPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 363 #define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 364 #define regPA_SC_BINNER_PERF_CNTL_0 0x02d1 365 #define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 366 #define regPA_SC_BINNER_PERF_CNTL_1 0x02d2 367 #define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 368 #define regPA_SC_BINNER_PERF_CNTL_2 0x02d3 369 #define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 370 #define regPA_SC_BINNER_PERF_CNTL_3 0x02d4 371 #define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 372 #define regPA_SC_ENHANCE_2 0x02dc 373 #define regPA_SC_ENHANCE_2_BASE_IDX 0 374 #define regPA_SC_FIFO_SIZE 0x02f3 375 #define regPA_SC_FIFO_SIZE_BASE_IDX 0 376 #define regPA_SC_IF_FIFO_SIZE 0x02f5 377 #define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0 378 #define regPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 379 #define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 380 #define regPA_UTCL1_CNTL1 0x02f9 381 #define regPA_UTCL1_CNTL1_BASE_IDX 0 382 #define regPA_UTCL1_CNTL2 0x02fa 383 #define regPA_UTCL1_CNTL2_BASE_IDX 0 384 #define regPA_SIDEBAND_REQUEST_DELAYS 0x02fb 385 #define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 386 #define regPA_SC_ENHANCE 0x02fc 387 #define regPA_SC_ENHANCE_BASE_IDX 0 388 #define regPA_SC_ENHANCE_1 0x02fd 389 #define regPA_SC_ENHANCE_1_BASE_IDX 0 390 #define regPA_SC_DSM_CNTL 0x02fe 391 #define regPA_SC_DSM_CNTL_BASE_IDX 0 392 #define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff 393 #define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 394 395 396 // addressBlock: xcd0_gc_sqdec 397 // base address: 0x8c00 398 #define regSQ_CONFIG 0x0300 399 #define regSQ_CONFIG_BASE_IDX 0 400 #define regSQC_CONFIG 0x0301 401 #define regSQC_CONFIG_BASE_IDX 0 402 #define regLDS_CONFIG 0x0302 403 #define regLDS_CONFIG_BASE_IDX 0 404 #define regSQ_RANDOM_WAVE_PRI 0x0303 405 #define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 406 #define regSQ_REG_CREDITS 0x0304 407 #define regSQ_REG_CREDITS_BASE_IDX 0 408 #define regSQ_FIFO_SIZES 0x0305 409 #define regSQ_FIFO_SIZES_BASE_IDX 0 410 #define regSQ_DSM_CNTL 0x0306 411 #define regSQ_DSM_CNTL_BASE_IDX 0 412 #define regSQ_DSM_CNTL2 0x0307 413 #define regSQ_DSM_CNTL2_BASE_IDX 0 414 #define regSQ_RUNTIME_CONFIG 0x0308 415 #define regSQ_RUNTIME_CONFIG_BASE_IDX 0 416 #define regSQ_DEBUG_STS_GLOBAL 0x0309 417 #define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 418 #define regSH_MEM_BASES 0x030a 419 #define regSH_MEM_BASES_BASE_IDX 0 420 #define regSQ_TIMEOUT_CONFIG 0x030b 421 #define regSQ_TIMEOUT_CONFIG_BASE_IDX 0 422 #define regSQ_TIMEOUT_STATUS 0x030c 423 #define regSQ_TIMEOUT_STATUS_BASE_IDX 0 424 #define regSH_MEM_CONFIG 0x030d 425 #define regSH_MEM_CONFIG_BASE_IDX 0 426 #define regSP_MFMA_PORTD_RD_CONFIG 0x030e 427 #define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX 0 428 #define regSH_CAC_CONFIG 0x030f 429 #define regSH_CAC_CONFIG_BASE_IDX 0 430 #define regSQ_DEBUG_STS_GLOBAL2 0x0310 431 #define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 432 #define regSQ_DEBUG_STS_GLOBAL3 0x0311 433 #define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0 434 #define regCC_GC_SHADER_RATE_CONFIG 0x0312 435 #define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 436 #define regGC_USER_SHADER_RATE_CONFIG 0x0313 437 #define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 438 #define regSQ_INTERRUPT_AUTO_MASK 0x0314 439 #define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 440 #define regSQ_INTERRUPT_MSG_CTRL 0x0315 441 #define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 442 #define regSQ_DEBUG_PERFCOUNT_TRAP 0x0316 443 #define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX 0 444 #define regSQ_UTCL1_CNTL1 0x0317 445 #define regSQ_UTCL1_CNTL1_BASE_IDX 0 446 #define regSQ_UTCL1_CNTL2 0x0318 447 #define regSQ_UTCL1_CNTL2_BASE_IDX 0 448 #define regSQ_UTCL1_STATUS 0x0319 449 #define regSQ_UTCL1_STATUS_BASE_IDX 0 450 #define regSQ_FED_INTERRUPT_STATUS 0x031a 451 #define regSQ_FED_INTERRUPT_STATUS_BASE_IDX 0 452 #define regSQ_CGTS_CONFIG 0x031b 453 #define regSQ_CGTS_CONFIG_BASE_IDX 0 454 #define regSQ_SHADER_TBA_LO 0x031c 455 #define regSQ_SHADER_TBA_LO_BASE_IDX 0 456 #define regSQ_SHADER_TBA_HI 0x031d 457 #define regSQ_SHADER_TBA_HI_BASE_IDX 0 458 #define regSQ_SHADER_TMA_LO 0x031e 459 #define regSQ_SHADER_TMA_LO_BASE_IDX 0 460 #define regSQ_SHADER_TMA_HI 0x031f 461 #define regSQ_SHADER_TMA_HI_BASE_IDX 0 462 #define regSQC_DSM_CNTL 0x0320 463 #define regSQC_DSM_CNTL_BASE_IDX 0 464 #define regSQC_DSM_CNTLA 0x0321 465 #define regSQC_DSM_CNTLA_BASE_IDX 0 466 #define regSQC_DSM_CNTLB 0x0322 467 #define regSQC_DSM_CNTLB_BASE_IDX 0 468 #define regSQC_DSM_CNTL2 0x0325 469 #define regSQC_DSM_CNTL2_BASE_IDX 0 470 #define regSQC_DSM_CNTL2A 0x0326 471 #define regSQC_DSM_CNTL2A_BASE_IDX 0 472 #define regSQC_DSM_CNTL2B 0x0327 473 #define regSQC_DSM_CNTL2B_BASE_IDX 0 474 #define regSQC_DSM_CNTL2E 0x032a 475 #define regSQC_DSM_CNTL2E_BASE_IDX 0 476 #define regSQC_EDC_FUE_CNTL 0x032b 477 #define regSQC_EDC_FUE_CNTL_BASE_IDX 0 478 #define regSQC_EDC_CNT2 0x032c 479 #define regSQC_EDC_CNT2_BASE_IDX 0 480 #define regSQC_EDC_CNT3 0x032d 481 #define regSQC_EDC_CNT3_BASE_IDX 0 482 #define regSQC_EDC_PARITY_CNT3 0x032e 483 #define regSQC_EDC_PARITY_CNT3_BASE_IDX 0 484 #define regSQ_DEBUG 0x0332 485 #define regSQ_DEBUG_BASE_IDX 0 486 #define regSQ_PERF_SNAPSHOT_CTRL 0x0334 487 #define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 488 #define regSQ_DEBUG_FOR_INTERNAL_CTRL 0x0335 489 #define regSQ_DEBUG_FOR_INTERNAL_CTRL_BASE_IDX 0 490 #define regSQ_REG_TIMESTAMP 0x0374 491 #define regSQ_REG_TIMESTAMP_BASE_IDX 0 492 #define regSQ_CMD_TIMESTAMP 0x0375 493 #define regSQ_CMD_TIMESTAMP_BASE_IDX 0 494 #define regSQ_HOSTTRAP_STATUS 0x0376 495 #define regSQ_HOSTTRAP_STATUS_BASE_IDX 0 496 #define regSQ_IND_INDEX 0x0378 497 #define regSQ_IND_INDEX_BASE_IDX 0 498 #define regSQ_IND_DATA 0x0379 499 #define regSQ_IND_DATA_BASE_IDX 0 500 #define regSQ_CONFIG1 0x037a 501 #define regSQ_CONFIG1_BASE_IDX 0 502 #define regSQ_CMD 0x037b 503 #define regSQ_CMD_BASE_IDX 0 504 #define regSQ_TIME_HI 0x037c 505 #define regSQ_TIME_HI_BASE_IDX 0 506 #define regSQ_TIME_LO 0x037d 507 #define regSQ_TIME_LO_BASE_IDX 0 508 #define regSQ_DS_0 0x037f 509 #define regSQ_DS_0_BASE_IDX 0 510 #define regSQ_DS_1 0x037f 511 #define regSQ_DS_1_BASE_IDX 0 512 #define regSQ_EXP_0 0x037f 513 #define regSQ_EXP_0_BASE_IDX 0 514 #define regSQ_EXP_1 0x037f 515 #define regSQ_EXP_1_BASE_IDX 0 516 #define regSQ_FLAT_0 0x037f 517 #define regSQ_FLAT_0_BASE_IDX 0 518 #define regSQ_FLAT_1 0x037f 519 #define regSQ_FLAT_1_BASE_IDX 0 520 #define regSQ_GLBL_0 0x037f 521 #define regSQ_GLBL_0_BASE_IDX 0 522 #define regSQ_GLBL_1 0x037f 523 #define regSQ_GLBL_1_BASE_IDX 0 524 #define regSQ_INST 0x037f 525 #define regSQ_INST_BASE_IDX 0 526 #define regSQ_MIMG_0 0x037f 527 #define regSQ_MIMG_0_BASE_IDX 0 528 #define regSQ_MIMG_1 0x037f 529 #define regSQ_MIMG_1_BASE_IDX 0 530 #define regSQ_MTBUF_0 0x037f 531 #define regSQ_MTBUF_0_BASE_IDX 0 532 #define regSQ_MTBUF_1 0x037f 533 #define regSQ_MTBUF_1_BASE_IDX 0 534 #define regSQ_MUBUF_0 0x037f 535 #define regSQ_MUBUF_0_BASE_IDX 0 536 #define regSQ_MUBUF_1 0x037f 537 #define regSQ_MUBUF_1_BASE_IDX 0 538 #define regSQ_SCRATCH_0 0x037f 539 #define regSQ_SCRATCH_0_BASE_IDX 0 540 #define regSQ_SCRATCH_1 0x037f 541 #define regSQ_SCRATCH_1_BASE_IDX 0 542 #define regSQ_SMEM_0 0x037f 543 #define regSQ_SMEM_0_BASE_IDX 0 544 #define regSQ_SMEM_1 0x037f 545 #define regSQ_SMEM_1_BASE_IDX 0 546 #define regSQ_SOP1 0x037f 547 #define regSQ_SOP1_BASE_IDX 0 548 #define regSQ_SOP2 0x037f 549 #define regSQ_SOP2_BASE_IDX 0 550 #define regSQ_SOPC 0x037f 551 #define regSQ_SOPC_BASE_IDX 0 552 #define regSQ_SOPK 0x037f 553 #define regSQ_SOPK_BASE_IDX 0 554 #define regSQ_SOPP 0x037f 555 #define regSQ_SOPP_BASE_IDX 0 556 #define regSQ_VINTRP 0x037f 557 #define regSQ_VINTRP_BASE_IDX 0 558 #define regSQ_VOP1 0x037f 559 #define regSQ_VOP1_BASE_IDX 0 560 #define regSQ_VOP2 0x037f 561 #define regSQ_VOP2_BASE_IDX 0 562 #define regSQ_VOP3P_0 0x037f 563 #define regSQ_VOP3P_0_BASE_IDX 0 564 #define regSQ_VOP3P_1 0x037f 565 #define regSQ_VOP3P_1_BASE_IDX 0 566 #define regSQ_VOP3P_MFMA_0 0x037f 567 #define regSQ_VOP3P_MFMA_0_BASE_IDX 0 568 #define regSQ_VOP3P_MFMA_1 0x037f 569 #define regSQ_VOP3P_MFMA_1_BASE_IDX 0 570 #define regSQ_VOP3_0 0x037f 571 #define regSQ_VOP3_0_BASE_IDX 0 572 #define regSQ_VOP3_0_SDST_ENC 0x037f 573 #define regSQ_VOP3_0_SDST_ENC_BASE_IDX 0 574 #define regSQ_VOP3_1 0x037f 575 #define regSQ_VOP3_1_BASE_IDX 0 576 #define regSQ_VOPC 0x037f 577 #define regSQ_VOPC_BASE_IDX 0 578 #define regSQ_VOP_DPP 0x037f 579 #define regSQ_VOP_DPP_BASE_IDX 0 580 #define regSQ_VOP_SDWA 0x037f 581 #define regSQ_VOP_SDWA_BASE_IDX 0 582 #define regSQ_VOP_SDWA_SDST_ENC 0x037f 583 #define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 584 #define regSQ_LB_CTR_CTRL 0x0398 585 #define regSQ_LB_CTR_CTRL_BASE_IDX 0 586 #define regSQ_LB_DATA0 0x0399 587 #define regSQ_LB_DATA0_BASE_IDX 0 588 #define regSQ_LB_DATA1 0x039a 589 #define regSQ_LB_DATA1_BASE_IDX 0 590 #define regSQ_LB_DATA2 0x039b 591 #define regSQ_LB_DATA2_BASE_IDX 0 592 #define regSQ_LB_DATA3 0x039c 593 #define regSQ_LB_DATA3_BASE_IDX 0 594 #define regSQ_LB_CTR_SEL 0x039d 595 #define regSQ_LB_CTR_SEL_BASE_IDX 0 596 #define regSQ_LB_CTR0_CU 0x039e 597 #define regSQ_LB_CTR0_CU_BASE_IDX 0 598 #define regSQ_LB_CTR1_CU 0x039f 599 #define regSQ_LB_CTR1_CU_BASE_IDX 0 600 #define regSQ_LB_CTR2_CU 0x03a0 601 #define regSQ_LB_CTR2_CU_BASE_IDX 0 602 #define regSQ_LB_CTR3_CU 0x03a1 603 #define regSQ_LB_CTR3_CU_BASE_IDX 0 604 #define regSQC_EDC_CNT 0x03a2 605 #define regSQC_EDC_CNT_BASE_IDX 0 606 #define regSQ_EDC_SEC_CNT 0x03a3 607 #define regSQ_EDC_SEC_CNT_BASE_IDX 0 608 #define regSQ_EDC_DED_CNT 0x03a4 609 #define regSQ_EDC_DED_CNT_BASE_IDX 0 610 #define regSQ_EDC_INFO 0x03a5 611 #define regSQ_EDC_INFO_BASE_IDX 0 612 #define regSQ_EDC_CNT 0x03a6 613 #define regSQ_EDC_CNT_BASE_IDX 0 614 #define regSQ_EDC_FUE_CNTL 0x03a7 615 #define regSQ_EDC_FUE_CNTL_BASE_IDX 0 616 #define regSQ_THREAD_TRACE_WORD_CMN 0x03b0 617 #define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 618 #define regSQ_THREAD_TRACE_WORD_EVENT 0x03b0 619 #define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 620 #define regSQ_THREAD_TRACE_WORD_INST 0x03b0 621 #define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 622 #define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 623 #define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 624 #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 625 #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 626 #define regSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 627 #define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 628 #define regSQ_THREAD_TRACE_WORD_MISC 0x03b0 629 #define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 630 #define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 631 #define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 632 #define regSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 633 #define regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 634 #define regSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 635 #define regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 636 #define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 637 #define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 638 #define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 639 #define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 640 #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 641 #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 642 #define regSQ_THREAD_TRACE_WORD_WAVE 0x03b0 643 #define regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 644 #define regSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 645 #define regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 646 #define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 647 #define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 648 #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 649 #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 650 #define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 651 #define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 652 #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 653 #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 654 #define regSQ_WREXEC_EXEC_HI 0x03b1 655 #define regSQ_WREXEC_EXEC_HI_BASE_IDX 0 656 #define regSQ_WREXEC_EXEC_LO 0x03b1 657 #define regSQ_WREXEC_EXEC_LO_BASE_IDX 0 658 #define regSQ_BUF_RSRC_WORD0 0x03c0 659 #define regSQ_BUF_RSRC_WORD0_BASE_IDX 0 660 #define regSQ_BUF_RSRC_WORD1 0x03c1 661 #define regSQ_BUF_RSRC_WORD1_BASE_IDX 0 662 #define regSQ_BUF_RSRC_WORD2 0x03c2 663 #define regSQ_BUF_RSRC_WORD2_BASE_IDX 0 664 #define regSQ_BUF_RSRC_WORD3 0x03c3 665 #define regSQ_BUF_RSRC_WORD3_BASE_IDX 0 666 #define regSQ_IMG_RSRC_WORD0 0x03c4 667 #define regSQ_IMG_RSRC_WORD0_BASE_IDX 0 668 #define regSQ_IMG_RSRC_WORD1 0x03c5 669 #define regSQ_IMG_RSRC_WORD1_BASE_IDX 0 670 #define regSQ_IMG_RSRC_WORD2 0x03c6 671 #define regSQ_IMG_RSRC_WORD2_BASE_IDX 0 672 #define regSQ_IMG_RSRC_WORD3 0x03c7 673 #define regSQ_IMG_RSRC_WORD3_BASE_IDX 0 674 #define regSQ_IMG_RSRC_WORD4 0x03c8 675 #define regSQ_IMG_RSRC_WORD4_BASE_IDX 0 676 #define regSQ_IMG_RSRC_WORD5 0x03c9 677 #define regSQ_IMG_RSRC_WORD5_BASE_IDX 0 678 #define regSQ_IMG_RSRC_WORD6 0x03ca 679 #define regSQ_IMG_RSRC_WORD6_BASE_IDX 0 680 #define regSQ_IMG_RSRC_WORD7 0x03cb 681 #define regSQ_IMG_RSRC_WORD7_BASE_IDX 0 682 #define regSQ_IMG_SAMP_WORD0 0x03cc 683 #define regSQ_IMG_SAMP_WORD0_BASE_IDX 0 684 #define regSQ_IMG_SAMP_WORD1 0x03cd 685 #define regSQ_IMG_SAMP_WORD1_BASE_IDX 0 686 #define regSQ_IMG_SAMP_WORD2 0x03ce 687 #define regSQ_IMG_SAMP_WORD2_BASE_IDX 0 688 #define regSQ_IMG_SAMP_WORD3 0x03cf 689 #define regSQ_IMG_SAMP_WORD3_BASE_IDX 0 690 #define regSQ_FLAT_SCRATCH_WORD0 0x03d0 691 #define regSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 692 #define regSQ_FLAT_SCRATCH_WORD1 0x03d1 693 #define regSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 694 #define regSQ_M0_GPR_IDX_WORD 0x03d2 695 #define regSQ_M0_GPR_IDX_WORD_BASE_IDX 0 696 #define regSQC_ICACHE_UTCL1_CNTL1 0x03d3 697 #define regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 698 #define regSQC_ICACHE_UTCL1_CNTL2 0x03d4 699 #define regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 700 #define regSQC_DCACHE_UTCL1_CNTL1 0x03d5 701 #define regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 702 #define regSQC_DCACHE_UTCL1_CNTL2 0x03d6 703 #define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 704 #define regSQC_ICACHE_UTCL1_STATUS 0x03d7 705 #define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 706 #define regSQC_DCACHE_UTCL1_STATUS 0x03d8 707 #define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 708 709 710 // addressBlock: xcd0_gc_shsdec 711 // base address: 0x9000 712 #define regSX_DEBUG_BUSY 0x0414 713 #define regSX_DEBUG_BUSY_BASE_IDX 0 714 #define regSX_DEBUG_1 0x0419 715 #define regSX_DEBUG_1_BASE_IDX 0 716 #define regSPI_PS_MAX_WAVE_ID 0x043a 717 #define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 718 #define regSPI_START_PHASE 0x043b 719 #define regSPI_START_PHASE_BASE_IDX 0 720 #define regSPI_GFX_CNTL 0x043c 721 #define regSPI_GFX_CNTL_BASE_IDX 0 722 #define regSPI_DEBUG_READ 0x0442 723 #define regSPI_DEBUG_READ_BASE_IDX 0 724 #define regSPI_DSM_CNTL 0x0443 725 #define regSPI_DSM_CNTL_BASE_IDX 0 726 #define regSPI_DSM_CNTL2 0x0444 727 #define regSPI_DSM_CNTL2_BASE_IDX 0 728 #define regSPI_EDC_CNT 0x0445 729 #define regSPI_EDC_CNT_BASE_IDX 0 730 #define regSPI_DEBUG_BUSY 0x0450 731 #define regSPI_DEBUG_BUSY_BASE_IDX 0 732 #define regSPI_CONFIG_PS_CU_EN 0x0452 733 #define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 734 #define regSPI_WF_LIFETIME_CNTL 0x04aa 735 #define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 736 #define regSPI_WF_LIFETIME_LIMIT_0 0x04ab 737 #define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 738 #define regSPI_WF_LIFETIME_LIMIT_1 0x04ac 739 #define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 740 #define regSPI_WF_LIFETIME_LIMIT_2 0x04ad 741 #define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 742 #define regSPI_WF_LIFETIME_LIMIT_3 0x04ae 743 #define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 744 #define regSPI_WF_LIFETIME_LIMIT_4 0x04af 745 #define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 746 #define regSPI_WF_LIFETIME_LIMIT_5 0x04b0 747 #define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 748 #define regSPI_WF_LIFETIME_LIMIT_6 0x04b1 749 #define regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 750 #define regSPI_WF_LIFETIME_LIMIT_7 0x04b2 751 #define regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 752 #define regSPI_WF_LIFETIME_LIMIT_8 0x04b3 753 #define regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 754 #define regSPI_WF_LIFETIME_LIMIT_9 0x04b4 755 #define regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 756 #define regSPI_WF_LIFETIME_STATUS_0 0x04b5 757 #define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 758 #define regSPI_WF_LIFETIME_STATUS_1 0x04b6 759 #define regSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 760 #define regSPI_WF_LIFETIME_STATUS_2 0x04b7 761 #define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 762 #define regSPI_WF_LIFETIME_STATUS_3 0x04b8 763 #define regSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 764 #define regSPI_WF_LIFETIME_STATUS_4 0x04b9 765 #define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 766 #define regSPI_WF_LIFETIME_STATUS_5 0x04ba 767 #define regSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 768 #define regSPI_WF_LIFETIME_STATUS_6 0x04bb 769 #define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 770 #define regSPI_WF_LIFETIME_STATUS_7 0x04bc 771 #define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 772 #define regSPI_WF_LIFETIME_STATUS_8 0x04bd 773 #define regSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 774 #define regSPI_WF_LIFETIME_STATUS_9 0x04be 775 #define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 776 #define regSPI_WF_LIFETIME_STATUS_10 0x04bf 777 #define regSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 778 #define regSPI_WF_LIFETIME_STATUS_11 0x04c0 779 #define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 780 #define regSPI_WF_LIFETIME_STATUS_12 0x04c1 781 #define regSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 782 #define regSPI_WF_LIFETIME_STATUS_13 0x04c2 783 #define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 784 #define regSPI_WF_LIFETIME_STATUS_14 0x04c3 785 #define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 786 #define regSPI_WF_LIFETIME_STATUS_15 0x04c4 787 #define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 788 #define regSPI_WF_LIFETIME_STATUS_16 0x04c5 789 #define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 790 #define regSPI_WF_LIFETIME_STATUS_17 0x04c6 791 #define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 792 #define regSPI_WF_LIFETIME_STATUS_18 0x04c7 793 #define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 794 #define regSPI_WF_LIFETIME_STATUS_19 0x04c8 795 #define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 796 #define regSPI_WF_LIFETIME_STATUS_20 0x04c9 797 #define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 798 #define regSPI_WF_LIFETIME_DEBUG 0x04ca 799 #define regSPI_WF_LIFETIME_DEBUG_BASE_IDX 0 800 #define regSPI_LB_CTR_CTRL 0x04d4 801 #define regSPI_LB_CTR_CTRL_BASE_IDX 0 802 #define regSPI_LB_CU_MASK 0x04d5 803 #define regSPI_LB_CU_MASK_BASE_IDX 0 804 #define regSPI_LB_DATA_REG 0x04d6 805 #define regSPI_LB_DATA_REG_BASE_IDX 0 806 #define regSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 807 #define regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 808 #define regSPI_GDS_CREDITS 0x04d8 809 #define regSPI_GDS_CREDITS_BASE_IDX 0 810 #define regSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 811 #define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 812 #define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da 813 #define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 814 #define regSPI_CSQ_WF_ACTIVE_STATUS 0x04db 815 #define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 816 #define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc 817 #define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 818 #define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd 819 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 820 #define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de 821 #define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 822 #define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df 823 #define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 824 #define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 825 #define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 826 #define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 827 #define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 828 #define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 829 #define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 830 #define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 831 #define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 832 #define regSPI_LB_DATA_WAVES 0x04e4 833 #define regSPI_LB_DATA_WAVES_BASE_IDX 0 834 #define regSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 835 #define regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 836 #define regSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 837 #define regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 838 #define regSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 839 #define regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 840 #define regSPIS_DEBUG_READ 0x04ea 841 #define regSPIS_DEBUG_READ_BASE_IDX 0 842 #define regBCI_DEBUG_READ 0x04eb 843 #define regBCI_DEBUG_READ_BASE_IDX 0 844 #define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec 845 #define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 846 #define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed 847 #define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 848 #define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee 849 #define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 850 #define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef 851 #define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 852 #define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 853 #define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 854 #define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 855 #define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 856 #define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 857 #define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 858 #define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 859 #define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 860 #define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 861 #define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 862 #define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 863 #define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 864 865 866 // addressBlock: xcd0_gc_tpdec 867 // base address: 0x9400 868 #define regTD_CNTL 0x0525 869 #define regTD_CNTL_BASE_IDX 0 870 #define regTD_STATUS 0x0526 871 #define regTD_STATUS_BASE_IDX 0 872 #define regTD_POWER_CNTL 0x052a 873 #define regTD_POWER_CNTL_BASE_IDX 0 874 #define regTD_DSM_CNTL 0x052f 875 #define regTD_DSM_CNTL_BASE_IDX 0 876 #define regTD_DSM_CNTL2 0x0530 877 #define regTD_DSM_CNTL2_BASE_IDX 0 878 #define regTD_SCRATCH 0x0533 879 #define regTD_SCRATCH_BASE_IDX 0 880 #define regTA_POWER_CNTL 0x0540 881 #define regTA_POWER_CNTL_BASE_IDX 0 882 #define regTA_CNTL 0x0541 883 #define regTA_CNTL_BASE_IDX 0 884 #define regTA_CNTL_AUX 0x0542 885 #define regTA_CNTL_AUX_BASE_IDX 0 886 #define regTA_FEATURE_CNTL 0x0543 887 #define regTA_FEATURE_CNTL_BASE_IDX 0 888 #define regTA_STATUS 0x0548 889 #define regTA_STATUS_BASE_IDX 0 890 #define regTA_SCRATCH 0x0564 891 #define regTA_SCRATCH_BASE_IDX 0 892 #define regTA_DSM_CNTL 0x0584 893 #define regTA_DSM_CNTL_BASE_IDX 0 894 #define regTA_DSM_CNTL2 0x0585 895 #define regTA_DSM_CNTL2_BASE_IDX 0 896 897 898 // addressBlock: xcd0_gc_gdsdec 899 // base address: 0x9700 900 #define regGDS_CONFIG 0x05c0 901 #define regGDS_CONFIG_BASE_IDX 0 902 #define regGDS_CNTL_STATUS 0x05c1 903 #define regGDS_CNTL_STATUS_BASE_IDX 0 904 #define regGDS_ENHANCE2 0x05c2 905 #define regGDS_ENHANCE2_BASE_IDX 0 906 #define regGDS_PROTECTION_FAULT 0x05c3 907 #define regGDS_PROTECTION_FAULT_BASE_IDX 0 908 #define regGDS_VM_PROTECTION_FAULT 0x05c4 909 #define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 910 #define regGDS_EDC_CNT 0x05c5 911 #define regGDS_EDC_CNT_BASE_IDX 0 912 #define regGDS_EDC_GRBM_CNT 0x05c6 913 #define regGDS_EDC_GRBM_CNT_BASE_IDX 0 914 #define regGDS_EDC_OA_DED 0x05c7 915 #define regGDS_EDC_OA_DED_BASE_IDX 0 916 #define regGDS_DSM_CNTL 0x05ca 917 #define regGDS_DSM_CNTL_BASE_IDX 0 918 #define regGDS_EDC_OA_PHY_CNT 0x05cb 919 #define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 920 #define regGDS_EDC_OA_PIPE_CNT 0x05cc 921 #define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 922 #define regGDS_DSM_CNTL2 0x05cd 923 #define regGDS_DSM_CNTL2_BASE_IDX 0 924 #define regGDS_WD_GDS_CSB 0x05ce 925 #define regGDS_WD_GDS_CSB_BASE_IDX 0 926 927 928 // addressBlock: xcd0_gc_rbdec 929 // base address: 0x9800 930 #define regDB_DEBUG 0x060c 931 #define regDB_DEBUG_BASE_IDX 0 932 #define regDB_DEBUG2 0x060d 933 #define regDB_DEBUG2_BASE_IDX 0 934 #define regDB_DEBUG3 0x060e 935 #define regDB_DEBUG3_BASE_IDX 0 936 #define regDB_DEBUG4 0x060f 937 #define regDB_DEBUG4_BASE_IDX 0 938 #define regDB_CREDIT_LIMIT 0x0614 939 #define regDB_CREDIT_LIMIT_BASE_IDX 0 940 #define regDB_WATERMARKS 0x0615 941 #define regDB_WATERMARKS_BASE_IDX 0 942 #define regDB_SUBTILE_CONTROL 0x0616 943 #define regDB_SUBTILE_CONTROL_BASE_IDX 0 944 #define regDB_FREE_CACHELINES 0x0617 945 #define regDB_FREE_CACHELINES_BASE_IDX 0 946 #define regDB_FIFO_DEPTH1 0x0618 947 #define regDB_FIFO_DEPTH1_BASE_IDX 0 948 #define regDB_FIFO_DEPTH2 0x0619 949 #define regDB_FIFO_DEPTH2_BASE_IDX 0 950 #define regDB_EXCEPTION_CONTROL 0x061a 951 #define regDB_EXCEPTION_CONTROL_BASE_IDX 0 952 #define regDB_RING_CONTROL 0x061b 953 #define regDB_RING_CONTROL_BASE_IDX 0 954 #define regDB_MEM_ARB_WATERMARKS 0x061c 955 #define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 956 #define regDB_RMI_CACHE_POLICY 0x061e 957 #define regDB_RMI_CACHE_POLICY_BASE_IDX 0 958 #define regDB_DFSM_CONFIG 0x0630 959 #define regDB_DFSM_CONFIG_BASE_IDX 0 960 #define regDB_DFSM_WATERMARK 0x0631 961 #define regDB_DFSM_WATERMARK_BASE_IDX 0 962 #define regDB_DFSM_TILES_IN_FLIGHT 0x0632 963 #define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 964 #define regDB_DFSM_PRIMS_IN_FLIGHT 0x0633 965 #define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 966 #define regDB_DFSM_WATCHDOG 0x0634 967 #define regDB_DFSM_WATCHDOG_BASE_IDX 0 968 #define regDB_DFSM_FLUSH_ENABLE 0x0635 969 #define regDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 970 #define regDB_DFSM_FLUSH_AUX_EVENT 0x0636 971 #define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 972 #define regCC_RB_REDUNDANCY 0x063c 973 #define regCC_RB_REDUNDANCY_BASE_IDX 0 974 #define regCC_RB_BACKEND_DISABLE 0x063d 975 #define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 976 #define regGB_ADDR_CONFIG 0x063e 977 #define regGB_ADDR_CONFIG_BASE_IDX 0 978 #define regGB_BACKEND_MAP 0x063f 979 #define regGB_BACKEND_MAP_BASE_IDX 0 980 #define regGB_GPU_ID 0x0640 981 #define regGB_GPU_ID_BASE_IDX 0 982 #define regCC_RB_DAISY_CHAIN 0x0641 983 #define regCC_RB_DAISY_CHAIN_BASE_IDX 0 984 #define regGB_ADDR_CONFIG_READ 0x0642 985 #define regGB_ADDR_CONFIG_READ_BASE_IDX 0 986 #define regGB_TILE_MODE0 0x0644 987 #define regGB_TILE_MODE0_BASE_IDX 0 988 #define regGB_TILE_MODE1 0x0645 989 #define regGB_TILE_MODE1_BASE_IDX 0 990 #define regGB_TILE_MODE2 0x0646 991 #define regGB_TILE_MODE2_BASE_IDX 0 992 #define regGB_TILE_MODE3 0x0647 993 #define regGB_TILE_MODE3_BASE_IDX 0 994 #define regGB_TILE_MODE4 0x0648 995 #define regGB_TILE_MODE4_BASE_IDX 0 996 #define regGB_TILE_MODE5 0x0649 997 #define regGB_TILE_MODE5_BASE_IDX 0 998 #define regGB_TILE_MODE6 0x064a 999 #define regGB_TILE_MODE6_BASE_IDX 0 1000 #define regGB_TILE_MODE7 0x064b 1001 #define regGB_TILE_MODE7_BASE_IDX 0 1002 #define regGB_TILE_MODE8 0x064c 1003 #define regGB_TILE_MODE8_BASE_IDX 0 1004 #define regGB_TILE_MODE9 0x064d 1005 #define regGB_TILE_MODE9_BASE_IDX 0 1006 #define regGB_TILE_MODE10 0x064e 1007 #define regGB_TILE_MODE10_BASE_IDX 0 1008 #define regGB_TILE_MODE11 0x064f 1009 #define regGB_TILE_MODE11_BASE_IDX 0 1010 #define regGB_TILE_MODE12 0x0650 1011 #define regGB_TILE_MODE12_BASE_IDX 0 1012 #define regGB_TILE_MODE13 0x0651 1013 #define regGB_TILE_MODE13_BASE_IDX 0 1014 #define regGB_TILE_MODE14 0x0652 1015 #define regGB_TILE_MODE14_BASE_IDX 0 1016 #define regGB_TILE_MODE15 0x0653 1017 #define regGB_TILE_MODE15_BASE_IDX 0 1018 #define regGB_TILE_MODE16 0x0654 1019 #define regGB_TILE_MODE16_BASE_IDX 0 1020 #define regGB_TILE_MODE17 0x0655 1021 #define regGB_TILE_MODE17_BASE_IDX 0 1022 #define regGB_TILE_MODE18 0x0656 1023 #define regGB_TILE_MODE18_BASE_IDX 0 1024 #define regGB_TILE_MODE19 0x0657 1025 #define regGB_TILE_MODE19_BASE_IDX 0 1026 #define regGB_TILE_MODE20 0x0658 1027 #define regGB_TILE_MODE20_BASE_IDX 0 1028 #define regGB_TILE_MODE21 0x0659 1029 #define regGB_TILE_MODE21_BASE_IDX 0 1030 #define regGB_TILE_MODE22 0x065a 1031 #define regGB_TILE_MODE22_BASE_IDX 0 1032 #define regGB_TILE_MODE23 0x065b 1033 #define regGB_TILE_MODE23_BASE_IDX 0 1034 #define regGB_TILE_MODE24 0x065c 1035 #define regGB_TILE_MODE24_BASE_IDX 0 1036 #define regGB_TILE_MODE25 0x065d 1037 #define regGB_TILE_MODE25_BASE_IDX 0 1038 #define regGB_TILE_MODE26 0x065e 1039 #define regGB_TILE_MODE26_BASE_IDX 0 1040 #define regGB_TILE_MODE27 0x065f 1041 #define regGB_TILE_MODE27_BASE_IDX 0 1042 #define regGB_TILE_MODE28 0x0660 1043 #define regGB_TILE_MODE28_BASE_IDX 0 1044 #define regGB_TILE_MODE29 0x0661 1045 #define regGB_TILE_MODE29_BASE_IDX 0 1046 #define regGB_TILE_MODE30 0x0662 1047 #define regGB_TILE_MODE30_BASE_IDX 0 1048 #define regGB_TILE_MODE31 0x0663 1049 #define regGB_TILE_MODE31_BASE_IDX 0 1050 #define regGB_MACROTILE_MODE0 0x0664 1051 #define regGB_MACROTILE_MODE0_BASE_IDX 0 1052 #define regGB_MACROTILE_MODE1 0x0665 1053 #define regGB_MACROTILE_MODE1_BASE_IDX 0 1054 #define regGB_MACROTILE_MODE2 0x0666 1055 #define regGB_MACROTILE_MODE2_BASE_IDX 0 1056 #define regGB_MACROTILE_MODE3 0x0667 1057 #define regGB_MACROTILE_MODE3_BASE_IDX 0 1058 #define regGB_MACROTILE_MODE4 0x0668 1059 #define regGB_MACROTILE_MODE4_BASE_IDX 0 1060 #define regGB_MACROTILE_MODE5 0x0669 1061 #define regGB_MACROTILE_MODE5_BASE_IDX 0 1062 #define regGB_MACROTILE_MODE6 0x066a 1063 #define regGB_MACROTILE_MODE6_BASE_IDX 0 1064 #define regGB_MACROTILE_MODE7 0x066b 1065 #define regGB_MACROTILE_MODE7_BASE_IDX 0 1066 #define regGB_MACROTILE_MODE8 0x066c 1067 #define regGB_MACROTILE_MODE8_BASE_IDX 0 1068 #define regGB_MACROTILE_MODE9 0x066d 1069 #define regGB_MACROTILE_MODE9_BASE_IDX 0 1070 #define regGB_MACROTILE_MODE10 0x066e 1071 #define regGB_MACROTILE_MODE10_BASE_IDX 0 1072 #define regGB_MACROTILE_MODE11 0x066f 1073 #define regGB_MACROTILE_MODE11_BASE_IDX 0 1074 #define regGB_MACROTILE_MODE12 0x0670 1075 #define regGB_MACROTILE_MODE12_BASE_IDX 0 1076 #define regGB_MACROTILE_MODE13 0x0671 1077 #define regGB_MACROTILE_MODE13_BASE_IDX 0 1078 #define regGB_MACROTILE_MODE14 0x0672 1079 #define regGB_MACROTILE_MODE14_BASE_IDX 0 1080 #define regGB_MACROTILE_MODE15 0x0673 1081 #define regGB_MACROTILE_MODE15_BASE_IDX 0 1082 #define regCB_HW_CONTROL 0x0680 1083 #define regCB_HW_CONTROL_BASE_IDX 0 1084 #define regCB_HW_CONTROL_1 0x0681 1085 #define regCB_HW_CONTROL_1_BASE_IDX 0 1086 #define regCB_HW_CONTROL_2 0x0682 1087 #define regCB_HW_CONTROL_2_BASE_IDX 0 1088 #define regCB_HW_CONTROL_3 0x0683 1089 #define regCB_HW_CONTROL_3_BASE_IDX 0 1090 #define regCB_HW_MEM_ARBITER_RD 0x0686 1091 #define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 1092 #define regCB_HW_MEM_ARBITER_WR 0x0687 1093 #define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 1094 #define regCB_DCC_CONFIG 0x0688 1095 #define regCB_DCC_CONFIG_BASE_IDX 0 1096 #define regGC_USER_RB_REDUNDANCY 0x06de 1097 #define regGC_USER_RB_REDUNDANCY_BASE_IDX 0 1098 #define regGC_USER_RB_BACKEND_DISABLE 0x06df 1099 #define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 1100 1101 1102 // addressBlock: xcd0_gc_ea_gceadec 1103 // base address: 0xa800 1104 #define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 1105 #define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1106 #define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 1107 #define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1108 #define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 1109 #define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1110 #define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 1111 #define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1112 #define regGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 1113 #define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1114 #define regGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 1115 #define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1116 #define regGCEA_DRAM_RD_LAZY 0x0a06 1117 #define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 1118 #define regGCEA_DRAM_WR_LAZY 0x0a07 1119 #define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 1120 #define regGCEA_DRAM_RD_CAM_CNTL 0x0a08 1121 #define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 1122 #define regGCEA_DRAM_WR_CAM_CNTL 0x0a09 1123 #define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 1124 #define regGCEA_DRAM_PAGE_BURST 0x0a0a 1125 #define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 1126 #define regGCEA_DRAM_RD_PRI_AGE 0x0a0b 1127 #define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 1128 #define regGCEA_DRAM_WR_PRI_AGE 0x0a0c 1129 #define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 1130 #define regGCEA_DRAM_RD_PRI_QUEUING 0x0a0d 1131 #define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 1132 #define regGCEA_DRAM_WR_PRI_QUEUING 0x0a0e 1133 #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 1134 #define regGCEA_DRAM_RD_PRI_FIXED 0x0a0f 1135 #define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 1136 #define regGCEA_DRAM_WR_PRI_FIXED 0x0a10 1137 #define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 1138 #define regGCEA_DRAM_RD_PRI_URGENCY 0x0a11 1139 #define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 1140 #define regGCEA_DRAM_WR_PRI_URGENCY 0x0a12 1141 #define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 1142 #define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 1143 #define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 1144 #define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 1145 #define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 1146 #define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 1147 #define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 1148 #define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 1149 #define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 1150 #define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 1151 #define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 1152 #define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 1153 #define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 1154 #define regGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5 1155 #define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1156 #define regGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6 1157 #define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1158 #define regGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7 1159 #define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1160 #define regGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8 1161 #define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1162 #define regGCEA_IO_RD_COMBINE_FLUSH 0x0ad9 1163 #define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1164 #define regGCEA_IO_WR_COMBINE_FLUSH 0x0ada 1165 #define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1166 #define regGCEA_IO_GROUP_BURST 0x0adb 1167 #define regGCEA_IO_GROUP_BURST_BASE_IDX 0 1168 #define regGCEA_IO_RD_PRI_AGE 0x0adc 1169 #define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 1170 #define regGCEA_IO_WR_PRI_AGE 0x0add 1171 #define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 1172 #define regGCEA_IO_RD_PRI_QUEUING 0x0ade 1173 #define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 1174 #define regGCEA_IO_WR_PRI_QUEUING 0x0adf 1175 #define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 1176 #define regGCEA_IO_RD_PRI_FIXED 0x0ae0 1177 #define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 1178 #define regGCEA_IO_WR_PRI_FIXED 0x0ae1 1179 #define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 1180 #define regGCEA_IO_RD_PRI_URGENCY 0x0ae2 1181 #define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 1182 #define regGCEA_IO_WR_PRI_URGENCY 0x0ae3 1183 #define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 1184 #define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x0ae4 1185 #define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1186 #define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x0ae5 1187 #define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1188 #define regGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6 1189 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1190 #define regGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7 1191 #define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1192 #define regGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8 1193 #define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1194 #define regGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9 1195 #define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1196 #define regGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea 1197 #define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1198 #define regGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb 1199 #define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1200 #define regGCEA_SDP_ARB_DRAM 0x0aec 1201 #define regGCEA_SDP_ARB_DRAM_BASE_IDX 0 1202 #define regGCEA_SDP_ARB_FINAL 0x0aee 1203 #define regGCEA_SDP_ARB_FINAL_BASE_IDX 0 1204 #define regGCEA_SDP_DRAM_PRIORITY 0x0aef 1205 #define regGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0 1206 #define regGCEA_SDP_IO_PRIORITY 0x0af1 1207 #define regGCEA_SDP_IO_PRIORITY_BASE_IDX 0 1208 #define regGCEA_SDP_CREDITS 0x0af2 1209 #define regGCEA_SDP_CREDITS_BASE_IDX 0 1210 #define regGCEA_SDP_TAG_RESERVE0 0x0af3 1211 #define regGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 1212 #define regGCEA_SDP_TAG_RESERVE1 0x0af4 1213 #define regGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 1214 #define regGCEA_SDP_VCC_RESERVE0 0x0af5 1215 #define regGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 1216 #define regGCEA_SDP_VCC_RESERVE1 0x0af6 1217 #define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 1218 #define regGCEA_SDP_VCD_RESERVE0 0x0af7 1219 #define regGCEA_SDP_VCD_RESERVE0_BASE_IDX 0 1220 #define regGCEA_SDP_VCD_RESERVE1 0x0af8 1221 #define regGCEA_SDP_VCD_RESERVE1_BASE_IDX 0 1222 #define regGCEA_SDP_REQ_CNTL 0x0af9 1223 #define regGCEA_SDP_REQ_CNTL_BASE_IDX 0 1224 #define regGCEA_MISC 0x0afa 1225 #define regGCEA_MISC_BASE_IDX 0 1226 #define regGCEA_LATENCY_SAMPLING 0x0afb 1227 #define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 1228 #define regGCEA_PERFCOUNTER_LO 0x0afc 1229 #define regGCEA_PERFCOUNTER_LO_BASE_IDX 0 1230 #define regGCEA_PERFCOUNTER_HI 0x0afd 1231 #define regGCEA_PERFCOUNTER_HI_BASE_IDX 0 1232 #define regGCEA_PERFCOUNTER0_CFG 0x0afe 1233 #define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 1234 #define regGCEA_PERFCOUNTER1_CFG 0x0aff 1235 #define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 1236 1237 1238 // addressBlock: xcd0_gc_ea_gceadec2 1239 // base address: 0x9c00 1240 #define regGCEA_PERFCOUNTER_RSLT_CNTL 0x0700 1241 #define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1242 #define regGCEA_MAM_CTRL 0x0701 1243 #define regGCEA_MAM_CTRL_BASE_IDX 0 1244 #define regGCEA_MAM_CTRL2 0x0702 1245 #define regGCEA_MAM_CTRL2_BASE_IDX 0 1246 #define regGCEA_DSM_CNTL 0x0708 1247 #define regGCEA_DSM_CNTL_BASE_IDX 0 1248 #define regGCEA_DSM_CNTLA 0x0709 1249 #define regGCEA_DSM_CNTLA_BASE_IDX 0 1250 #define regGCEA_DSM_CNTLB 0x070a 1251 #define regGCEA_DSM_CNTLB_BASE_IDX 0 1252 #define regGCEA_DSM_CNTL2 0x070b 1253 #define regGCEA_DSM_CNTL2_BASE_IDX 0 1254 #define regGCEA_DSM_CNTL2A 0x070c 1255 #define regGCEA_DSM_CNTL2A_BASE_IDX 0 1256 #define regGCEA_DSM_CNTL2B 0x070d 1257 #define regGCEA_DSM_CNTL2B_BASE_IDX 0 1258 #define regGCEA_TCC_XBR_CREDITS 0x070e 1259 #define regGCEA_TCC_XBR_CREDITS_BASE_IDX 0 1260 #define regGCEA_TCC_XBR_MAXBURST 0x070f 1261 #define regGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 1262 #define regGCEA_PROBE_CNTL 0x0710 1263 #define regGCEA_PROBE_CNTL_BASE_IDX 0 1264 #define regGCEA_PROBE_MAP 0x0711 1265 #define regGCEA_PROBE_MAP_BASE_IDX 0 1266 #define regGCEA_ERR_STATUS 0x0712 1267 #define regGCEA_ERR_STATUS_BASE_IDX 0 1268 #define regGCEA_MISC2 0x0713 1269 #define regGCEA_MISC2_BASE_IDX 0 1270 #define regGCEA_SDP_BACKDOOR_CMDCREDITS0 0x0715 1271 #define regGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 1272 #define regGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0716 1273 #define regGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 1274 #define regGCEA_SDP_BACKDOOR_DATACREDITS0 0x0717 1275 #define regGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 1276 #define regGCEA_SDP_BACKDOOR_DATACREDITS1 0x0718 1277 #define regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 1278 #define regGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719 1279 #define regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 1280 #define regGCEA_SDP_ENABLE 0x071f 1281 #define regGCEA_SDP_ENABLE_BASE_IDX 0 1282 1283 1284 // addressBlock: xcd0_gc_ea_pwrdec 1285 // base address: 0x3c000 1286 #define regGCEA_ICG_CTRL 0x50c4 1287 #define regGCEA_ICG_CTRL_BASE_IDX 1 1288 1289 1290 // addressBlock: xcd0_gc_rmi_rmidec 1291 // base address: 0x9e00 1292 #define regRMI_GENERAL_CNTL 0x0780 1293 #define regRMI_GENERAL_CNTL_BASE_IDX 0 1294 #define regRMI_GENERAL_CNTL1 0x0781 1295 #define regRMI_GENERAL_CNTL1_BASE_IDX 0 1296 #define regRMI_GENERAL_STATUS 0x0782 1297 #define regRMI_GENERAL_STATUS_BASE_IDX 0 1298 #define regRMI_SUBBLOCK_STATUS0 0x0783 1299 #define regRMI_SUBBLOCK_STATUS0_BASE_IDX 0 1300 #define regRMI_SUBBLOCK_STATUS1 0x0784 1301 #define regRMI_SUBBLOCK_STATUS1_BASE_IDX 0 1302 #define regRMI_SUBBLOCK_STATUS2 0x0785 1303 #define regRMI_SUBBLOCK_STATUS2_BASE_IDX 0 1304 #define regRMI_SUBBLOCK_STATUS3 0x0786 1305 #define regRMI_SUBBLOCK_STATUS3_BASE_IDX 0 1306 #define regRMI_XBAR_CONFIG 0x0787 1307 #define regRMI_XBAR_CONFIG_BASE_IDX 0 1308 #define regRMI_PROBE_POP_LOGIC_CNTL 0x0788 1309 #define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 1310 #define regRMI_UTC_XNACK_N_MISC_CNTL 0x0789 1311 #define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 1312 #define regRMI_DEMUX_CNTL 0x078a 1313 #define regRMI_DEMUX_CNTL_BASE_IDX 0 1314 #define regRMI_UTCL1_CNTL1 0x078b 1315 #define regRMI_UTCL1_CNTL1_BASE_IDX 0 1316 #define regRMI_UTCL1_CNTL2 0x078c 1317 #define regRMI_UTCL1_CNTL2_BASE_IDX 0 1318 #define regRMI_UTC_UNIT_CONFIG 0x078d 1319 #define regRMI_UTC_UNIT_CONFIG_BASE_IDX 0 1320 #define regRMI_TCIW_FORMATTER0_CNTL 0x078e 1321 #define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 1322 #define regRMI_TCIW_FORMATTER1_CNTL 0x078f 1323 #define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 1324 #define regRMI_SCOREBOARD_CNTL 0x0790 1325 #define regRMI_SCOREBOARD_CNTL_BASE_IDX 0 1326 #define regRMI_SCOREBOARD_STATUS0 0x0791 1327 #define regRMI_SCOREBOARD_STATUS0_BASE_IDX 0 1328 #define regRMI_SCOREBOARD_STATUS1 0x0792 1329 #define regRMI_SCOREBOARD_STATUS1_BASE_IDX 0 1330 #define regRMI_SCOREBOARD_STATUS2 0x0793 1331 #define regRMI_SCOREBOARD_STATUS2_BASE_IDX 0 1332 #define regRMI_XBAR_ARBITER_CONFIG 0x0794 1333 #define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 1334 #define regRMI_XBAR_ARBITER_CONFIG_1 0x0795 1335 #define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 1336 #define regRMI_CLOCK_CNTRL 0x0796 1337 #define regRMI_CLOCK_CNTRL_BASE_IDX 0 1338 #define regRMI_UTCL1_STATUS 0x0797 1339 #define regRMI_UTCL1_STATUS_BASE_IDX 0 1340 #define regRMI_XNACK_DEBUG 0x079d 1341 #define regRMI_XNACK_DEBUG_BASE_IDX 0 1342 #define regRMI_SPARE 0x079e 1343 #define regRMI_SPARE_BASE_IDX 0 1344 #define regRMI_SPARE_1 0x079f 1345 #define regRMI_SPARE_1_BASE_IDX 0 1346 #define regRMI_SPARE_2 0x07a0 1347 #define regRMI_SPARE_2_BASE_IDX 0 1348 1349 1350 // addressBlock: xcd0_gc_utcl2_atcl2dec 1351 // base address: 0xa000 1352 #define regATC_L2_CNTL 0x0800 1353 #define regATC_L2_CNTL_BASE_IDX 0 1354 #define regATC_L2_CNTL2 0x0801 1355 #define regATC_L2_CNTL2_BASE_IDX 0 1356 #define regATC_L2_CACHE_DATA0 0x0804 1357 #define regATC_L2_CACHE_DATA0_BASE_IDX 0 1358 #define regATC_L2_CACHE_DATA1 0x0805 1359 #define regATC_L2_CACHE_DATA1_BASE_IDX 0 1360 #define regATC_L2_CACHE_DATA2 0x0806 1361 #define regATC_L2_CACHE_DATA2_BASE_IDX 0 1362 #define regATC_L2_CACHE_DATA3 0x0807 1363 #define regATC_L2_CACHE_DATA3_BASE_IDX 0 1364 #define regATC_L2_CNTL3 0x0808 1365 #define regATC_L2_CNTL3_BASE_IDX 0 1366 #define regATC_L2_STATUS 0x0809 1367 #define regATC_L2_STATUS_BASE_IDX 0 1368 #define regATC_L2_STATUS2 0x080a 1369 #define regATC_L2_STATUS2_BASE_IDX 0 1370 #define regATC_L2_MISC_CG 0x080b 1371 #define regATC_L2_MISC_CG_BASE_IDX 0 1372 #define regATC_L2_MEM_POWER_LS 0x080c 1373 #define regATC_L2_MEM_POWER_LS_BASE_IDX 0 1374 #define regATC_L2_CGTT_CLK_CTRL 0x080d 1375 #define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1376 #define regATC_L2_CACHE_4K_DSM_INDEX 0x080f 1377 #define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 1378 #define regATC_L2_CACHE_32K_DSM_INDEX 0x0810 1379 #define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 1380 #define regATC_L2_CACHE_2M_DSM_INDEX 0x0811 1381 #define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 1382 #define regATC_L2_CACHE_4K_DSM_CNTL 0x0812 1383 #define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 1384 #define regATC_L2_CACHE_32K_DSM_CNTL 0x0813 1385 #define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 1386 #define regATC_L2_CACHE_2M_DSM_CNTL 0x0814 1387 #define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 1388 #define regATC_L2_CNTL4 0x0815 1389 #define regATC_L2_CNTL4_BASE_IDX 0 1390 #define regATC_L2_MM_GROUP_RT_CLASSES 0x0816 1391 #define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1392 1393 1394 // addressBlock: xcd0_gc_utcl2_vml2pfdec 1395 // base address: 0xa080 1396 #define regVM_L2_CNTL 0x0820 1397 #define regVM_L2_CNTL_BASE_IDX 0 1398 #define regVM_L2_CNTL2 0x0821 1399 #define regVM_L2_CNTL2_BASE_IDX 0 1400 #define regVM_L2_CNTL3 0x0822 1401 #define regVM_L2_CNTL3_BASE_IDX 0 1402 #define regVM_L2_STATUS 0x0823 1403 #define regVM_L2_STATUS_BASE_IDX 0 1404 #define regVM_DUMMY_PAGE_FAULT_CNTL 0x0824 1405 #define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1406 #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0825 1407 #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1408 #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0826 1409 #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1410 #define regVM_L2_PROTECTION_FAULT_CNTL 0x0827 1411 #define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1412 #define regVM_L2_PROTECTION_FAULT_CNTL2 0x0828 1413 #define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1414 #define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0829 1415 #define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1416 #define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x082a 1417 #define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1418 #define regVM_L2_PROTECTION_FAULT_STATUS 0x082b 1419 #define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1420 #define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x082c 1421 #define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1422 #define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x082d 1423 #define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1424 #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x082e 1425 #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1426 #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x082f 1427 #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1428 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0831 1429 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1430 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0832 1431 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1432 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0833 1433 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1434 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0834 1435 #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1436 #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0835 1437 #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1438 #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0836 1439 #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1440 #define regVM_L2_CNTL4 0x0837 1441 #define regVM_L2_CNTL4_BASE_IDX 0 1442 #define regVM_L2_CNTL5 0x0838 1443 #define regVM_L2_CNTL5_BASE_IDX 0 1444 #define regVM_L2_MM_GROUP_RT_CLASSES 0x0839 1445 #define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1446 #define regVM_L2_BANK_SELECT_RESERVED_CID 0x083a 1447 #define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1448 #define regVM_L2_BANK_SELECT_RESERVED_CID2 0x083b 1449 #define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1450 #define regVM_L2_CACHE_PARITY_CNTL 0x083c 1451 #define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1452 #define regVM_L2_CGTT_CLK_CTRL 0x083d 1453 #define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1454 #define regVM_L2_CGTT_BUSY_CTRL 0x083e 1455 #define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 1456 #define regVML2_MEM_ECC_INDEX 0x0842 1457 #define regVML2_MEM_ECC_INDEX_BASE_IDX 0 1458 #define regVML2_WALKER_MEM_ECC_INDEX 0x0843 1459 #define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 1460 #define regUTCL2_MEM_ECC_INDEX 0x0844 1461 #define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 1462 #define regVML2_MEM_ECC_CNTL 0x0845 1463 #define regVML2_MEM_ECC_CNTL_BASE_IDX 0 1464 #define regVML2_WALKER_MEM_ECC_CNTL 0x0846 1465 #define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 1466 #define regUTCL2_MEM_ECC_CNTL 0x0847 1467 #define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 1468 #define regVML2_MEM_ECC_STATUS 0x0848 1469 #define regVML2_MEM_ECC_STATUS_BASE_IDX 0 1470 #define regVML2_WALKER_MEM_ECC_STATUS 0x0849 1471 #define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 1472 #define regUTCL2_MEM_ECC_STATUS 0x084a 1473 #define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 1474 #define regUTCL2_EDC_MODE 0x084b 1475 #define regUTCL2_EDC_MODE_BASE_IDX 0 1476 #define regUTCL2_EDC_CONFIG 0x084c 1477 #define regUTCL2_EDC_CONFIG_BASE_IDX 0 1478 1479 1480 // addressBlock: xcd0_gc_utcl2_vml2vcdec 1481 // base address: 0xa180 1482 #define regVM_CONTEXT0_CNTL 0x0860 1483 #define regVM_CONTEXT0_CNTL_BASE_IDX 0 1484 #define regVM_CONTEXT1_CNTL 0x0861 1485 #define regVM_CONTEXT1_CNTL_BASE_IDX 0 1486 #define regVM_CONTEXT2_CNTL 0x0862 1487 #define regVM_CONTEXT2_CNTL_BASE_IDX 0 1488 #define regVM_CONTEXT3_CNTL 0x0863 1489 #define regVM_CONTEXT3_CNTL_BASE_IDX 0 1490 #define regVM_CONTEXT4_CNTL 0x0864 1491 #define regVM_CONTEXT4_CNTL_BASE_IDX 0 1492 #define regVM_CONTEXT5_CNTL 0x0865 1493 #define regVM_CONTEXT5_CNTL_BASE_IDX 0 1494 #define regVM_CONTEXT6_CNTL 0x0866 1495 #define regVM_CONTEXT6_CNTL_BASE_IDX 0 1496 #define regVM_CONTEXT7_CNTL 0x0867 1497 #define regVM_CONTEXT7_CNTL_BASE_IDX 0 1498 #define regVM_CONTEXT8_CNTL 0x0868 1499 #define regVM_CONTEXT8_CNTL_BASE_IDX 0 1500 #define regVM_CONTEXT9_CNTL 0x0869 1501 #define regVM_CONTEXT9_CNTL_BASE_IDX 0 1502 #define regVM_CONTEXT10_CNTL 0x086a 1503 #define regVM_CONTEXT10_CNTL_BASE_IDX 0 1504 #define regVM_CONTEXT11_CNTL 0x086b 1505 #define regVM_CONTEXT11_CNTL_BASE_IDX 0 1506 #define regVM_CONTEXT12_CNTL 0x086c 1507 #define regVM_CONTEXT12_CNTL_BASE_IDX 0 1508 #define regVM_CONTEXT13_CNTL 0x086d 1509 #define regVM_CONTEXT13_CNTL_BASE_IDX 0 1510 #define regVM_CONTEXT14_CNTL 0x086e 1511 #define regVM_CONTEXT14_CNTL_BASE_IDX 0 1512 #define regVM_CONTEXT15_CNTL 0x086f 1513 #define regVM_CONTEXT15_CNTL_BASE_IDX 0 1514 #define regVM_CONTEXTS_DISABLE 0x0870 1515 #define regVM_CONTEXTS_DISABLE_BASE_IDX 0 1516 #define regVM_INVALIDATE_ENG0_SEM 0x0871 1517 #define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1518 #define regVM_INVALIDATE_ENG1_SEM 0x0872 1519 #define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1520 #define regVM_INVALIDATE_ENG2_SEM 0x0873 1521 #define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1522 #define regVM_INVALIDATE_ENG3_SEM 0x0874 1523 #define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1524 #define regVM_INVALIDATE_ENG4_SEM 0x0875 1525 #define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1526 #define regVM_INVALIDATE_ENG5_SEM 0x0876 1527 #define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1528 #define regVM_INVALIDATE_ENG6_SEM 0x0877 1529 #define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1530 #define regVM_INVALIDATE_ENG7_SEM 0x0878 1531 #define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1532 #define regVM_INVALIDATE_ENG8_SEM 0x0879 1533 #define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1534 #define regVM_INVALIDATE_ENG9_SEM 0x087a 1535 #define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1536 #define regVM_INVALIDATE_ENG10_SEM 0x087b 1537 #define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1538 #define regVM_INVALIDATE_ENG11_SEM 0x087c 1539 #define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1540 #define regVM_INVALIDATE_ENG12_SEM 0x087d 1541 #define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1542 #define regVM_INVALIDATE_ENG13_SEM 0x087e 1543 #define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1544 #define regVM_INVALIDATE_ENG14_SEM 0x087f 1545 #define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1546 #define regVM_INVALIDATE_ENG15_SEM 0x0880 1547 #define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1548 #define regVM_INVALIDATE_ENG16_SEM 0x0881 1549 #define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1550 #define regVM_INVALIDATE_ENG17_SEM 0x0882 1551 #define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1552 #define regVM_INVALIDATE_ENG0_REQ 0x0883 1553 #define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1554 #define regVM_INVALIDATE_ENG1_REQ 0x0884 1555 #define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1556 #define regVM_INVALIDATE_ENG2_REQ 0x0885 1557 #define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1558 #define regVM_INVALIDATE_ENG3_REQ 0x0886 1559 #define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1560 #define regVM_INVALIDATE_ENG4_REQ 0x0887 1561 #define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1562 #define regVM_INVALIDATE_ENG5_REQ 0x0888 1563 #define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1564 #define regVM_INVALIDATE_ENG6_REQ 0x0889 1565 #define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1566 #define regVM_INVALIDATE_ENG7_REQ 0x088a 1567 #define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1568 #define regVM_INVALIDATE_ENG8_REQ 0x088b 1569 #define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1570 #define regVM_INVALIDATE_ENG9_REQ 0x088c 1571 #define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1572 #define regVM_INVALIDATE_ENG10_REQ 0x088d 1573 #define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1574 #define regVM_INVALIDATE_ENG11_REQ 0x088e 1575 #define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1576 #define regVM_INVALIDATE_ENG12_REQ 0x088f 1577 #define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1578 #define regVM_INVALIDATE_ENG13_REQ 0x0890 1579 #define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1580 #define regVM_INVALIDATE_ENG14_REQ 0x0891 1581 #define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1582 #define regVM_INVALIDATE_ENG15_REQ 0x0892 1583 #define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1584 #define regVM_INVALIDATE_ENG16_REQ 0x0893 1585 #define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1586 #define regVM_INVALIDATE_ENG17_REQ 0x0894 1587 #define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1588 #define regVM_INVALIDATE_ENG0_ACK 0x0895 1589 #define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1590 #define regVM_INVALIDATE_ENG1_ACK 0x0896 1591 #define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1592 #define regVM_INVALIDATE_ENG2_ACK 0x0897 1593 #define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1594 #define regVM_INVALIDATE_ENG3_ACK 0x0898 1595 #define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1596 #define regVM_INVALIDATE_ENG4_ACK 0x0899 1597 #define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1598 #define regVM_INVALIDATE_ENG5_ACK 0x089a 1599 #define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1600 #define regVM_INVALIDATE_ENG6_ACK 0x089b 1601 #define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1602 #define regVM_INVALIDATE_ENG7_ACK 0x089c 1603 #define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1604 #define regVM_INVALIDATE_ENG8_ACK 0x089d 1605 #define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1606 #define regVM_INVALIDATE_ENG9_ACK 0x089e 1607 #define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1608 #define regVM_INVALIDATE_ENG10_ACK 0x089f 1609 #define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1610 #define regVM_INVALIDATE_ENG11_ACK 0x08a0 1611 #define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1612 #define regVM_INVALIDATE_ENG12_ACK 0x08a1 1613 #define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1614 #define regVM_INVALIDATE_ENG13_ACK 0x08a2 1615 #define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1616 #define regVM_INVALIDATE_ENG14_ACK 0x08a3 1617 #define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1618 #define regVM_INVALIDATE_ENG15_ACK 0x08a4 1619 #define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1620 #define regVM_INVALIDATE_ENG16_ACK 0x08a5 1621 #define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1622 #define regVM_INVALIDATE_ENG17_ACK 0x08a6 1623 #define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1624 #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08a7 1625 #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1626 #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08a8 1627 #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1628 #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08a9 1629 #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1630 #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08aa 1631 #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1632 #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08ab 1633 #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1634 #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08ac 1635 #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1636 #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08ad 1637 #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1638 #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ae 1639 #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1640 #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08af 1641 #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1642 #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08b0 1643 #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1644 #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08b1 1645 #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1646 #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08b2 1647 #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1648 #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08b3 1649 #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1650 #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08b4 1651 #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1652 #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08b5 1653 #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1654 #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08b6 1655 #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1656 #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08b7 1657 #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1658 #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08b8 1659 #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1660 #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08b9 1661 #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1662 #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08ba 1663 #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1664 #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08bb 1665 #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1666 #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08bc 1667 #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1668 #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08bd 1669 #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1670 #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08be 1671 #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1672 #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08bf 1673 #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1674 #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08c0 1675 #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1676 #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08c1 1677 #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1678 #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08c2 1679 #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1680 #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08c3 1681 #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1682 #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08c4 1683 #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1684 #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08c5 1685 #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1686 #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08c6 1687 #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1688 #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08c7 1689 #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1690 #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08c8 1691 #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1692 #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08c9 1693 #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1694 #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ca 1695 #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1696 #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08cb 1697 #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1698 #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08cc 1699 #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1700 #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08cd 1701 #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1702 #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ce 1703 #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1704 #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08cf 1705 #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1706 #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08d0 1707 #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1708 #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08d1 1709 #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1710 #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08d2 1711 #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1712 #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08d3 1713 #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1714 #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08d4 1715 #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1716 #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08d5 1717 #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1718 #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08d6 1719 #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1720 #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08d7 1721 #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1722 #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08d8 1723 #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1724 #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08d9 1725 #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1726 #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08da 1727 #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1728 #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08db 1729 #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1730 #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08dc 1731 #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1732 #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08dd 1733 #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1734 #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08de 1735 #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1736 #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08df 1737 #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1738 #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x08e0 1739 #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1740 #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x08e1 1741 #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1742 #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x08e2 1743 #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1744 #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x08e3 1745 #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1746 #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x08e4 1747 #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1748 #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x08e5 1749 #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1750 #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x08e6 1751 #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1752 #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x08e7 1753 #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1754 #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x08e8 1755 #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1756 #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x08e9 1757 #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1758 #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x08ea 1759 #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1760 #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x08eb 1761 #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1762 #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x08ec 1763 #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1764 #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x08ed 1765 #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1766 #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x08ee 1767 #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1768 #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x08ef 1769 #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1770 #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x08f0 1771 #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1772 #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x08f1 1773 #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1774 #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x08f2 1775 #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1776 #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x08f3 1777 #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1778 #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x08f4 1779 #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1780 #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x08f5 1781 #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1782 #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x08f6 1783 #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1784 #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x08f7 1785 #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1786 #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x08f8 1787 #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1788 #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x08f9 1789 #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1790 #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x08fa 1791 #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1792 #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x08fb 1793 #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1794 #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x08fc 1795 #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1796 #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x08fd 1797 #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1798 #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x08fe 1799 #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1800 #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x08ff 1801 #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1802 #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0900 1803 #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1804 #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0901 1805 #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1806 #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0902 1807 #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1808 #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0903 1809 #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1810 #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0904 1811 #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1812 #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0905 1813 #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1814 #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0906 1815 #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1816 #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0907 1817 #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1818 #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0908 1819 #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1820 #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0909 1821 #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1822 #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x090a 1823 #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1824 #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x090b 1825 #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1826 #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x090c 1827 #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1828 #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x090d 1829 #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1830 #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x090e 1831 #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1832 #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x090f 1833 #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1834 #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0910 1835 #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1836 #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0911 1837 #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1838 #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0912 1839 #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1840 #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0913 1841 #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1842 #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0914 1843 #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1844 #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0915 1845 #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1846 #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0916 1847 #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1848 #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0917 1849 #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1850 #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0918 1851 #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1852 #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0919 1853 #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1854 #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x091a 1855 #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1856 #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x091b 1857 #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1858 #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x091c 1859 #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1860 #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x091d 1861 #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1862 #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x091e 1863 #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1864 #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x091f 1865 #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1866 #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0920 1867 #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1868 #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0921 1869 #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1870 #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0922 1871 #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1872 #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0923 1873 #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1874 #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0924 1875 #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1876 #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0925 1877 #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1878 #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0926 1879 #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1880 #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0927 1881 #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1882 #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0928 1883 #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1884 #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0929 1885 #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1886 #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x092a 1887 #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1888 1889 1890 // addressBlock: xcd0_gc_utcl2_vmsharedpfdec 1891 // base address: 0xa500 1892 #define regMC_VM_NB_MMIOBASE 0x0940 1893 #define regMC_VM_NB_MMIOBASE_BASE_IDX 0 1894 #define regMC_VM_NB_MMIOLIMIT 0x0941 1895 #define regMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1896 #define regMC_VM_NB_PCI_CTRL 0x0942 1897 #define regMC_VM_NB_PCI_CTRL_BASE_IDX 0 1898 #define regMC_VM_NB_PCI_ARB 0x0943 1899 #define regMC_VM_NB_PCI_ARB_BASE_IDX 0 1900 #define regMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0944 1901 #define regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1902 #define regMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0945 1903 #define regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1904 #define regMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0946 1905 #define regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1906 #define regMC_VM_FB_OFFSET 0x0947 1907 #define regMC_VM_FB_OFFSET_BASE_IDX 0 1908 #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0948 1909 #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1910 #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0949 1911 #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1912 #define regMC_VM_STEERING 0x094a 1913 #define regMC_VM_STEERING_BASE_IDX 0 1914 #define regMC_SHARED_VIRT_RESET_REQ 0x094b 1915 #define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1916 #define regMC_MEM_POWER_LS 0x094c 1917 #define regMC_MEM_POWER_LS_BASE_IDX 0 1918 #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x094d 1919 #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1920 #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x094e 1921 #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1922 #define regMC_VM_APT_CNTL 0x0951 1923 #define regMC_VM_APT_CNTL_BASE_IDX 0 1924 #define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0952 1925 #define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1926 #define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0953 1927 #define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1928 #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0954 1929 #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1930 #define regUTCL2_CGTT_CLK_CTRL 0x0955 1931 #define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 1932 #define regMC_VM_XGMI_LFB_CNTL 0x0957 1933 #define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 1934 #define regMC_VM_XGMI_LFB_SIZE 0x0958 1935 #define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 1936 #define regMC_VM_CACHEABLE_DRAM_CNTL 0x0959 1937 #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 1938 #define regMC_VM_HOST_MAPPING 0x095a 1939 #define regMC_VM_HOST_MAPPING_BASE_IDX 0 1940 1941 1942 // addressBlock: xcd0_gc_utcl2_vmsharedvcdec 1943 // base address: 0xa570 1944 #define regMC_VM_FB_LOCATION_BASE 0x095c 1945 #define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1946 #define regMC_VM_FB_LOCATION_TOP 0x095d 1947 #define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1948 #define regMC_VM_AGP_TOP 0x095e 1949 #define regMC_VM_AGP_TOP_BASE_IDX 0 1950 #define regMC_VM_AGP_BOT 0x095f 1951 #define regMC_VM_AGP_BOT_BASE_IDX 0 1952 #define regMC_VM_AGP_BASE 0x0960 1953 #define regMC_VM_AGP_BASE_BASE_IDX 0 1954 #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0961 1955 #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1956 #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0962 1957 #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1958 #define regMC_VM_MX_L1_TLB_CNTL 0x0963 1959 #define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1960 1961 1962 // addressBlock: xcd0_gc_utcl2_l2tlbdec 1963 // base address: 0xa5b0 1964 #define regL2TLB_TLB0_STATUS 0x096d 1965 #define regL2TLB_TLB0_STATUS_BASE_IDX 0 1966 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x096f 1967 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 1968 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0970 1969 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 1970 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0971 1971 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 1972 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0972 1973 #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 1974 1975 1976 // addressBlock: xcd0_gc_tcdec 1977 // base address: 0xac00 1978 #define regTCP_INVALIDATE 0x0b00 1979 #define regTCP_INVALIDATE_BASE_IDX 0 1980 #define regTCP_STATUS 0x0b01 1981 #define regTCP_STATUS_BASE_IDX 0 1982 #define regTCP_CNTL 0x0b02 1983 #define regTCP_CNTL_BASE_IDX 0 1984 #define regTCP_CHAN_STEER_0 0x0b03 1985 #define regTCP_CHAN_STEER_0_BASE_IDX 0 1986 #define regTCP_CHAN_STEER_1 0x0b04 1987 #define regTCP_CHAN_STEER_1_BASE_IDX 0 1988 #define regTCP_ADDR_CONFIG 0x0b05 1989 #define regTCP_ADDR_CONFIG_BASE_IDX 0 1990 #define regTCP_CREDIT 0x0b06 1991 #define regTCP_CREDIT_BASE_IDX 0 1992 #define regTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 1993 #define regTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 1994 #define regTC_CFG_L1_LOAD_POLICY0 0x0b1a 1995 #define regTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 1996 #define regTC_CFG_L1_LOAD_POLICY1 0x0b1b 1997 #define regTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 1998 #define regTC_CFG_L1_STORE_POLICY 0x0b1c 1999 #define regTC_CFG_L1_STORE_POLICY_BASE_IDX 0 2000 #define regTC_CFG_L2_LOAD_POLICY0 0x0b1d 2001 #define regTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 2002 #define regTC_CFG_L2_LOAD_POLICY1 0x0b1e 2003 #define regTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 2004 #define regTC_CFG_L2_STORE_POLICY0 0x0b1f 2005 #define regTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 2006 #define regTC_CFG_L2_STORE_POLICY1 0x0b20 2007 #define regTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 2008 #define regTC_CFG_L2_ATOMIC_POLICY 0x0b21 2009 #define regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 2010 #define regTC_CFG_L1_VOLATILE 0x0b22 2011 #define regTC_CFG_L1_VOLATILE_BASE_IDX 0 2012 #define regTC_CFG_L2_VOLATILE 0x0b23 2013 #define regTC_CFG_L2_VOLATILE_BASE_IDX 0 2014 #define regTCI_MISC 0x0b5c 2015 #define regTCI_MISC_BASE_IDX 0 2016 #define regTCI_CNTL_3 0x0b5d 2017 #define regTCI_CNTL_3_BASE_IDX 0 2018 #define regTCI_DSM_CNTL 0x0b5e 2019 #define regTCI_DSM_CNTL_BASE_IDX 0 2020 #define regTCI_DSM_CNTL2 0x0b5f 2021 #define regTCI_DSM_CNTL2_BASE_IDX 0 2022 #define regTCI_STATUS 0x0b61 2023 #define regTCI_STATUS_BASE_IDX 0 2024 #define regTCI_CNTL_1 0x0b62 2025 #define regTCI_CNTL_1_BASE_IDX 0 2026 #define regTCI_CNTL_2 0x0b63 2027 #define regTCI_CNTL_2_BASE_IDX 0 2028 #define regTCC_CTRL 0x0b80 2029 #define regTCC_CTRL_BASE_IDX 0 2030 #define regTCC_CTRL2 0x0b81 2031 #define regTCC_CTRL2_BASE_IDX 0 2032 #define regTCC_DSM_CNTL 0x0b86 2033 #define regTCC_DSM_CNTL_BASE_IDX 0 2034 #define regTCC_DSM_CNTLA 0x0b87 2035 #define regTCC_DSM_CNTLA_BASE_IDX 0 2036 #define regTCC_DSM_CNTL2 0x0b88 2037 #define regTCC_DSM_CNTL2_BASE_IDX 0 2038 #define regTCC_DSM_CNTL2A 0x0b89 2039 #define regTCC_DSM_CNTL2A_BASE_IDX 0 2040 #define regTCC_DSM_CNTL2B 0x0b8a 2041 #define regTCC_DSM_CNTL2B_BASE_IDX 0 2042 #define regTCC_WBINVL2 0x0b8b 2043 #define regTCC_WBINVL2_BASE_IDX 0 2044 #define regTCC_SOFT_RESET 0x0b8c 2045 #define regTCC_SOFT_RESET_BASE_IDX 0 2046 #define regTCC_DSM_CNTL3 0x0b8e 2047 #define regTCC_DSM_CNTL3_BASE_IDX 0 2048 #define regTCA_CTRL 0x0bc0 2049 #define regTCA_CTRL_BASE_IDX 0 2050 #define regTCA_BURST_MASK 0x0bc1 2051 #define regTCA_BURST_MASK_BASE_IDX 0 2052 #define regTCA_BURST_CTRL 0x0bc2 2053 #define regTCA_BURST_CTRL_BASE_IDX 0 2054 #define regTCA_DSM_CNTL 0x0bc3 2055 #define regTCA_DSM_CNTL_BASE_IDX 0 2056 #define regTCA_DSM_CNTL2 0x0bc4 2057 #define regTCA_DSM_CNTL2_BASE_IDX 0 2058 #define regTCX_CTRL 0x0bc6 2059 #define regTCX_CTRL_BASE_IDX 0 2060 #define regTCX_DSM_CNTL 0x0bc7 2061 #define regTCX_DSM_CNTL_BASE_IDX 0 2062 #define regTCX_DSM_CNTL2 0x0bc8 2063 #define regTCX_DSM_CNTL2_BASE_IDX 0 2064 2065 2066 // addressBlock: xcd0_gc_shdec 2067 // base address: 0xb000 2068 #define regSPI_SHADER_PGM_RSRC3_PS 0x0c07 2069 #define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 2070 #define regSPI_SHADER_PGM_LO_PS 0x0c08 2071 #define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 2072 #define regSPI_SHADER_PGM_HI_PS 0x0c09 2073 #define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 2074 #define regSPI_SHADER_PGM_RSRC1_PS 0x0c0a 2075 #define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 2076 #define regSPI_SHADER_PGM_RSRC2_PS 0x0c0b 2077 #define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 2078 #define regSPI_SHADER_USER_DATA_PS_0 0x0c0c 2079 #define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 2080 #define regSPI_SHADER_USER_DATA_PS_1 0x0c0d 2081 #define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 2082 #define regSPI_SHADER_USER_DATA_PS_2 0x0c0e 2083 #define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 2084 #define regSPI_SHADER_USER_DATA_PS_3 0x0c0f 2085 #define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 2086 #define regSPI_SHADER_USER_DATA_PS_4 0x0c10 2087 #define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 2088 #define regSPI_SHADER_USER_DATA_PS_5 0x0c11 2089 #define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 2090 #define regSPI_SHADER_USER_DATA_PS_6 0x0c12 2091 #define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 2092 #define regSPI_SHADER_USER_DATA_PS_7 0x0c13 2093 #define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 2094 #define regSPI_SHADER_USER_DATA_PS_8 0x0c14 2095 #define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 2096 #define regSPI_SHADER_USER_DATA_PS_9 0x0c15 2097 #define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 2098 #define regSPI_SHADER_USER_DATA_PS_10 0x0c16 2099 #define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 2100 #define regSPI_SHADER_USER_DATA_PS_11 0x0c17 2101 #define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 2102 #define regSPI_SHADER_USER_DATA_PS_12 0x0c18 2103 #define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 2104 #define regSPI_SHADER_USER_DATA_PS_13 0x0c19 2105 #define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 2106 #define regSPI_SHADER_USER_DATA_PS_14 0x0c1a 2107 #define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 2108 #define regSPI_SHADER_USER_DATA_PS_15 0x0c1b 2109 #define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 2110 #define regSPI_SHADER_USER_DATA_PS_16 0x0c1c 2111 #define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 2112 #define regSPI_SHADER_USER_DATA_PS_17 0x0c1d 2113 #define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 2114 #define regSPI_SHADER_USER_DATA_PS_18 0x0c1e 2115 #define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 2116 #define regSPI_SHADER_USER_DATA_PS_19 0x0c1f 2117 #define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 2118 #define regSPI_SHADER_USER_DATA_PS_20 0x0c20 2119 #define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 2120 #define regSPI_SHADER_USER_DATA_PS_21 0x0c21 2121 #define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 2122 #define regSPI_SHADER_USER_DATA_PS_22 0x0c22 2123 #define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 2124 #define regSPI_SHADER_USER_DATA_PS_23 0x0c23 2125 #define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 2126 #define regSPI_SHADER_USER_DATA_PS_24 0x0c24 2127 #define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 2128 #define regSPI_SHADER_USER_DATA_PS_25 0x0c25 2129 #define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 2130 #define regSPI_SHADER_USER_DATA_PS_26 0x0c26 2131 #define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 2132 #define regSPI_SHADER_USER_DATA_PS_27 0x0c27 2133 #define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 2134 #define regSPI_SHADER_USER_DATA_PS_28 0x0c28 2135 #define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 2136 #define regSPI_SHADER_USER_DATA_PS_29 0x0c29 2137 #define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 2138 #define regSPI_SHADER_USER_DATA_PS_30 0x0c2a 2139 #define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 2140 #define regSPI_SHADER_USER_DATA_PS_31 0x0c2b 2141 #define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 2142 #define regSPI_SHADER_PGM_RSRC3_VS 0x0c46 2143 #define regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 2144 #define regSPI_SHADER_LATE_ALLOC_VS 0x0c47 2145 #define regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 2146 #define regSPI_SHADER_PGM_LO_VS 0x0c48 2147 #define regSPI_SHADER_PGM_LO_VS_BASE_IDX 0 2148 #define regSPI_SHADER_PGM_HI_VS 0x0c49 2149 #define regSPI_SHADER_PGM_HI_VS_BASE_IDX 0 2150 #define regSPI_SHADER_PGM_RSRC1_VS 0x0c4a 2151 #define regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 2152 #define regSPI_SHADER_PGM_RSRC2_VS 0x0c4b 2153 #define regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 2154 #define regSPI_SHADER_USER_DATA_VS_0 0x0c4c 2155 #define regSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 2156 #define regSPI_SHADER_USER_DATA_VS_1 0x0c4d 2157 #define regSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 2158 #define regSPI_SHADER_USER_DATA_VS_2 0x0c4e 2159 #define regSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 2160 #define regSPI_SHADER_USER_DATA_VS_3 0x0c4f 2161 #define regSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 2162 #define regSPI_SHADER_USER_DATA_VS_4 0x0c50 2163 #define regSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 2164 #define regSPI_SHADER_USER_DATA_VS_5 0x0c51 2165 #define regSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 2166 #define regSPI_SHADER_USER_DATA_VS_6 0x0c52 2167 #define regSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 2168 #define regSPI_SHADER_USER_DATA_VS_7 0x0c53 2169 #define regSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 2170 #define regSPI_SHADER_USER_DATA_VS_8 0x0c54 2171 #define regSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 2172 #define regSPI_SHADER_USER_DATA_VS_9 0x0c55 2173 #define regSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 2174 #define regSPI_SHADER_USER_DATA_VS_10 0x0c56 2175 #define regSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 2176 #define regSPI_SHADER_USER_DATA_VS_11 0x0c57 2177 #define regSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 2178 #define regSPI_SHADER_USER_DATA_VS_12 0x0c58 2179 #define regSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 2180 #define regSPI_SHADER_USER_DATA_VS_13 0x0c59 2181 #define regSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 2182 #define regSPI_SHADER_USER_DATA_VS_14 0x0c5a 2183 #define regSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 2184 #define regSPI_SHADER_USER_DATA_VS_15 0x0c5b 2185 #define regSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 2186 #define regSPI_SHADER_USER_DATA_VS_16 0x0c5c 2187 #define regSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 2188 #define regSPI_SHADER_USER_DATA_VS_17 0x0c5d 2189 #define regSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 2190 #define regSPI_SHADER_USER_DATA_VS_18 0x0c5e 2191 #define regSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 2192 #define regSPI_SHADER_USER_DATA_VS_19 0x0c5f 2193 #define regSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 2194 #define regSPI_SHADER_USER_DATA_VS_20 0x0c60 2195 #define regSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 2196 #define regSPI_SHADER_USER_DATA_VS_21 0x0c61 2197 #define regSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 2198 #define regSPI_SHADER_USER_DATA_VS_22 0x0c62 2199 #define regSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 2200 #define regSPI_SHADER_USER_DATA_VS_23 0x0c63 2201 #define regSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 2202 #define regSPI_SHADER_USER_DATA_VS_24 0x0c64 2203 #define regSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 2204 #define regSPI_SHADER_USER_DATA_VS_25 0x0c65 2205 #define regSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 2206 #define regSPI_SHADER_USER_DATA_VS_26 0x0c66 2207 #define regSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 2208 #define regSPI_SHADER_USER_DATA_VS_27 0x0c67 2209 #define regSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 2210 #define regSPI_SHADER_USER_DATA_VS_28 0x0c68 2211 #define regSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 2212 #define regSPI_SHADER_USER_DATA_VS_29 0x0c69 2213 #define regSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 2214 #define regSPI_SHADER_USER_DATA_VS_30 0x0c6a 2215 #define regSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 2216 #define regSPI_SHADER_USER_DATA_VS_31 0x0c6b 2217 #define regSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 2218 #define regSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c 2219 #define regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 2220 #define regSPI_SHADER_PGM_RSRC4_GS 0x0c81 2221 #define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 2222 #define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 2223 #define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 2224 #define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 2225 #define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 2226 #define regSPI_SHADER_PGM_LO_ES 0x0c84 2227 #define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 2228 #define regSPI_SHADER_PGM_HI_ES 0x0c85 2229 #define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 2230 #define regSPI_SHADER_PGM_RSRC3_GS 0x0c87 2231 #define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 2232 #define regSPI_SHADER_PGM_LO_GS 0x0c88 2233 #define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 2234 #define regSPI_SHADER_PGM_HI_GS 0x0c89 2235 #define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 2236 #define regSPI_SHADER_PGM_RSRC1_GS 0x0c8a 2237 #define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 2238 #define regSPI_SHADER_PGM_RSRC2_GS 0x0c8b 2239 #define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 2240 #define regSPI_SHADER_USER_DATA_ES_0 0x0ccc 2241 #define regSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 2242 #define regSPI_SHADER_USER_DATA_ES_1 0x0ccd 2243 #define regSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 2244 #define regSPI_SHADER_USER_DATA_ES_2 0x0cce 2245 #define regSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 2246 #define regSPI_SHADER_USER_DATA_ES_3 0x0ccf 2247 #define regSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 2248 #define regSPI_SHADER_USER_DATA_ES_4 0x0cd0 2249 #define regSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 2250 #define regSPI_SHADER_USER_DATA_ES_5 0x0cd1 2251 #define regSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 2252 #define regSPI_SHADER_USER_DATA_ES_6 0x0cd2 2253 #define regSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 2254 #define regSPI_SHADER_USER_DATA_ES_7 0x0cd3 2255 #define regSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 2256 #define regSPI_SHADER_USER_DATA_ES_8 0x0cd4 2257 #define regSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 2258 #define regSPI_SHADER_USER_DATA_ES_9 0x0cd5 2259 #define regSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 2260 #define regSPI_SHADER_USER_DATA_ES_10 0x0cd6 2261 #define regSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 2262 #define regSPI_SHADER_USER_DATA_ES_11 0x0cd7 2263 #define regSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 2264 #define regSPI_SHADER_USER_DATA_ES_12 0x0cd8 2265 #define regSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 2266 #define regSPI_SHADER_USER_DATA_ES_13 0x0cd9 2267 #define regSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 2268 #define regSPI_SHADER_USER_DATA_ES_14 0x0cda 2269 #define regSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 2270 #define regSPI_SHADER_USER_DATA_ES_15 0x0cdb 2271 #define regSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 2272 #define regSPI_SHADER_USER_DATA_ES_16 0x0cdc 2273 #define regSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 2274 #define regSPI_SHADER_USER_DATA_ES_17 0x0cdd 2275 #define regSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 2276 #define regSPI_SHADER_USER_DATA_ES_18 0x0cde 2277 #define regSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 2278 #define regSPI_SHADER_USER_DATA_ES_19 0x0cdf 2279 #define regSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 2280 #define regSPI_SHADER_USER_DATA_ES_20 0x0ce0 2281 #define regSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 2282 #define regSPI_SHADER_USER_DATA_ES_21 0x0ce1 2283 #define regSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 2284 #define regSPI_SHADER_USER_DATA_ES_22 0x0ce2 2285 #define regSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 2286 #define regSPI_SHADER_USER_DATA_ES_23 0x0ce3 2287 #define regSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 2288 #define regSPI_SHADER_USER_DATA_ES_24 0x0ce4 2289 #define regSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 2290 #define regSPI_SHADER_USER_DATA_ES_25 0x0ce5 2291 #define regSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 2292 #define regSPI_SHADER_USER_DATA_ES_26 0x0ce6 2293 #define regSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 2294 #define regSPI_SHADER_USER_DATA_ES_27 0x0ce7 2295 #define regSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 2296 #define regSPI_SHADER_USER_DATA_ES_28 0x0ce8 2297 #define regSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 2298 #define regSPI_SHADER_USER_DATA_ES_29 0x0ce9 2299 #define regSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 2300 #define regSPI_SHADER_USER_DATA_ES_30 0x0cea 2301 #define regSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 2302 #define regSPI_SHADER_USER_DATA_ES_31 0x0ceb 2303 #define regSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 2304 #define regSPI_SHADER_PGM_RSRC4_HS 0x0d01 2305 #define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 2306 #define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 2307 #define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 2308 #define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 2309 #define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 2310 #define regSPI_SHADER_PGM_LO_LS 0x0d04 2311 #define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 2312 #define regSPI_SHADER_PGM_HI_LS 0x0d05 2313 #define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 2314 #define regSPI_SHADER_PGM_RSRC3_HS 0x0d07 2315 #define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 2316 #define regSPI_SHADER_PGM_LO_HS 0x0d08 2317 #define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 2318 #define regSPI_SHADER_PGM_HI_HS 0x0d09 2319 #define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 2320 #define regSPI_SHADER_PGM_RSRC1_HS 0x0d0a 2321 #define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 2322 #define regSPI_SHADER_PGM_RSRC2_HS 0x0d0b 2323 #define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 2324 #define regSPI_SHADER_USER_DATA_LS_0 0x0d0c 2325 #define regSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 2326 #define regSPI_SHADER_USER_DATA_LS_1 0x0d0d 2327 #define regSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 2328 #define regSPI_SHADER_USER_DATA_LS_2 0x0d0e 2329 #define regSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 2330 #define regSPI_SHADER_USER_DATA_LS_3 0x0d0f 2331 #define regSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 2332 #define regSPI_SHADER_USER_DATA_LS_4 0x0d10 2333 #define regSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 2334 #define regSPI_SHADER_USER_DATA_LS_5 0x0d11 2335 #define regSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 2336 #define regSPI_SHADER_USER_DATA_LS_6 0x0d12 2337 #define regSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 2338 #define regSPI_SHADER_USER_DATA_LS_7 0x0d13 2339 #define regSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 2340 #define regSPI_SHADER_USER_DATA_LS_8 0x0d14 2341 #define regSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 2342 #define regSPI_SHADER_USER_DATA_LS_9 0x0d15 2343 #define regSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 2344 #define regSPI_SHADER_USER_DATA_LS_10 0x0d16 2345 #define regSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 2346 #define regSPI_SHADER_USER_DATA_LS_11 0x0d17 2347 #define regSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 2348 #define regSPI_SHADER_USER_DATA_LS_12 0x0d18 2349 #define regSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 2350 #define regSPI_SHADER_USER_DATA_LS_13 0x0d19 2351 #define regSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 2352 #define regSPI_SHADER_USER_DATA_LS_14 0x0d1a 2353 #define regSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 2354 #define regSPI_SHADER_USER_DATA_LS_15 0x0d1b 2355 #define regSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 2356 #define regSPI_SHADER_USER_DATA_LS_16 0x0d1c 2357 #define regSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 2358 #define regSPI_SHADER_USER_DATA_LS_17 0x0d1d 2359 #define regSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 2360 #define regSPI_SHADER_USER_DATA_LS_18 0x0d1e 2361 #define regSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 2362 #define regSPI_SHADER_USER_DATA_LS_19 0x0d1f 2363 #define regSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 2364 #define regSPI_SHADER_USER_DATA_LS_20 0x0d20 2365 #define regSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 2366 #define regSPI_SHADER_USER_DATA_LS_21 0x0d21 2367 #define regSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 2368 #define regSPI_SHADER_USER_DATA_LS_22 0x0d22 2369 #define regSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 2370 #define regSPI_SHADER_USER_DATA_LS_23 0x0d23 2371 #define regSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 2372 #define regSPI_SHADER_USER_DATA_LS_24 0x0d24 2373 #define regSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 2374 #define regSPI_SHADER_USER_DATA_LS_25 0x0d25 2375 #define regSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 2376 #define regSPI_SHADER_USER_DATA_LS_26 0x0d26 2377 #define regSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 2378 #define regSPI_SHADER_USER_DATA_LS_27 0x0d27 2379 #define regSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 2380 #define regSPI_SHADER_USER_DATA_LS_28 0x0d28 2381 #define regSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 2382 #define regSPI_SHADER_USER_DATA_LS_29 0x0d29 2383 #define regSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 2384 #define regSPI_SHADER_USER_DATA_LS_30 0x0d2a 2385 #define regSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 2386 #define regSPI_SHADER_USER_DATA_LS_31 0x0d2b 2387 #define regSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 2388 #define regSPI_SHADER_USER_DATA_COMMON_0 0x0d4c 2389 #define regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 2390 #define regSPI_SHADER_USER_DATA_COMMON_1 0x0d4d 2391 #define regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 2392 #define regSPI_SHADER_USER_DATA_COMMON_2 0x0d4e 2393 #define regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 2394 #define regSPI_SHADER_USER_DATA_COMMON_3 0x0d4f 2395 #define regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 2396 #define regSPI_SHADER_USER_DATA_COMMON_4 0x0d50 2397 #define regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 2398 #define regSPI_SHADER_USER_DATA_COMMON_5 0x0d51 2399 #define regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 2400 #define regSPI_SHADER_USER_DATA_COMMON_6 0x0d52 2401 #define regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 2402 #define regSPI_SHADER_USER_DATA_COMMON_7 0x0d53 2403 #define regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 2404 #define regSPI_SHADER_USER_DATA_COMMON_8 0x0d54 2405 #define regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 2406 #define regSPI_SHADER_USER_DATA_COMMON_9 0x0d55 2407 #define regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 2408 #define regSPI_SHADER_USER_DATA_COMMON_10 0x0d56 2409 #define regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 2410 #define regSPI_SHADER_USER_DATA_COMMON_11 0x0d57 2411 #define regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 2412 #define regSPI_SHADER_USER_DATA_COMMON_12 0x0d58 2413 #define regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 2414 #define regSPI_SHADER_USER_DATA_COMMON_13 0x0d59 2415 #define regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 2416 #define regSPI_SHADER_USER_DATA_COMMON_14 0x0d5a 2417 #define regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 2418 #define regSPI_SHADER_USER_DATA_COMMON_15 0x0d5b 2419 #define regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 2420 #define regSPI_SHADER_USER_DATA_COMMON_16 0x0d5c 2421 #define regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 2422 #define regSPI_SHADER_USER_DATA_COMMON_17 0x0d5d 2423 #define regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 2424 #define regSPI_SHADER_USER_DATA_COMMON_18 0x0d5e 2425 #define regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 2426 #define regSPI_SHADER_USER_DATA_COMMON_19 0x0d5f 2427 #define regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 2428 #define regSPI_SHADER_USER_DATA_COMMON_20 0x0d60 2429 #define regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 2430 #define regSPI_SHADER_USER_DATA_COMMON_21 0x0d61 2431 #define regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 2432 #define regSPI_SHADER_USER_DATA_COMMON_22 0x0d62 2433 #define regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 2434 #define regSPI_SHADER_USER_DATA_COMMON_23 0x0d63 2435 #define regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 2436 #define regSPI_SHADER_USER_DATA_COMMON_24 0x0d64 2437 #define regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 2438 #define regSPI_SHADER_USER_DATA_COMMON_25 0x0d65 2439 #define regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 2440 #define regSPI_SHADER_USER_DATA_COMMON_26 0x0d66 2441 #define regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 2442 #define regSPI_SHADER_USER_DATA_COMMON_27 0x0d67 2443 #define regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 2444 #define regSPI_SHADER_USER_DATA_COMMON_28 0x0d68 2445 #define regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 2446 #define regSPI_SHADER_USER_DATA_COMMON_29 0x0d69 2447 #define regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 2448 #define regSPI_SHADER_USER_DATA_COMMON_30 0x0d6a 2449 #define regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 2450 #define regSPI_SHADER_USER_DATA_COMMON_31 0x0d6b 2451 #define regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 2452 #define regCOMPUTE_DISPATCH_INITIATOR 0x0e00 2453 #define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 2454 #define regCOMPUTE_DIM_X 0x0e01 2455 #define regCOMPUTE_DIM_X_BASE_IDX 0 2456 #define regCOMPUTE_DIM_Y 0x0e02 2457 #define regCOMPUTE_DIM_Y_BASE_IDX 0 2458 #define regCOMPUTE_DIM_Z 0x0e03 2459 #define regCOMPUTE_DIM_Z_BASE_IDX 0 2460 #define regCOMPUTE_START_X 0x0e04 2461 #define regCOMPUTE_START_X_BASE_IDX 0 2462 #define regCOMPUTE_START_Y 0x0e05 2463 #define regCOMPUTE_START_Y_BASE_IDX 0 2464 #define regCOMPUTE_START_Z 0x0e06 2465 #define regCOMPUTE_START_Z_BASE_IDX 0 2466 #define regCOMPUTE_NUM_THREAD_X 0x0e07 2467 #define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 2468 #define regCOMPUTE_NUM_THREAD_Y 0x0e08 2469 #define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 2470 #define regCOMPUTE_NUM_THREAD_Z 0x0e09 2471 #define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 2472 #define regCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a 2473 #define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 2474 #define regCOMPUTE_PERFCOUNT_ENABLE 0x0e0b 2475 #define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 2476 #define regCOMPUTE_PGM_LO 0x0e0c 2477 #define regCOMPUTE_PGM_LO_BASE_IDX 0 2478 #define regCOMPUTE_PGM_HI 0x0e0d 2479 #define regCOMPUTE_PGM_HI_BASE_IDX 0 2480 #define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e 2481 #define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 2482 #define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f 2483 #define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 2484 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 2485 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 2486 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 2487 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 2488 #define regCOMPUTE_PGM_RSRC1 0x0e12 2489 #define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 2490 #define regCOMPUTE_PGM_RSRC2 0x0e13 2491 #define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 2492 #define regCOMPUTE_VMID 0x0e14 2493 #define regCOMPUTE_VMID_BASE_IDX 0 2494 #define regCOMPUTE_RESOURCE_LIMITS 0x0e15 2495 #define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 2496 #define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 2497 #define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 2498 #define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 2499 #define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 2500 #define regCOMPUTE_TMPRING_SIZE 0x0e18 2501 #define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 2502 #define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 2503 #define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 2504 #define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a 2505 #define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 2506 #define regCOMPUTE_RESTART_X 0x0e1b 2507 #define regCOMPUTE_RESTART_X_BASE_IDX 0 2508 #define regCOMPUTE_RESTART_Y 0x0e1c 2509 #define regCOMPUTE_RESTART_Y_BASE_IDX 0 2510 #define regCOMPUTE_RESTART_Z 0x0e1d 2511 #define regCOMPUTE_RESTART_Z_BASE_IDX 0 2512 #define regCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e 2513 #define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 2514 #define regCOMPUTE_MISC_RESERVED 0x0e1f 2515 #define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 2516 #define regCOMPUTE_DISPATCH_ID 0x0e20 2517 #define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 2518 #define regCOMPUTE_THREADGROUP_ID 0x0e21 2519 #define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 2520 #define regCOMPUTE_RELAUNCH 0x0e22 2521 #define regCOMPUTE_RELAUNCH_BASE_IDX 0 2522 #define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 2523 #define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 2524 #define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 2525 #define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 2526 #define regCOMPUTE_TG_CHUNK_SIZE 0x0e27 2527 #define regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX 0 2528 #define regCOMPUTE_SHADER_CHKSUM 0x0e2c 2529 #define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 2530 #define regCOMPUTE_PGM_RSRC3 0x0e2d 2531 #define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 2532 #define regCOMPUTE_USER_DATA_0 0x0e40 2533 #define regCOMPUTE_USER_DATA_0_BASE_IDX 0 2534 #define regCOMPUTE_USER_DATA_1 0x0e41 2535 #define regCOMPUTE_USER_DATA_1_BASE_IDX 0 2536 #define regCOMPUTE_USER_DATA_2 0x0e42 2537 #define regCOMPUTE_USER_DATA_2_BASE_IDX 0 2538 #define regCOMPUTE_USER_DATA_3 0x0e43 2539 #define regCOMPUTE_USER_DATA_3_BASE_IDX 0 2540 #define regCOMPUTE_USER_DATA_4 0x0e44 2541 #define regCOMPUTE_USER_DATA_4_BASE_IDX 0 2542 #define regCOMPUTE_USER_DATA_5 0x0e45 2543 #define regCOMPUTE_USER_DATA_5_BASE_IDX 0 2544 #define regCOMPUTE_USER_DATA_6 0x0e46 2545 #define regCOMPUTE_USER_DATA_6_BASE_IDX 0 2546 #define regCOMPUTE_USER_DATA_7 0x0e47 2547 #define regCOMPUTE_USER_DATA_7_BASE_IDX 0 2548 #define regCOMPUTE_USER_DATA_8 0x0e48 2549 #define regCOMPUTE_USER_DATA_8_BASE_IDX 0 2550 #define regCOMPUTE_USER_DATA_9 0x0e49 2551 #define regCOMPUTE_USER_DATA_9_BASE_IDX 0 2552 #define regCOMPUTE_USER_DATA_10 0x0e4a 2553 #define regCOMPUTE_USER_DATA_10_BASE_IDX 0 2554 #define regCOMPUTE_USER_DATA_11 0x0e4b 2555 #define regCOMPUTE_USER_DATA_11_BASE_IDX 0 2556 #define regCOMPUTE_USER_DATA_12 0x0e4c 2557 #define regCOMPUTE_USER_DATA_12_BASE_IDX 0 2558 #define regCOMPUTE_USER_DATA_13 0x0e4d 2559 #define regCOMPUTE_USER_DATA_13_BASE_IDX 0 2560 #define regCOMPUTE_USER_DATA_14 0x0e4e 2561 #define regCOMPUTE_USER_DATA_14_BASE_IDX 0 2562 #define regCOMPUTE_USER_DATA_15 0x0e4f 2563 #define regCOMPUTE_USER_DATA_15_BASE_IDX 0 2564 #define regCOMPUTE_DISPATCH_END 0x0e7e 2565 #define regCOMPUTE_DISPATCH_END_BASE_IDX 0 2566 #define regCOMPUTE_NOWHERE 0x0e7f 2567 #define regCOMPUTE_NOWHERE_BASE_IDX 0 2568 2569 2570 // addressBlock: xcd0_gc_cppdec 2571 // base address: 0xc080 2572 #define regCP_DFY_CNTL 0x1020 2573 #define regCP_DFY_CNTL_BASE_IDX 0 2574 #define regCP_DFY_STAT 0x1021 2575 #define regCP_DFY_STAT_BASE_IDX 0 2576 #define regCP_DFY_ADDR_HI 0x1022 2577 #define regCP_DFY_ADDR_HI_BASE_IDX 0 2578 #define regCP_DFY_ADDR_LO 0x1023 2579 #define regCP_DFY_ADDR_LO_BASE_IDX 0 2580 #define regCP_DFY_DATA_0 0x1024 2581 #define regCP_DFY_DATA_0_BASE_IDX 0 2582 #define regCP_DFY_DATA_1 0x1025 2583 #define regCP_DFY_DATA_1_BASE_IDX 0 2584 #define regCP_DFY_DATA_2 0x1026 2585 #define regCP_DFY_DATA_2_BASE_IDX 0 2586 #define regCP_DFY_DATA_3 0x1027 2587 #define regCP_DFY_DATA_3_BASE_IDX 0 2588 #define regCP_DFY_DATA_4 0x1028 2589 #define regCP_DFY_DATA_4_BASE_IDX 0 2590 #define regCP_DFY_DATA_5 0x1029 2591 #define regCP_DFY_DATA_5_BASE_IDX 0 2592 #define regCP_DFY_DATA_6 0x102a 2593 #define regCP_DFY_DATA_6_BASE_IDX 0 2594 #define regCP_DFY_DATA_7 0x102b 2595 #define regCP_DFY_DATA_7_BASE_IDX 0 2596 #define regCP_DFY_DATA_8 0x102c 2597 #define regCP_DFY_DATA_8_BASE_IDX 0 2598 #define regCP_DFY_DATA_9 0x102d 2599 #define regCP_DFY_DATA_9_BASE_IDX 0 2600 #define regCP_DFY_DATA_10 0x102e 2601 #define regCP_DFY_DATA_10_BASE_IDX 0 2602 #define regCP_DFY_DATA_11 0x102f 2603 #define regCP_DFY_DATA_11_BASE_IDX 0 2604 #define regCP_DFY_DATA_12 0x1030 2605 #define regCP_DFY_DATA_12_BASE_IDX 0 2606 #define regCP_DFY_DATA_13 0x1031 2607 #define regCP_DFY_DATA_13_BASE_IDX 0 2608 #define regCP_DFY_DATA_14 0x1032 2609 #define regCP_DFY_DATA_14_BASE_IDX 0 2610 #define regCP_DFY_DATA_15 0x1033 2611 #define regCP_DFY_DATA_15_BASE_IDX 0 2612 #define regCP_DFY_CMD 0x1034 2613 #define regCP_DFY_CMD_BASE_IDX 0 2614 #define regCP_EOPQ_WAIT_TIME 0x1035 2615 #define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 2616 #define regCP_CPC_MGCG_SYNC_CNTL 0x1036 2617 #define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 2618 #define regCPC_INT_INFO 0x1037 2619 #define regCPC_INT_INFO_BASE_IDX 0 2620 #define regCP_VIRT_STATUS 0x1038 2621 #define regCP_VIRT_STATUS_BASE_IDX 0 2622 #define regCPC_INT_ADDR 0x1039 2623 #define regCPC_INT_ADDR_BASE_IDX 0 2624 #define regCPC_INT_PASID 0x103a 2625 #define regCPC_INT_PASID_BASE_IDX 0 2626 #define regCP_GFX_ERROR 0x103b 2627 #define regCP_GFX_ERROR_BASE_IDX 0 2628 #define regCPG_UTCL1_CNTL 0x103c 2629 #define regCPG_UTCL1_CNTL_BASE_IDX 0 2630 #define regCPC_UTCL1_CNTL 0x103d 2631 #define regCPC_UTCL1_CNTL_BASE_IDX 0 2632 #define regCPF_UTCL1_CNTL 0x103e 2633 #define regCPF_UTCL1_CNTL_BASE_IDX 0 2634 #define regCP_AQL_SMM_STATUS 0x103f 2635 #define regCP_AQL_SMM_STATUS_BASE_IDX 0 2636 #define regCP_RB0_BASE 0x1040 2637 #define regCP_RB0_BASE_BASE_IDX 0 2638 #define regCP_RB_BASE 0x1040 2639 #define regCP_RB_BASE_BASE_IDX 0 2640 #define regCP_RB0_CNTL 0x1041 2641 #define regCP_RB0_CNTL_BASE_IDX 0 2642 #define regCP_RB_CNTL 0x1041 2643 #define regCP_RB_CNTL_BASE_IDX 0 2644 #define regCP_RB_RPTR_WR 0x1042 2645 #define regCP_RB_RPTR_WR_BASE_IDX 0 2646 #define regCP_RB0_RPTR_ADDR 0x1043 2647 #define regCP_RB0_RPTR_ADDR_BASE_IDX 0 2648 #define regCP_RB_RPTR_ADDR 0x1043 2649 #define regCP_RB_RPTR_ADDR_BASE_IDX 0 2650 #define regCP_RB0_RPTR_ADDR_HI 0x1044 2651 #define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 2652 #define regCP_RB_RPTR_ADDR_HI 0x1044 2653 #define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 2654 #define regCP_RB0_BUFSZ_MASK 0x1045 2655 #define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 2656 #define regCP_RB_BUFSZ_MASK 0x1045 2657 #define regCP_RB_BUFSZ_MASK_BASE_IDX 0 2658 #define regCP_RB_WPTR_POLL_ADDR_LO 0x1046 2659 #define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 2660 #define regCP_RB_WPTR_POLL_ADDR_HI 0x1047 2661 #define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 2662 #define regGC_PRIV_MODE 0x1048 2663 #define regGC_PRIV_MODE_BASE_IDX 0 2664 #define regCP_INT_CNTL 0x1049 2665 #define regCP_INT_CNTL_BASE_IDX 0 2666 #define regCP_INT_STATUS 0x104a 2667 #define regCP_INT_STATUS_BASE_IDX 0 2668 #define regCP_DEVICE_ID 0x104b 2669 #define regCP_DEVICE_ID_BASE_IDX 0 2670 #define regCP_ME0_PIPE_PRIORITY_CNTS 0x104c 2671 #define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 2672 #define regCP_RING_PRIORITY_CNTS 0x104c 2673 #define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 2674 #define regCP_ME0_PIPE0_PRIORITY 0x104d 2675 #define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 2676 #define regCP_RING0_PRIORITY 0x104d 2677 #define regCP_RING0_PRIORITY_BASE_IDX 0 2678 #define regCP_ME0_PIPE1_PRIORITY 0x104e 2679 #define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 2680 #define regCP_RING1_PRIORITY 0x104e 2681 #define regCP_RING1_PRIORITY_BASE_IDX 0 2682 #define regCP_ME0_PIPE2_PRIORITY 0x104f 2683 #define regCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 2684 #define regCP_RING2_PRIORITY 0x104f 2685 #define regCP_RING2_PRIORITY_BASE_IDX 0 2686 #define regCP_FATAL_ERROR 0x1050 2687 #define regCP_FATAL_ERROR_BASE_IDX 0 2688 #define regCP_RB_VMID 0x1051 2689 #define regCP_RB_VMID_BASE_IDX 0 2690 #define regCP_ME0_PIPE0_VMID 0x1052 2691 #define regCP_ME0_PIPE0_VMID_BASE_IDX 0 2692 #define regCP_ME0_PIPE1_VMID 0x1053 2693 #define regCP_ME0_PIPE1_VMID_BASE_IDX 0 2694 #define regCP_RB0_WPTR 0x1054 2695 #define regCP_RB0_WPTR_BASE_IDX 0 2696 #define regCP_RB_WPTR 0x1054 2697 #define regCP_RB_WPTR_BASE_IDX 0 2698 #define regCP_RB0_WPTR_HI 0x1055 2699 #define regCP_RB0_WPTR_HI_BASE_IDX 0 2700 #define regCP_RB_WPTR_HI 0x1055 2701 #define regCP_RB_WPTR_HI_BASE_IDX 0 2702 #define regCP_RB1_WPTR 0x1056 2703 #define regCP_RB1_WPTR_BASE_IDX 0 2704 #define regCP_RB1_WPTR_HI 0x1057 2705 #define regCP_RB1_WPTR_HI_BASE_IDX 0 2706 #define regCP_RB2_WPTR 0x1058 2707 #define regCP_RB2_WPTR_BASE_IDX 0 2708 #define regCP_RB_DOORBELL_CONTROL 0x1059 2709 #define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 2710 #define regCP_RB_DOORBELL_RANGE_LOWER 0x105a 2711 #define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 2712 #define regCP_RB_DOORBELL_RANGE_UPPER 0x105b 2713 #define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 2714 #define regCP_MEC_DOORBELL_RANGE_LOWER 0x105c 2715 #define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 2716 #define regCP_MEC_DOORBELL_RANGE_UPPER 0x105d 2717 #define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 2718 #define regCPG_UTCL1_ERROR 0x105e 2719 #define regCPG_UTCL1_ERROR_BASE_IDX 0 2720 #define regCPC_UTCL1_ERROR 0x105f 2721 #define regCPC_UTCL1_ERROR_BASE_IDX 0 2722 #define regCP_RB1_BASE 0x1060 2723 #define regCP_RB1_BASE_BASE_IDX 0 2724 #define regCP_RB1_CNTL 0x1061 2725 #define regCP_RB1_CNTL_BASE_IDX 0 2726 #define regCP_RB1_RPTR_ADDR 0x1062 2727 #define regCP_RB1_RPTR_ADDR_BASE_IDX 0 2728 #define regCP_RB1_RPTR_ADDR_HI 0x1063 2729 #define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 2730 #define regCP_RB2_BASE 0x1065 2731 #define regCP_RB2_BASE_BASE_IDX 0 2732 #define regCP_RB2_CNTL 0x1066 2733 #define regCP_RB2_CNTL_BASE_IDX 0 2734 #define regCP_RB2_RPTR_ADDR 0x1067 2735 #define regCP_RB2_RPTR_ADDR_BASE_IDX 0 2736 #define regCP_RB2_RPTR_ADDR_HI 0x1068 2737 #define regCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 2738 #define regCP_RB0_ACTIVE 0x1069 2739 #define regCP_RB0_ACTIVE_BASE_IDX 0 2740 #define regCP_RB_ACTIVE 0x1069 2741 #define regCP_RB_ACTIVE_BASE_IDX 0 2742 #define regCP_INT_CNTL_RING0 0x106a 2743 #define regCP_INT_CNTL_RING0_BASE_IDX 0 2744 #define regCP_INT_CNTL_RING1 0x106b 2745 #define regCP_INT_CNTL_RING1_BASE_IDX 0 2746 #define regCP_INT_CNTL_RING2 0x106c 2747 #define regCP_INT_CNTL_RING2_BASE_IDX 0 2748 #define regCP_INT_STATUS_RING0 0x106d 2749 #define regCP_INT_STATUS_RING0_BASE_IDX 0 2750 #define regCP_INT_STATUS_RING1 0x106e 2751 #define regCP_INT_STATUS_RING1_BASE_IDX 0 2752 #define regCP_INT_STATUS_RING2 0x106f 2753 #define regCP_INT_STATUS_RING2_BASE_IDX 0 2754 #define regCP_ME_F32_INTERRUPT 0x1073 2755 #define regCP_ME_F32_INTERRUPT_BASE_IDX 0 2756 #define regCP_PFP_F32_INTERRUPT 0x1074 2757 #define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 2758 #define regCP_CE_F32_INTERRUPT 0x1075 2759 #define regCP_CE_F32_INTERRUPT_BASE_IDX 0 2760 #define regCP_MEC1_F32_INTERRUPT 0x1076 2761 #define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 2762 #define regCP_MEC2_F32_INTERRUPT 0x1077 2763 #define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 2764 #define regCP_PWR_CNTL 0x1078 2765 #define regCP_PWR_CNTL_BASE_IDX 0 2766 #define regCP_MEM_SLP_CNTL 0x1079 2767 #define regCP_MEM_SLP_CNTL_BASE_IDX 0 2768 #define regCP_ECC_DMA_FIRST_OCCURRENCE 0x107a 2769 #define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX 0 2770 #define regCP_ECC_FIRSTOCCURRENCE 0x107a 2771 #define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 2772 #define regCP_ECC_FIRSTOCCURRENCE_RING0 0x107b 2773 #define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 2774 #define regCP_ECC_FIRSTOCCURRENCE_RING1 0x107c 2775 #define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 2776 #define regCP_ECC_FIRSTOCCURRENCE_RING2 0x107d 2777 #define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 2778 #define regGB_EDC_MODE 0x107e 2779 #define regGB_EDC_MODE_BASE_IDX 0 2780 #define regCP_DEBUG 0x107f 2781 #define regCP_DEBUG_BASE_IDX 0 2782 #define regCP_CPF_DEBUG 0x1080 2783 #define regCP_CPF_DEBUG_BASE_IDX 0 2784 #define regCP_CPC_DEBUG 0x1081 2785 #define regCP_CPC_DEBUG_BASE_IDX 0 2786 #define regCP_CPC_DEBUG_2 0x1082 2787 #define regCP_CPC_DEBUG_2_BASE_IDX 0 2788 #define regCP_PQ_WPTR_POLL_CNTL 0x1083 2789 #define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 2790 #define regCP_PQ_WPTR_POLL_CNTL1 0x1084 2791 #define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 2792 #define regCP_ME1_PIPE0_INT_CNTL 0x1085 2793 #define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 2794 #define regCP_ME1_PIPE1_INT_CNTL 0x1086 2795 #define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 2796 #define regCP_ME1_PIPE2_INT_CNTL 0x1087 2797 #define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 2798 #define regCP_ME1_PIPE3_INT_CNTL 0x1088 2799 #define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 2800 #define regCP_ME2_PIPE0_INT_CNTL 0x1089 2801 #define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 2802 #define regCP_ME2_PIPE1_INT_CNTL 0x108a 2803 #define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 2804 #define regCP_ME2_PIPE2_INT_CNTL 0x108b 2805 #define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 2806 #define regCP_ME2_PIPE3_INT_CNTL 0x108c 2807 #define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 2808 #define regCP_ME1_PIPE0_INT_STATUS 0x108d 2809 #define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 2810 #define regCP_ME1_PIPE1_INT_STATUS 0x108e 2811 #define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 2812 #define regCP_ME1_PIPE2_INT_STATUS 0x108f 2813 #define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 2814 #define regCP_ME1_PIPE3_INT_STATUS 0x1090 2815 #define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 2816 #define regCP_ME2_PIPE0_INT_STATUS 0x1091 2817 #define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 2818 #define regCP_ME2_PIPE1_INT_STATUS 0x1092 2819 #define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 2820 #define regCP_ME2_PIPE2_INT_STATUS 0x1093 2821 #define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 2822 #define regCP_ME2_PIPE3_INT_STATUS 0x1094 2823 #define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 2824 #define regCP_ME1_INT_STAT_DEBUG 0x1095 2825 #define regCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 2826 #define regCP_ME2_INT_STAT_DEBUG 0x1096 2827 #define regCP_ME2_INT_STAT_DEBUG_BASE_IDX 0 2828 #define regCC_GC_EDC_CONFIG 0x1098 2829 #define regCC_GC_EDC_CONFIG_BASE_IDX 0 2830 #define regCP_ME1_PIPE_PRIORITY_CNTS 0x1099 2831 #define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 2832 #define regCP_ME1_PIPE0_PRIORITY 0x109a 2833 #define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 2834 #define regCP_ME1_PIPE1_PRIORITY 0x109b 2835 #define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 2836 #define regCP_ME1_PIPE2_PRIORITY 0x109c 2837 #define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 2838 #define regCP_ME1_PIPE3_PRIORITY 0x109d 2839 #define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 2840 #define regCP_ME2_PIPE_PRIORITY_CNTS 0x109e 2841 #define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 2842 #define regCP_ME2_PIPE0_PRIORITY 0x109f 2843 #define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 2844 #define regCP_ME2_PIPE1_PRIORITY 0x10a0 2845 #define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 2846 #define regCP_ME2_PIPE2_PRIORITY 0x10a1 2847 #define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 2848 #define regCP_ME2_PIPE3_PRIORITY 0x10a2 2849 #define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 2850 #define regCP_CE_PRGRM_CNTR_START 0x10a3 2851 #define regCP_CE_PRGRM_CNTR_START_BASE_IDX 0 2852 #define regCP_PFP_PRGRM_CNTR_START 0x10a4 2853 #define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 2854 #define regCP_ME_PRGRM_CNTR_START 0x10a5 2855 #define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 2856 #define regCP_MEC1_PRGRM_CNTR_START 0x10a6 2857 #define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 2858 #define regCP_MEC2_PRGRM_CNTR_START 0x10a7 2859 #define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 2860 #define regCP_CE_INTR_ROUTINE_START 0x10a8 2861 #define regCP_CE_INTR_ROUTINE_START_BASE_IDX 0 2862 #define regCP_PFP_INTR_ROUTINE_START 0x10a9 2863 #define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 2864 #define regCP_ME_INTR_ROUTINE_START 0x10aa 2865 #define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 2866 #define regCP_MEC1_INTR_ROUTINE_START 0x10ab 2867 #define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 2868 #define regCP_MEC2_INTR_ROUTINE_START 0x10ac 2869 #define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 2870 #define regCP_CONTEXT_CNTL 0x10ad 2871 #define regCP_CONTEXT_CNTL_BASE_IDX 0 2872 #define regCP_MAX_CONTEXT 0x10ae 2873 #define regCP_MAX_CONTEXT_BASE_IDX 0 2874 #define regCP_IQ_WAIT_TIME1 0x10af 2875 #define regCP_IQ_WAIT_TIME1_BASE_IDX 0 2876 #define regCP_IQ_WAIT_TIME2 0x10b0 2877 #define regCP_IQ_WAIT_TIME2_BASE_IDX 0 2878 #define regCP_RB0_BASE_HI 0x10b1 2879 #define regCP_RB0_BASE_HI_BASE_IDX 0 2880 #define regCP_RB1_BASE_HI 0x10b2 2881 #define regCP_RB1_BASE_HI_BASE_IDX 0 2882 #define regCP_VMID_RESET 0x10b3 2883 #define regCP_VMID_RESET_BASE_IDX 0 2884 #define regCPC_INT_CNTL 0x10b4 2885 #define regCPC_INT_CNTL_BASE_IDX 0 2886 #define regCPC_INT_STATUS 0x10b5 2887 #define regCPC_INT_STATUS_BASE_IDX 0 2888 #define regCP_VMID_PREEMPT 0x10b6 2889 #define regCP_VMID_PREEMPT_BASE_IDX 0 2890 #define regCPC_INT_CNTX_ID 0x10b7 2891 #define regCPC_INT_CNTX_ID_BASE_IDX 0 2892 #define regCP_PQ_STATUS 0x10b8 2893 #define regCP_PQ_STATUS_BASE_IDX 0 2894 #define regCP_CPC_IC_BASE_LO 0x10b9 2895 #define regCP_CPC_IC_BASE_LO_BASE_IDX 0 2896 #define regCP_CPC_IC_BASE_HI 0x10ba 2897 #define regCP_CPC_IC_BASE_HI_BASE_IDX 0 2898 #define regCP_CPC_IC_BASE_CNTL 0x10bb 2899 #define regCP_CPC_IC_BASE_CNTL_BASE_IDX 0 2900 #define regCP_CPC_IC_OP_CNTL 0x10bc 2901 #define regCP_CPC_IC_OP_CNTL_BASE_IDX 0 2902 #define regCP_MEC1_F32_INT_DIS 0x10bd 2903 #define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 2904 #define regCP_MEC2_F32_INT_DIS 0x10be 2905 #define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 2906 #define regCP_VMID_STATUS 0x10bf 2907 #define regCP_VMID_STATUS_BASE_IDX 0 2908 2909 2910 // addressBlock: xcd0_gc_cppdec2 2911 // base address: 0xc600 2912 #define regCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 2913 #define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 2914 #define regCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 2915 #define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 2916 #define regCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 2917 #define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 2918 #define regCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 2919 #define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 2920 #define regCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 2921 #define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 2922 #define regCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 2923 #define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 2924 #define regCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 2925 #define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 2926 #define regCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 2927 #define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 2928 #define regCP_RB_DOORBELL_CLEAR 0x1188 2929 #define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 2930 #define regCP_CPF_DSM_CNTL 0x1194 2931 #define regCP_CPF_DSM_CNTL_BASE_IDX 0 2932 #define regCP_CPG_DSM_CNTL 0x1195 2933 #define regCP_CPG_DSM_CNTL_BASE_IDX 0 2934 #define regCP_CPC_DSM_CNTL 0x1196 2935 #define regCP_CPC_DSM_CNTL_BASE_IDX 0 2936 #define regCP_CPF_DSM_CNTL2 0x1197 2937 #define regCP_CPF_DSM_CNTL2_BASE_IDX 0 2938 #define regCP_CPG_DSM_CNTL2 0x1198 2939 #define regCP_CPG_DSM_CNTL2_BASE_IDX 0 2940 #define regCP_CPC_DSM_CNTL2 0x1199 2941 #define regCP_CPC_DSM_CNTL2_BASE_IDX 0 2942 #define regCP_CPF_DSM_CNTL2A 0x119a 2943 #define regCP_CPF_DSM_CNTL2A_BASE_IDX 0 2944 #define regCP_CPG_DSM_CNTL2A 0x119b 2945 #define regCP_CPG_DSM_CNTL2A_BASE_IDX 0 2946 #define regCP_CPC_DSM_CNTL2A 0x119c 2947 #define regCP_CPC_DSM_CNTL2A_BASE_IDX 0 2948 #define regCP_EDC_FUE_CNTL 0x119d 2949 #define regCP_EDC_FUE_CNTL_BASE_IDX 0 2950 #define regCP_GFX_MQD_CONTROL 0x11a0 2951 #define regCP_GFX_MQD_CONTROL_BASE_IDX 0 2952 #define regCP_GFX_MQD_BASE_ADDR 0x11a1 2953 #define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 2954 #define regCP_GFX_MQD_BASE_ADDR_HI 0x11a2 2955 #define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 2956 #define regCP_RB_STATUS 0x11a3 2957 #define regCP_RB_STATUS_BASE_IDX 0 2958 #define regCPG_UTCL1_STATUS 0x11b4 2959 #define regCPG_UTCL1_STATUS_BASE_IDX 0 2960 #define regCPC_UTCL1_STATUS 0x11b5 2961 #define regCPC_UTCL1_STATUS_BASE_IDX 0 2962 #define regCPF_UTCL1_STATUS 0x11b6 2963 #define regCPF_UTCL1_STATUS_BASE_IDX 0 2964 #define regCP_SD_CNTL 0x11b7 2965 #define regCP_SD_CNTL_BASE_IDX 0 2966 #define regCP_SOFT_RESET_CNTL 0x11b9 2967 #define regCP_SOFT_RESET_CNTL_BASE_IDX 0 2968 #define regCP_CPC_GFX_CNTL 0x11ba 2969 #define regCP_CPC_GFX_CNTL_BASE_IDX 0 2970 2971 2972 // addressBlock: xcd0_gc_spipdec 2973 // base address: 0xc700 2974 #define regSPI_ARB_PRIORITY 0x11c0 2975 #define regSPI_ARB_PRIORITY_BASE_IDX 0 2976 #define regSPI_ARB_CYCLES_0 0x11c1 2977 #define regSPI_ARB_CYCLES_0_BASE_IDX 0 2978 #define regSPI_ARB_CYCLES_1 0x11c2 2979 #define regSPI_ARB_CYCLES_1_BASE_IDX 0 2980 #define regSPI_CDBG_SYS_GFX 0x11c3 2981 #define regSPI_CDBG_SYS_GFX_BASE_IDX 0 2982 #define regSPI_CDBG_SYS_HP3D 0x11c4 2983 #define regSPI_CDBG_SYS_HP3D_BASE_IDX 0 2984 #define regSPI_CDBG_SYS_CS0 0x11c5 2985 #define regSPI_CDBG_SYS_CS0_BASE_IDX 0 2986 #define regSPI_CDBG_SYS_CS1 0x11c6 2987 #define regSPI_CDBG_SYS_CS1_BASE_IDX 0 2988 #define regSPI_WCL_PIPE_PERCENT_GFX 0x11c7 2989 #define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 2990 #define regSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 2991 #define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 2992 #define regSPI_WCL_PIPE_PERCENT_CS0 0x11c9 2993 #define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 2994 #define regSPI_WCL_PIPE_PERCENT_CS1 0x11ca 2995 #define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 2996 #define regSPI_WCL_PIPE_PERCENT_CS2 0x11cb 2997 #define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 2998 #define regSPI_WCL_PIPE_PERCENT_CS3 0x11cc 2999 #define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 3000 #define regSPI_WCL_PIPE_PERCENT_CS4 0x11cd 3001 #define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 3002 #define regSPI_WCL_PIPE_PERCENT_CS5 0x11ce 3003 #define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 3004 #define regSPI_WCL_PIPE_PERCENT_CS6 0x11cf 3005 #define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 3006 #define regSPI_WCL_PIPE_PERCENT_CS7 0x11d0 3007 #define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 3008 #define regSPI_GDBG_WAVE_CNTL 0x11d1 3009 #define regSPI_GDBG_WAVE_CNTL_BASE_IDX 0 3010 #define regSPI_GDBG_TRAP_CONFIG 0x11d2 3011 #define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 3012 #define regSPI_GDBG_PER_VMID_CNTL 0x11d3 3013 #define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 3014 #define regSPI_GDBG_WAVE_CNTL3 0x11d5 3015 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 3016 #define regSPI_SCRATCH_ADDR_CHECK 0x11d8 3017 #define regSPI_SCRATCH_ADDR_CHECK_BASE_IDX 0 3018 #define regSPI_SCRATCH_ADDR_STATUS 0x11d9 3019 #define regSPI_SCRATCH_ADDR_STATUS_BASE_IDX 0 3020 #define regSPI_RESET_DEBUG 0x11da 3021 #define regSPI_RESET_DEBUG_BASE_IDX 0 3022 #define regSPI_COMPUTE_QUEUE_RESET 0x11db 3023 #define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 3024 #define regSPI_RESOURCE_RESERVE_CU_0 0x11dc 3025 #define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 3026 #define regSPI_RESOURCE_RESERVE_CU_1 0x11dd 3027 #define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 3028 #define regSPI_RESOURCE_RESERVE_CU_2 0x11de 3029 #define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 3030 #define regSPI_RESOURCE_RESERVE_CU_3 0x11df 3031 #define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 3032 #define regSPI_RESOURCE_RESERVE_CU_4 0x11e0 3033 #define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 3034 #define regSPI_RESOURCE_RESERVE_CU_5 0x11e1 3035 #define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 3036 #define regSPI_RESOURCE_RESERVE_CU_6 0x11e2 3037 #define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 3038 #define regSPI_RESOURCE_RESERVE_CU_7 0x11e3 3039 #define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 3040 #define regSPI_RESOURCE_RESERVE_CU_8 0x11e4 3041 #define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 3042 #define regSPI_RESOURCE_RESERVE_CU_9 0x11e5 3043 #define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 3044 #define regSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 3045 #define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 3046 #define regSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 3047 #define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 3048 #define regSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 3049 #define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 3050 #define regSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 3051 #define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 3052 #define regSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea 3053 #define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 3054 #define regSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb 3055 #define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 3056 #define regSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec 3057 #define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 3058 #define regSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed 3059 #define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 3060 #define regSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee 3061 #define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 3062 #define regSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef 3063 #define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 3064 #define regSPI_RESOURCE_RESERVE_CU_10 0x11f0 3065 #define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 3066 #define regSPI_RESOURCE_RESERVE_CU_11 0x11f1 3067 #define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 3068 #define regSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 3069 #define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 3070 #define regSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 3071 #define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 3072 #define regSPI_RESOURCE_RESERVE_CU_12 0x11f4 3073 #define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 3074 #define regSPI_RESOURCE_RESERVE_CU_13 0x11f5 3075 #define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 3076 #define regSPI_RESOURCE_RESERVE_CU_14 0x11f6 3077 #define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 3078 #define regSPI_RESOURCE_RESERVE_CU_15 0x11f7 3079 #define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 3080 #define regSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 3081 #define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 3082 #define regSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 3083 #define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 3084 #define regSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa 3085 #define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 3086 #define regSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb 3087 #define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 3088 #define regSPI_COMPUTE_WF_CTX_SAVE 0x11fc 3089 #define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 3090 #define regSPI_ARB_CNTL_0 0x11fd 3091 #define regSPI_ARB_CNTL_0_BASE_IDX 0 3092 3093 3094 // addressBlock: xcd0_gc_cpphqddec 3095 // base address: 0xc800 3096 #define regCP_HQD_GFX_CONTROL 0x123e 3097 #define regCP_HQD_GFX_CONTROL_BASE_IDX 0 3098 #define regCP_HQD_GFX_STATUS 0x123f 3099 #define regCP_HQD_GFX_STATUS_BASE_IDX 0 3100 #define regCP_HPD_ROQ_OFFSETS 0x1240 3101 #define regCP_HPD_ROQ_OFFSETS_BASE_IDX 0 3102 #define regCP_HPD_STATUS0 0x1241 3103 #define regCP_HPD_STATUS0_BASE_IDX 0 3104 #define regCP_HPD_UTCL1_CNTL 0x1242 3105 #define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 3106 #define regCP_HPD_UTCL1_ERROR 0x1243 3107 #define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 3108 #define regCP_HPD_UTCL1_ERROR_ADDR 0x1244 3109 #define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 3110 #define regCP_MQD_BASE_ADDR 0x1245 3111 #define regCP_MQD_BASE_ADDR_BASE_IDX 0 3112 #define regCP_MQD_BASE_ADDR_HI 0x1246 3113 #define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 3114 #define regCP_HQD_ACTIVE 0x1247 3115 #define regCP_HQD_ACTIVE_BASE_IDX 0 3116 #define regCP_HQD_VMID 0x1248 3117 #define regCP_HQD_VMID_BASE_IDX 0 3118 #define regCP_HQD_PERSISTENT_STATE 0x1249 3119 #define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 3120 #define regCP_HQD_PIPE_PRIORITY 0x124a 3121 #define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 3122 #define regCP_HQD_QUEUE_PRIORITY 0x124b 3123 #define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 3124 #define regCP_HQD_QUANTUM 0x124c 3125 #define regCP_HQD_QUANTUM_BASE_IDX 0 3126 #define regCP_HQD_PQ_BASE 0x124d 3127 #define regCP_HQD_PQ_BASE_BASE_IDX 0 3128 #define regCP_HQD_PQ_BASE_HI 0x124e 3129 #define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 3130 #define regCP_HQD_PQ_RPTR 0x124f 3131 #define regCP_HQD_PQ_RPTR_BASE_IDX 0 3132 #define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 3133 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 3134 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 3135 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 3136 #define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 3137 #define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 3138 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 3139 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 3140 #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254 3141 #define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 3142 #define regCP_HQD_PQ_CONTROL 0x1256 3143 #define regCP_HQD_PQ_CONTROL_BASE_IDX 0 3144 #define regCP_HQD_IB_BASE_ADDR 0x1257 3145 #define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 3146 #define regCP_HQD_IB_BASE_ADDR_HI 0x1258 3147 #define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 3148 #define regCP_HQD_IB_RPTR 0x1259 3149 #define regCP_HQD_IB_RPTR_BASE_IDX 0 3150 #define regCP_HQD_IB_CONTROL 0x125a 3151 #define regCP_HQD_IB_CONTROL_BASE_IDX 0 3152 #define regCP_HQD_IQ_TIMER 0x125b 3153 #define regCP_HQD_IQ_TIMER_BASE_IDX 0 3154 #define regCP_HQD_IQ_RPTR 0x125c 3155 #define regCP_HQD_IQ_RPTR_BASE_IDX 0 3156 #define regCP_HQD_DEQUEUE_REQUEST 0x125d 3157 #define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 3158 #define regCP_HQD_DMA_OFFLOAD 0x125e 3159 #define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 3160 #define regCP_HQD_OFFLOAD 0x125e 3161 #define regCP_HQD_OFFLOAD_BASE_IDX 0 3162 #define regCP_HQD_SEMA_CMD 0x125f 3163 #define regCP_HQD_SEMA_CMD_BASE_IDX 0 3164 #define regCP_HQD_MSG_TYPE 0x1260 3165 #define regCP_HQD_MSG_TYPE_BASE_IDX 0 3166 #define regCP_HQD_ATOMIC0_PREOP_LO 0x1261 3167 #define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 3168 #define regCP_HQD_ATOMIC0_PREOP_HI 0x1262 3169 #define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 3170 #define regCP_HQD_ATOMIC1_PREOP_LO 0x1263 3171 #define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 3172 #define regCP_HQD_ATOMIC1_PREOP_HI 0x1264 3173 #define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 3174 #define regCP_HQD_HQ_SCHEDULER0 0x1265 3175 #define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 3176 #define regCP_HQD_HQ_STATUS0 0x1265 3177 #define regCP_HQD_HQ_STATUS0_BASE_IDX 0 3178 #define regCP_HQD_HQ_CONTROL0 0x1266 3179 #define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 3180 #define regCP_HQD_HQ_SCHEDULER1 0x1266 3181 #define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 3182 #define regCP_MQD_CONTROL 0x1267 3183 #define regCP_MQD_CONTROL_BASE_IDX 0 3184 #define regCP_HQD_HQ_STATUS1 0x1268 3185 #define regCP_HQD_HQ_STATUS1_BASE_IDX 0 3186 #define regCP_HQD_HQ_CONTROL1 0x1269 3187 #define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 3188 #define regCP_HQD_EOP_BASE_ADDR 0x126a 3189 #define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 3190 #define regCP_HQD_EOP_BASE_ADDR_HI 0x126b 3191 #define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 3192 #define regCP_HQD_EOP_CONTROL 0x126c 3193 #define regCP_HQD_EOP_CONTROL_BASE_IDX 0 3194 #define regCP_HQD_EOP_RPTR 0x126d 3195 #define regCP_HQD_EOP_RPTR_BASE_IDX 0 3196 #define regCP_HQD_EOP_WPTR 0x126e 3197 #define regCP_HQD_EOP_WPTR_BASE_IDX 0 3198 #define regCP_HQD_EOP_EVENTS 0x126f 3199 #define regCP_HQD_EOP_EVENTS_BASE_IDX 0 3200 #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 3201 #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 3202 #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 3203 #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 3204 #define regCP_HQD_CTX_SAVE_CONTROL 0x1272 3205 #define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 3206 #define regCP_HQD_CNTL_STACK_OFFSET 0x1273 3207 #define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 3208 #define regCP_HQD_CNTL_STACK_SIZE 0x1274 3209 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 3210 #define regCP_HQD_WG_STATE_OFFSET 0x1275 3211 #define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 3212 #define regCP_HQD_CTX_SAVE_SIZE 0x1276 3213 #define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 3214 #define regCP_HQD_GDS_RESOURCE_STATE 0x1277 3215 #define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 3216 #define regCP_HQD_ERROR 0x1278 3217 #define regCP_HQD_ERROR_BASE_IDX 0 3218 #define regCP_HQD_EOP_WPTR_MEM 0x1279 3219 #define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 3220 #define regCP_HQD_AQL_CONTROL 0x127a 3221 #define regCP_HQD_AQL_CONTROL_BASE_IDX 0 3222 #define regCP_HQD_PQ_WPTR_LO 0x127b 3223 #define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 3224 #define regCP_HQD_PQ_WPTR_HI 0x127c 3225 #define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 3226 #define regCP_HQD_AQL_CONTROL_1 0x127d 3227 #define regCP_HQD_AQL_CONTROL_1_BASE_IDX 0 3228 #define regCP_HQD_AQL_DISPATCH_ID 0x127e 3229 #define regCP_HQD_AQL_DISPATCH_ID_BASE_IDX 0 3230 #define regCP_HQD_AQL_DISPATCH_ID_HI 0x127f 3231 #define regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX 0 3232 3233 3234 // addressBlock: xcd0_gc_tcpdec 3235 // base address: 0xca80 3236 #define regTCP_WATCH0_ADDR_H 0x12a0 3237 #define regTCP_WATCH0_ADDR_H_BASE_IDX 0 3238 #define regTCP_WATCH0_ADDR_L 0x12a1 3239 #define regTCP_WATCH0_ADDR_L_BASE_IDX 0 3240 #define regTCP_WATCH0_CNTL 0x12a2 3241 #define regTCP_WATCH0_CNTL_BASE_IDX 0 3242 #define regTCP_WATCH1_ADDR_H 0x12a3 3243 #define regTCP_WATCH1_ADDR_H_BASE_IDX 0 3244 #define regTCP_WATCH1_ADDR_L 0x12a4 3245 #define regTCP_WATCH1_ADDR_L_BASE_IDX 0 3246 #define regTCP_WATCH1_CNTL 0x12a5 3247 #define regTCP_WATCH1_CNTL_BASE_IDX 0 3248 #define regTCP_WATCH2_ADDR_H 0x12a6 3249 #define regTCP_WATCH2_ADDR_H_BASE_IDX 0 3250 #define regTCP_WATCH2_ADDR_L 0x12a7 3251 #define regTCP_WATCH2_ADDR_L_BASE_IDX 0 3252 #define regTCP_WATCH2_CNTL 0x12a8 3253 #define regTCP_WATCH2_CNTL_BASE_IDX 0 3254 #define regTCP_WATCH3_ADDR_H 0x12a9 3255 #define regTCP_WATCH3_ADDR_H_BASE_IDX 0 3256 #define regTCP_WATCH3_ADDR_L 0x12aa 3257 #define regTCP_WATCH3_ADDR_L_BASE_IDX 0 3258 #define regTCP_WATCH3_CNTL 0x12ab 3259 #define regTCP_WATCH3_CNTL_BASE_IDX 0 3260 #define regTCP_GATCL1_CNTL 0x12b0 3261 #define regTCP_GATCL1_CNTL_BASE_IDX 0 3262 #define regTCP_ATC_EDC_GATCL1_CNT 0x12b1 3263 #define regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 3264 #define regTCP_GATCL1_DSM_CNTL 0x12b2 3265 #define regTCP_GATCL1_DSM_CNTL_BASE_IDX 0 3266 #define regTCP_DSM_CNTL 0x12b3 3267 #define regTCP_DSM_CNTL_BASE_IDX 0 3268 #define regTCP_CNTL2 0x12b4 3269 #define regTCP_CNTL2_BASE_IDX 0 3270 #define regTCP_UTCL1_CNTL1 0x12b5 3271 #define regTCP_UTCL1_CNTL1_BASE_IDX 0 3272 #define regTCP_UTCL1_CNTL2 0x12b6 3273 #define regTCP_UTCL1_CNTL2_BASE_IDX 0 3274 #define regTCP_UTCL1_STATUS 0x12b7 3275 #define regTCP_UTCL1_STATUS_BASE_IDX 0 3276 #define regTCP_DSM_CNTL2 0x12b8 3277 #define regTCP_DSM_CNTL2_BASE_IDX 0 3278 #define regTCP_PERFCOUNTER_FILTER 0x12b9 3279 #define regTCP_PERFCOUNTER_FILTER_BASE_IDX 0 3280 #define regTCP_PERFCOUNTER_FILTER_EN 0x12ba 3281 #define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 3282 3283 3284 // addressBlock: xcd0_gc_gdspdec 3285 // base address: 0xcc00 3286 #define regGDS_VMID0_BASE 0x1300 3287 #define regGDS_VMID0_BASE_BASE_IDX 0 3288 #define regGDS_VMID0_SIZE 0x1301 3289 #define regGDS_VMID0_SIZE_BASE_IDX 0 3290 #define regGDS_VMID1_BASE 0x1302 3291 #define regGDS_VMID1_BASE_BASE_IDX 0 3292 #define regGDS_VMID1_SIZE 0x1303 3293 #define regGDS_VMID1_SIZE_BASE_IDX 0 3294 #define regGDS_VMID2_BASE 0x1304 3295 #define regGDS_VMID2_BASE_BASE_IDX 0 3296 #define regGDS_VMID2_SIZE 0x1305 3297 #define regGDS_VMID2_SIZE_BASE_IDX 0 3298 #define regGDS_VMID3_BASE 0x1306 3299 #define regGDS_VMID3_BASE_BASE_IDX 0 3300 #define regGDS_VMID3_SIZE 0x1307 3301 #define regGDS_VMID3_SIZE_BASE_IDX 0 3302 #define regGDS_VMID4_BASE 0x1308 3303 #define regGDS_VMID4_BASE_BASE_IDX 0 3304 #define regGDS_VMID4_SIZE 0x1309 3305 #define regGDS_VMID4_SIZE_BASE_IDX 0 3306 #define regGDS_VMID5_BASE 0x130a 3307 #define regGDS_VMID5_BASE_BASE_IDX 0 3308 #define regGDS_VMID5_SIZE 0x130b 3309 #define regGDS_VMID5_SIZE_BASE_IDX 0 3310 #define regGDS_VMID6_BASE 0x130c 3311 #define regGDS_VMID6_BASE_BASE_IDX 0 3312 #define regGDS_VMID6_SIZE 0x130d 3313 #define regGDS_VMID6_SIZE_BASE_IDX 0 3314 #define regGDS_VMID7_BASE 0x130e 3315 #define regGDS_VMID7_BASE_BASE_IDX 0 3316 #define regGDS_VMID7_SIZE 0x130f 3317 #define regGDS_VMID7_SIZE_BASE_IDX 0 3318 #define regGDS_VMID8_BASE 0x1310 3319 #define regGDS_VMID8_BASE_BASE_IDX 0 3320 #define regGDS_VMID8_SIZE 0x1311 3321 #define regGDS_VMID8_SIZE_BASE_IDX 0 3322 #define regGDS_VMID9_BASE 0x1312 3323 #define regGDS_VMID9_BASE_BASE_IDX 0 3324 #define regGDS_VMID9_SIZE 0x1313 3325 #define regGDS_VMID9_SIZE_BASE_IDX 0 3326 #define regGDS_VMID10_BASE 0x1314 3327 #define regGDS_VMID10_BASE_BASE_IDX 0 3328 #define regGDS_VMID10_SIZE 0x1315 3329 #define regGDS_VMID10_SIZE_BASE_IDX 0 3330 #define regGDS_VMID11_BASE 0x1316 3331 #define regGDS_VMID11_BASE_BASE_IDX 0 3332 #define regGDS_VMID11_SIZE 0x1317 3333 #define regGDS_VMID11_SIZE_BASE_IDX 0 3334 #define regGDS_VMID12_BASE 0x1318 3335 #define regGDS_VMID12_BASE_BASE_IDX 0 3336 #define regGDS_VMID12_SIZE 0x1319 3337 #define regGDS_VMID12_SIZE_BASE_IDX 0 3338 #define regGDS_VMID13_BASE 0x131a 3339 #define regGDS_VMID13_BASE_BASE_IDX 0 3340 #define regGDS_VMID13_SIZE 0x131b 3341 #define regGDS_VMID13_SIZE_BASE_IDX 0 3342 #define regGDS_VMID14_BASE 0x131c 3343 #define regGDS_VMID14_BASE_BASE_IDX 0 3344 #define regGDS_VMID14_SIZE 0x131d 3345 #define regGDS_VMID14_SIZE_BASE_IDX 0 3346 #define regGDS_VMID15_BASE 0x131e 3347 #define regGDS_VMID15_BASE_BASE_IDX 0 3348 #define regGDS_VMID15_SIZE 0x131f 3349 #define regGDS_VMID15_SIZE_BASE_IDX 0 3350 #define regGDS_GWS_VMID0 0x1320 3351 #define regGDS_GWS_VMID0_BASE_IDX 0 3352 #define regGDS_GWS_VMID1 0x1321 3353 #define regGDS_GWS_VMID1_BASE_IDX 0 3354 #define regGDS_GWS_VMID2 0x1322 3355 #define regGDS_GWS_VMID2_BASE_IDX 0 3356 #define regGDS_GWS_VMID3 0x1323 3357 #define regGDS_GWS_VMID3_BASE_IDX 0 3358 #define regGDS_GWS_VMID4 0x1324 3359 #define regGDS_GWS_VMID4_BASE_IDX 0 3360 #define regGDS_GWS_VMID5 0x1325 3361 #define regGDS_GWS_VMID5_BASE_IDX 0 3362 #define regGDS_GWS_VMID6 0x1326 3363 #define regGDS_GWS_VMID6_BASE_IDX 0 3364 #define regGDS_GWS_VMID7 0x1327 3365 #define regGDS_GWS_VMID7_BASE_IDX 0 3366 #define regGDS_GWS_VMID8 0x1328 3367 #define regGDS_GWS_VMID8_BASE_IDX 0 3368 #define regGDS_GWS_VMID9 0x1329 3369 #define regGDS_GWS_VMID9_BASE_IDX 0 3370 #define regGDS_GWS_VMID10 0x132a 3371 #define regGDS_GWS_VMID10_BASE_IDX 0 3372 #define regGDS_GWS_VMID11 0x132b 3373 #define regGDS_GWS_VMID11_BASE_IDX 0 3374 #define regGDS_GWS_VMID12 0x132c 3375 #define regGDS_GWS_VMID12_BASE_IDX 0 3376 #define regGDS_GWS_VMID13 0x132d 3377 #define regGDS_GWS_VMID13_BASE_IDX 0 3378 #define regGDS_GWS_VMID14 0x132e 3379 #define regGDS_GWS_VMID14_BASE_IDX 0 3380 #define regGDS_GWS_VMID15 0x132f 3381 #define regGDS_GWS_VMID15_BASE_IDX 0 3382 #define regGDS_OA_VMID0 0x1330 3383 #define regGDS_OA_VMID0_BASE_IDX 0 3384 #define regGDS_OA_VMID1 0x1331 3385 #define regGDS_OA_VMID1_BASE_IDX 0 3386 #define regGDS_OA_VMID2 0x1332 3387 #define regGDS_OA_VMID2_BASE_IDX 0 3388 #define regGDS_OA_VMID3 0x1333 3389 #define regGDS_OA_VMID3_BASE_IDX 0 3390 #define regGDS_OA_VMID4 0x1334 3391 #define regGDS_OA_VMID4_BASE_IDX 0 3392 #define regGDS_OA_VMID5 0x1335 3393 #define regGDS_OA_VMID5_BASE_IDX 0 3394 #define regGDS_OA_VMID6 0x1336 3395 #define regGDS_OA_VMID6_BASE_IDX 0 3396 #define regGDS_OA_VMID7 0x1337 3397 #define regGDS_OA_VMID7_BASE_IDX 0 3398 #define regGDS_OA_VMID8 0x1338 3399 #define regGDS_OA_VMID8_BASE_IDX 0 3400 #define regGDS_OA_VMID9 0x1339 3401 #define regGDS_OA_VMID9_BASE_IDX 0 3402 #define regGDS_OA_VMID10 0x133a 3403 #define regGDS_OA_VMID10_BASE_IDX 0 3404 #define regGDS_OA_VMID11 0x133b 3405 #define regGDS_OA_VMID11_BASE_IDX 0 3406 #define regGDS_OA_VMID12 0x133c 3407 #define regGDS_OA_VMID12_BASE_IDX 0 3408 #define regGDS_OA_VMID13 0x133d 3409 #define regGDS_OA_VMID13_BASE_IDX 0 3410 #define regGDS_OA_VMID14 0x133e 3411 #define regGDS_OA_VMID14_BASE_IDX 0 3412 #define regGDS_OA_VMID15 0x133f 3413 #define regGDS_OA_VMID15_BASE_IDX 0 3414 #define regGDS_GWS_RESET0 0x1344 3415 #define regGDS_GWS_RESET0_BASE_IDX 0 3416 #define regGDS_GWS_RESET1 0x1345 3417 #define regGDS_GWS_RESET1_BASE_IDX 0 3418 #define regGDS_GWS_RESOURCE_RESET 0x1346 3419 #define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 3420 #define regGDS_COMPUTE_MAX_WAVE_ID 0x1348 3421 #define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 3422 #define regGDS_OA_RESET_MASK 0x1349 3423 #define regGDS_OA_RESET_MASK_BASE_IDX 0 3424 #define regGDS_OA_RESET 0x134a 3425 #define regGDS_OA_RESET_BASE_IDX 0 3426 #define regGDS_ENHANCE 0x134b 3427 #define regGDS_ENHANCE_BASE_IDX 0 3428 #define regGDS_OA_CGPG_RESTORE 0x134c 3429 #define regGDS_OA_CGPG_RESTORE_BASE_IDX 0 3430 #define regGDS_CS_CTXSW_STATUS 0x134d 3431 #define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 3432 #define regGDS_CS_CTXSW_CNT0 0x134e 3433 #define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 3434 #define regGDS_CS_CTXSW_CNT1 0x134f 3435 #define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 3436 #define regGDS_CS_CTXSW_CNT2 0x1350 3437 #define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 3438 #define regGDS_CS_CTXSW_CNT3 0x1351 3439 #define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 3440 #define regGDS_GFX_CTXSW_STATUS 0x1352 3441 #define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 3442 #define regGDS_VS_CTXSW_CNT0 0x1353 3443 #define regGDS_VS_CTXSW_CNT0_BASE_IDX 0 3444 #define regGDS_VS_CTXSW_CNT1 0x1354 3445 #define regGDS_VS_CTXSW_CNT1_BASE_IDX 0 3446 #define regGDS_VS_CTXSW_CNT2 0x1355 3447 #define regGDS_VS_CTXSW_CNT2_BASE_IDX 0 3448 #define regGDS_VS_CTXSW_CNT3 0x1356 3449 #define regGDS_VS_CTXSW_CNT3_BASE_IDX 0 3450 #define regGDS_PS0_CTXSW_CNT0 0x1357 3451 #define regGDS_PS0_CTXSW_CNT0_BASE_IDX 0 3452 #define regGDS_PS0_CTXSW_CNT1 0x1358 3453 #define regGDS_PS0_CTXSW_CNT1_BASE_IDX 0 3454 #define regGDS_PS0_CTXSW_CNT2 0x1359 3455 #define regGDS_PS0_CTXSW_CNT2_BASE_IDX 0 3456 #define regGDS_PS0_CTXSW_CNT3 0x135a 3457 #define regGDS_PS0_CTXSW_CNT3_BASE_IDX 0 3458 #define regGDS_PS1_CTXSW_CNT0 0x135b 3459 #define regGDS_PS1_CTXSW_CNT0_BASE_IDX 0 3460 #define regGDS_PS1_CTXSW_CNT1 0x135c 3461 #define regGDS_PS1_CTXSW_CNT1_BASE_IDX 0 3462 #define regGDS_PS1_CTXSW_CNT2 0x135d 3463 #define regGDS_PS1_CTXSW_CNT2_BASE_IDX 0 3464 #define regGDS_PS1_CTXSW_CNT3 0x135e 3465 #define regGDS_PS1_CTXSW_CNT3_BASE_IDX 0 3466 #define regGDS_PS2_CTXSW_CNT0 0x135f 3467 #define regGDS_PS2_CTXSW_CNT0_BASE_IDX 0 3468 #define regGDS_PS2_CTXSW_CNT1 0x1360 3469 #define regGDS_PS2_CTXSW_CNT1_BASE_IDX 0 3470 #define regGDS_PS2_CTXSW_CNT2 0x1361 3471 #define regGDS_PS2_CTXSW_CNT2_BASE_IDX 0 3472 #define regGDS_PS2_CTXSW_CNT3 0x1362 3473 #define regGDS_PS2_CTXSW_CNT3_BASE_IDX 0 3474 #define regGDS_PS3_CTXSW_CNT0 0x1363 3475 #define regGDS_PS3_CTXSW_CNT0_BASE_IDX 0 3476 #define regGDS_PS3_CTXSW_CNT1 0x1364 3477 #define regGDS_PS3_CTXSW_CNT1_BASE_IDX 0 3478 #define regGDS_PS3_CTXSW_CNT2 0x1365 3479 #define regGDS_PS3_CTXSW_CNT2_BASE_IDX 0 3480 #define regGDS_PS3_CTXSW_CNT3 0x1366 3481 #define regGDS_PS3_CTXSW_CNT3_BASE_IDX 0 3482 #define regGDS_PS4_CTXSW_CNT0 0x1367 3483 #define regGDS_PS4_CTXSW_CNT0_BASE_IDX 0 3484 #define regGDS_PS4_CTXSW_CNT1 0x1368 3485 #define regGDS_PS4_CTXSW_CNT1_BASE_IDX 0 3486 #define regGDS_PS4_CTXSW_CNT2 0x1369 3487 #define regGDS_PS4_CTXSW_CNT2_BASE_IDX 0 3488 #define regGDS_PS4_CTXSW_CNT3 0x136a 3489 #define regGDS_PS4_CTXSW_CNT3_BASE_IDX 0 3490 #define regGDS_PS5_CTXSW_CNT0 0x136b 3491 #define regGDS_PS5_CTXSW_CNT0_BASE_IDX 0 3492 #define regGDS_PS5_CTXSW_CNT1 0x136c 3493 #define regGDS_PS5_CTXSW_CNT1_BASE_IDX 0 3494 #define regGDS_PS5_CTXSW_CNT2 0x136d 3495 #define regGDS_PS5_CTXSW_CNT2_BASE_IDX 0 3496 #define regGDS_PS5_CTXSW_CNT3 0x136e 3497 #define regGDS_PS5_CTXSW_CNT3_BASE_IDX 0 3498 #define regGDS_PS6_CTXSW_CNT0 0x136f 3499 #define regGDS_PS6_CTXSW_CNT0_BASE_IDX 0 3500 #define regGDS_PS6_CTXSW_CNT1 0x1370 3501 #define regGDS_PS6_CTXSW_CNT1_BASE_IDX 0 3502 #define regGDS_PS6_CTXSW_CNT2 0x1371 3503 #define regGDS_PS6_CTXSW_CNT2_BASE_IDX 0 3504 #define regGDS_PS6_CTXSW_CNT3 0x1372 3505 #define regGDS_PS6_CTXSW_CNT3_BASE_IDX 0 3506 #define regGDS_PS7_CTXSW_CNT0 0x1373 3507 #define regGDS_PS7_CTXSW_CNT0_BASE_IDX 0 3508 #define regGDS_PS7_CTXSW_CNT1 0x1374 3509 #define regGDS_PS7_CTXSW_CNT1_BASE_IDX 0 3510 #define regGDS_PS7_CTXSW_CNT2 0x1375 3511 #define regGDS_PS7_CTXSW_CNT2_BASE_IDX 0 3512 #define regGDS_PS7_CTXSW_CNT3 0x1376 3513 #define regGDS_PS7_CTXSW_CNT3_BASE_IDX 0 3514 #define regGDS_GS_CTXSW_CNT0 0x1377 3515 #define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 3516 #define regGDS_GS_CTXSW_CNT1 0x1378 3517 #define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 3518 #define regGDS_GS_CTXSW_CNT2 0x1379 3519 #define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 3520 #define regGDS_GS_CTXSW_CNT3 0x137a 3521 #define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 3522 3523 3524 // addressBlock: xcd0_gc_rasdec 3525 // base address: 0xce00 3526 #define regRAS_SIGNATURE_CONTROL 0x1380 3527 #define regRAS_SIGNATURE_CONTROL_BASE_IDX 0 3528 #define regRAS_SIGNATURE_MASK 0x1381 3529 #define regRAS_SIGNATURE_MASK_BASE_IDX 0 3530 #define regRAS_SX_SIGNATURE0 0x1382 3531 #define regRAS_SX_SIGNATURE0_BASE_IDX 0 3532 #define regRAS_SX_SIGNATURE1 0x1383 3533 #define regRAS_SX_SIGNATURE1_BASE_IDX 0 3534 #define regRAS_SX_SIGNATURE2 0x1384 3535 #define regRAS_SX_SIGNATURE2_BASE_IDX 0 3536 #define regRAS_SX_SIGNATURE3 0x1385 3537 #define regRAS_SX_SIGNATURE3_BASE_IDX 0 3538 #define regRAS_DB_SIGNATURE0 0x138b 3539 #define regRAS_DB_SIGNATURE0_BASE_IDX 0 3540 #define regRAS_PA_SIGNATURE0 0x138c 3541 #define regRAS_PA_SIGNATURE0_BASE_IDX 0 3542 #define regRAS_VGT_SIGNATURE0 0x138d 3543 #define regRAS_VGT_SIGNATURE0_BASE_IDX 0 3544 #define regRAS_SQ_SIGNATURE0 0x138e 3545 #define regRAS_SQ_SIGNATURE0_BASE_IDX 0 3546 #define regRAS_SC_SIGNATURE0 0x138f 3547 #define regRAS_SC_SIGNATURE0_BASE_IDX 0 3548 #define regRAS_SC_SIGNATURE1 0x1390 3549 #define regRAS_SC_SIGNATURE1_BASE_IDX 0 3550 #define regRAS_SC_SIGNATURE2 0x1391 3551 #define regRAS_SC_SIGNATURE2_BASE_IDX 0 3552 #define regRAS_SC_SIGNATURE3 0x1392 3553 #define regRAS_SC_SIGNATURE3_BASE_IDX 0 3554 #define regRAS_SC_SIGNATURE4 0x1393 3555 #define regRAS_SC_SIGNATURE4_BASE_IDX 0 3556 #define regRAS_SC_SIGNATURE5 0x1394 3557 #define regRAS_SC_SIGNATURE5_BASE_IDX 0 3558 #define regRAS_SC_SIGNATURE6 0x1395 3559 #define regRAS_SC_SIGNATURE6_BASE_IDX 0 3560 #define regRAS_SC_SIGNATURE7 0x1396 3561 #define regRAS_SC_SIGNATURE7_BASE_IDX 0 3562 #define regRAS_IA_SIGNATURE0 0x1397 3563 #define regRAS_IA_SIGNATURE0_BASE_IDX 0 3564 #define regRAS_IA_SIGNATURE1 0x1398 3565 #define regRAS_IA_SIGNATURE1_BASE_IDX 0 3566 #define regRAS_SPI_SIGNATURE0 0x1399 3567 #define regRAS_SPI_SIGNATURE0_BASE_IDX 0 3568 #define regRAS_SPI_SIGNATURE1 0x139a 3569 #define regRAS_SPI_SIGNATURE1_BASE_IDX 0 3570 #define regRAS_TA_SIGNATURE0 0x139b 3571 #define regRAS_TA_SIGNATURE0_BASE_IDX 0 3572 #define regRAS_TD_SIGNATURE0 0x139c 3573 #define regRAS_TD_SIGNATURE0_BASE_IDX 0 3574 #define regRAS_CB_SIGNATURE0 0x139d 3575 #define regRAS_CB_SIGNATURE0_BASE_IDX 0 3576 #define regRAS_BCI_SIGNATURE0 0x139e 3577 #define regRAS_BCI_SIGNATURE0_BASE_IDX 0 3578 #define regRAS_BCI_SIGNATURE1 0x139f 3579 #define regRAS_BCI_SIGNATURE1_BASE_IDX 0 3580 #define regRAS_TA_SIGNATURE1 0x13a0 3581 #define regRAS_TA_SIGNATURE1_BASE_IDX 0 3582 3583 3584 // addressBlock: xcd0_gc_gfxdec0 3585 // base address: 0x28000 3586 #define regDB_RENDER_CONTROL 0x0000 3587 #define regDB_RENDER_CONTROL_BASE_IDX 1 3588 #define regDB_COUNT_CONTROL 0x0001 3589 #define regDB_COUNT_CONTROL_BASE_IDX 1 3590 #define regDB_DEPTH_VIEW 0x0002 3591 #define regDB_DEPTH_VIEW_BASE_IDX 1 3592 #define regDB_RENDER_OVERRIDE 0x0003 3593 #define regDB_RENDER_OVERRIDE_BASE_IDX 1 3594 #define regDB_RENDER_OVERRIDE2 0x0004 3595 #define regDB_RENDER_OVERRIDE2_BASE_IDX 1 3596 #define regDB_HTILE_DATA_BASE 0x0005 3597 #define regDB_HTILE_DATA_BASE_BASE_IDX 1 3598 #define regDB_HTILE_DATA_BASE_HI 0x0006 3599 #define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 3600 #define regDB_DEPTH_SIZE 0x0007 3601 #define regDB_DEPTH_SIZE_BASE_IDX 1 3602 #define regDB_DEPTH_BOUNDS_MIN 0x0008 3603 #define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 3604 #define regDB_DEPTH_BOUNDS_MAX 0x0009 3605 #define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 3606 #define regDB_STENCIL_CLEAR 0x000a 3607 #define regDB_STENCIL_CLEAR_BASE_IDX 1 3608 #define regDB_DEPTH_CLEAR 0x000b 3609 #define regDB_DEPTH_CLEAR_BASE_IDX 1 3610 #define regPA_SC_SCREEN_SCISSOR_TL 0x000c 3611 #define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 3612 #define regPA_SC_SCREEN_SCISSOR_BR 0x000d 3613 #define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 3614 #define regDB_Z_INFO 0x000e 3615 #define regDB_Z_INFO_BASE_IDX 1 3616 #define regDB_STENCIL_INFO 0x000f 3617 #define regDB_STENCIL_INFO_BASE_IDX 1 3618 #define regDB_Z_READ_BASE 0x0010 3619 #define regDB_Z_READ_BASE_BASE_IDX 1 3620 #define regDB_Z_READ_BASE_HI 0x0011 3621 #define regDB_Z_READ_BASE_HI_BASE_IDX 1 3622 #define regDB_STENCIL_READ_BASE 0x0012 3623 #define regDB_STENCIL_READ_BASE_BASE_IDX 1 3624 #define regDB_STENCIL_READ_BASE_HI 0x0013 3625 #define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 3626 #define regDB_Z_WRITE_BASE 0x0014 3627 #define regDB_Z_WRITE_BASE_BASE_IDX 1 3628 #define regDB_Z_WRITE_BASE_HI 0x0015 3629 #define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 3630 #define regDB_STENCIL_WRITE_BASE 0x0016 3631 #define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 3632 #define regDB_STENCIL_WRITE_BASE_HI 0x0017 3633 #define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 3634 #define regDB_DFSM_CONTROL 0x0018 3635 #define regDB_DFSM_CONTROL_BASE_IDX 1 3636 #define regDB_Z_INFO2 0x001a 3637 #define regDB_Z_INFO2_BASE_IDX 1 3638 #define regDB_STENCIL_INFO2 0x001b 3639 #define regDB_STENCIL_INFO2_BASE_IDX 1 3640 #define regCOHER_DEST_BASE_HI_0 0x007a 3641 #define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 3642 #define regCOHER_DEST_BASE_HI_1 0x007b 3643 #define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 3644 #define regCOHER_DEST_BASE_HI_2 0x007c 3645 #define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 3646 #define regCOHER_DEST_BASE_HI_3 0x007d 3647 #define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 3648 #define regCOHER_DEST_BASE_2 0x007e 3649 #define regCOHER_DEST_BASE_2_BASE_IDX 1 3650 #define regCOHER_DEST_BASE_3 0x007f 3651 #define regCOHER_DEST_BASE_3_BASE_IDX 1 3652 #define regPA_SC_WINDOW_OFFSET 0x0080 3653 #define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 3654 #define regPA_SC_WINDOW_SCISSOR_TL 0x0081 3655 #define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 3656 #define regPA_SC_WINDOW_SCISSOR_BR 0x0082 3657 #define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 3658 #define regPA_SC_CLIPRECT_RULE 0x0083 3659 #define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 3660 #define regPA_SC_CLIPRECT_0_TL 0x0084 3661 #define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 3662 #define regPA_SC_CLIPRECT_0_BR 0x0085 3663 #define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 3664 #define regPA_SC_CLIPRECT_1_TL 0x0086 3665 #define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 3666 #define regPA_SC_CLIPRECT_1_BR 0x0087 3667 #define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 3668 #define regPA_SC_CLIPRECT_2_TL 0x0088 3669 #define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 3670 #define regPA_SC_CLIPRECT_2_BR 0x0089 3671 #define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 3672 #define regPA_SC_CLIPRECT_3_TL 0x008a 3673 #define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 3674 #define regPA_SC_CLIPRECT_3_BR 0x008b 3675 #define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 3676 #define regPA_SC_EDGERULE 0x008c 3677 #define regPA_SC_EDGERULE_BASE_IDX 1 3678 #define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d 3679 #define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 3680 #define regCB_TARGET_MASK 0x008e 3681 #define regCB_TARGET_MASK_BASE_IDX 1 3682 #define regCB_SHADER_MASK 0x008f 3683 #define regCB_SHADER_MASK_BASE_IDX 1 3684 #define regPA_SC_GENERIC_SCISSOR_TL 0x0090 3685 #define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 3686 #define regPA_SC_GENERIC_SCISSOR_BR 0x0091 3687 #define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 3688 #define regCOHER_DEST_BASE_0 0x0092 3689 #define regCOHER_DEST_BASE_0_BASE_IDX 1 3690 #define regCOHER_DEST_BASE_1 0x0093 3691 #define regCOHER_DEST_BASE_1_BASE_IDX 1 3692 #define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 3693 #define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 3694 #define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 3695 #define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 3696 #define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 3697 #define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 3698 #define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 3699 #define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 3700 #define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 3701 #define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 3702 #define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 3703 #define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 3704 #define regPA_SC_VPORT_SCISSOR_3_TL 0x009a 3705 #define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 3706 #define regPA_SC_VPORT_SCISSOR_3_BR 0x009b 3707 #define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 3708 #define regPA_SC_VPORT_SCISSOR_4_TL 0x009c 3709 #define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 3710 #define regPA_SC_VPORT_SCISSOR_4_BR 0x009d 3711 #define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 3712 #define regPA_SC_VPORT_SCISSOR_5_TL 0x009e 3713 #define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 3714 #define regPA_SC_VPORT_SCISSOR_5_BR 0x009f 3715 #define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 3716 #define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 3717 #define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 3718 #define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 3719 #define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 3720 #define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 3721 #define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 3722 #define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 3723 #define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 3724 #define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 3725 #define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 3726 #define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 3727 #define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 3728 #define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 3729 #define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 3730 #define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 3731 #define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 3732 #define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 3733 #define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 3734 #define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 3735 #define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 3736 #define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa 3737 #define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 3738 #define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab 3739 #define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 3740 #define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac 3741 #define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 3742 #define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad 3743 #define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 3744 #define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae 3745 #define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 3746 #define regPA_SC_VPORT_SCISSOR_13_BR 0x00af 3747 #define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 3748 #define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 3749 #define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 3750 #define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 3751 #define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 3752 #define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 3753 #define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 3754 #define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 3755 #define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 3756 #define regPA_SC_VPORT_ZMIN_0 0x00b4 3757 #define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 3758 #define regPA_SC_VPORT_ZMAX_0 0x00b5 3759 #define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 3760 #define regPA_SC_VPORT_ZMIN_1 0x00b6 3761 #define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 3762 #define regPA_SC_VPORT_ZMAX_1 0x00b7 3763 #define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 3764 #define regPA_SC_VPORT_ZMIN_2 0x00b8 3765 #define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 3766 #define regPA_SC_VPORT_ZMAX_2 0x00b9 3767 #define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 3768 #define regPA_SC_VPORT_ZMIN_3 0x00ba 3769 #define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 3770 #define regPA_SC_VPORT_ZMAX_3 0x00bb 3771 #define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 3772 #define regPA_SC_VPORT_ZMIN_4 0x00bc 3773 #define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 3774 #define regPA_SC_VPORT_ZMAX_4 0x00bd 3775 #define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 3776 #define regPA_SC_VPORT_ZMIN_5 0x00be 3777 #define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 3778 #define regPA_SC_VPORT_ZMAX_5 0x00bf 3779 #define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 3780 #define regPA_SC_VPORT_ZMIN_6 0x00c0 3781 #define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 3782 #define regPA_SC_VPORT_ZMAX_6 0x00c1 3783 #define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 3784 #define regPA_SC_VPORT_ZMIN_7 0x00c2 3785 #define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 3786 #define regPA_SC_VPORT_ZMAX_7 0x00c3 3787 #define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 3788 #define regPA_SC_VPORT_ZMIN_8 0x00c4 3789 #define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 3790 #define regPA_SC_VPORT_ZMAX_8 0x00c5 3791 #define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 3792 #define regPA_SC_VPORT_ZMIN_9 0x00c6 3793 #define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 3794 #define regPA_SC_VPORT_ZMAX_9 0x00c7 3795 #define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 3796 #define regPA_SC_VPORT_ZMIN_10 0x00c8 3797 #define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 3798 #define regPA_SC_VPORT_ZMAX_10 0x00c9 3799 #define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 3800 #define regPA_SC_VPORT_ZMIN_11 0x00ca 3801 #define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 3802 #define regPA_SC_VPORT_ZMAX_11 0x00cb 3803 #define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 3804 #define regPA_SC_VPORT_ZMIN_12 0x00cc 3805 #define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 3806 #define regPA_SC_VPORT_ZMAX_12 0x00cd 3807 #define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 3808 #define regPA_SC_VPORT_ZMIN_13 0x00ce 3809 #define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 3810 #define regPA_SC_VPORT_ZMAX_13 0x00cf 3811 #define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 3812 #define regPA_SC_VPORT_ZMIN_14 0x00d0 3813 #define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 3814 #define regPA_SC_VPORT_ZMAX_14 0x00d1 3815 #define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 3816 #define regPA_SC_VPORT_ZMIN_15 0x00d2 3817 #define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 3818 #define regPA_SC_VPORT_ZMAX_15 0x00d3 3819 #define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 3820 #define regPA_SC_RASTER_CONFIG 0x00d4 3821 #define regPA_SC_RASTER_CONFIG_BASE_IDX 1 3822 #define regPA_SC_RASTER_CONFIG_1 0x00d5 3823 #define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 3824 #define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 3825 #define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 3826 #define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 3827 #define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 3828 #define regCP_PERFMON_CNTX_CNTL 0x00d8 3829 #define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 3830 #define regCP_PIPEID 0x00d9 3831 #define regCP_PIPEID_BASE_IDX 1 3832 #define regCP_RINGID 0x00d9 3833 #define regCP_RINGID_BASE_IDX 1 3834 #define regCP_VMID 0x00da 3835 #define regCP_VMID_BASE_IDX 1 3836 #define regPA_SC_RIGHT_VERT_GRID 0x00e8 3837 #define regPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 3838 #define regPA_SC_LEFT_VERT_GRID 0x00e9 3839 #define regPA_SC_LEFT_VERT_GRID_BASE_IDX 1 3840 #define regPA_SC_HORIZ_GRID 0x00ea 3841 #define regPA_SC_HORIZ_GRID_BASE_IDX 1 3842 #define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 3843 #define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 3844 #define regCB_BLEND_RED 0x0105 3845 #define regCB_BLEND_RED_BASE_IDX 1 3846 #define regCB_BLEND_GREEN 0x0106 3847 #define regCB_BLEND_GREEN_BASE_IDX 1 3848 #define regCB_BLEND_BLUE 0x0107 3849 #define regCB_BLEND_BLUE_BASE_IDX 1 3850 #define regCB_BLEND_ALPHA 0x0108 3851 #define regCB_BLEND_ALPHA_BASE_IDX 1 3852 #define regCB_DCC_CONTROL 0x0109 3853 #define regCB_DCC_CONTROL_BASE_IDX 1 3854 #define regDB_STENCIL_CONTROL 0x010b 3855 #define regDB_STENCIL_CONTROL_BASE_IDX 1 3856 #define regDB_STENCILREFMASK 0x010c 3857 #define regDB_STENCILREFMASK_BASE_IDX 1 3858 #define regDB_STENCILREFMASK_BF 0x010d 3859 #define regDB_STENCILREFMASK_BF_BASE_IDX 1 3860 #define regPA_CL_VPORT_XSCALE 0x010f 3861 #define regPA_CL_VPORT_XSCALE_BASE_IDX 1 3862 #define regPA_CL_VPORT_XOFFSET 0x0110 3863 #define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 3864 #define regPA_CL_VPORT_YSCALE 0x0111 3865 #define regPA_CL_VPORT_YSCALE_BASE_IDX 1 3866 #define regPA_CL_VPORT_YOFFSET 0x0112 3867 #define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 3868 #define regPA_CL_VPORT_ZSCALE 0x0113 3869 #define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 3870 #define regPA_CL_VPORT_ZOFFSET 0x0114 3871 #define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 3872 #define regPA_CL_VPORT_XSCALE_1 0x0115 3873 #define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 3874 #define regPA_CL_VPORT_XOFFSET_1 0x0116 3875 #define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 3876 #define regPA_CL_VPORT_YSCALE_1 0x0117 3877 #define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 3878 #define regPA_CL_VPORT_YOFFSET_1 0x0118 3879 #define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 3880 #define regPA_CL_VPORT_ZSCALE_1 0x0119 3881 #define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 3882 #define regPA_CL_VPORT_ZOFFSET_1 0x011a 3883 #define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 3884 #define regPA_CL_VPORT_XSCALE_2 0x011b 3885 #define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 3886 #define regPA_CL_VPORT_XOFFSET_2 0x011c 3887 #define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 3888 #define regPA_CL_VPORT_YSCALE_2 0x011d 3889 #define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 3890 #define regPA_CL_VPORT_YOFFSET_2 0x011e 3891 #define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 3892 #define regPA_CL_VPORT_ZSCALE_2 0x011f 3893 #define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 3894 #define regPA_CL_VPORT_ZOFFSET_2 0x0120 3895 #define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 3896 #define regPA_CL_VPORT_XSCALE_3 0x0121 3897 #define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 3898 #define regPA_CL_VPORT_XOFFSET_3 0x0122 3899 #define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 3900 #define regPA_CL_VPORT_YSCALE_3 0x0123 3901 #define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 3902 #define regPA_CL_VPORT_YOFFSET_3 0x0124 3903 #define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 3904 #define regPA_CL_VPORT_ZSCALE_3 0x0125 3905 #define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 3906 #define regPA_CL_VPORT_ZOFFSET_3 0x0126 3907 #define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 3908 #define regPA_CL_VPORT_XSCALE_4 0x0127 3909 #define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 3910 #define regPA_CL_VPORT_XOFFSET_4 0x0128 3911 #define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 3912 #define regPA_CL_VPORT_YSCALE_4 0x0129 3913 #define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 3914 #define regPA_CL_VPORT_YOFFSET_4 0x012a 3915 #define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 3916 #define regPA_CL_VPORT_ZSCALE_4 0x012b 3917 #define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 3918 #define regPA_CL_VPORT_ZOFFSET_4 0x012c 3919 #define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 3920 #define regPA_CL_VPORT_XSCALE_5 0x012d 3921 #define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 3922 #define regPA_CL_VPORT_XOFFSET_5 0x012e 3923 #define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 3924 #define regPA_CL_VPORT_YSCALE_5 0x012f 3925 #define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 3926 #define regPA_CL_VPORT_YOFFSET_5 0x0130 3927 #define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 3928 #define regPA_CL_VPORT_ZSCALE_5 0x0131 3929 #define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 3930 #define regPA_CL_VPORT_ZOFFSET_5 0x0132 3931 #define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 3932 #define regPA_CL_VPORT_XSCALE_6 0x0133 3933 #define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 3934 #define regPA_CL_VPORT_XOFFSET_6 0x0134 3935 #define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 3936 #define regPA_CL_VPORT_YSCALE_6 0x0135 3937 #define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 3938 #define regPA_CL_VPORT_YOFFSET_6 0x0136 3939 #define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 3940 #define regPA_CL_VPORT_ZSCALE_6 0x0137 3941 #define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 3942 #define regPA_CL_VPORT_ZOFFSET_6 0x0138 3943 #define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 3944 #define regPA_CL_VPORT_XSCALE_7 0x0139 3945 #define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 3946 #define regPA_CL_VPORT_XOFFSET_7 0x013a 3947 #define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 3948 #define regPA_CL_VPORT_YSCALE_7 0x013b 3949 #define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 3950 #define regPA_CL_VPORT_YOFFSET_7 0x013c 3951 #define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 3952 #define regPA_CL_VPORT_ZSCALE_7 0x013d 3953 #define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 3954 #define regPA_CL_VPORT_ZOFFSET_7 0x013e 3955 #define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 3956 #define regPA_CL_VPORT_XSCALE_8 0x013f 3957 #define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 3958 #define regPA_CL_VPORT_XOFFSET_8 0x0140 3959 #define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 3960 #define regPA_CL_VPORT_YSCALE_8 0x0141 3961 #define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 3962 #define regPA_CL_VPORT_YOFFSET_8 0x0142 3963 #define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 3964 #define regPA_CL_VPORT_ZSCALE_8 0x0143 3965 #define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 3966 #define regPA_CL_VPORT_ZOFFSET_8 0x0144 3967 #define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 3968 #define regPA_CL_VPORT_XSCALE_9 0x0145 3969 #define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 3970 #define regPA_CL_VPORT_XOFFSET_9 0x0146 3971 #define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 3972 #define regPA_CL_VPORT_YSCALE_9 0x0147 3973 #define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 3974 #define regPA_CL_VPORT_YOFFSET_9 0x0148 3975 #define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 3976 #define regPA_CL_VPORT_ZSCALE_9 0x0149 3977 #define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 3978 #define regPA_CL_VPORT_ZOFFSET_9 0x014a 3979 #define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 3980 #define regPA_CL_VPORT_XSCALE_10 0x014b 3981 #define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 3982 #define regPA_CL_VPORT_XOFFSET_10 0x014c 3983 #define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 3984 #define regPA_CL_VPORT_YSCALE_10 0x014d 3985 #define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 3986 #define regPA_CL_VPORT_YOFFSET_10 0x014e 3987 #define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 3988 #define regPA_CL_VPORT_ZSCALE_10 0x014f 3989 #define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 3990 #define regPA_CL_VPORT_ZOFFSET_10 0x0150 3991 #define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 3992 #define regPA_CL_VPORT_XSCALE_11 0x0151 3993 #define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 3994 #define regPA_CL_VPORT_XOFFSET_11 0x0152 3995 #define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 3996 #define regPA_CL_VPORT_YSCALE_11 0x0153 3997 #define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 3998 #define regPA_CL_VPORT_YOFFSET_11 0x0154 3999 #define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 4000 #define regPA_CL_VPORT_ZSCALE_11 0x0155 4001 #define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 4002 #define regPA_CL_VPORT_ZOFFSET_11 0x0156 4003 #define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 4004 #define regPA_CL_VPORT_XSCALE_12 0x0157 4005 #define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 4006 #define regPA_CL_VPORT_XOFFSET_12 0x0158 4007 #define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 4008 #define regPA_CL_VPORT_YSCALE_12 0x0159 4009 #define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 4010 #define regPA_CL_VPORT_YOFFSET_12 0x015a 4011 #define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 4012 #define regPA_CL_VPORT_ZSCALE_12 0x015b 4013 #define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 4014 #define regPA_CL_VPORT_ZOFFSET_12 0x015c 4015 #define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 4016 #define regPA_CL_VPORT_XSCALE_13 0x015d 4017 #define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 4018 #define regPA_CL_VPORT_XOFFSET_13 0x015e 4019 #define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 4020 #define regPA_CL_VPORT_YSCALE_13 0x015f 4021 #define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 4022 #define regPA_CL_VPORT_YOFFSET_13 0x0160 4023 #define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 4024 #define regPA_CL_VPORT_ZSCALE_13 0x0161 4025 #define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 4026 #define regPA_CL_VPORT_ZOFFSET_13 0x0162 4027 #define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 4028 #define regPA_CL_VPORT_XSCALE_14 0x0163 4029 #define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 4030 #define regPA_CL_VPORT_XOFFSET_14 0x0164 4031 #define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 4032 #define regPA_CL_VPORT_YSCALE_14 0x0165 4033 #define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 4034 #define regPA_CL_VPORT_YOFFSET_14 0x0166 4035 #define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 4036 #define regPA_CL_VPORT_ZSCALE_14 0x0167 4037 #define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 4038 #define regPA_CL_VPORT_ZOFFSET_14 0x0168 4039 #define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 4040 #define regPA_CL_VPORT_XSCALE_15 0x0169 4041 #define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 4042 #define regPA_CL_VPORT_XOFFSET_15 0x016a 4043 #define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 4044 #define regPA_CL_VPORT_YSCALE_15 0x016b 4045 #define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 4046 #define regPA_CL_VPORT_YOFFSET_15 0x016c 4047 #define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 4048 #define regPA_CL_VPORT_ZSCALE_15 0x016d 4049 #define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 4050 #define regPA_CL_VPORT_ZOFFSET_15 0x016e 4051 #define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 4052 #define regPA_CL_UCP_0_X 0x016f 4053 #define regPA_CL_UCP_0_X_BASE_IDX 1 4054 #define regPA_CL_UCP_0_Y 0x0170 4055 #define regPA_CL_UCP_0_Y_BASE_IDX 1 4056 #define regPA_CL_UCP_0_Z 0x0171 4057 #define regPA_CL_UCP_0_Z_BASE_IDX 1 4058 #define regPA_CL_UCP_0_W 0x0172 4059 #define regPA_CL_UCP_0_W_BASE_IDX 1 4060 #define regPA_CL_UCP_1_X 0x0173 4061 #define regPA_CL_UCP_1_X_BASE_IDX 1 4062 #define regPA_CL_UCP_1_Y 0x0174 4063 #define regPA_CL_UCP_1_Y_BASE_IDX 1 4064 #define regPA_CL_UCP_1_Z 0x0175 4065 #define regPA_CL_UCP_1_Z_BASE_IDX 1 4066 #define regPA_CL_UCP_1_W 0x0176 4067 #define regPA_CL_UCP_1_W_BASE_IDX 1 4068 #define regPA_CL_UCP_2_X 0x0177 4069 #define regPA_CL_UCP_2_X_BASE_IDX 1 4070 #define regPA_CL_UCP_2_Y 0x0178 4071 #define regPA_CL_UCP_2_Y_BASE_IDX 1 4072 #define regPA_CL_UCP_2_Z 0x0179 4073 #define regPA_CL_UCP_2_Z_BASE_IDX 1 4074 #define regPA_CL_UCP_2_W 0x017a 4075 #define regPA_CL_UCP_2_W_BASE_IDX 1 4076 #define regPA_CL_UCP_3_X 0x017b 4077 #define regPA_CL_UCP_3_X_BASE_IDX 1 4078 #define regPA_CL_UCP_3_Y 0x017c 4079 #define regPA_CL_UCP_3_Y_BASE_IDX 1 4080 #define regPA_CL_UCP_3_Z 0x017d 4081 #define regPA_CL_UCP_3_Z_BASE_IDX 1 4082 #define regPA_CL_UCP_3_W 0x017e 4083 #define regPA_CL_UCP_3_W_BASE_IDX 1 4084 #define regPA_CL_UCP_4_X 0x017f 4085 #define regPA_CL_UCP_4_X_BASE_IDX 1 4086 #define regPA_CL_UCP_4_Y 0x0180 4087 #define regPA_CL_UCP_4_Y_BASE_IDX 1 4088 #define regPA_CL_UCP_4_Z 0x0181 4089 #define regPA_CL_UCP_4_Z_BASE_IDX 1 4090 #define regPA_CL_UCP_4_W 0x0182 4091 #define regPA_CL_UCP_4_W_BASE_IDX 1 4092 #define regPA_CL_UCP_5_X 0x0183 4093 #define regPA_CL_UCP_5_X_BASE_IDX 1 4094 #define regPA_CL_UCP_5_Y 0x0184 4095 #define regPA_CL_UCP_5_Y_BASE_IDX 1 4096 #define regPA_CL_UCP_5_Z 0x0185 4097 #define regPA_CL_UCP_5_Z_BASE_IDX 1 4098 #define regPA_CL_UCP_5_W 0x0186 4099 #define regPA_CL_UCP_5_W_BASE_IDX 1 4100 #define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 4101 #define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 4102 #define regSPI_PS_INPUT_CNTL_0 0x0191 4103 #define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 4104 #define regSPI_PS_INPUT_CNTL_1 0x0192 4105 #define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 4106 #define regSPI_PS_INPUT_CNTL_2 0x0193 4107 #define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 4108 #define regSPI_PS_INPUT_CNTL_3 0x0194 4109 #define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 4110 #define regSPI_PS_INPUT_CNTL_4 0x0195 4111 #define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 4112 #define regSPI_PS_INPUT_CNTL_5 0x0196 4113 #define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 4114 #define regSPI_PS_INPUT_CNTL_6 0x0197 4115 #define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 4116 #define regSPI_PS_INPUT_CNTL_7 0x0198 4117 #define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 4118 #define regSPI_PS_INPUT_CNTL_8 0x0199 4119 #define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 4120 #define regSPI_PS_INPUT_CNTL_9 0x019a 4121 #define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 4122 #define regSPI_PS_INPUT_CNTL_10 0x019b 4123 #define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 4124 #define regSPI_PS_INPUT_CNTL_11 0x019c 4125 #define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 4126 #define regSPI_PS_INPUT_CNTL_12 0x019d 4127 #define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 4128 #define regSPI_PS_INPUT_CNTL_13 0x019e 4129 #define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 4130 #define regSPI_PS_INPUT_CNTL_14 0x019f 4131 #define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 4132 #define regSPI_PS_INPUT_CNTL_15 0x01a0 4133 #define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 4134 #define regSPI_PS_INPUT_CNTL_16 0x01a1 4135 #define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 4136 #define regSPI_PS_INPUT_CNTL_17 0x01a2 4137 #define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 4138 #define regSPI_PS_INPUT_CNTL_18 0x01a3 4139 #define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 4140 #define regSPI_PS_INPUT_CNTL_19 0x01a4 4141 #define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 4142 #define regSPI_PS_INPUT_CNTL_20 0x01a5 4143 #define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 4144 #define regSPI_PS_INPUT_CNTL_21 0x01a6 4145 #define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 4146 #define regSPI_PS_INPUT_CNTL_22 0x01a7 4147 #define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 4148 #define regSPI_PS_INPUT_CNTL_23 0x01a8 4149 #define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 4150 #define regSPI_PS_INPUT_CNTL_24 0x01a9 4151 #define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 4152 #define regSPI_PS_INPUT_CNTL_25 0x01aa 4153 #define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 4154 #define regSPI_PS_INPUT_CNTL_26 0x01ab 4155 #define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 4156 #define regSPI_PS_INPUT_CNTL_27 0x01ac 4157 #define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 4158 #define regSPI_PS_INPUT_CNTL_28 0x01ad 4159 #define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 4160 #define regSPI_PS_INPUT_CNTL_29 0x01ae 4161 #define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 4162 #define regSPI_PS_INPUT_CNTL_30 0x01af 4163 #define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 4164 #define regSPI_PS_INPUT_CNTL_31 0x01b0 4165 #define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 4166 #define regSPI_VS_OUT_CONFIG 0x01b1 4167 #define regSPI_VS_OUT_CONFIG_BASE_IDX 1 4168 #define regSPI_PS_INPUT_ENA 0x01b3 4169 #define regSPI_PS_INPUT_ENA_BASE_IDX 1 4170 #define regSPI_PS_INPUT_ADDR 0x01b4 4171 #define regSPI_PS_INPUT_ADDR_BASE_IDX 1 4172 #define regSPI_INTERP_CONTROL_0 0x01b5 4173 #define regSPI_INTERP_CONTROL_0_BASE_IDX 1 4174 #define regSPI_PS_IN_CONTROL 0x01b6 4175 #define regSPI_PS_IN_CONTROL_BASE_IDX 1 4176 #define regSPI_BARYC_CNTL 0x01b8 4177 #define regSPI_BARYC_CNTL_BASE_IDX 1 4178 #define regSPI_TMPRING_SIZE 0x01ba 4179 #define regSPI_TMPRING_SIZE_BASE_IDX 1 4180 #define regSPI_SHADER_POS_FORMAT 0x01c3 4181 #define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 4182 #define regSPI_SHADER_Z_FORMAT 0x01c4 4183 #define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 4184 #define regSPI_SHADER_COL_FORMAT 0x01c5 4185 #define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 4186 #define regCB_BLEND0_CONTROL 0x01e0 4187 #define regCB_BLEND0_CONTROL_BASE_IDX 1 4188 #define regCB_BLEND1_CONTROL 0x01e1 4189 #define regCB_BLEND1_CONTROL_BASE_IDX 1 4190 #define regCB_BLEND2_CONTROL 0x01e2 4191 #define regCB_BLEND2_CONTROL_BASE_IDX 1 4192 #define regCB_BLEND3_CONTROL 0x01e3 4193 #define regCB_BLEND3_CONTROL_BASE_IDX 1 4194 #define regCB_BLEND4_CONTROL 0x01e4 4195 #define regCB_BLEND4_CONTROL_BASE_IDX 1 4196 #define regCB_BLEND5_CONTROL 0x01e5 4197 #define regCB_BLEND5_CONTROL_BASE_IDX 1 4198 #define regCB_BLEND6_CONTROL 0x01e6 4199 #define regCB_BLEND6_CONTROL_BASE_IDX 1 4200 #define regCB_BLEND7_CONTROL 0x01e7 4201 #define regCB_BLEND7_CONTROL_BASE_IDX 1 4202 #define regCB_MRT0_EPITCH 0x01e8 4203 #define regCB_MRT0_EPITCH_BASE_IDX 1 4204 #define regCB_MRT1_EPITCH 0x01e9 4205 #define regCB_MRT1_EPITCH_BASE_IDX 1 4206 #define regCB_MRT2_EPITCH 0x01ea 4207 #define regCB_MRT2_EPITCH_BASE_IDX 1 4208 #define regCB_MRT3_EPITCH 0x01eb 4209 #define regCB_MRT3_EPITCH_BASE_IDX 1 4210 #define regCB_MRT4_EPITCH 0x01ec 4211 #define regCB_MRT4_EPITCH_BASE_IDX 1 4212 #define regCB_MRT5_EPITCH 0x01ed 4213 #define regCB_MRT5_EPITCH_BASE_IDX 1 4214 #define regCB_MRT6_EPITCH 0x01ee 4215 #define regCB_MRT6_EPITCH_BASE_IDX 1 4216 #define regCB_MRT7_EPITCH 0x01ef 4217 #define regCB_MRT7_EPITCH_BASE_IDX 1 4218 #define regCS_COPY_STATE 0x01f3 4219 #define regCS_COPY_STATE_BASE_IDX 1 4220 #define regGFX_COPY_STATE 0x01f4 4221 #define regGFX_COPY_STATE_BASE_IDX 1 4222 #define regPA_CL_POINT_X_RAD 0x01f5 4223 #define regPA_CL_POINT_X_RAD_BASE_IDX 1 4224 #define regPA_CL_POINT_Y_RAD 0x01f6 4225 #define regPA_CL_POINT_Y_RAD_BASE_IDX 1 4226 #define regPA_CL_POINT_SIZE 0x01f7 4227 #define regPA_CL_POINT_SIZE_BASE_IDX 1 4228 #define regPA_CL_POINT_CULL_RAD 0x01f8 4229 #define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 4230 #define regVGT_DMA_BASE_HI 0x01f9 4231 #define regVGT_DMA_BASE_HI_BASE_IDX 1 4232 #define regVGT_DMA_BASE 0x01fa 4233 #define regVGT_DMA_BASE_BASE_IDX 1 4234 #define regVGT_DRAW_INITIATOR 0x01fc 4235 #define regVGT_DRAW_INITIATOR_BASE_IDX 1 4236 #define regVGT_IMMED_DATA 0x01fd 4237 #define regVGT_IMMED_DATA_BASE_IDX 1 4238 #define regVGT_EVENT_ADDRESS_REG 0x01fe 4239 #define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 4240 #define regDB_DEPTH_CONTROL 0x0200 4241 #define regDB_DEPTH_CONTROL_BASE_IDX 1 4242 #define regDB_EQAA 0x0201 4243 #define regDB_EQAA_BASE_IDX 1 4244 #define regCB_COLOR_CONTROL 0x0202 4245 #define regCB_COLOR_CONTROL_BASE_IDX 1 4246 #define regDB_SHADER_CONTROL 0x0203 4247 #define regDB_SHADER_CONTROL_BASE_IDX 1 4248 #define regPA_CL_CLIP_CNTL 0x0204 4249 #define regPA_CL_CLIP_CNTL_BASE_IDX 1 4250 #define regPA_SU_SC_MODE_CNTL 0x0205 4251 #define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 4252 #define regPA_CL_VTE_CNTL 0x0206 4253 #define regPA_CL_VTE_CNTL_BASE_IDX 1 4254 #define regPA_CL_VS_OUT_CNTL 0x0207 4255 #define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 4256 #define regPA_CL_NANINF_CNTL 0x0208 4257 #define regPA_CL_NANINF_CNTL_BASE_IDX 1 4258 #define regPA_SU_LINE_STIPPLE_CNTL 0x0209 4259 #define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 4260 #define regPA_SU_LINE_STIPPLE_SCALE 0x020a 4261 #define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 4262 #define regPA_SU_PRIM_FILTER_CNTL 0x020b 4263 #define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 4264 #define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c 4265 #define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 4266 #define regPA_CL_OBJPRIM_ID_CNTL 0x020d 4267 #define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 4268 #define regPA_CL_NGG_CNTL 0x020e 4269 #define regPA_CL_NGG_CNTL_BASE_IDX 1 4270 #define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f 4271 #define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 4272 #define regPA_STEREO_CNTL 0x0210 4273 #define regPA_STEREO_CNTL_BASE_IDX 1 4274 #define regPA_SU_POINT_SIZE 0x0280 4275 #define regPA_SU_POINT_SIZE_BASE_IDX 1 4276 #define regPA_SU_POINT_MINMAX 0x0281 4277 #define regPA_SU_POINT_MINMAX_BASE_IDX 1 4278 #define regPA_SU_LINE_CNTL 0x0282 4279 #define regPA_SU_LINE_CNTL_BASE_IDX 1 4280 #define regPA_SC_LINE_STIPPLE 0x0283 4281 #define regPA_SC_LINE_STIPPLE_BASE_IDX 1 4282 #define regVGT_OUTPUT_PATH_CNTL 0x0284 4283 #define regVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 4284 #define regVGT_HOS_CNTL 0x0285 4285 #define regVGT_HOS_CNTL_BASE_IDX 1 4286 #define regVGT_HOS_MAX_TESS_LEVEL 0x0286 4287 #define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 4288 #define regVGT_HOS_MIN_TESS_LEVEL 0x0287 4289 #define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 4290 #define regVGT_HOS_REUSE_DEPTH 0x0288 4291 #define regVGT_HOS_REUSE_DEPTH_BASE_IDX 1 4292 #define regVGT_GROUP_PRIM_TYPE 0x0289 4293 #define regVGT_GROUP_PRIM_TYPE_BASE_IDX 1 4294 #define regVGT_GROUP_FIRST_DECR 0x028a 4295 #define regVGT_GROUP_FIRST_DECR_BASE_IDX 1 4296 #define regVGT_GROUP_DECR 0x028b 4297 #define regVGT_GROUP_DECR_BASE_IDX 1 4298 #define regVGT_GROUP_VECT_0_CNTL 0x028c 4299 #define regVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 4300 #define regVGT_GROUP_VECT_1_CNTL 0x028d 4301 #define regVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 4302 #define regVGT_GROUP_VECT_0_FMT_CNTL 0x028e 4303 #define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 4304 #define regVGT_GROUP_VECT_1_FMT_CNTL 0x028f 4305 #define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 4306 #define regVGT_GS_MODE 0x0290 4307 #define regVGT_GS_MODE_BASE_IDX 1 4308 #define regVGT_GS_ONCHIP_CNTL 0x0291 4309 #define regVGT_GS_ONCHIP_CNTL_BASE_IDX 1 4310 #define regPA_SC_MODE_CNTL_0 0x0292 4311 #define regPA_SC_MODE_CNTL_0_BASE_IDX 1 4312 #define regPA_SC_MODE_CNTL_1 0x0293 4313 #define regPA_SC_MODE_CNTL_1_BASE_IDX 1 4314 #define regVGT_ENHANCE 0x0294 4315 #define regVGT_ENHANCE_BASE_IDX 1 4316 #define regVGT_GS_PER_ES 0x0295 4317 #define regVGT_GS_PER_ES_BASE_IDX 1 4318 #define regVGT_ES_PER_GS 0x0296 4319 #define regVGT_ES_PER_GS_BASE_IDX 1 4320 #define regVGT_GS_PER_VS 0x0297 4321 #define regVGT_GS_PER_VS_BASE_IDX 1 4322 #define regVGT_GSVS_RING_OFFSET_1 0x0298 4323 #define regVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 4324 #define regVGT_GSVS_RING_OFFSET_2 0x0299 4325 #define regVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 4326 #define regVGT_GSVS_RING_OFFSET_3 0x029a 4327 #define regVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 4328 #define regVGT_GS_OUT_PRIM_TYPE 0x029b 4329 #define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 4330 #define regIA_ENHANCE 0x029c 4331 #define regIA_ENHANCE_BASE_IDX 1 4332 #define regVGT_DMA_SIZE 0x029d 4333 #define regVGT_DMA_SIZE_BASE_IDX 1 4334 #define regVGT_DMA_MAX_SIZE 0x029e 4335 #define regVGT_DMA_MAX_SIZE_BASE_IDX 1 4336 #define regVGT_DMA_INDEX_TYPE 0x029f 4337 #define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 4338 #define regWD_ENHANCE 0x02a0 4339 #define regWD_ENHANCE_BASE_IDX 1 4340 #define regVGT_PRIMITIVEID_EN 0x02a1 4341 #define regVGT_PRIMITIVEID_EN_BASE_IDX 1 4342 #define regVGT_DMA_NUM_INSTANCES 0x02a2 4343 #define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 4344 #define regVGT_PRIMITIVEID_RESET 0x02a3 4345 #define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 4346 #define regVGT_EVENT_INITIATOR 0x02a4 4347 #define regVGT_EVENT_INITIATOR_BASE_IDX 1 4348 #define regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 4349 #define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 4350 #define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 4351 #define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 4352 #define regVGT_INSTANCE_STEP_RATE_0 0x02a8 4353 #define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 4354 #define regVGT_INSTANCE_STEP_RATE_1 0x02a9 4355 #define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 4356 #define regIA_MULTI_VGT_PARAM_BC 0x02aa 4357 #define regIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 4358 #define regVGT_ESGS_RING_ITEMSIZE 0x02ab 4359 #define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 4360 #define regVGT_GSVS_RING_ITEMSIZE 0x02ac 4361 #define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 4362 #define regVGT_REUSE_OFF 0x02ad 4363 #define regVGT_REUSE_OFF_BASE_IDX 1 4364 #define regVGT_VTX_CNT_EN 0x02ae 4365 #define regVGT_VTX_CNT_EN_BASE_IDX 1 4366 #define regDB_HTILE_SURFACE 0x02af 4367 #define regDB_HTILE_SURFACE_BASE_IDX 1 4368 #define regDB_SRESULTS_COMPARE_STATE0 0x02b0 4369 #define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 4370 #define regDB_SRESULTS_COMPARE_STATE1 0x02b1 4371 #define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 4372 #define regDB_PRELOAD_CONTROL 0x02b2 4373 #define regDB_PRELOAD_CONTROL_BASE_IDX 1 4374 #define regVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 4375 #define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 4376 #define regVGT_STRMOUT_VTX_STRIDE_0 0x02b5 4377 #define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 4378 #define regVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 4379 #define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 4380 #define regVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 4381 #define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 4382 #define regVGT_STRMOUT_VTX_STRIDE_1 0x02b9 4383 #define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 4384 #define regVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb 4385 #define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 4386 #define regVGT_STRMOUT_BUFFER_SIZE_2 0x02bc 4387 #define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 4388 #define regVGT_STRMOUT_VTX_STRIDE_2 0x02bd 4389 #define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 4390 #define regVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf 4391 #define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 4392 #define regVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 4393 #define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 4394 #define regVGT_STRMOUT_VTX_STRIDE_3 0x02c1 4395 #define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 4396 #define regVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 4397 #define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 4398 #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca 4399 #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 4400 #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb 4401 #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 4402 #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc 4403 #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 4404 #define regVGT_GS_MAX_VERT_OUT 0x02ce 4405 #define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 4406 #define regVGT_TESS_DISTRIBUTION 0x02d4 4407 #define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 4408 #define regVGT_SHADER_STAGES_EN 0x02d5 4409 #define regVGT_SHADER_STAGES_EN_BASE_IDX 1 4410 #define regVGT_LS_HS_CONFIG 0x02d6 4411 #define regVGT_LS_HS_CONFIG_BASE_IDX 1 4412 #define regVGT_GS_VERT_ITEMSIZE 0x02d7 4413 #define regVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 4414 #define regVGT_GS_VERT_ITEMSIZE_1 0x02d8 4415 #define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 4416 #define regVGT_GS_VERT_ITEMSIZE_2 0x02d9 4417 #define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 4418 #define regVGT_GS_VERT_ITEMSIZE_3 0x02da 4419 #define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 4420 #define regVGT_TF_PARAM 0x02db 4421 #define regVGT_TF_PARAM_BASE_IDX 1 4422 #define regDB_ALPHA_TO_MASK 0x02dc 4423 #define regDB_ALPHA_TO_MASK_BASE_IDX 1 4424 #define regVGT_DISPATCH_DRAW_INDEX 0x02dd 4425 #define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 4426 #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de 4427 #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 4428 #define regPA_SU_POLY_OFFSET_CLAMP 0x02df 4429 #define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 4430 #define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 4431 #define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 4432 #define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 4433 #define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 4434 #define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 4435 #define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 4436 #define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 4437 #define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 4438 #define regVGT_GS_INSTANCE_CNT 0x02e4 4439 #define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 4440 #define regVGT_STRMOUT_CONFIG 0x02e5 4441 #define regVGT_STRMOUT_CONFIG_BASE_IDX 1 4442 #define regVGT_STRMOUT_BUFFER_CONFIG 0x02e6 4443 #define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 4444 #define regVGT_DMA_EVENT_INITIATOR 0x02e7 4445 #define regVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 4446 #define regPA_SC_CENTROID_PRIORITY_0 0x02f5 4447 #define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 4448 #define regPA_SC_CENTROID_PRIORITY_1 0x02f6 4449 #define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 4450 #define regPA_SC_LINE_CNTL 0x02f7 4451 #define regPA_SC_LINE_CNTL_BASE_IDX 1 4452 #define regPA_SC_AA_CONFIG 0x02f8 4453 #define regPA_SC_AA_CONFIG_BASE_IDX 1 4454 #define regPA_SU_VTX_CNTL 0x02f9 4455 #define regPA_SU_VTX_CNTL_BASE_IDX 1 4456 #define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa 4457 #define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 4458 #define regPA_CL_GB_VERT_DISC_ADJ 0x02fb 4459 #define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 4460 #define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc 4461 #define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 4462 #define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd 4463 #define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 4464 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe 4465 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 4466 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff 4467 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 4468 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 4469 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 4470 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 4471 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 4472 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 4473 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 4474 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 4475 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 4476 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 4477 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 4478 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 4479 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 4480 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 4481 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 4482 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 4483 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 4484 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 4485 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 4486 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 4487 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 4488 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a 4489 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 4490 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b 4491 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 4492 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c 4493 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 4494 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d 4495 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 4496 #define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e 4497 #define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 4498 #define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f 4499 #define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 4500 #define regPA_SC_SHADER_CONTROL 0x0310 4501 #define regPA_SC_SHADER_CONTROL_BASE_IDX 1 4502 #define regPA_SC_BINNER_CNTL_0 0x0311 4503 #define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 4504 #define regPA_SC_BINNER_CNTL_1 0x0312 4505 #define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 4506 #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 4507 #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 4508 #define regPA_SC_NGG_MODE_CNTL 0x0314 4509 #define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 4510 #define regVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 4511 #define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 4512 #define regVGT_OUT_DEALLOC_CNTL 0x0317 4513 #define regVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 4514 #define regCB_COLOR0_BASE 0x0318 4515 #define regCB_COLOR0_BASE_BASE_IDX 1 4516 #define regCB_COLOR0_BASE_EXT 0x0319 4517 #define regCB_COLOR0_BASE_EXT_BASE_IDX 1 4518 #define regCB_COLOR0_ATTRIB2 0x031a 4519 #define regCB_COLOR0_ATTRIB2_BASE_IDX 1 4520 #define regCB_COLOR0_VIEW 0x031b 4521 #define regCB_COLOR0_VIEW_BASE_IDX 1 4522 #define regCB_COLOR0_INFO 0x031c 4523 #define regCB_COLOR0_INFO_BASE_IDX 1 4524 #define regCB_COLOR0_ATTRIB 0x031d 4525 #define regCB_COLOR0_ATTRIB_BASE_IDX 1 4526 #define regCB_COLOR0_DCC_CONTROL 0x031e 4527 #define regCB_COLOR0_DCC_CONTROL_BASE_IDX 1 4528 #define regCB_COLOR0_CMASK 0x031f 4529 #define regCB_COLOR0_CMASK_BASE_IDX 1 4530 #define regCB_COLOR0_CMASK_BASE_EXT 0x0320 4531 #define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 4532 #define regCB_COLOR0_FMASK 0x0321 4533 #define regCB_COLOR0_FMASK_BASE_IDX 1 4534 #define regCB_COLOR0_FMASK_BASE_EXT 0x0322 4535 #define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 4536 #define regCB_COLOR0_CLEAR_WORD0 0x0323 4537 #define regCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 4538 #define regCB_COLOR0_CLEAR_WORD1 0x0324 4539 #define regCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 4540 #define regCB_COLOR0_DCC_BASE 0x0325 4541 #define regCB_COLOR0_DCC_BASE_BASE_IDX 1 4542 #define regCB_COLOR0_DCC_BASE_EXT 0x0326 4543 #define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 4544 #define regCB_COLOR1_BASE 0x0327 4545 #define regCB_COLOR1_BASE_BASE_IDX 1 4546 #define regCB_COLOR1_BASE_EXT 0x0328 4547 #define regCB_COLOR1_BASE_EXT_BASE_IDX 1 4548 #define regCB_COLOR1_ATTRIB2 0x0329 4549 #define regCB_COLOR1_ATTRIB2_BASE_IDX 1 4550 #define regCB_COLOR1_VIEW 0x032a 4551 #define regCB_COLOR1_VIEW_BASE_IDX 1 4552 #define regCB_COLOR1_INFO 0x032b 4553 #define regCB_COLOR1_INFO_BASE_IDX 1 4554 #define regCB_COLOR1_ATTRIB 0x032c 4555 #define regCB_COLOR1_ATTRIB_BASE_IDX 1 4556 #define regCB_COLOR1_DCC_CONTROL 0x032d 4557 #define regCB_COLOR1_DCC_CONTROL_BASE_IDX 1 4558 #define regCB_COLOR1_CMASK 0x032e 4559 #define regCB_COLOR1_CMASK_BASE_IDX 1 4560 #define regCB_COLOR1_CMASK_BASE_EXT 0x032f 4561 #define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 4562 #define regCB_COLOR1_FMASK 0x0330 4563 #define regCB_COLOR1_FMASK_BASE_IDX 1 4564 #define regCB_COLOR1_FMASK_BASE_EXT 0x0331 4565 #define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 4566 #define regCB_COLOR1_CLEAR_WORD0 0x0332 4567 #define regCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 4568 #define regCB_COLOR1_CLEAR_WORD1 0x0333 4569 #define regCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 4570 #define regCB_COLOR1_DCC_BASE 0x0334 4571 #define regCB_COLOR1_DCC_BASE_BASE_IDX 1 4572 #define regCB_COLOR1_DCC_BASE_EXT 0x0335 4573 #define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 4574 #define regCB_COLOR2_BASE 0x0336 4575 #define regCB_COLOR2_BASE_BASE_IDX 1 4576 #define regCB_COLOR2_BASE_EXT 0x0337 4577 #define regCB_COLOR2_BASE_EXT_BASE_IDX 1 4578 #define regCB_COLOR2_ATTRIB2 0x0338 4579 #define regCB_COLOR2_ATTRIB2_BASE_IDX 1 4580 #define regCB_COLOR2_VIEW 0x0339 4581 #define regCB_COLOR2_VIEW_BASE_IDX 1 4582 #define regCB_COLOR2_INFO 0x033a 4583 #define regCB_COLOR2_INFO_BASE_IDX 1 4584 #define regCB_COLOR2_ATTRIB 0x033b 4585 #define regCB_COLOR2_ATTRIB_BASE_IDX 1 4586 #define regCB_COLOR2_DCC_CONTROL 0x033c 4587 #define regCB_COLOR2_DCC_CONTROL_BASE_IDX 1 4588 #define regCB_COLOR2_CMASK 0x033d 4589 #define regCB_COLOR2_CMASK_BASE_IDX 1 4590 #define regCB_COLOR2_CMASK_BASE_EXT 0x033e 4591 #define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 4592 #define regCB_COLOR2_FMASK 0x033f 4593 #define regCB_COLOR2_FMASK_BASE_IDX 1 4594 #define regCB_COLOR2_FMASK_BASE_EXT 0x0340 4595 #define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 4596 #define regCB_COLOR2_CLEAR_WORD0 0x0341 4597 #define regCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 4598 #define regCB_COLOR2_CLEAR_WORD1 0x0342 4599 #define regCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 4600 #define regCB_COLOR2_DCC_BASE 0x0343 4601 #define regCB_COLOR2_DCC_BASE_BASE_IDX 1 4602 #define regCB_COLOR2_DCC_BASE_EXT 0x0344 4603 #define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 4604 #define regCB_COLOR3_BASE 0x0345 4605 #define regCB_COLOR3_BASE_BASE_IDX 1 4606 #define regCB_COLOR3_BASE_EXT 0x0346 4607 #define regCB_COLOR3_BASE_EXT_BASE_IDX 1 4608 #define regCB_COLOR3_ATTRIB2 0x0347 4609 #define regCB_COLOR3_ATTRIB2_BASE_IDX 1 4610 #define regCB_COLOR3_VIEW 0x0348 4611 #define regCB_COLOR3_VIEW_BASE_IDX 1 4612 #define regCB_COLOR3_INFO 0x0349 4613 #define regCB_COLOR3_INFO_BASE_IDX 1 4614 #define regCB_COLOR3_ATTRIB 0x034a 4615 #define regCB_COLOR3_ATTRIB_BASE_IDX 1 4616 #define regCB_COLOR3_DCC_CONTROL 0x034b 4617 #define regCB_COLOR3_DCC_CONTROL_BASE_IDX 1 4618 #define regCB_COLOR3_CMASK 0x034c 4619 #define regCB_COLOR3_CMASK_BASE_IDX 1 4620 #define regCB_COLOR3_CMASK_BASE_EXT 0x034d 4621 #define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 4622 #define regCB_COLOR3_FMASK 0x034e 4623 #define regCB_COLOR3_FMASK_BASE_IDX 1 4624 #define regCB_COLOR3_FMASK_BASE_EXT 0x034f 4625 #define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 4626 #define regCB_COLOR3_CLEAR_WORD0 0x0350 4627 #define regCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 4628 #define regCB_COLOR3_CLEAR_WORD1 0x0351 4629 #define regCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 4630 #define regCB_COLOR3_DCC_BASE 0x0352 4631 #define regCB_COLOR3_DCC_BASE_BASE_IDX 1 4632 #define regCB_COLOR3_DCC_BASE_EXT 0x0353 4633 #define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 4634 #define regCB_COLOR4_BASE 0x0354 4635 #define regCB_COLOR4_BASE_BASE_IDX 1 4636 #define regCB_COLOR4_BASE_EXT 0x0355 4637 #define regCB_COLOR4_BASE_EXT_BASE_IDX 1 4638 #define regCB_COLOR4_ATTRIB2 0x0356 4639 #define regCB_COLOR4_ATTRIB2_BASE_IDX 1 4640 #define regCB_COLOR4_VIEW 0x0357 4641 #define regCB_COLOR4_VIEW_BASE_IDX 1 4642 #define regCB_COLOR4_INFO 0x0358 4643 #define regCB_COLOR4_INFO_BASE_IDX 1 4644 #define regCB_COLOR4_ATTRIB 0x0359 4645 #define regCB_COLOR4_ATTRIB_BASE_IDX 1 4646 #define regCB_COLOR4_DCC_CONTROL 0x035a 4647 #define regCB_COLOR4_DCC_CONTROL_BASE_IDX 1 4648 #define regCB_COLOR4_CMASK 0x035b 4649 #define regCB_COLOR4_CMASK_BASE_IDX 1 4650 #define regCB_COLOR4_CMASK_BASE_EXT 0x035c 4651 #define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 4652 #define regCB_COLOR4_FMASK 0x035d 4653 #define regCB_COLOR4_FMASK_BASE_IDX 1 4654 #define regCB_COLOR4_FMASK_BASE_EXT 0x035e 4655 #define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 4656 #define regCB_COLOR4_CLEAR_WORD0 0x035f 4657 #define regCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 4658 #define regCB_COLOR4_CLEAR_WORD1 0x0360 4659 #define regCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 4660 #define regCB_COLOR4_DCC_BASE 0x0361 4661 #define regCB_COLOR4_DCC_BASE_BASE_IDX 1 4662 #define regCB_COLOR4_DCC_BASE_EXT 0x0362 4663 #define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 4664 #define regCB_COLOR5_BASE 0x0363 4665 #define regCB_COLOR5_BASE_BASE_IDX 1 4666 #define regCB_COLOR5_BASE_EXT 0x0364 4667 #define regCB_COLOR5_BASE_EXT_BASE_IDX 1 4668 #define regCB_COLOR5_ATTRIB2 0x0365 4669 #define regCB_COLOR5_ATTRIB2_BASE_IDX 1 4670 #define regCB_COLOR5_VIEW 0x0366 4671 #define regCB_COLOR5_VIEW_BASE_IDX 1 4672 #define regCB_COLOR5_INFO 0x0367 4673 #define regCB_COLOR5_INFO_BASE_IDX 1 4674 #define regCB_COLOR5_ATTRIB 0x0368 4675 #define regCB_COLOR5_ATTRIB_BASE_IDX 1 4676 #define regCB_COLOR5_DCC_CONTROL 0x0369 4677 #define regCB_COLOR5_DCC_CONTROL_BASE_IDX 1 4678 #define regCB_COLOR5_CMASK 0x036a 4679 #define regCB_COLOR5_CMASK_BASE_IDX 1 4680 #define regCB_COLOR5_CMASK_BASE_EXT 0x036b 4681 #define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 4682 #define regCB_COLOR5_FMASK 0x036c 4683 #define regCB_COLOR5_FMASK_BASE_IDX 1 4684 #define regCB_COLOR5_FMASK_BASE_EXT 0x036d 4685 #define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 4686 #define regCB_COLOR5_CLEAR_WORD0 0x036e 4687 #define regCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 4688 #define regCB_COLOR5_CLEAR_WORD1 0x036f 4689 #define regCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 4690 #define regCB_COLOR5_DCC_BASE 0x0370 4691 #define regCB_COLOR5_DCC_BASE_BASE_IDX 1 4692 #define regCB_COLOR5_DCC_BASE_EXT 0x0371 4693 #define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 4694 #define regCB_COLOR6_BASE 0x0372 4695 #define regCB_COLOR6_BASE_BASE_IDX 1 4696 #define regCB_COLOR6_BASE_EXT 0x0373 4697 #define regCB_COLOR6_BASE_EXT_BASE_IDX 1 4698 #define regCB_COLOR6_ATTRIB2 0x0374 4699 #define regCB_COLOR6_ATTRIB2_BASE_IDX 1 4700 #define regCB_COLOR6_VIEW 0x0375 4701 #define regCB_COLOR6_VIEW_BASE_IDX 1 4702 #define regCB_COLOR6_INFO 0x0376 4703 #define regCB_COLOR6_INFO_BASE_IDX 1 4704 #define regCB_COLOR6_ATTRIB 0x0377 4705 #define regCB_COLOR6_ATTRIB_BASE_IDX 1 4706 #define regCB_COLOR6_DCC_CONTROL 0x0378 4707 #define regCB_COLOR6_DCC_CONTROL_BASE_IDX 1 4708 #define regCB_COLOR6_CMASK 0x0379 4709 #define regCB_COLOR6_CMASK_BASE_IDX 1 4710 #define regCB_COLOR6_CMASK_BASE_EXT 0x037a 4711 #define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 4712 #define regCB_COLOR6_FMASK 0x037b 4713 #define regCB_COLOR6_FMASK_BASE_IDX 1 4714 #define regCB_COLOR6_FMASK_BASE_EXT 0x037c 4715 #define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 4716 #define regCB_COLOR6_CLEAR_WORD0 0x037d 4717 #define regCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 4718 #define regCB_COLOR6_CLEAR_WORD1 0x037e 4719 #define regCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 4720 #define regCB_COLOR6_DCC_BASE 0x037f 4721 #define regCB_COLOR6_DCC_BASE_BASE_IDX 1 4722 #define regCB_COLOR6_DCC_BASE_EXT 0x0380 4723 #define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 4724 #define regCB_COLOR7_BASE 0x0381 4725 #define regCB_COLOR7_BASE_BASE_IDX 1 4726 #define regCB_COLOR7_BASE_EXT 0x0382 4727 #define regCB_COLOR7_BASE_EXT_BASE_IDX 1 4728 #define regCB_COLOR7_ATTRIB2 0x0383 4729 #define regCB_COLOR7_ATTRIB2_BASE_IDX 1 4730 #define regCB_COLOR7_VIEW 0x0384 4731 #define regCB_COLOR7_VIEW_BASE_IDX 1 4732 #define regCB_COLOR7_INFO 0x0385 4733 #define regCB_COLOR7_INFO_BASE_IDX 1 4734 #define regCB_COLOR7_ATTRIB 0x0386 4735 #define regCB_COLOR7_ATTRIB_BASE_IDX 1 4736 #define regCB_COLOR7_DCC_CONTROL 0x0387 4737 #define regCB_COLOR7_DCC_CONTROL_BASE_IDX 1 4738 #define regCB_COLOR7_CMASK 0x0388 4739 #define regCB_COLOR7_CMASK_BASE_IDX 1 4740 #define regCB_COLOR7_CMASK_BASE_EXT 0x0389 4741 #define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 4742 #define regCB_COLOR7_FMASK 0x038a 4743 #define regCB_COLOR7_FMASK_BASE_IDX 1 4744 #define regCB_COLOR7_FMASK_BASE_EXT 0x038b 4745 #define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 4746 #define regCB_COLOR7_CLEAR_WORD0 0x038c 4747 #define regCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 4748 #define regCB_COLOR7_CLEAR_WORD1 0x038d 4749 #define regCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 4750 #define regCB_COLOR7_DCC_BASE 0x038e 4751 #define regCB_COLOR7_DCC_BASE_BASE_IDX 1 4752 #define regCB_COLOR7_DCC_BASE_EXT 0x038f 4753 #define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 4754 4755 4756 // addressBlock: xcd0_gc_gfxudec 4757 // base address: 0x30000 4758 #define regCP_EOP_DONE_ADDR_LO 0x2000 4759 #define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 4760 #define regCP_EOP_DONE_ADDR_HI 0x2001 4761 #define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 4762 #define regCP_EOP_DONE_DATA_LO 0x2002 4763 #define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 4764 #define regCP_EOP_DONE_DATA_HI 0x2003 4765 #define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 4766 #define regCP_EOP_LAST_FENCE_LO 0x2004 4767 #define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 4768 #define regCP_EOP_LAST_FENCE_HI 0x2005 4769 #define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 4770 #define regCP_STREAM_OUT_ADDR_LO 0x2006 4771 #define regCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 4772 #define regCP_STREAM_OUT_ADDR_HI 0x2007 4773 #define regCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 4774 #define regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 4775 #define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 4776 #define regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 4777 #define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 4778 #define regCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a 4779 #define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 4780 #define regCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b 4781 #define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 4782 #define regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c 4783 #define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 4784 #define regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d 4785 #define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 4786 #define regCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e 4787 #define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 4788 #define regCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f 4789 #define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 4790 #define regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 4791 #define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 4792 #define regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 4793 #define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 4794 #define regCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 4795 #define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 4796 #define regCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 4797 #define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 4798 #define regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 4799 #define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 4800 #define regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 4801 #define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 4802 #define regCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 4803 #define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 4804 #define regCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 4805 #define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 4806 #define regCP_PIPE_STATS_ADDR_LO 0x2018 4807 #define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 4808 #define regCP_PIPE_STATS_ADDR_HI 0x2019 4809 #define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 4810 #define regCP_VGT_IAVERT_COUNT_LO 0x201a 4811 #define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 4812 #define regCP_VGT_IAVERT_COUNT_HI 0x201b 4813 #define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 4814 #define regCP_VGT_IAPRIM_COUNT_LO 0x201c 4815 #define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 4816 #define regCP_VGT_IAPRIM_COUNT_HI 0x201d 4817 #define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 4818 #define regCP_VGT_GSPRIM_COUNT_LO 0x201e 4819 #define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 4820 #define regCP_VGT_GSPRIM_COUNT_HI 0x201f 4821 #define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 4822 #define regCP_VGT_VSINVOC_COUNT_LO 0x2020 4823 #define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 4824 #define regCP_VGT_VSINVOC_COUNT_HI 0x2021 4825 #define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 4826 #define regCP_VGT_GSINVOC_COUNT_LO 0x2022 4827 #define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 4828 #define regCP_VGT_GSINVOC_COUNT_HI 0x2023 4829 #define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 4830 #define regCP_VGT_HSINVOC_COUNT_LO 0x2024 4831 #define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 4832 #define regCP_VGT_HSINVOC_COUNT_HI 0x2025 4833 #define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 4834 #define regCP_VGT_DSINVOC_COUNT_LO 0x2026 4835 #define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 4836 #define regCP_VGT_DSINVOC_COUNT_HI 0x2027 4837 #define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 4838 #define regCP_PA_CINVOC_COUNT_LO 0x2028 4839 #define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 4840 #define regCP_PA_CINVOC_COUNT_HI 0x2029 4841 #define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 4842 #define regCP_PA_CPRIM_COUNT_LO 0x202a 4843 #define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 4844 #define regCP_PA_CPRIM_COUNT_HI 0x202b 4845 #define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 4846 #define regCP_SC_PSINVOC_COUNT0_LO 0x202c 4847 #define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 4848 #define regCP_SC_PSINVOC_COUNT0_HI 0x202d 4849 #define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 4850 #define regCP_SC_PSINVOC_COUNT1_LO 0x202e 4851 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 4852 #define regCP_SC_PSINVOC_COUNT1_HI 0x202f 4853 #define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 4854 #define regCP_VGT_CSINVOC_COUNT_LO 0x2030 4855 #define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 4856 #define regCP_VGT_CSINVOC_COUNT_HI 0x2031 4857 #define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 4858 #define regCP_PIPE_STATS_CONTROL 0x203d 4859 #define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 4860 #define regCP_STREAM_OUT_CONTROL 0x203e 4861 #define regCP_STREAM_OUT_CONTROL_BASE_IDX 1 4862 #define regCP_STRMOUT_CNTL 0x203f 4863 #define regCP_STRMOUT_CNTL_BASE_IDX 1 4864 #define regSCRATCH_REG0 0x2040 4865 #define regSCRATCH_REG0_BASE_IDX 1 4866 #define regSCRATCH_REG1 0x2041 4867 #define regSCRATCH_REG1_BASE_IDX 1 4868 #define regSCRATCH_REG2 0x2042 4869 #define regSCRATCH_REG2_BASE_IDX 1 4870 #define regSCRATCH_REG3 0x2043 4871 #define regSCRATCH_REG3_BASE_IDX 1 4872 #define regSCRATCH_REG4 0x2044 4873 #define regSCRATCH_REG4_BASE_IDX 1 4874 #define regSCRATCH_REG5 0x2045 4875 #define regSCRATCH_REG5_BASE_IDX 1 4876 #define regSCRATCH_REG6 0x2046 4877 #define regSCRATCH_REG6_BASE_IDX 1 4878 #define regSCRATCH_REG7 0x2047 4879 #define regSCRATCH_REG7_BASE_IDX 1 4880 #define regCP_APPEND_DATA_HI 0x204c 4881 #define regCP_APPEND_DATA_HI_BASE_IDX 1 4882 #define regCP_APPEND_LAST_CS_FENCE_HI 0x204d 4883 #define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 4884 #define regCP_APPEND_LAST_PS_FENCE_HI 0x204e 4885 #define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 4886 #define regSCRATCH_UMSK 0x2050 4887 #define regSCRATCH_UMSK_BASE_IDX 1 4888 #define regSCRATCH_ADDR 0x2051 4889 #define regSCRATCH_ADDR_BASE_IDX 1 4890 #define regCP_PFP_ATOMIC_PREOP_LO 0x2052 4891 #define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 4892 #define regCP_PFP_ATOMIC_PREOP_HI 0x2053 4893 #define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 4894 #define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 4895 #define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4896 #define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 4897 #define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4898 #define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 4899 #define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4900 #define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 4901 #define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4902 #define regCP_APPEND_ADDR_LO 0x2058 4903 #define regCP_APPEND_ADDR_LO_BASE_IDX 1 4904 #define regCP_APPEND_ADDR_HI 0x2059 4905 #define regCP_APPEND_ADDR_HI_BASE_IDX 1 4906 #define regCP_APPEND_DATA_LO 0x205a 4907 #define regCP_APPEND_DATA_LO_BASE_IDX 1 4908 #define regCP_APPEND_LAST_CS_FENCE_LO 0x205b 4909 #define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 4910 #define regCP_APPEND_LAST_PS_FENCE_LO 0x205c 4911 #define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 4912 #define regCP_ATOMIC_PREOP_LO 0x205d 4913 #define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 4914 #define regCP_ME_ATOMIC_PREOP_LO 0x205d 4915 #define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 4916 #define regCP_ATOMIC_PREOP_HI 0x205e 4917 #define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 4918 #define regCP_ME_ATOMIC_PREOP_HI 0x205e 4919 #define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 4920 #define regCP_GDS_ATOMIC0_PREOP_LO 0x205f 4921 #define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4922 #define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f 4923 #define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4924 #define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 4925 #define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4926 #define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 4927 #define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4928 #define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 4929 #define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4930 #define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 4931 #define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4932 #define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 4933 #define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4934 #define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 4935 #define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4936 #define regCP_ME_MC_WADDR_LO 0x2069 4937 #define regCP_ME_MC_WADDR_LO_BASE_IDX 1 4938 #define regCP_ME_MC_WADDR_HI 0x206a 4939 #define regCP_ME_MC_WADDR_HI_BASE_IDX 1 4940 #define regCP_ME_MC_WDATA_LO 0x206b 4941 #define regCP_ME_MC_WDATA_LO_BASE_IDX 1 4942 #define regCP_ME_MC_WDATA_HI 0x206c 4943 #define regCP_ME_MC_WDATA_HI_BASE_IDX 1 4944 #define regCP_ME_MC_RADDR_LO 0x206d 4945 #define regCP_ME_MC_RADDR_LO_BASE_IDX 1 4946 #define regCP_ME_MC_RADDR_HI 0x206e 4947 #define regCP_ME_MC_RADDR_HI_BASE_IDX 1 4948 #define regCP_SEM_WAIT_TIMER 0x206f 4949 #define regCP_SEM_WAIT_TIMER_BASE_IDX 1 4950 #define regCP_SIG_SEM_ADDR_LO 0x2070 4951 #define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 4952 #define regCP_SIG_SEM_ADDR_HI 0x2071 4953 #define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 4954 #define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 4955 #define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 4956 #define regCP_WAIT_SEM_ADDR_LO 0x2075 4957 #define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 4958 #define regCP_WAIT_SEM_ADDR_HI 0x2076 4959 #define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 4960 #define regCP_DMA_PFP_CONTROL 0x2077 4961 #define regCP_DMA_PFP_CONTROL_BASE_IDX 1 4962 #define regCP_DMA_ME_CONTROL 0x2078 4963 #define regCP_DMA_ME_CONTROL_BASE_IDX 1 4964 #define regCP_COHER_BASE_HI 0x2079 4965 #define regCP_COHER_BASE_HI_BASE_IDX 1 4966 #define regCP_COHER_START_DELAY 0x207b 4967 #define regCP_COHER_START_DELAY_BASE_IDX 1 4968 #define regCP_COHER_CNTL 0x207c 4969 #define regCP_COHER_CNTL_BASE_IDX 1 4970 #define regCP_COHER_SIZE 0x207d 4971 #define regCP_COHER_SIZE_BASE_IDX 1 4972 #define regCP_COHER_BASE 0x207e 4973 #define regCP_COHER_BASE_BASE_IDX 1 4974 #define regCP_COHER_STATUS 0x207f 4975 #define regCP_COHER_STATUS_BASE_IDX 1 4976 #define regCP_DMA_ME_SRC_ADDR 0x2080 4977 #define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 4978 #define regCP_DMA_ME_SRC_ADDR_HI 0x2081 4979 #define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 4980 #define regCP_DMA_ME_DST_ADDR 0x2082 4981 #define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 4982 #define regCP_DMA_ME_DST_ADDR_HI 0x2083 4983 #define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 4984 #define regCP_DMA_ME_COMMAND 0x2084 4985 #define regCP_DMA_ME_COMMAND_BASE_IDX 1 4986 #define regCP_DMA_PFP_SRC_ADDR 0x2085 4987 #define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 4988 #define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 4989 #define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 4990 #define regCP_DMA_PFP_DST_ADDR 0x2087 4991 #define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 4992 #define regCP_DMA_PFP_DST_ADDR_HI 0x2088 4993 #define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 4994 #define regCP_DMA_PFP_COMMAND 0x2089 4995 #define regCP_DMA_PFP_COMMAND_BASE_IDX 1 4996 #define regCP_DMA_CNTL 0x208a 4997 #define regCP_DMA_CNTL_BASE_IDX 1 4998 #define regCP_DMA_READ_TAGS 0x208b 4999 #define regCP_DMA_READ_TAGS_BASE_IDX 1 5000 #define regCP_COHER_SIZE_HI 0x208c 5001 #define regCP_COHER_SIZE_HI_BASE_IDX 1 5002 #define regCP_PFP_IB_CONTROL 0x208d 5003 #define regCP_PFP_IB_CONTROL_BASE_IDX 1 5004 #define regCP_PFP_LOAD_CONTROL 0x208e 5005 #define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 5006 #define regCP_SCRATCH_INDEX 0x208f 5007 #define regCP_SCRATCH_INDEX_BASE_IDX 1 5008 #define regCP_SCRATCH_DATA 0x2090 5009 #define regCP_SCRATCH_DATA_BASE_IDX 1 5010 #define regCP_RB_OFFSET 0x2091 5011 #define regCP_RB_OFFSET_BASE_IDX 1 5012 #define regCP_IB1_OFFSET 0x2092 5013 #define regCP_IB1_OFFSET_BASE_IDX 1 5014 #define regCP_IB2_OFFSET 0x2093 5015 #define regCP_IB2_OFFSET_BASE_IDX 1 5016 #define regCP_IB1_PREAMBLE_BEGIN 0x2094 5017 #define regCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 5018 #define regCP_IB1_PREAMBLE_END 0x2095 5019 #define regCP_IB1_PREAMBLE_END_BASE_IDX 1 5020 #define regCP_IB2_PREAMBLE_BEGIN 0x2096 5021 #define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 5022 #define regCP_IB2_PREAMBLE_END 0x2097 5023 #define regCP_IB2_PREAMBLE_END_BASE_IDX 1 5024 #define regCP_CE_IB1_OFFSET 0x2098 5025 #define regCP_CE_IB1_OFFSET_BASE_IDX 1 5026 #define regCP_CE_IB2_OFFSET 0x2099 5027 #define regCP_CE_IB2_OFFSET_BASE_IDX 1 5028 #define regCP_CE_COUNTER 0x209a 5029 #define regCP_CE_COUNTER_BASE_IDX 1 5030 #define regCP_CE_RB_OFFSET 0x209b 5031 #define regCP_CE_RB_OFFSET_BASE_IDX 1 5032 #define regCP_CE_INIT_CMD_BUFSZ 0x20bd 5033 #define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 5034 #define regCP_CE_IB1_CMD_BUFSZ 0x20be 5035 #define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 5036 #define regCP_CE_IB2_CMD_BUFSZ 0x20bf 5037 #define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 5038 #define regCP_IB1_CMD_BUFSZ 0x20c0 5039 #define regCP_IB1_CMD_BUFSZ_BASE_IDX 1 5040 #define regCP_IB2_CMD_BUFSZ 0x20c1 5041 #define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 5042 #define regCP_ST_CMD_BUFSZ 0x20c2 5043 #define regCP_ST_CMD_BUFSZ_BASE_IDX 1 5044 #define regCP_CE_INIT_BASE_LO 0x20c3 5045 #define regCP_CE_INIT_BASE_LO_BASE_IDX 1 5046 #define regCP_CE_INIT_BASE_HI 0x20c4 5047 #define regCP_CE_INIT_BASE_HI_BASE_IDX 1 5048 #define regCP_CE_INIT_BUFSZ 0x20c5 5049 #define regCP_CE_INIT_BUFSZ_BASE_IDX 1 5050 #define regCP_CE_IB1_BASE_LO 0x20c6 5051 #define regCP_CE_IB1_BASE_LO_BASE_IDX 1 5052 #define regCP_CE_IB1_BASE_HI 0x20c7 5053 #define regCP_CE_IB1_BASE_HI_BASE_IDX 1 5054 #define regCP_CE_IB1_BUFSZ 0x20c8 5055 #define regCP_CE_IB1_BUFSZ_BASE_IDX 1 5056 #define regCP_CE_IB2_BASE_LO 0x20c9 5057 #define regCP_CE_IB2_BASE_LO_BASE_IDX 1 5058 #define regCP_CE_IB2_BASE_HI 0x20ca 5059 #define regCP_CE_IB2_BASE_HI_BASE_IDX 1 5060 #define regCP_CE_IB2_BUFSZ 0x20cb 5061 #define regCP_CE_IB2_BUFSZ_BASE_IDX 1 5062 #define regCP_IB1_BASE_LO 0x20cc 5063 #define regCP_IB1_BASE_LO_BASE_IDX 1 5064 #define regCP_IB1_BASE_HI 0x20cd 5065 #define regCP_IB1_BASE_HI_BASE_IDX 1 5066 #define regCP_IB1_BUFSZ 0x20ce 5067 #define regCP_IB1_BUFSZ_BASE_IDX 1 5068 #define regCP_IB2_BASE_LO 0x20cf 5069 #define regCP_IB2_BASE_LO_BASE_IDX 1 5070 #define regCP_IB2_BASE_HI 0x20d0 5071 #define regCP_IB2_BASE_HI_BASE_IDX 1 5072 #define regCP_IB2_BUFSZ 0x20d1 5073 #define regCP_IB2_BUFSZ_BASE_IDX 1 5074 #define regCP_ST_BASE_LO 0x20d2 5075 #define regCP_ST_BASE_LO_BASE_IDX 1 5076 #define regCP_ST_BASE_HI 0x20d3 5077 #define regCP_ST_BASE_HI_BASE_IDX 1 5078 #define regCP_ST_BUFSZ 0x20d4 5079 #define regCP_ST_BUFSZ_BASE_IDX 1 5080 #define regCP_EOP_DONE_EVENT_CNTL 0x20d5 5081 #define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 5082 #define regCP_EOP_DONE_DATA_CNTL 0x20d6 5083 #define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 5084 #define regCP_EOP_DONE_CNTX_ID 0x20d7 5085 #define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 5086 #define regCP_PFP_COMPLETION_STATUS 0x20ec 5087 #define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 5088 #define regCP_CE_COMPLETION_STATUS 0x20ed 5089 #define regCP_CE_COMPLETION_STATUS_BASE_IDX 1 5090 #define regCP_PRED_NOT_VISIBLE 0x20ee 5091 #define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 5092 #define regCP_PFP_METADATA_BASE_ADDR 0x20f0 5093 #define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 5094 #define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 5095 #define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 5096 #define regCP_CE_METADATA_BASE_ADDR 0x20f2 5097 #define regCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 5098 #define regCP_CE_METADATA_BASE_ADDR_HI 0x20f3 5099 #define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 5100 #define regCP_DRAW_INDX_INDR_ADDR 0x20f4 5101 #define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 5102 #define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 5103 #define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 5104 #define regCP_DISPATCH_INDR_ADDR 0x20f6 5105 #define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 5106 #define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 5107 #define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 5108 #define regCP_INDEX_BASE_ADDR 0x20f8 5109 #define regCP_INDEX_BASE_ADDR_BASE_IDX 1 5110 #define regCP_INDEX_BASE_ADDR_HI 0x20f9 5111 #define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 5112 #define regCP_INDEX_TYPE 0x20fa 5113 #define regCP_INDEX_TYPE_BASE_IDX 1 5114 #define regCP_GDS_BKUP_ADDR 0x20fb 5115 #define regCP_GDS_BKUP_ADDR_BASE_IDX 1 5116 #define regCP_GDS_BKUP_ADDR_HI 0x20fc 5117 #define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 5118 #define regCP_SAMPLE_STATUS 0x20fd 5119 #define regCP_SAMPLE_STATUS_BASE_IDX 1 5120 #define regCP_ME_COHER_CNTL 0x20fe 5121 #define regCP_ME_COHER_CNTL_BASE_IDX 1 5122 #define regCP_ME_COHER_SIZE 0x20ff 5123 #define regCP_ME_COHER_SIZE_BASE_IDX 1 5124 #define regCP_ME_COHER_SIZE_HI 0x2100 5125 #define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 5126 #define regCP_ME_COHER_BASE 0x2101 5127 #define regCP_ME_COHER_BASE_BASE_IDX 1 5128 #define regCP_ME_COHER_BASE_HI 0x2102 5129 #define regCP_ME_COHER_BASE_HI_BASE_IDX 1 5130 #define regCP_ME_COHER_STATUS 0x2103 5131 #define regCP_ME_COHER_STATUS_BASE_IDX 1 5132 #define regRLC_GPM_PERF_COUNT_0 0x2140 5133 #define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 5134 #define regRLC_GPM_PERF_COUNT_1 0x2141 5135 #define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 5136 #define regGRBM_GFX_INDEX 0x2200 5137 #define regGRBM_GFX_INDEX_BASE_IDX 1 5138 #define regVGT_GSVS_RING_SIZE 0x2241 5139 #define regVGT_GSVS_RING_SIZE_BASE_IDX 1 5140 #define regVGT_PRIMITIVE_TYPE 0x2242 5141 #define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 5142 #define regVGT_INDEX_TYPE 0x2243 5143 #define regVGT_INDEX_TYPE_BASE_IDX 1 5144 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 5145 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 5146 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 5147 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 5148 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 5149 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 5150 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 5151 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 5152 #define regVGT_MAX_VTX_INDX 0x2248 5153 #define regVGT_MAX_VTX_INDX_BASE_IDX 1 5154 #define regVGT_MIN_VTX_INDX 0x2249 5155 #define regVGT_MIN_VTX_INDX_BASE_IDX 1 5156 #define regVGT_INDX_OFFSET 0x224a 5157 #define regVGT_INDX_OFFSET_BASE_IDX 1 5158 #define regVGT_MULTI_PRIM_IB_RESET_EN 0x224b 5159 #define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 5160 #define regVGT_NUM_INDICES 0x224c 5161 #define regVGT_NUM_INDICES_BASE_IDX 1 5162 #define regVGT_NUM_INSTANCES 0x224d 5163 #define regVGT_NUM_INSTANCES_BASE_IDX 1 5164 #define regVGT_TF_RING_SIZE 0x224e 5165 #define regVGT_TF_RING_SIZE_BASE_IDX 1 5166 #define regVGT_HS_OFFCHIP_PARAM 0x224f 5167 #define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 5168 #define regVGT_TF_MEMORY_BASE 0x2250 5169 #define regVGT_TF_MEMORY_BASE_BASE_IDX 1 5170 #define regVGT_TF_MEMORY_BASE_HI 0x2251 5171 #define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 5172 #define regWD_POS_BUF_BASE 0x2252 5173 #define regWD_POS_BUF_BASE_BASE_IDX 1 5174 #define regWD_POS_BUF_BASE_HI 0x2253 5175 #define regWD_POS_BUF_BASE_HI_BASE_IDX 1 5176 #define regWD_CNTL_SB_BUF_BASE 0x2254 5177 #define regWD_CNTL_SB_BUF_BASE_BASE_IDX 1 5178 #define regWD_CNTL_SB_BUF_BASE_HI 0x2255 5179 #define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 5180 #define regWD_INDEX_BUF_BASE 0x2256 5181 #define regWD_INDEX_BUF_BASE_BASE_IDX 1 5182 #define regWD_INDEX_BUF_BASE_HI 0x2257 5183 #define regWD_INDEX_BUF_BASE_HI_BASE_IDX 1 5184 #define regIA_MULTI_VGT_PARAM 0x2258 5185 #define regIA_MULTI_VGT_PARAM_BASE_IDX 1 5186 #define regVGT_INSTANCE_BASE_ID 0x225a 5187 #define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 5188 #define regPA_SU_LINE_STIPPLE_VALUE 0x2280 5189 #define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 5190 #define regPA_SC_LINE_STIPPLE_STATE 0x2281 5191 #define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 5192 #define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 5193 #define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 5194 #define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 5195 #define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 5196 #define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 5197 #define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 5198 #define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b 5199 #define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 5200 #define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 5201 #define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 5202 #define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 5203 #define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 5204 #define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 5205 #define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 5206 #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 5207 #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5208 #define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 5209 #define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 5210 #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 5211 #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 5212 #define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 5213 #define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 5214 #define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa 5215 #define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 5216 #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab 5217 #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5218 #define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac 5219 #define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 5220 #define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 5221 #define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 5222 #define regPA_SC_TRAP_SCREEN_H 0x22b1 5223 #define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 5224 #define regPA_SC_TRAP_SCREEN_V 0x22b2 5225 #define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 5226 #define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 5227 #define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5228 #define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 5229 #define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 5230 #define regPA_STATE_STEREO_X 0x22b5 5231 #define regPA_STATE_STEREO_X_BASE_IDX 1 5232 #define regSQ_THREAD_TRACE_BASE 0x2330 5233 #define regSQ_THREAD_TRACE_BASE_BASE_IDX 1 5234 #define regSQ_THREAD_TRACE_SIZE 0x2331 5235 #define regSQ_THREAD_TRACE_SIZE_BASE_IDX 1 5236 #define regSQ_THREAD_TRACE_MASK 0x2332 5237 #define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 5238 #define regSQ_THREAD_TRACE_TOKEN_MASK 0x2333 5239 #define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 5240 #define regSQ_THREAD_TRACE_PERF_MASK 0x2334 5241 #define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 5242 #define regSQ_THREAD_TRACE_CTRL 0x2335 5243 #define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 5244 #define regSQ_THREAD_TRACE_MODE 0x2336 5245 #define regSQ_THREAD_TRACE_MODE_BASE_IDX 1 5246 #define regSQ_THREAD_TRACE_BASE2 0x2337 5247 #define regSQ_THREAD_TRACE_BASE2_BASE_IDX 1 5248 #define regSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 5249 #define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 5250 #define regSQ_THREAD_TRACE_WPTR 0x2339 5251 #define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 5252 #define regSQ_THREAD_TRACE_STATUS 0x233a 5253 #define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 5254 #define regSQ_THREAD_TRACE_HIWATER 0x233b 5255 #define regSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 5256 #define regSQ_THREAD_TRACE_CNTR 0x233c 5257 #define regSQ_THREAD_TRACE_CNTR_BASE_IDX 1 5258 #define regSQ_THREAD_TRACE_USERDATA_0 0x2340 5259 #define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 5260 #define regSQ_THREAD_TRACE_USERDATA_1 0x2341 5261 #define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 5262 #define regSQ_THREAD_TRACE_USERDATA_2 0x2342 5263 #define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 5264 #define regSQ_THREAD_TRACE_USERDATA_3 0x2343 5265 #define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 5266 #define regSQC_CACHES 0x2348 5267 #define regSQC_CACHES_BASE_IDX 1 5268 #define regSQC_WRITEBACK 0x2349 5269 #define regSQC_WRITEBACK_BASE_IDX 1 5270 #define regDB_OCCLUSION_COUNT0_LOW 0x23c0 5271 #define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 5272 #define regDB_OCCLUSION_COUNT0_HI 0x23c1 5273 #define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 5274 #define regDB_OCCLUSION_COUNT1_LOW 0x23c2 5275 #define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 5276 #define regDB_OCCLUSION_COUNT1_HI 0x23c3 5277 #define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 5278 #define regDB_OCCLUSION_COUNT2_LOW 0x23c4 5279 #define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 5280 #define regDB_OCCLUSION_COUNT2_HI 0x23c5 5281 #define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 5282 #define regDB_OCCLUSION_COUNT3_LOW 0x23c6 5283 #define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 5284 #define regDB_OCCLUSION_COUNT3_HI 0x23c7 5285 #define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 5286 #define regDB_ZPASS_COUNT_LOW 0x23fe 5287 #define regDB_ZPASS_COUNT_LOW_BASE_IDX 1 5288 #define regDB_ZPASS_COUNT_HI 0x23ff 5289 #define regDB_ZPASS_COUNT_HI_BASE_IDX 1 5290 #define regGDS_RD_ADDR 0x2400 5291 #define regGDS_RD_ADDR_BASE_IDX 1 5292 #define regGDS_RD_DATA 0x2401 5293 #define regGDS_RD_DATA_BASE_IDX 1 5294 #define regGDS_RD_BURST_ADDR 0x2402 5295 #define regGDS_RD_BURST_ADDR_BASE_IDX 1 5296 #define regGDS_RD_BURST_COUNT 0x2403 5297 #define regGDS_RD_BURST_COUNT_BASE_IDX 1 5298 #define regGDS_RD_BURST_DATA 0x2404 5299 #define regGDS_RD_BURST_DATA_BASE_IDX 1 5300 #define regGDS_WR_ADDR 0x2405 5301 #define regGDS_WR_ADDR_BASE_IDX 1 5302 #define regGDS_WR_DATA 0x2406 5303 #define regGDS_WR_DATA_BASE_IDX 1 5304 #define regGDS_WR_BURST_ADDR 0x2407 5305 #define regGDS_WR_BURST_ADDR_BASE_IDX 1 5306 #define regGDS_WR_BURST_DATA 0x2408 5307 #define regGDS_WR_BURST_DATA_BASE_IDX 1 5308 #define regGDS_WRITE_COMPLETE 0x2409 5309 #define regGDS_WRITE_COMPLETE_BASE_IDX 1 5310 #define regGDS_ATOM_CNTL 0x240a 5311 #define regGDS_ATOM_CNTL_BASE_IDX 1 5312 #define regGDS_ATOM_COMPLETE 0x240b 5313 #define regGDS_ATOM_COMPLETE_BASE_IDX 1 5314 #define regGDS_ATOM_BASE 0x240c 5315 #define regGDS_ATOM_BASE_BASE_IDX 1 5316 #define regGDS_ATOM_SIZE 0x240d 5317 #define regGDS_ATOM_SIZE_BASE_IDX 1 5318 #define regGDS_ATOM_OFFSET0 0x240e 5319 #define regGDS_ATOM_OFFSET0_BASE_IDX 1 5320 #define regGDS_ATOM_OFFSET1 0x240f 5321 #define regGDS_ATOM_OFFSET1_BASE_IDX 1 5322 #define regGDS_ATOM_DST 0x2410 5323 #define regGDS_ATOM_DST_BASE_IDX 1 5324 #define regGDS_ATOM_OP 0x2411 5325 #define regGDS_ATOM_OP_BASE_IDX 1 5326 #define regGDS_ATOM_SRC0 0x2412 5327 #define regGDS_ATOM_SRC0_BASE_IDX 1 5328 #define regGDS_ATOM_SRC0_U 0x2413 5329 #define regGDS_ATOM_SRC0_U_BASE_IDX 1 5330 #define regGDS_ATOM_SRC1 0x2414 5331 #define regGDS_ATOM_SRC1_BASE_IDX 1 5332 #define regGDS_ATOM_SRC1_U 0x2415 5333 #define regGDS_ATOM_SRC1_U_BASE_IDX 1 5334 #define regGDS_ATOM_READ0 0x2416 5335 #define regGDS_ATOM_READ0_BASE_IDX 1 5336 #define regGDS_ATOM_READ0_U 0x2417 5337 #define regGDS_ATOM_READ0_U_BASE_IDX 1 5338 #define regGDS_ATOM_READ1 0x2418 5339 #define regGDS_ATOM_READ1_BASE_IDX 1 5340 #define regGDS_ATOM_READ1_U 0x2419 5341 #define regGDS_ATOM_READ1_U_BASE_IDX 1 5342 #define regGDS_GWS_RESOURCE_CNTL 0x241a 5343 #define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 5344 #define regGDS_GWS_RESOURCE 0x241b 5345 #define regGDS_GWS_RESOURCE_BASE_IDX 1 5346 #define regGDS_GWS_RESOURCE_CNT 0x241c 5347 #define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 5348 #define regGDS_OA_CNTL 0x241d 5349 #define regGDS_OA_CNTL_BASE_IDX 1 5350 #define regGDS_OA_COUNTER 0x241e 5351 #define regGDS_OA_COUNTER_BASE_IDX 1 5352 #define regGDS_OA_ADDRESS 0x241f 5353 #define regGDS_OA_ADDRESS_BASE_IDX 1 5354 #define regGDS_OA_INCDEC 0x2420 5355 #define regGDS_OA_INCDEC_BASE_IDX 1 5356 #define regGDS_OA_RING_SIZE 0x2421 5357 #define regGDS_OA_RING_SIZE_BASE_IDX 1 5358 #define regSPI_CONFIG_CNTL 0x2440 5359 #define regSPI_CONFIG_CNTL_BASE_IDX 1 5360 #define regSPI_CONFIG_CNTL_1 0x2441 5361 #define regSPI_CONFIG_CNTL_1_BASE_IDX 1 5362 #define regSPI_CONFIG_CNTL_2 0x2442 5363 #define regSPI_CONFIG_CNTL_2_BASE_IDX 1 5364 #define regSPI_WAVE_LIMIT_CNTL 0x2443 5365 #define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 5366 5367 5368 // addressBlock: xcd0_gc_perfddec 5369 // base address: 0x34000 5370 #define regCPG_PERFCOUNTER1_LO 0x3000 5371 #define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 5372 #define regCPG_PERFCOUNTER1_HI 0x3001 5373 #define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 5374 #define regCPG_PERFCOUNTER0_LO 0x3002 5375 #define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 5376 #define regCPG_PERFCOUNTER0_HI 0x3003 5377 #define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 5378 #define regCPC_PERFCOUNTER1_LO 0x3004 5379 #define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 5380 #define regCPC_PERFCOUNTER1_HI 0x3005 5381 #define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 5382 #define regCPC_PERFCOUNTER0_LO 0x3006 5383 #define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 5384 #define regCPC_PERFCOUNTER0_HI 0x3007 5385 #define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 5386 #define regCPF_PERFCOUNTER1_LO 0x3008 5387 #define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 5388 #define regCPF_PERFCOUNTER1_HI 0x3009 5389 #define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 5390 #define regCPF_PERFCOUNTER0_LO 0x300a 5391 #define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 5392 #define regCPF_PERFCOUNTER0_HI 0x300b 5393 #define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 5394 #define regCPF_LATENCY_STATS_DATA 0x300c 5395 #define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 5396 #define regCPG_LATENCY_STATS_DATA 0x300d 5397 #define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 5398 #define regCPC_LATENCY_STATS_DATA 0x300e 5399 #define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 5400 #define regGRBM_PERFCOUNTER0_LO 0x3040 5401 #define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 5402 #define regGRBM_PERFCOUNTER0_HI 0x3041 5403 #define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 5404 #define regGRBM_PERFCOUNTER1_LO 0x3043 5405 #define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 5406 #define regGRBM_PERFCOUNTER1_HI 0x3044 5407 #define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 5408 #define regGRBM_SE0_PERFCOUNTER_LO 0x3045 5409 #define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 5410 #define regGRBM_SE0_PERFCOUNTER_HI 0x3046 5411 #define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 5412 #define regGRBM_SE1_PERFCOUNTER_LO 0x3047 5413 #define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 5414 #define regGRBM_SE1_PERFCOUNTER_HI 0x3048 5415 #define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 5416 #define regGRBM_SE2_PERFCOUNTER_LO 0x3049 5417 #define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 5418 #define regGRBM_SE2_PERFCOUNTER_HI 0x304a 5419 #define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 5420 #define regGRBM_SE3_PERFCOUNTER_LO 0x304b 5421 #define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 5422 #define regGRBM_SE3_PERFCOUNTER_HI 0x304c 5423 #define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 5424 #define regWD_PERFCOUNTER0_LO 0x3080 5425 #define regWD_PERFCOUNTER0_LO_BASE_IDX 1 5426 #define regWD_PERFCOUNTER0_HI 0x3081 5427 #define regWD_PERFCOUNTER0_HI_BASE_IDX 1 5428 #define regWD_PERFCOUNTER1_LO 0x3082 5429 #define regWD_PERFCOUNTER1_LO_BASE_IDX 1 5430 #define regWD_PERFCOUNTER1_HI 0x3083 5431 #define regWD_PERFCOUNTER1_HI_BASE_IDX 1 5432 #define regWD_PERFCOUNTER2_LO 0x3084 5433 #define regWD_PERFCOUNTER2_LO_BASE_IDX 1 5434 #define regWD_PERFCOUNTER2_HI 0x3085 5435 #define regWD_PERFCOUNTER2_HI_BASE_IDX 1 5436 #define regWD_PERFCOUNTER3_LO 0x3086 5437 #define regWD_PERFCOUNTER3_LO_BASE_IDX 1 5438 #define regWD_PERFCOUNTER3_HI 0x3087 5439 #define regWD_PERFCOUNTER3_HI_BASE_IDX 1 5440 #define regIA_PERFCOUNTER0_LO 0x3088 5441 #define regIA_PERFCOUNTER0_LO_BASE_IDX 1 5442 #define regIA_PERFCOUNTER0_HI 0x3089 5443 #define regIA_PERFCOUNTER0_HI_BASE_IDX 1 5444 #define regIA_PERFCOUNTER1_LO 0x308a 5445 #define regIA_PERFCOUNTER1_LO_BASE_IDX 1 5446 #define regIA_PERFCOUNTER1_HI 0x308b 5447 #define regIA_PERFCOUNTER1_HI_BASE_IDX 1 5448 #define regIA_PERFCOUNTER2_LO 0x308c 5449 #define regIA_PERFCOUNTER2_LO_BASE_IDX 1 5450 #define regIA_PERFCOUNTER2_HI 0x308d 5451 #define regIA_PERFCOUNTER2_HI_BASE_IDX 1 5452 #define regIA_PERFCOUNTER3_LO 0x308e 5453 #define regIA_PERFCOUNTER3_LO_BASE_IDX 1 5454 #define regIA_PERFCOUNTER3_HI 0x308f 5455 #define regIA_PERFCOUNTER3_HI_BASE_IDX 1 5456 #define regVGT_PERFCOUNTER0_LO 0x3090 5457 #define regVGT_PERFCOUNTER0_LO_BASE_IDX 1 5458 #define regVGT_PERFCOUNTER0_HI 0x3091 5459 #define regVGT_PERFCOUNTER0_HI_BASE_IDX 1 5460 #define regVGT_PERFCOUNTER1_LO 0x3092 5461 #define regVGT_PERFCOUNTER1_LO_BASE_IDX 1 5462 #define regVGT_PERFCOUNTER1_HI 0x3093 5463 #define regVGT_PERFCOUNTER1_HI_BASE_IDX 1 5464 #define regVGT_PERFCOUNTER2_LO 0x3094 5465 #define regVGT_PERFCOUNTER2_LO_BASE_IDX 1 5466 #define regVGT_PERFCOUNTER2_HI 0x3095 5467 #define regVGT_PERFCOUNTER2_HI_BASE_IDX 1 5468 #define regVGT_PERFCOUNTER3_LO 0x3096 5469 #define regVGT_PERFCOUNTER3_LO_BASE_IDX 1 5470 #define regVGT_PERFCOUNTER3_HI 0x3097 5471 #define regVGT_PERFCOUNTER3_HI_BASE_IDX 1 5472 #define regPA_SU_PERFCOUNTER0_LO 0x3100 5473 #define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 5474 #define regPA_SU_PERFCOUNTER0_HI 0x3101 5475 #define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 5476 #define regPA_SU_PERFCOUNTER1_LO 0x3102 5477 #define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 5478 #define regPA_SU_PERFCOUNTER1_HI 0x3103 5479 #define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 5480 #define regPA_SU_PERFCOUNTER2_LO 0x3104 5481 #define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 5482 #define regPA_SU_PERFCOUNTER2_HI 0x3105 5483 #define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 5484 #define regPA_SU_PERFCOUNTER3_LO 0x3106 5485 #define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 5486 #define regPA_SU_PERFCOUNTER3_HI 0x3107 5487 #define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 5488 #define regPA_SC_PERFCOUNTER0_LO 0x3140 5489 #define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 5490 #define regPA_SC_PERFCOUNTER0_HI 0x3141 5491 #define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 5492 #define regPA_SC_PERFCOUNTER1_LO 0x3142 5493 #define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 5494 #define regPA_SC_PERFCOUNTER1_HI 0x3143 5495 #define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 5496 #define regPA_SC_PERFCOUNTER2_LO 0x3144 5497 #define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 5498 #define regPA_SC_PERFCOUNTER2_HI 0x3145 5499 #define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 5500 #define regPA_SC_PERFCOUNTER3_LO 0x3146 5501 #define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 5502 #define regPA_SC_PERFCOUNTER3_HI 0x3147 5503 #define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 5504 #define regPA_SC_PERFCOUNTER4_LO 0x3148 5505 #define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 5506 #define regPA_SC_PERFCOUNTER4_HI 0x3149 5507 #define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 5508 #define regPA_SC_PERFCOUNTER5_LO 0x314a 5509 #define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 5510 #define regPA_SC_PERFCOUNTER5_HI 0x314b 5511 #define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 5512 #define regPA_SC_PERFCOUNTER6_LO 0x314c 5513 #define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 5514 #define regPA_SC_PERFCOUNTER6_HI 0x314d 5515 #define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 5516 #define regPA_SC_PERFCOUNTER7_LO 0x314e 5517 #define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 5518 #define regPA_SC_PERFCOUNTER7_HI 0x314f 5519 #define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 5520 #define regSPI_PERFCOUNTER0_HI 0x3180 5521 #define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 5522 #define regSPI_PERFCOUNTER0_LO 0x3181 5523 #define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 5524 #define regSPI_PERFCOUNTER1_HI 0x3182 5525 #define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 5526 #define regSPI_PERFCOUNTER1_LO 0x3183 5527 #define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 5528 #define regSPI_PERFCOUNTER2_HI 0x3184 5529 #define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 5530 #define regSPI_PERFCOUNTER2_LO 0x3185 5531 #define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 5532 #define regSPI_PERFCOUNTER3_HI 0x3186 5533 #define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 5534 #define regSPI_PERFCOUNTER3_LO 0x3187 5535 #define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 5536 #define regSPI_PERFCOUNTER4_HI 0x3188 5537 #define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 5538 #define regSPI_PERFCOUNTER4_LO 0x3189 5539 #define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 5540 #define regSPI_PERFCOUNTER5_HI 0x318a 5541 #define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 5542 #define regSPI_PERFCOUNTER5_LO 0x318b 5543 #define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 5544 #define regSQ_PERFCOUNTER0_LO 0x31c0 5545 #define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 5546 #define regSQ_PERFCOUNTER0_HI 0x31c1 5547 #define regSQ_PERFCOUNTER0_HI_BASE_IDX 1 5548 #define regSQ_PERFCOUNTER1_LO 0x31c2 5549 #define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 5550 #define regSQ_PERFCOUNTER1_HI 0x31c3 5551 #define regSQ_PERFCOUNTER1_HI_BASE_IDX 1 5552 #define regSQ_PERFCOUNTER2_LO 0x31c4 5553 #define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 5554 #define regSQ_PERFCOUNTER2_HI 0x31c5 5555 #define regSQ_PERFCOUNTER2_HI_BASE_IDX 1 5556 #define regSQ_PERFCOUNTER3_LO 0x31c6 5557 #define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 5558 #define regSQ_PERFCOUNTER3_HI 0x31c7 5559 #define regSQ_PERFCOUNTER3_HI_BASE_IDX 1 5560 #define regSQ_PERFCOUNTER4_LO 0x31c8 5561 #define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 5562 #define regSQ_PERFCOUNTER4_HI 0x31c9 5563 #define regSQ_PERFCOUNTER4_HI_BASE_IDX 1 5564 #define regSQ_PERFCOUNTER5_LO 0x31ca 5565 #define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 5566 #define regSQ_PERFCOUNTER5_HI 0x31cb 5567 #define regSQ_PERFCOUNTER5_HI_BASE_IDX 1 5568 #define regSQ_PERFCOUNTER6_LO 0x31cc 5569 #define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 5570 #define regSQ_PERFCOUNTER6_HI 0x31cd 5571 #define regSQ_PERFCOUNTER6_HI_BASE_IDX 1 5572 #define regSQ_PERFCOUNTER7_LO 0x31ce 5573 #define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 5574 #define regSQ_PERFCOUNTER7_HI 0x31cf 5575 #define regSQ_PERFCOUNTER7_HI_BASE_IDX 1 5576 #define regSQ_PERFCOUNTER8_LO 0x31d0 5577 #define regSQ_PERFCOUNTER8_LO_BASE_IDX 1 5578 #define regSQ_PERFCOUNTER8_HI 0x31d1 5579 #define regSQ_PERFCOUNTER8_HI_BASE_IDX 1 5580 #define regSQ_PERFCOUNTER9_LO 0x31d2 5581 #define regSQ_PERFCOUNTER9_LO_BASE_IDX 1 5582 #define regSQ_PERFCOUNTER9_HI 0x31d3 5583 #define regSQ_PERFCOUNTER9_HI_BASE_IDX 1 5584 #define regSQ_PERFCOUNTER10_LO 0x31d4 5585 #define regSQ_PERFCOUNTER10_LO_BASE_IDX 1 5586 #define regSQ_PERFCOUNTER10_HI 0x31d5 5587 #define regSQ_PERFCOUNTER10_HI_BASE_IDX 1 5588 #define regSQ_PERFCOUNTER11_LO 0x31d6 5589 #define regSQ_PERFCOUNTER11_LO_BASE_IDX 1 5590 #define regSQ_PERFCOUNTER11_HI 0x31d7 5591 #define regSQ_PERFCOUNTER11_HI_BASE_IDX 1 5592 #define regSQ_PERFCOUNTER12_LO 0x31d8 5593 #define regSQ_PERFCOUNTER12_LO_BASE_IDX 1 5594 #define regSQ_PERFCOUNTER12_HI 0x31d9 5595 #define regSQ_PERFCOUNTER12_HI_BASE_IDX 1 5596 #define regSQ_PERFCOUNTER13_LO 0x31da 5597 #define regSQ_PERFCOUNTER13_LO_BASE_IDX 1 5598 #define regSQ_PERFCOUNTER13_HI 0x31db 5599 #define regSQ_PERFCOUNTER13_HI_BASE_IDX 1 5600 #define regSQ_PERFCOUNTER14_LO 0x31dc 5601 #define regSQ_PERFCOUNTER14_LO_BASE_IDX 1 5602 #define regSQ_PERFCOUNTER14_HI 0x31dd 5603 #define regSQ_PERFCOUNTER14_HI_BASE_IDX 1 5604 #define regSQ_PERFCOUNTER15_LO 0x31de 5605 #define regSQ_PERFCOUNTER15_LO_BASE_IDX 1 5606 #define regSQ_PERFCOUNTER15_HI 0x31df 5607 #define regSQ_PERFCOUNTER15_HI_BASE_IDX 1 5608 #define regSX_PERFCOUNTER0_LO 0x3240 5609 #define regSX_PERFCOUNTER0_LO_BASE_IDX 1 5610 #define regSX_PERFCOUNTER0_HI 0x3241 5611 #define regSX_PERFCOUNTER0_HI_BASE_IDX 1 5612 #define regSX_PERFCOUNTER1_LO 0x3242 5613 #define regSX_PERFCOUNTER1_LO_BASE_IDX 1 5614 #define regSX_PERFCOUNTER1_HI 0x3243 5615 #define regSX_PERFCOUNTER1_HI_BASE_IDX 1 5616 #define regSX_PERFCOUNTER2_LO 0x3244 5617 #define regSX_PERFCOUNTER2_LO_BASE_IDX 1 5618 #define regSX_PERFCOUNTER2_HI 0x3245 5619 #define regSX_PERFCOUNTER2_HI_BASE_IDX 1 5620 #define regSX_PERFCOUNTER3_LO 0x3246 5621 #define regSX_PERFCOUNTER3_LO_BASE_IDX 1 5622 #define regSX_PERFCOUNTER3_HI 0x3247 5623 #define regSX_PERFCOUNTER3_HI_BASE_IDX 1 5624 #define regGDS_PERFCOUNTER0_LO 0x3280 5625 #define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 5626 #define regGDS_PERFCOUNTER0_HI 0x3281 5627 #define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 5628 #define regGDS_PERFCOUNTER1_LO 0x3282 5629 #define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 5630 #define regGDS_PERFCOUNTER1_HI 0x3283 5631 #define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 5632 #define regGDS_PERFCOUNTER2_LO 0x3284 5633 #define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 5634 #define regGDS_PERFCOUNTER2_HI 0x3285 5635 #define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 5636 #define regGDS_PERFCOUNTER3_LO 0x3286 5637 #define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 5638 #define regGDS_PERFCOUNTER3_HI 0x3287 5639 #define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 5640 #define regTA_PERFCOUNTER0_LO 0x32c0 5641 #define regTA_PERFCOUNTER0_LO_BASE_IDX 1 5642 #define regTA_PERFCOUNTER0_HI 0x32c1 5643 #define regTA_PERFCOUNTER0_HI_BASE_IDX 1 5644 #define regTA_PERFCOUNTER1_LO 0x32c2 5645 #define regTA_PERFCOUNTER1_LO_BASE_IDX 1 5646 #define regTA_PERFCOUNTER1_HI 0x32c3 5647 #define regTA_PERFCOUNTER1_HI_BASE_IDX 1 5648 #define regTD_PERFCOUNTER0_LO 0x3300 5649 #define regTD_PERFCOUNTER0_LO_BASE_IDX 1 5650 #define regTD_PERFCOUNTER0_HI 0x3301 5651 #define regTD_PERFCOUNTER0_HI_BASE_IDX 1 5652 #define regTD_PERFCOUNTER1_LO 0x3302 5653 #define regTD_PERFCOUNTER1_LO_BASE_IDX 1 5654 #define regTD_PERFCOUNTER1_HI 0x3303 5655 #define regTD_PERFCOUNTER1_HI_BASE_IDX 1 5656 #define regTCP_PERFCOUNTER0_LO 0x3340 5657 #define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 5658 #define regTCP_PERFCOUNTER0_HI 0x3341 5659 #define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 5660 #define regTCP_PERFCOUNTER1_LO 0x3342 5661 #define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 5662 #define regTCP_PERFCOUNTER1_HI 0x3343 5663 #define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 5664 #define regTCP_PERFCOUNTER2_LO 0x3344 5665 #define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 5666 #define regTCP_PERFCOUNTER2_HI 0x3345 5667 #define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 5668 #define regTCP_PERFCOUNTER3_LO 0x3346 5669 #define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 5670 #define regTCP_PERFCOUNTER3_HI 0x3347 5671 #define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 5672 #define regTCC_PERFCOUNTER0_LO 0x3380 5673 #define regTCC_PERFCOUNTER0_LO_BASE_IDX 1 5674 #define regTCC_PERFCOUNTER0_HI 0x3381 5675 #define regTCC_PERFCOUNTER0_HI_BASE_IDX 1 5676 #define regTCC_PERFCOUNTER1_LO 0x3382 5677 #define regTCC_PERFCOUNTER1_LO_BASE_IDX 1 5678 #define regTCC_PERFCOUNTER1_HI 0x3383 5679 #define regTCC_PERFCOUNTER1_HI_BASE_IDX 1 5680 #define regTCC_PERFCOUNTER2_LO 0x3384 5681 #define regTCC_PERFCOUNTER2_LO_BASE_IDX 1 5682 #define regTCC_PERFCOUNTER2_HI 0x3385 5683 #define regTCC_PERFCOUNTER2_HI_BASE_IDX 1 5684 #define regTCC_PERFCOUNTER3_LO 0x3386 5685 #define regTCC_PERFCOUNTER3_LO_BASE_IDX 1 5686 #define regTCC_PERFCOUNTER3_HI 0x3387 5687 #define regTCC_PERFCOUNTER3_HI_BASE_IDX 1 5688 #define regTCA_PERFCOUNTER0_LO 0x3390 5689 #define regTCA_PERFCOUNTER0_LO_BASE_IDX 1 5690 #define regTCA_PERFCOUNTER0_HI 0x3391 5691 #define regTCA_PERFCOUNTER0_HI_BASE_IDX 1 5692 #define regTCA_PERFCOUNTER1_LO 0x3392 5693 #define regTCA_PERFCOUNTER1_LO_BASE_IDX 1 5694 #define regTCA_PERFCOUNTER1_HI 0x3393 5695 #define regTCA_PERFCOUNTER1_HI_BASE_IDX 1 5696 #define regTCA_PERFCOUNTER2_LO 0x3394 5697 #define regTCA_PERFCOUNTER2_LO_BASE_IDX 1 5698 #define regTCA_PERFCOUNTER2_HI 0x3395 5699 #define regTCA_PERFCOUNTER2_HI_BASE_IDX 1 5700 #define regTCA_PERFCOUNTER3_LO 0x3396 5701 #define regTCA_PERFCOUNTER3_LO_BASE_IDX 1 5702 #define regTCA_PERFCOUNTER3_HI 0x3397 5703 #define regTCA_PERFCOUNTER3_HI_BASE_IDX 1 5704 #define regCB_PERFCOUNTER0_LO 0x3406 5705 #define regCB_PERFCOUNTER0_LO_BASE_IDX 1 5706 #define regCB_PERFCOUNTER0_HI 0x3407 5707 #define regCB_PERFCOUNTER0_HI_BASE_IDX 1 5708 #define regCB_PERFCOUNTER1_LO 0x3408 5709 #define regCB_PERFCOUNTER1_LO_BASE_IDX 1 5710 #define regCB_PERFCOUNTER1_HI 0x3409 5711 #define regCB_PERFCOUNTER1_HI_BASE_IDX 1 5712 #define regCB_PERFCOUNTER2_LO 0x340a 5713 #define regCB_PERFCOUNTER2_LO_BASE_IDX 1 5714 #define regCB_PERFCOUNTER2_HI 0x340b 5715 #define regCB_PERFCOUNTER2_HI_BASE_IDX 1 5716 #define regCB_PERFCOUNTER3_LO 0x340c 5717 #define regCB_PERFCOUNTER3_LO_BASE_IDX 1 5718 #define regCB_PERFCOUNTER3_HI 0x340d 5719 #define regCB_PERFCOUNTER3_HI_BASE_IDX 1 5720 #define regDB_PERFCOUNTER0_LO 0x3440 5721 #define regDB_PERFCOUNTER0_LO_BASE_IDX 1 5722 #define regDB_PERFCOUNTER0_HI 0x3441 5723 #define regDB_PERFCOUNTER0_HI_BASE_IDX 1 5724 #define regDB_PERFCOUNTER1_LO 0x3442 5725 #define regDB_PERFCOUNTER1_LO_BASE_IDX 1 5726 #define regDB_PERFCOUNTER1_HI 0x3443 5727 #define regDB_PERFCOUNTER1_HI_BASE_IDX 1 5728 #define regDB_PERFCOUNTER2_LO 0x3444 5729 #define regDB_PERFCOUNTER2_LO_BASE_IDX 1 5730 #define regDB_PERFCOUNTER2_HI 0x3445 5731 #define regDB_PERFCOUNTER2_HI_BASE_IDX 1 5732 #define regDB_PERFCOUNTER3_LO 0x3446 5733 #define regDB_PERFCOUNTER3_LO_BASE_IDX 1 5734 #define regDB_PERFCOUNTER3_HI 0x3447 5735 #define regDB_PERFCOUNTER3_HI_BASE_IDX 1 5736 #define regRLC_PERFCOUNTER0_LO 0x3480 5737 #define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 5738 #define regRLC_PERFCOUNTER0_HI 0x3481 5739 #define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 5740 #define regRLC_PERFCOUNTER1_LO 0x3482 5741 #define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 5742 #define regRLC_PERFCOUNTER1_HI 0x3483 5743 #define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 5744 #define regRMI_PERFCOUNTER0_LO 0x34c0 5745 #define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 5746 #define regRMI_PERFCOUNTER0_HI 0x34c1 5747 #define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 5748 #define regRMI_PERFCOUNTER1_LO 0x34c2 5749 #define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 5750 #define regRMI_PERFCOUNTER1_HI 0x34c3 5751 #define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 5752 #define regRMI_PERFCOUNTER2_LO 0x34c4 5753 #define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 5754 #define regRMI_PERFCOUNTER2_HI 0x34c5 5755 #define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 5756 #define regRMI_PERFCOUNTER3_LO 0x34c6 5757 #define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 5758 #define regRMI_PERFCOUNTER3_HI 0x34c7 5759 #define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 5760 5761 5762 // addressBlock: xcd0_gc_utcl2_atcl2pfcntrdec 5763 // base address: 0x35400 5764 #define regATC_L2_PERFCOUNTER_LO 0x3500 5765 #define regATC_L2_PERFCOUNTER_LO_BASE_IDX 1 5766 #define regATC_L2_PERFCOUNTER_HI 0x3501 5767 #define regATC_L2_PERFCOUNTER_HI_BASE_IDX 1 5768 5769 5770 // addressBlock: xcd0_gc_utcl2_vml2prdec 5771 // base address: 0x35408 5772 #define regMC_VM_L2_PERFCOUNTER_LO 0x3502 5773 #define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 5774 #define regMC_VM_L2_PERFCOUNTER_HI 0x3503 5775 #define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 5776 5777 5778 // addressBlock: xcd0_gc_utcl2_l2tlbprdec 5779 // base address: 0x35448 5780 #define regL2TLB_PERFCOUNTER_LO 0x3512 5781 #define regL2TLB_PERFCOUNTER_LO_BASE_IDX 1 5782 #define regL2TLB_PERFCOUNTER_HI 0x3513 5783 #define regL2TLB_PERFCOUNTER_HI_BASE_IDX 1 5784 5785 5786 // addressBlock: xcd0_gc_perfsdec 5787 // base address: 0x36000 5788 #define regCPG_PERFCOUNTER1_SELECT 0x3800 5789 #define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 5790 #define regCPG_PERFCOUNTER0_SELECT1 0x3801 5791 #define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 5792 #define regCPG_PERFCOUNTER0_SELECT 0x3802 5793 #define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 5794 #define regCPC_PERFCOUNTER1_SELECT 0x3803 5795 #define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 5796 #define regCPC_PERFCOUNTER0_SELECT1 0x3804 5797 #define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5798 #define regCPF_PERFCOUNTER1_SELECT 0x3805 5799 #define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 5800 #define regCPF_PERFCOUNTER0_SELECT1 0x3806 5801 #define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 5802 #define regCPF_PERFCOUNTER0_SELECT 0x3807 5803 #define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 5804 #define regCP_PERFMON_CNTL 0x3808 5805 #define regCP_PERFMON_CNTL_BASE_IDX 1 5806 #define regCPC_PERFCOUNTER0_SELECT 0x3809 5807 #define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 5808 #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a 5809 #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5810 #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b 5811 #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5812 #define regCPF_LATENCY_STATS_SELECT 0x380c 5813 #define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 5814 #define regCPG_LATENCY_STATS_SELECT 0x380d 5815 #define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 5816 #define regCPC_LATENCY_STATS_SELECT 0x380e 5817 #define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 5818 #define regCP_DRAW_OBJECT 0x3810 5819 #define regCP_DRAW_OBJECT_BASE_IDX 1 5820 #define regCP_DRAW_OBJECT_COUNTER 0x3811 5821 #define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 5822 #define regCP_DRAW_WINDOW_MASK_HI 0x3812 5823 #define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 5824 #define regCP_DRAW_WINDOW_HI 0x3813 5825 #define regCP_DRAW_WINDOW_HI_BASE_IDX 1 5826 #define regCP_DRAW_WINDOW_LO 0x3814 5827 #define regCP_DRAW_WINDOW_LO_BASE_IDX 1 5828 #define regCP_DRAW_WINDOW_CNTL 0x3815 5829 #define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 5830 #define regGRBM_PERFCOUNTER0_SELECT 0x3840 5831 #define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 5832 #define regGRBM_PERFCOUNTER1_SELECT 0x3841 5833 #define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 5834 #define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 5835 #define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 5836 #define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 5837 #define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 5838 #define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 5839 #define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 5840 #define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 5841 #define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 5842 #define regWD_PERFCOUNTER0_SELECT 0x3880 5843 #define regWD_PERFCOUNTER0_SELECT_BASE_IDX 1 5844 #define regWD_PERFCOUNTER1_SELECT 0x3881 5845 #define regWD_PERFCOUNTER1_SELECT_BASE_IDX 1 5846 #define regWD_PERFCOUNTER2_SELECT 0x3882 5847 #define regWD_PERFCOUNTER2_SELECT_BASE_IDX 1 5848 #define regWD_PERFCOUNTER3_SELECT 0x3883 5849 #define regWD_PERFCOUNTER3_SELECT_BASE_IDX 1 5850 #define regIA_PERFCOUNTER0_SELECT 0x3884 5851 #define regIA_PERFCOUNTER0_SELECT_BASE_IDX 1 5852 #define regIA_PERFCOUNTER1_SELECT 0x3885 5853 #define regIA_PERFCOUNTER1_SELECT_BASE_IDX 1 5854 #define regIA_PERFCOUNTER2_SELECT 0x3886 5855 #define regIA_PERFCOUNTER2_SELECT_BASE_IDX 1 5856 #define regIA_PERFCOUNTER3_SELECT 0x3887 5857 #define regIA_PERFCOUNTER3_SELECT_BASE_IDX 1 5858 #define regIA_PERFCOUNTER0_SELECT1 0x3888 5859 #define regIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5860 #define regVGT_PERFCOUNTER0_SELECT 0x388c 5861 #define regVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 5862 #define regVGT_PERFCOUNTER1_SELECT 0x388d 5863 #define regVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 5864 #define regVGT_PERFCOUNTER2_SELECT 0x388e 5865 #define regVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 5866 #define regVGT_PERFCOUNTER3_SELECT 0x388f 5867 #define regVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 5868 #define regVGT_PERFCOUNTER0_SELECT1 0x3890 5869 #define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 5870 #define regVGT_PERFCOUNTER1_SELECT1 0x3891 5871 #define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 5872 #define regVGT_PERFCOUNTER_SEID_MASK 0x3894 5873 #define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 5874 #define regPA_SU_PERFCOUNTER0_SELECT 0x3900 5875 #define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 5876 #define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 5877 #define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 5878 #define regPA_SU_PERFCOUNTER1_SELECT 0x3902 5879 #define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 5880 #define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 5881 #define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 5882 #define regPA_SU_PERFCOUNTER2_SELECT 0x3904 5883 #define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 5884 #define regPA_SU_PERFCOUNTER3_SELECT 0x3905 5885 #define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 5886 #define regPA_SC_PERFCOUNTER0_SELECT 0x3940 5887 #define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 5888 #define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 5889 #define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5890 #define regPA_SC_PERFCOUNTER1_SELECT 0x3942 5891 #define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 5892 #define regPA_SC_PERFCOUNTER2_SELECT 0x3943 5893 #define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 5894 #define regPA_SC_PERFCOUNTER3_SELECT 0x3944 5895 #define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 5896 #define regPA_SC_PERFCOUNTER4_SELECT 0x3945 5897 #define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 5898 #define regPA_SC_PERFCOUNTER5_SELECT 0x3946 5899 #define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 5900 #define regPA_SC_PERFCOUNTER6_SELECT 0x3947 5901 #define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 5902 #define regPA_SC_PERFCOUNTER7_SELECT 0x3948 5903 #define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 5904 #define regSPI_PERFCOUNTER0_SELECT 0x3980 5905 #define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 5906 #define regSPI_PERFCOUNTER1_SELECT 0x3981 5907 #define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 5908 #define regSPI_PERFCOUNTER2_SELECT 0x3982 5909 #define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 5910 #define regSPI_PERFCOUNTER3_SELECT 0x3983 5911 #define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 5912 #define regSPI_PERFCOUNTER0_SELECT1 0x3984 5913 #define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 5914 #define regSPI_PERFCOUNTER1_SELECT1 0x3985 5915 #define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 5916 #define regSPI_PERFCOUNTER2_SELECT1 0x3986 5917 #define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 5918 #define regSPI_PERFCOUNTER3_SELECT1 0x3987 5919 #define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 5920 #define regSPI_PERFCOUNTER4_SELECT 0x3988 5921 #define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 5922 #define regSPI_PERFCOUNTER5_SELECT 0x3989 5923 #define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 5924 #define regSPI_PERFCOUNTER_BINS 0x398a 5925 #define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 5926 #define regSQ_PERFCOUNTER0_SELECT 0x39c0 5927 #define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 5928 #define regSQ_PERFCOUNTER1_SELECT 0x39c1 5929 #define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 5930 #define regSQ_PERFCOUNTER2_SELECT 0x39c2 5931 #define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 5932 #define regSQ_PERFCOUNTER3_SELECT 0x39c3 5933 #define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 5934 #define regSQ_PERFCOUNTER4_SELECT 0x39c4 5935 #define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 5936 #define regSQ_PERFCOUNTER5_SELECT 0x39c5 5937 #define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 5938 #define regSQ_PERFCOUNTER6_SELECT 0x39c6 5939 #define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 5940 #define regSQ_PERFCOUNTER7_SELECT 0x39c7 5941 #define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 5942 #define regSQ_PERFCOUNTER8_SELECT 0x39c8 5943 #define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 5944 #define regSQ_PERFCOUNTER9_SELECT 0x39c9 5945 #define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 5946 #define regSQ_PERFCOUNTER10_SELECT 0x39ca 5947 #define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 5948 #define regSQ_PERFCOUNTER11_SELECT 0x39cb 5949 #define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 5950 #define regSQ_PERFCOUNTER12_SELECT 0x39cc 5951 #define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 5952 #define regSQ_PERFCOUNTER13_SELECT 0x39cd 5953 #define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 5954 #define regSQ_PERFCOUNTER14_SELECT 0x39ce 5955 #define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 5956 #define regSQ_PERFCOUNTER15_SELECT 0x39cf 5957 #define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 5958 #define regSQ_PERFCOUNTER_CTRL 0x39e0 5959 #define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 5960 #define regSQ_PERFCOUNTER_MASK 0x39e1 5961 #define regSQ_PERFCOUNTER_MASK_BASE_IDX 1 5962 #define regSQ_PERFCOUNTER_CTRL2 0x39e2 5963 #define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 5964 #define regSX_PERFCOUNTER0_SELECT 0x3a40 5965 #define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 5966 #define regSX_PERFCOUNTER1_SELECT 0x3a41 5967 #define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 5968 #define regSX_PERFCOUNTER2_SELECT 0x3a42 5969 #define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 5970 #define regSX_PERFCOUNTER3_SELECT 0x3a43 5971 #define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 5972 #define regSX_PERFCOUNTER0_SELECT1 0x3a44 5973 #define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 5974 #define regSX_PERFCOUNTER1_SELECT1 0x3a45 5975 #define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 5976 #define regGDS_PERFCOUNTER0_SELECT 0x3a80 5977 #define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 5978 #define regGDS_PERFCOUNTER1_SELECT 0x3a81 5979 #define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 5980 #define regGDS_PERFCOUNTER2_SELECT 0x3a82 5981 #define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 5982 #define regGDS_PERFCOUNTER3_SELECT 0x3a83 5983 #define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 5984 #define regGDS_PERFCOUNTER0_SELECT1 0x3a84 5985 #define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 5986 #define regTA_PERFCOUNTER0_SELECT 0x3ac0 5987 #define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 5988 #define regTA_PERFCOUNTER0_SELECT1 0x3ac1 5989 #define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5990 #define regTA_PERFCOUNTER1_SELECT 0x3ac2 5991 #define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 5992 #define regTD_PERFCOUNTER0_SELECT 0x3b00 5993 #define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 5994 #define regTD_PERFCOUNTER0_SELECT1 0x3b01 5995 #define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 5996 #define regTD_PERFCOUNTER1_SELECT 0x3b02 5997 #define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 5998 #define regTCP_PERFCOUNTER0_SELECT 0x3b40 5999 #define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 6000 #define regTCP_PERFCOUNTER0_SELECT1 0x3b41 6001 #define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 6002 #define regTCP_PERFCOUNTER1_SELECT 0x3b42 6003 #define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 6004 #define regTCP_PERFCOUNTER1_SELECT1 0x3b43 6005 #define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 6006 #define regTCP_PERFCOUNTER2_SELECT 0x3b44 6007 #define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 6008 #define regTCP_PERFCOUNTER3_SELECT 0x3b45 6009 #define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 6010 #define regTCC_PERFCOUNTER0_SELECT 0x3b80 6011 #define regTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 6012 #define regTCC_PERFCOUNTER0_SELECT1 0x3b81 6013 #define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 6014 #define regTCC_PERFCOUNTER1_SELECT 0x3b82 6015 #define regTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 6016 #define regTCC_PERFCOUNTER1_SELECT1 0x3b83 6017 #define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 6018 #define regTCC_PERFCOUNTER2_SELECT 0x3b84 6019 #define regTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 6020 #define regTCC_PERFCOUNTER3_SELECT 0x3b85 6021 #define regTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 6022 #define regTCA_PERFCOUNTER0_SELECT 0x3b90 6023 #define regTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 6024 #define regTCA_PERFCOUNTER0_SELECT1 0x3b91 6025 #define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 6026 #define regTCA_PERFCOUNTER1_SELECT 0x3b92 6027 #define regTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 6028 #define regTCA_PERFCOUNTER1_SELECT1 0x3b93 6029 #define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 6030 #define regTCA_PERFCOUNTER2_SELECT 0x3b94 6031 #define regTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 6032 #define regTCA_PERFCOUNTER3_SELECT 0x3b95 6033 #define regTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 6034 #define regCB_PERFCOUNTER_FILTER 0x3c00 6035 #define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 6036 #define regCB_PERFCOUNTER0_SELECT 0x3c01 6037 #define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 6038 #define regCB_PERFCOUNTER0_SELECT1 0x3c02 6039 #define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 6040 #define regCB_PERFCOUNTER1_SELECT 0x3c03 6041 #define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 6042 #define regCB_PERFCOUNTER2_SELECT 0x3c04 6043 #define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 6044 #define regCB_PERFCOUNTER3_SELECT 0x3c05 6045 #define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 6046 #define regDB_PERFCOUNTER0_SELECT 0x3c40 6047 #define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 6048 #define regDB_PERFCOUNTER0_SELECT1 0x3c41 6049 #define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 6050 #define regDB_PERFCOUNTER1_SELECT 0x3c42 6051 #define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 6052 #define regDB_PERFCOUNTER1_SELECT1 0x3c43 6053 #define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 6054 #define regDB_PERFCOUNTER2_SELECT 0x3c44 6055 #define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 6056 #define regDB_PERFCOUNTER3_SELECT 0x3c46 6057 #define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 6058 #define regRLC_SPM_PERFMON_CNTL 0x3c80 6059 #define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 6060 #define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 6061 #define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 6062 #define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 6063 #define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 6064 #define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 6065 #define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 6066 #define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 6067 #define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 6068 #define regRLC_SPM_SE_MUXSEL_ADDR 0x3c85 6069 #define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 6070 #define regRLC_SPM_SE_MUXSEL_DATA 0x3c86 6071 #define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 6072 #define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 6073 #define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6074 #define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 6075 #define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6076 #define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 6077 #define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6078 #define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a 6079 #define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6080 #define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b 6081 #define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6082 #define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c 6083 #define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6084 #define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d 6085 #define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6086 #define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e 6087 #define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6088 #define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 6089 #define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6090 #define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 6091 #define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6092 #define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 6093 #define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6094 #define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 6095 #define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6096 #define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 6097 #define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6098 #define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 6099 #define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6100 #define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 6101 #define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6102 #define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 6103 #define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6104 #define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 6105 #define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6106 #define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a 6107 #define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6108 #define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b 6109 #define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 6110 #define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c 6111 #define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 6112 #define regRLC_SPM_RING_RDPTR 0x3c9d 6113 #define regRLC_SPM_RING_RDPTR_BASE_IDX 1 6114 #define regRLC_SPM_SEGMENT_THRESHOLD 0x3c9e 6115 #define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 6116 #define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 6117 #define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6118 #define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4 6119 #define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 6120 #define regRLC_PERFMON_CNTL 0x3cc0 6121 #define regRLC_PERFMON_CNTL_BASE_IDX 1 6122 #define regRLC_PERFCOUNTER0_SELECT 0x3cc1 6123 #define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 6124 #define regRLC_PERFCOUNTER1_SELECT 0x3cc2 6125 #define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 6126 #define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 6127 #define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 6128 #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 6129 #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 6130 #define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 6131 #define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 6132 #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 6133 #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 6134 #define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 6135 #define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 6136 #define regRMI_PERFCOUNTER0_SELECT 0x3d00 6137 #define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 6138 #define regRMI_PERFCOUNTER0_SELECT1 0x3d01 6139 #define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 6140 #define regRMI_PERFCOUNTER1_SELECT 0x3d02 6141 #define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 6142 #define regRMI_PERFCOUNTER2_SELECT 0x3d03 6143 #define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 6144 #define regRMI_PERFCOUNTER2_SELECT1 0x3d04 6145 #define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 6146 #define regRMI_PERFCOUNTER3_SELECT 0x3d05 6147 #define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 6148 #define regRMI_PERF_COUNTER_CNTL 0x3d06 6149 #define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 6150 6151 6152 // addressBlock: xcd0_gc_utcl2_atcl2pfcntldec 6153 // base address: 0x37500 6154 #define regATC_L2_PERFCOUNTER0_CFG 0x3d40 6155 #define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6156 #define regATC_L2_PERFCOUNTER1_CFG 0x3d41 6157 #define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6158 #define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 6159 #define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6160 6161 6162 // addressBlock: xcd0_gc_utcl2_vml2pldec 6163 // base address: 0x37518 6164 #define regMC_VM_L2_PERFCOUNTER0_CFG 0x3d46 6165 #define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6166 #define regMC_VM_L2_PERFCOUNTER1_CFG 0x3d47 6167 #define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6168 #define regMC_VM_L2_PERFCOUNTER2_CFG 0x3d48 6169 #define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 6170 #define regMC_VM_L2_PERFCOUNTER3_CFG 0x3d49 6171 #define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 6172 #define regMC_VM_L2_PERFCOUNTER4_CFG 0x3d4a 6173 #define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 6174 #define regMC_VM_L2_PERFCOUNTER5_CFG 0x3d4b 6175 #define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 6176 #define regMC_VM_L2_PERFCOUNTER6_CFG 0x3d4c 6177 #define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 6178 #define regMC_VM_L2_PERFCOUNTER7_CFG 0x3d4d 6179 #define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 6180 #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d56 6181 #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6182 6183 6184 // addressBlock: xcd0_gc_utcl2_l2tlbpldec 6185 // base address: 0x37578 6186 #define regL2TLB_PERFCOUNTER0_CFG 0x3d5e 6187 #define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 6188 #define regL2TLB_PERFCOUNTER1_CFG 0x3d5f 6189 #define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 6190 #define regL2TLB_PERFCOUNTER2_CFG 0x3d60 6191 #define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 6192 #define regL2TLB_PERFCOUNTER3_CFG 0x3d61 6193 #define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 6194 #define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x3d62 6195 #define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6196 6197 6198 // addressBlock: xcd0_gc_gdflldec 6199 // base address: 0x3a000 6200 #define regGDFLL_EDC_HYSTERESIS_CNTL 0x481b 6201 #define regGDFLL_EDC_HYSTERESIS_CNTL_BASE_IDX 1 6202 #define regGDFLL_EDC_HYSTERESIS_STAT 0x481c 6203 #define regGDFLL_EDC_HYSTERESIS_STAT_BASE_IDX 1 6204 6205 6206 // addressBlock: xcd0_gc_rlcpdec 6207 // base address: 0x3b000 6208 #define regRLC_CNTL 0x4c00 6209 #define regRLC_CNTL_BASE_IDX 1 6210 #define regRLC_CGCG_CGLS_CTRL_2 0x4c03 6211 #define regRLC_CGCG_CGLS_CTRL_2_BASE_IDX 1 6212 #define regRLC_STAT 0x4c04 6213 #define regRLC_STAT_BASE_IDX 1 6214 #define regRLC_SAFE_MODE 0x4c05 6215 #define regRLC_SAFE_MODE_BASE_IDX 1 6216 #define regRLC_MEM_SLP_CNTL 0x4c06 6217 #define regRLC_MEM_SLP_CNTL_BASE_IDX 1 6218 #define regSMU_RLC_RESPONSE 0x4c07 6219 #define regSMU_RLC_RESPONSE_BASE_IDX 1 6220 #define regRLC_RLCV_SAFE_MODE 0x4c08 6221 #define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 6222 #define regRLC_SMU_SAFE_MODE 0x4c09 6223 #define regRLC_SMU_SAFE_MODE_BASE_IDX 1 6224 #define regRLC_RLCV_COMMAND 0x4c0a 6225 #define regRLC_RLCV_COMMAND_BASE_IDX 1 6226 #define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c 6227 #define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 6228 #define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d 6229 #define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 6230 #define regRLC_GPM_TIMER_INT_0 0x4c0e 6231 #define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 6232 #define regRLC_GPM_TIMER_INT_1 0x4c0f 6233 #define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 6234 #define regRLC_GPM_TIMER_INT_2 0x4c10 6235 #define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 6236 #define regRLC_GPM_TIMER_CTRL 0x4c11 6237 #define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 6238 #define regRLC_LB_CNTR_MAX 0x4c12 6239 #define regRLC_LB_CNTR_MAX_BASE_IDX 1 6240 #define regRLC_GPM_TIMER_STAT 0x4c13 6241 #define regRLC_GPM_TIMER_STAT_BASE_IDX 1 6242 #define regRLC_GPM_TIMER_INT_3 0x4c15 6243 #define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 6244 #define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 6245 #define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 6246 #define regRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 6247 #define regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 6248 #define regRLC_INT_STAT 0x4c18 6249 #define regRLC_INT_STAT_BASE_IDX 1 6250 #define regRLC_LB_CNTL 0x4c19 6251 #define regRLC_LB_CNTL_BASE_IDX 1 6252 #define regRLC_MGCG_CTRL 0x4c1a 6253 #define regRLC_MGCG_CTRL_BASE_IDX 1 6254 #define regRLC_LB_CNTR_INIT 0x4c1b 6255 #define regRLC_LB_CNTR_INIT_BASE_IDX 1 6256 #define regRLC_LOAD_BALANCE_CNTR 0x4c1c 6257 #define regRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 6258 #define regRLC_JUMP_TABLE_RESTORE 0x4c1e 6259 #define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 6260 #define regRLC_PG_DELAY_2 0x4c1f 6261 #define regRLC_PG_DELAY_2_BASE_IDX 1 6262 #define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 6263 #define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 6264 #define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 6265 #define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 6266 #define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 6267 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 6268 #define regRLC_UCODE_CNTL 0x4c27 6269 #define regRLC_UCODE_CNTL_BASE_IDX 1 6270 #define regRLC_GPM_THREAD_RESET 0x4c28 6271 #define regRLC_GPM_THREAD_RESET_BASE_IDX 1 6272 #define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 6273 #define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 6274 #define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a 6275 #define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 6276 #define regRLC_FIREWALL_VIOLATION 0x4c2b 6277 #define regRLC_FIREWALL_VIOLATION_BASE_IDX 1 6278 #define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 6279 #define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 6280 #define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 6281 #define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 6282 #define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 6283 #define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 6284 #define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 6285 #define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 6286 #define regRLC_CLK_COUNT_CTRL 0x4c34 6287 #define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 6288 #define regRLC_CLK_COUNT_STAT 0x4c35 6289 #define regRLC_CLK_COUNT_STAT_BASE_IDX 1 6290 #define regRLC_GPM_STAT 0x4c40 6291 #define regRLC_GPM_STAT_BASE_IDX 1 6292 #define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 6293 #define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 6294 #define regRLC_GPU_CLOCK_32 0x4c42 6295 #define regRLC_GPU_CLOCK_32_BASE_IDX 1 6296 #define regRLC_PG_CNTL 0x4c43 6297 #define regRLC_PG_CNTL_BASE_IDX 1 6298 #define regRLC_GPM_THREAD_PRIORITY 0x4c44 6299 #define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 6300 #define regRLC_GPM_THREAD_ENABLE 0x4c45 6301 #define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 6302 #define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 6303 #define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 6304 #define regRLC_CGCG_CGLS_CTRL 0x4c49 6305 #define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 6306 #define regRLC_CGCG_RAMP_CTRL 0x4c4a 6307 #define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 6308 #define regRLC_DYN_PG_STATUS 0x4c4b 6309 #define regRLC_DYN_PG_STATUS_BASE_IDX 1 6310 #define regRLC_DYN_PG_REQUEST 0x4c4c 6311 #define regRLC_DYN_PG_REQUEST_BASE_IDX 1 6312 #define regRLC_PG_DELAY 0x4c4d 6313 #define regRLC_PG_DELAY_BASE_IDX 1 6314 #define regRLC_CU_STATUS 0x4c4e 6315 #define regRLC_CU_STATUS_BASE_IDX 1 6316 #define regRLC_LB_INIT_CU_MASK 0x4c4f 6317 #define regRLC_LB_INIT_CU_MASK_BASE_IDX 1 6318 #define regRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 6319 #define regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 6320 #define regRLC_LB_PARAMS 0x4c51 6321 #define regRLC_LB_PARAMS_BASE_IDX 1 6322 #define regRLC_THREAD1_DELAY 0x4c52 6323 #define regRLC_THREAD1_DELAY_BASE_IDX 1 6324 #define regRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 6325 #define regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 6326 #define regRLC_MAX_PG_CU 0x4c54 6327 #define regRLC_MAX_PG_CU_BASE_IDX 1 6328 #define regRLC_AUTO_PG_CTRL 0x4c55 6329 #define regRLC_AUTO_PG_CTRL_BASE_IDX 1 6330 #define regRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 6331 #define regRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 6332 #define regRLC_SERDES_RD_PENDING 0x4c58 6333 #define regRLC_SERDES_RD_PENDING_BASE_IDX 1 6334 #define regRLC_SERDES_RD_MASTER_INDEX 0x4c59 6335 #define regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 6336 #define regRLC_SERDES_RD_DATA_0 0x4c5a 6337 #define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 6338 #define regRLC_SERDES_RD_DATA_1 0x4c5b 6339 #define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 6340 #define regRLC_SERDES_RD_DATA_2 0x4c5c 6341 #define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 6342 #define regRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d 6343 #define regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 6344 #define regRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e 6345 #define regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 6346 #define regRLC_SERDES_WR_CTRL 0x4c5f 6347 #define regRLC_SERDES_WR_CTRL_BASE_IDX 1 6348 #define regRLC_SERDES_WR_DATA 0x4c60 6349 #define regRLC_SERDES_WR_DATA_BASE_IDX 1 6350 #define regRLC_SERDES_CU_MASTER_BUSY 0x4c61 6351 #define regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 6352 #define regRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 6353 #define regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 6354 #define regRLC_GPM_GENERAL_0 0x4c63 6355 #define regRLC_GPM_GENERAL_0_BASE_IDX 1 6356 #define regRLC_GPM_GENERAL_1 0x4c64 6357 #define regRLC_GPM_GENERAL_1_BASE_IDX 1 6358 #define regRLC_GPM_GENERAL_2 0x4c65 6359 #define regRLC_GPM_GENERAL_2_BASE_IDX 1 6360 #define regRLC_GPM_GENERAL_3 0x4c66 6361 #define regRLC_GPM_GENERAL_3_BASE_IDX 1 6362 #define regRLC_GPM_GENERAL_4 0x4c67 6363 #define regRLC_GPM_GENERAL_4_BASE_IDX 1 6364 #define regRLC_GPM_GENERAL_5 0x4c68 6365 #define regRLC_GPM_GENERAL_5_BASE_IDX 1 6366 #define regRLC_GPM_GENERAL_6 0x4c69 6367 #define regRLC_GPM_GENERAL_6_BASE_IDX 1 6368 #define regRLC_GPM_GENERAL_7 0x4c6a 6369 #define regRLC_GPM_GENERAL_7_BASE_IDX 1 6370 #define regRLC_GPM_SCRATCH_ADDR 0x4c6c 6371 #define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 6372 #define regRLC_GPM_SCRATCH_DATA 0x4c6d 6373 #define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 6374 #define regRLC_STATIC_PG_STATUS 0x4c6e 6375 #define regRLC_STATIC_PG_STATUS_BASE_IDX 1 6376 #define regRLC_SPM_MC_CNTL 0x4c71 6377 #define regRLC_SPM_MC_CNTL_BASE_IDX 1 6378 #define regRLC_SPM_INT_CNTL 0x4c72 6379 #define regRLC_SPM_INT_CNTL_BASE_IDX 1 6380 #define regRLC_SPM_INT_STATUS 0x4c73 6381 #define regRLC_SPM_INT_STATUS_BASE_IDX 1 6382 #define regRLC_SMU_MESSAGE 0x4c76 6383 #define regRLC_SMU_MESSAGE_BASE_IDX 1 6384 #define regRLC_GPM_LOG_SIZE 0x4c77 6385 #define regRLC_GPM_LOG_SIZE_BASE_IDX 1 6386 #define regRLC_PG_DELAY_3 0x4c78 6387 #define regRLC_PG_DELAY_3_BASE_IDX 1 6388 #define regRLC_GPR_REG1 0x4c79 6389 #define regRLC_GPR_REG1_BASE_IDX 1 6390 #define regRLC_GPR_REG2 0x4c7a 6391 #define regRLC_GPR_REG2_BASE_IDX 1 6392 #define regRLC_GPM_LOG_CONT 0x4c7b 6393 #define regRLC_GPM_LOG_CONT_BASE_IDX 1 6394 #define regRLC_GPM_INT_DISABLE_TH0 0x4c7c 6395 #define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 6396 #define regRLC_GPM_INT_FORCE_TH0 0x4c7e 6397 #define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 6398 #define regRLC_GPM_INT_FORCE_TH1 0x4c7f 6399 #define regRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 6400 #define regRLC_SRM_CNTL 0x4c80 6401 #define regRLC_SRM_CNTL_BASE_IDX 1 6402 #define regRLC_SRM_ARAM_ADDR 0x4c83 6403 #define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 6404 #define regRLC_SRM_ARAM_DATA 0x4c84 6405 #define regRLC_SRM_ARAM_DATA_BASE_IDX 1 6406 #define regRLC_SRM_DRAM_ADDR 0x4c85 6407 #define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 6408 #define regRLC_SRM_DRAM_DATA 0x4c86 6409 #define regRLC_SRM_DRAM_DATA_BASE_IDX 1 6410 #define regRLC_SRM_GPM_COMMAND 0x4c87 6411 #define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 6412 #define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 6413 #define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 6414 #define regRLC_SRM_RLCV_COMMAND 0x4c89 6415 #define regRLC_SRM_RLCV_COMMAND_BASE_IDX 1 6416 #define regRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a 6417 #define regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 6418 #define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b 6419 #define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 6420 #define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c 6421 #define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 6422 #define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d 6423 #define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 6424 #define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e 6425 #define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 6426 #define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f 6427 #define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 6428 #define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 6429 #define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 6430 #define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 6431 #define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 6432 #define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 6433 #define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 6434 #define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 6435 #define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 6436 #define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 6437 #define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 6438 #define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 6439 #define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 6440 #define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 6441 #define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 6442 #define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 6443 #define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 6444 #define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 6445 #define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 6446 #define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 6447 #define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 6448 #define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a 6449 #define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 6450 #define regRLC_SRM_STAT 0x4c9b 6451 #define regRLC_SRM_STAT_BASE_IDX 1 6452 #define regRLC_SRM_GPM_ABORT 0x4c9c 6453 #define regRLC_SRM_GPM_ABORT_BASE_IDX 1 6454 #define regRLC_CSIB_ADDR_LO 0x4ca2 6455 #define regRLC_CSIB_ADDR_LO_BASE_IDX 1 6456 #define regRLC_CSIB_ADDR_HI 0x4ca3 6457 #define regRLC_CSIB_ADDR_HI_BASE_IDX 1 6458 #define regRLC_CSIB_LENGTH 0x4ca4 6459 #define regRLC_CSIB_LENGTH_BASE_IDX 1 6460 #define regRLC_SMU_COMMAND 0x4ca9 6461 #define regRLC_SMU_COMMAND_BASE_IDX 1 6462 #define regRLC_CP_SCHEDULERS 0x4caa 6463 #define regRLC_CP_SCHEDULERS_BASE_IDX 1 6464 #define regRLC_SMU_ARGUMENT_1 0x4cab 6465 #define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 6466 #define regRLC_SMU_ARGUMENT_2 0x4cac 6467 #define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 6468 #define regRLC_GPM_GENERAL_8 0x4cad 6469 #define regRLC_GPM_GENERAL_8_BASE_IDX 1 6470 #define regRLC_GPM_GENERAL_9 0x4cae 6471 #define regRLC_GPM_GENERAL_9_BASE_IDX 1 6472 #define regRLC_GPM_GENERAL_10 0x4caf 6473 #define regRLC_GPM_GENERAL_10_BASE_IDX 1 6474 #define regRLC_GPM_GENERAL_11 0x4cb0 6475 #define regRLC_GPM_GENERAL_11_BASE_IDX 1 6476 #define regRLC_GPM_GENERAL_12 0x4cb1 6477 #define regRLC_GPM_GENERAL_12_BASE_IDX 1 6478 #define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 6479 #define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 6480 #define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 6481 #define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 6482 #define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 6483 #define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 6484 #define regRLC_SPM_UTCL1_CNTL 0x4cb5 6485 #define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 6486 #define regRLC_UTCL1_STATUS_2 0x4cb6 6487 #define regRLC_UTCL1_STATUS_2_BASE_IDX 1 6488 #define regRLC_LB_THR_CONFIG_2 0x4cb8 6489 #define regRLC_LB_THR_CONFIG_2_BASE_IDX 1 6490 #define regRLC_LB_THR_CONFIG_3 0x4cb9 6491 #define regRLC_LB_THR_CONFIG_3_BASE_IDX 1 6492 #define regRLC_LB_THR_CONFIG_4 0x4cba 6493 #define regRLC_LB_THR_CONFIG_4_BASE_IDX 1 6494 #define regRLC_SPM_UTCL1_ERROR_1 0x4cbc 6495 #define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 6496 #define regRLC_SPM_UTCL1_ERROR_2 0x4cbd 6497 #define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 6498 #define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe 6499 #define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 6500 #define regRLC_LB_THR_CONFIG_1 0x4cbf 6501 #define regRLC_LB_THR_CONFIG_1_BASE_IDX 1 6502 #define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 6503 #define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 6504 #define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 6505 #define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 6506 #define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 6507 #define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 6508 #define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 6509 #define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 6510 #define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 6511 #define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 6512 #define regRLC_SEMAPHORE_0 0x4cc7 6513 #define regRLC_SEMAPHORE_0_BASE_IDX 1 6514 #define regRLC_SEMAPHORE_1 0x4cc8 6515 #define regRLC_SEMAPHORE_1_BASE_IDX 1 6516 #define regRLC_CP_EOF_INT 0x4cca 6517 #define regRLC_CP_EOF_INT_BASE_IDX 1 6518 #define regRLC_CP_EOF_INT_CNT 0x4ccb 6519 #define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 6520 #define regRLC_SPARE_INT 0x4ccc 6521 #define regRLC_SPARE_INT_BASE_IDX 1 6522 #define regRLC_PREWALKER_UTCL1_CNTL 0x4ccd 6523 #define regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 6524 #define regRLC_PREWALKER_UTCL1_TRIG 0x4cce 6525 #define regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 6526 #define regRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf 6527 #define regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 6528 #define regRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 6529 #define regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 6530 #define regRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 6531 #define regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 6532 #define regRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 6533 #define regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 6534 #define regRLC_DSM_TRIG 0x4cd3 6535 #define regRLC_DSM_TRIG_BASE_IDX 1 6536 #define regRLC_UTCL1_STATUS 0x4cd4 6537 #define regRLC_UTCL1_STATUS_BASE_IDX 1 6538 #define regRLC_R2I_CNTL_0 0x4cd5 6539 #define regRLC_R2I_CNTL_0_BASE_IDX 1 6540 #define regRLC_R2I_CNTL_1 0x4cd6 6541 #define regRLC_R2I_CNTL_1_BASE_IDX 1 6542 #define regRLC_R2I_CNTL_2 0x4cd7 6543 #define regRLC_R2I_CNTL_2_BASE_IDX 1 6544 #define regRLC_R2I_CNTL_3 0x4cd8 6545 #define regRLC_R2I_CNTL_3_BASE_IDX 1 6546 #define regRLC_UTCL2_CNTL 0x4cd9 6547 #define regRLC_UTCL2_CNTL_BASE_IDX 1 6548 #define regRLC_LBPW_CU_STAT 0x4cda 6549 #define regRLC_LBPW_CU_STAT_BASE_IDX 1 6550 #define regRLC_DS_CNTL 0x4cdb 6551 #define regRLC_DS_CNTL_BASE_IDX 1 6552 #define regRLC_GPM_INT_STAT_TH0 0x4cdc 6553 #define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 6554 #define regRLC_GPM_GENERAL_13 0x4cdd 6555 #define regRLC_GPM_GENERAL_13_BASE_IDX 1 6556 #define regRLC_GPM_GENERAL_14 0x4cde 6557 #define regRLC_GPM_GENERAL_14_BASE_IDX 1 6558 #define regRLC_GPM_GENERAL_15 0x4cdf 6559 #define regRLC_GPM_GENERAL_15_BASE_IDX 1 6560 #define regRLC_SPARE_INT_1 0x4ce0 6561 #define regRLC_SPARE_INT_1_BASE_IDX 1 6562 #define regRLC_RLCV_SPARE_INT_1 0x4ce1 6563 #define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 6564 #define regRLC_SEMAPHORE_2 0x4ce3 6565 #define regRLC_SEMAPHORE_2_BASE_IDX 1 6566 #define regRLC_SEMAPHORE_3 0x4ce4 6567 #define regRLC_SEMAPHORE_3_BASE_IDX 1 6568 #define regRLC_SMU_ARGUMENT_3 0x4ce5 6569 #define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 6570 #define regRLC_SMU_ARGUMENT_4 0x4ce6 6571 #define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 6572 #define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 6573 #define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 6574 #define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 6575 #define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 6576 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea 6577 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 6578 #define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb 6579 #define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 6580 #define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec 6581 #define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 6582 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef 6583 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 6584 #define regRLC_CPG_STAT_INVAL 0x4d09 6585 #define regRLC_CPG_STAT_INVAL_BASE_IDX 1 6586 #define regRLC_DSM_CNTL 0x4d42 6587 #define regRLC_DSM_CNTL_BASE_IDX 1 6588 #define regRLC_DSM_CNTLA 0x4d43 6589 #define regRLC_DSM_CNTLA_BASE_IDX 1 6590 #define regRLC_DSM_CNTL2 0x4d44 6591 #define regRLC_DSM_CNTL2_BASE_IDX 1 6592 #define regRLC_DSM_CNTL2A 0x4d45 6593 #define regRLC_DSM_CNTL2A_BASE_IDX 1 6594 #define regRLC_RLCV_SPARE_INT 0x4f30 6595 #define regRLC_RLCV_SPARE_INT_BASE_IDX 1 6596 #define regRLC_SMU_CLK_REQ 0x4f97 6597 #define regRLC_SMU_CLK_REQ_BASE_IDX 1 6598 6599 6600 // addressBlock: xcd0_gc_pwrdec 6601 // base address: 0x3c000 6602 #define regCGTS_SM_CTRL_REG 0x5000 6603 #define regCGTS_SM_CTRL_REG_BASE_IDX 1 6604 #define regCGTS_RD_CTRL_REG 0x5001 6605 #define regCGTS_RD_CTRL_REG_BASE_IDX 1 6606 #define regCGTS_RD_REG 0x5002 6607 #define regCGTS_RD_REG_BASE_IDX 1 6608 #define regCGTS_TCC_DISABLE 0x5003 6609 #define regCGTS_TCC_DISABLE_BASE_IDX 1 6610 #define regCGTS_USER_TCC_DISABLE 0x5004 6611 #define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 6612 #define regCGTS_CU0_SP0_CTRL_REG 0x5008 6613 #define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 6614 #define regCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 6615 #define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 6616 #define regCGTS_CU0_TA_SQC_CTRL_REG 0x500a 6617 #define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 6618 #define regCGTS_CU0_SP1_CTRL_REG 0x500b 6619 #define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 6620 #define regCGTS_CU0_TD_TCP_CTRL_REG 0x500c 6621 #define regCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 6622 #define regCGTS_CU1_SP0_CTRL_REG 0x500d 6623 #define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 6624 #define regCGTS_CU1_LDS_SQ_CTRL_REG 0x500e 6625 #define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 6626 #define regCGTS_CU1_TA_SQC_CTRL_REG 0x500f 6627 #define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 6628 #define regCGTS_CU1_SP1_CTRL_REG 0x5010 6629 #define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 6630 #define regCGTS_CU1_TD_TCP_CTRL_REG 0x5011 6631 #define regCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 6632 #define regCGTS_CU2_SP0_CTRL_REG 0x5012 6633 #define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 6634 #define regCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 6635 #define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 6636 #define regCGTS_CU2_TA_SQC_CTRL_REG 0x5014 6637 #define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 6638 #define regCGTS_CU2_SP1_CTRL_REG 0x5015 6639 #define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 6640 #define regCGTS_CU2_TD_TCP_CTRL_REG 0x5016 6641 #define regCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 6642 #define regCGTS_CU3_SP0_CTRL_REG 0x5017 6643 #define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 6644 #define regCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 6645 #define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 6646 #define regCGTS_CU3_TA_SQC_CTRL_REG 0x5019 6647 #define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 6648 #define regCGTS_CU3_SP1_CTRL_REG 0x501a 6649 #define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 6650 #define regCGTS_CU3_TD_TCP_CTRL_REG 0x501b 6651 #define regCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 6652 #define regCGTS_CU4_SP0_CTRL_REG 0x501c 6653 #define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 6654 #define regCGTS_CU4_LDS_SQ_CTRL_REG 0x501d 6655 #define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 6656 #define regCGTS_CU4_TA_SQC_CTRL_REG 0x501e 6657 #define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 6658 #define regCGTS_CU4_SP1_CTRL_REG 0x501f 6659 #define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 6660 #define regCGTS_CU4_TD_TCP_CTRL_REG 0x5020 6661 #define regCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 6662 #define regCGTS_CU5_SP0_CTRL_REG 0x5021 6663 #define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 6664 #define regCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 6665 #define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 6666 #define regCGTS_CU5_TA_SQC_CTRL_REG 0x5023 6667 #define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 6668 #define regCGTS_CU5_SP1_CTRL_REG 0x5024 6669 #define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 6670 #define regCGTS_CU5_TD_TCP_CTRL_REG 0x5025 6671 #define regCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 6672 #define regCGTS_CU6_SP0_CTRL_REG 0x5026 6673 #define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 6674 #define regCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 6675 #define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 6676 #define regCGTS_CU6_TA_SQC_CTRL_REG 0x5028 6677 #define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 6678 #define regCGTS_CU6_SP1_CTRL_REG 0x5029 6679 #define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 6680 #define regCGTS_CU6_TD_TCP_CTRL_REG 0x502a 6681 #define regCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 6682 #define regCGTS_CU7_SP0_CTRL_REG 0x502b 6683 #define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 6684 #define regCGTS_CU7_LDS_SQ_CTRL_REG 0x502c 6685 #define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 6686 #define regCGTS_CU7_TA_SQC_CTRL_REG 0x502d 6687 #define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 6688 #define regCGTS_CU7_SP1_CTRL_REG 0x502e 6689 #define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 6690 #define regCGTS_CU7_TD_TCP_CTRL_REG 0x502f 6691 #define regCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 6692 #define regCGTS_CU8_SP0_CTRL_REG 0x5030 6693 #define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 6694 #define regCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 6695 #define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 6696 #define regCGTS_CU8_TA_SQC_CTRL_REG 0x5032 6697 #define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 6698 #define regCGTS_CU8_SP1_CTRL_REG 0x5033 6699 #define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 6700 #define regCGTS_CU8_TD_TCP_CTRL_REG 0x5034 6701 #define regCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 6702 #define regCGTS_CU9_SP0_CTRL_REG 0x5035 6703 #define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 6704 #define regCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 6705 #define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 6706 #define regCGTS_CU9_TA_SQC_CTRL_REG 0x5037 6707 #define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 6708 #define regCGTS_CU9_SP1_CTRL_REG 0x5038 6709 #define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 6710 #define regCGTS_CU9_TD_TCP_CTRL_REG 0x5039 6711 #define regCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 6712 #define regCGTS_CU10_SP0_CTRL_REG 0x503a 6713 #define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 6714 #define regCGTS_CU10_LDS_SQ_CTRL_REG 0x503b 6715 #define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 6716 #define regCGTS_CU10_TA_SQC_CTRL_REG 0x503c 6717 #define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 6718 #define regCGTS_CU10_SP1_CTRL_REG 0x503d 6719 #define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 6720 #define regCGTS_CU10_TD_TCP_CTRL_REG 0x503e 6721 #define regCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 6722 #define regCGTS_CU11_SP0_CTRL_REG 0x503f 6723 #define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 6724 #define regCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 6725 #define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 6726 #define regCGTS_CU11_TA_SQC_CTRL_REG 0x5041 6727 #define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 6728 #define regCGTS_CU11_SP1_CTRL_REG 0x5042 6729 #define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 6730 #define regCGTS_CU11_TD_TCP_CTRL_REG 0x5043 6731 #define regCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 6732 #define regCGTS_CU12_SP0_CTRL_REG 0x5044 6733 #define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 6734 #define regCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 6735 #define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 6736 #define regCGTS_CU12_TA_SQC_CTRL_REG 0x5046 6737 #define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 6738 #define regCGTS_CU12_SP1_CTRL_REG 0x5047 6739 #define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 6740 #define regCGTS_CU12_TD_TCP_CTRL_REG 0x5048 6741 #define regCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 6742 #define regCGTS_CU13_SP0_CTRL_REG 0x5049 6743 #define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 6744 #define regCGTS_CU13_LDS_SQ_CTRL_REG 0x504a 6745 #define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 6746 #define regCGTS_CU13_TA_SQC_CTRL_REG 0x504b 6747 #define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 6748 #define regCGTS_CU13_SP1_CTRL_REG 0x504c 6749 #define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 6750 #define regCGTS_CU13_TD_TCP_CTRL_REG 0x504d 6751 #define regCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 6752 #define regCGTS_CU14_SP0_CTRL_REG 0x504e 6753 #define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 6754 #define regCGTS_CU14_LDS_SQ_CTRL_REG 0x504f 6755 #define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 6756 #define regCGTS_CU14_TA_SQC_CTRL_REG 0x5050 6757 #define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 6758 #define regCGTS_CU14_SP1_CTRL_REG 0x5051 6759 #define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 6760 #define regCGTS_CU14_TD_TCP_CTRL_REG 0x5052 6761 #define regCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 6762 #define regCGTS_CU15_SP0_CTRL_REG 0x5053 6763 #define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 6764 #define regCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 6765 #define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 6766 #define regCGTS_CU15_TA_SQC_CTRL_REG 0x5055 6767 #define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 6768 #define regCGTS_CU15_SP1_CTRL_REG 0x5056 6769 #define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 6770 #define regCGTS_CU15_TD_TCP_CTRL_REG 0x5057 6771 #define regCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 6772 #define regCGTS_CU0_TCPI_CTRL_REG 0x5058 6773 #define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 6774 #define regCGTS_CU1_TCPI_CTRL_REG 0x5059 6775 #define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 6776 #define regCGTS_CU2_TCPI_CTRL_REG 0x505a 6777 #define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 6778 #define regCGTS_CU3_TCPI_CTRL_REG 0x505b 6779 #define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 6780 #define regCGTS_CU4_TCPI_CTRL_REG 0x505c 6781 #define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 6782 #define regCGTS_CU5_TCPI_CTRL_REG 0x505d 6783 #define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 6784 #define regCGTS_CU6_TCPI_CTRL_REG 0x505e 6785 #define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 6786 #define regCGTS_CU7_TCPI_CTRL_REG 0x505f 6787 #define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 6788 #define regCGTS_CU8_TCPI_CTRL_REG 0x5060 6789 #define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 6790 #define regCGTS_CU9_TCPI_CTRL_REG 0x5061 6791 #define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 6792 #define regCGTS_CU10_TCPI_CTRL_REG 0x5062 6793 #define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 6794 #define regCGTS_CU11_TCPI_CTRL_REG 0x5063 6795 #define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 6796 #define regCGTS_CU12_TCPI_CTRL_REG 0x5064 6797 #define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 6798 #define regCGTS_CU13_TCPI_CTRL_REG 0x5065 6799 #define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 6800 #define regCGTS_CU14_TCPI_CTRL_REG 0x5066 6801 #define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 6802 #define regCGTS_CU15_TCPI_CTRL_REG 0x5067 6803 #define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 6804 #define regCGTT_SPI_PS_CLK_CTRL 0x507d 6805 #define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 6806 #define regCGTT_SPIS_CLK_CTRL 0x507e 6807 #define regCGTT_SPIS_CLK_CTRL_BASE_IDX 1 6808 #define regCGTX_SPI_DEBUG_CLK_CTRL 0x507f 6809 #define regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX 1 6810 #define regCGTT_SPI_CLK_CTRL 0x5080 6811 #define regCGTT_SPI_CLK_CTRL_BASE_IDX 1 6812 #define regCGTT_PC_CLK_CTRL 0x5081 6813 #define regCGTT_PC_CLK_CTRL_BASE_IDX 1 6814 #define regCGTT_BCI_CLK_CTRL 0x5082 6815 #define regCGTT_BCI_CLK_CTRL_BASE_IDX 1 6816 #define regCGTT_VGT_CLK_CTRL 0x5084 6817 #define regCGTT_VGT_CLK_CTRL_BASE_IDX 1 6818 #define regCGTT_IA_CLK_CTRL 0x5085 6819 #define regCGTT_IA_CLK_CTRL_BASE_IDX 1 6820 #define regCGTT_WD_CLK_CTRL 0x5086 6821 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 6822 #define regCGTT_PA_CLK_CTRL 0x5088 6823 #define regCGTT_PA_CLK_CTRL_BASE_IDX 1 6824 #define regCGTT_SC_CLK_CTRL0 0x5089 6825 #define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 6826 #define regCGTT_SC_CLK_CTRL1 0x508a 6827 #define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 6828 #define regCGTT_SC_CLK_CTRL2 0x508b 6829 #define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 6830 #define regCGTT_SQ_CLK_CTRL 0x508c 6831 #define regCGTT_SQ_CLK_CTRL_BASE_IDX 1 6832 #define regCGTT_SQG_CLK_CTRL 0x508d 6833 #define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 6834 #define regSQ_ALU_CLK_CTRL 0x508e 6835 #define regSQ_ALU_CLK_CTRL_BASE_IDX 1 6836 #define regSQ_TEX_CLK_CTRL 0x508f 6837 #define regSQ_TEX_CLK_CTRL_BASE_IDX 1 6838 #define regSQ_LDS_CLK_CTRL 0x5090 6839 #define regSQ_LDS_CLK_CTRL_BASE_IDX 1 6840 #define regSQ_POWER_THROTTLE 0x5091 6841 #define regSQ_POWER_THROTTLE_BASE_IDX 1 6842 #define regSQ_POWER_THROTTLE2 0x5092 6843 #define regSQ_POWER_THROTTLE2_BASE_IDX 1 6844 #define regTD_CGTT_CTRL 0x509c 6845 #define regTD_CGTT_CTRL_BASE_IDX 1 6846 #define regTA_CGTT_CTRL 0x509d 6847 #define regTA_CGTT_CTRL_BASE_IDX 1 6848 #define regCGTT_TCPI_CLK_CTRL 0x509e 6849 #define regCGTT_TCPI_CLK_CTRL_BASE_IDX 1 6850 #define regTCX_CGTT_SCLK_CTRL 0x50a3 6851 #define regTCX_CGTT_SCLK_CTRL_BASE_IDX 1 6852 #define regDB_CGTT_CLK_CTRL_0 0x50a4 6853 #define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 6854 #define regCB_CGTT_SCLK_CTRL 0x50a8 6855 #define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 6856 #define regTCC_CGTT_SCLK_CTRL 0x50ac 6857 #define regTCC_CGTT_SCLK_CTRL_BASE_IDX 1 6858 #define regTCC_CGTT_SCLK_CTRL2 0x50ad 6859 #define regTCC_CGTT_SCLK_CTRL2_BASE_IDX 1 6860 #define regTCC_CGTT_SCLK_CTRL3 0x50ae 6861 #define regTCC_CGTT_SCLK_CTRL3_BASE_IDX 1 6862 #define regTCA_CGTT_SCLK_CTRL 0x50af 6863 #define regTCA_CGTT_SCLK_CTRL_BASE_IDX 1 6864 #define regCGTT_CP_CLK_CTRL 0x50b0 6865 #define regCGTT_CP_CLK_CTRL_BASE_IDX 1 6866 #define regCGTT_CPC_CLK_CTRL 0x50b2 6867 #define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 6868 #define regCGTT_RLC_CLK_CTRL 0x50b5 6869 #define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 6870 #define regRLC_GFX_RM_CNTL 0x50b6 6871 #define regRLC_GFX_RM_CNTL_BASE_IDX 1 6872 #define regRMI_CGTT_SCLK_CTRL 0x50c0 6873 #define regRMI_CGTT_SCLK_CTRL_BASE_IDX 1 6874 #define regCGTT_TCPF_CLK_CTRL 0x50c1 6875 #define regCGTT_TCPF_CLK_CTRL_BASE_IDX 1 6876 6877 6878 // addressBlock: xcd0_gc_hypdec 6879 // base address: 0x3e000 6880 #define regCP_HYP_PFP_UCODE_ADDR 0x5814 6881 #define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 6882 #define regCP_PFP_UCODE_ADDR 0x5814 6883 #define regCP_PFP_UCODE_ADDR_BASE_IDX 1 6884 #define regCP_HYP_PFP_UCODE_DATA 0x5815 6885 #define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 6886 #define regCP_PFP_UCODE_DATA 0x5815 6887 #define regCP_PFP_UCODE_DATA_BASE_IDX 1 6888 #define regCP_HYP_ME_UCODE_ADDR 0x5816 6889 #define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 6890 #define regCP_ME_RAM_RADDR 0x5816 6891 #define regCP_ME_RAM_RADDR_BASE_IDX 1 6892 #define regCP_ME_RAM_WADDR 0x5816 6893 #define regCP_ME_RAM_WADDR_BASE_IDX 1 6894 #define regCP_HYP_ME_UCODE_DATA 0x5817 6895 #define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 6896 #define regCP_ME_RAM_DATA 0x5817 6897 #define regCP_ME_RAM_DATA_BASE_IDX 1 6898 #define regCP_CE_UCODE_ADDR 0x5818 6899 #define regCP_CE_UCODE_ADDR_BASE_IDX 1 6900 #define regCP_HYP_CE_UCODE_ADDR 0x5818 6901 #define regCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 6902 #define regCP_CE_UCODE_DATA 0x5819 6903 #define regCP_CE_UCODE_DATA_BASE_IDX 1 6904 #define regCP_HYP_CE_UCODE_DATA 0x5819 6905 #define regCP_HYP_CE_UCODE_DATA_BASE_IDX 1 6906 #define regCP_HYP_MEC1_UCODE_ADDR 0x581a 6907 #define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 6908 #define regCP_MEC_ME1_UCODE_ADDR 0x581a 6909 #define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 6910 #define regCP_HYP_MEC1_UCODE_DATA 0x581b 6911 #define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 6912 #define regCP_MEC_ME1_UCODE_DATA 0x581b 6913 #define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 6914 #define regCP_HYP_MEC2_UCODE_ADDR 0x581c 6915 #define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 6916 #define regCP_MEC_ME2_UCODE_ADDR 0x581c 6917 #define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 6918 #define regCP_HYP_MEC2_UCODE_DATA 0x581d 6919 #define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 6920 #define regCP_MEC_ME2_UCODE_DATA 0x581d 6921 #define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 6922 #define regCP_HYP_PFP_UCODE_CHKSUM 0x581e 6923 #define regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX 1 6924 #define regCP_HYP_CE_UCODE_CHKSUM 0x581f 6925 #define regCP_HYP_CE_UCODE_CHKSUM_BASE_IDX 1 6926 #define regCP_HYP_ME_UCODE_CHKSUM 0x5820 6927 #define regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX 1 6928 #define regCP_HYP_MEC_ME1_UCODE_CHKSUM 0x5821 6929 #define regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX 1 6930 #define regCP_HYP_MEC_ME2_UCODE_CHKSUM 0x5822 6931 #define regCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX 1 6932 #define regCP_HYP_XCP_CTL 0x5828 6933 #define regCP_HYP_XCP_CTL_BASE_IDX 1 6934 #define regRLC_GPM_UCODE_ADDR 0x583c 6935 #define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 6936 #define regRLC_GPM_UCODE_DATA 0x583d 6937 #define regRLC_GPM_UCODE_DATA_BASE_IDX 1 6938 #define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 6939 #define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 6940 #define regGRBM_GFX_INDEX_SR_DATA 0x5a01 6941 #define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 6942 #define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 6943 #define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 6944 #define regGRBM_GFX_CNTL_SR_DATA 0x5a03 6945 #define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 6946 #define regGRBM_MCM_ADDR 0x5a07 6947 #define regGRBM_MCM_ADDR_BASE_IDX 1 6948 #define regRLC_GPU_IOV_VF_ENABLE 0x5b00 6949 #define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 6950 #define regRLC_GPU_IOV_CFG_REG6 0x5b06 6951 #define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 6952 #define regRLC_GPU_IOV_CFG_REG8 0x5b20 6953 #define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 6954 #define regRLC_RLCV_TIMER_INT_0 0x5b25 6955 #define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 6956 #define regRLC_RLCV_TIMER_CTRL 0x5b26 6957 #define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 6958 #define regRLC_RLCV_TIMER_STAT 0x5b27 6959 #define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 6960 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a 6961 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 6962 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b 6963 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 6964 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c 6965 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 6966 #define regRLC_GPU_IOV_VF_MASK 0x5b2d 6967 #define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 6968 #define regRLC_HYP_SEMAPHORE_0 0x5b2e 6969 #define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 6970 #define regRLC_HYP_SEMAPHORE_1 0x5b2f 6971 #define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 6972 #define regRLC_CLK_CNTL 0x5b31 6973 #define regRLC_CLK_CNTL_BASE_IDX 1 6974 #define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 6975 #define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 6976 #define regRLC_GPU_IOV_CFG_REG1 0x5b35 6977 #define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 6978 #define regRLC_GPU_IOV_CFG_REG2 0x5b36 6979 #define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 6980 #define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 6981 #define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 6982 #define regRLC_GPU_IOV_SCH_0 0x5b38 6983 #define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 6984 #define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 6985 #define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 6986 #define regRLC_GPU_IOV_SCH_3 0x5b3a 6987 #define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 6988 #define regRLC_GPU_IOV_SCH_1 0x5b3b 6989 #define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 6990 #define regRLC_GPU_IOV_SCH_2 0x5b3c 6991 #define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 6992 #define regRLC_GPU_IOV_INT_STAT 0x5b3f 6993 #define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 6994 #define regRLC_RLCV_TIMER_INT_1 0x5b40 6995 #define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 6996 #define regRLC_GPU_IOV_UCODE_ADDR 0x5b42 6997 #define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 6998 #define regRLC_GPU_IOV_UCODE_DATA 0x5b43 6999 #define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 7000 #define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 7001 #define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 7002 #define regRLC_GPU_IOV_SCRATCH_DATA 0x5b45 7003 #define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 7004 #define regRLC_GPU_IOV_F32_CNTL 0x5b46 7005 #define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 7006 #define regRLC_GPU_IOV_F32_RESET 0x5b47 7007 #define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 7008 #define regRLC_GPU_IOV_SDMA0_STATUS 0x5b48 7009 #define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 7010 #define regRLC_GPU_IOV_SDMA1_STATUS 0x5b49 7011 #define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 7012 #define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a 7013 #define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 7014 #define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c 7015 #define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 7016 #define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d 7017 #define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 7018 #define regRLC_GPU_IOV_INT_DISABLE 0x5b4e 7019 #define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 7020 #define regRLC_GPU_IOV_INT_FORCE 0x5b4f 7021 #define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 7022 #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 7023 #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 7024 #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 7025 #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 7026 #define regRLC_HYP_SEMAPHORE_2 0x5b52 7027 #define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 7028 #define regRLC_HYP_SEMAPHORE_3 0x5b53 7029 #define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 7030 #define regRLC_GPU_IOV_SDMA2_STATUS 0x5b54 7031 #define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 7032 #define regRLC_GPU_IOV_SDMA3_STATUS 0x5b55 7033 #define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 7034 #define regRLC_GPU_IOV_SDMA4_STATUS 0x5b56 7035 #define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 7036 #define regRLC_GPU_IOV_SDMA5_STATUS 0x5b57 7037 #define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 7038 #define regRLC_GPU_IOV_SDMA6_STATUS 0x5b58 7039 #define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 7040 #define regRLC_GPU_IOV_SDMA7_STATUS 0x5b59 7041 #define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 7042 #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5b5a 7043 #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 7044 #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5b5b 7045 #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 7046 #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5b5c 7047 #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 7048 #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5b5d 7049 #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 7050 #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5b5e 7051 #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 7052 #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5b5f 7053 #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 7054 7055 7056 // addressBlock: xcd0_gc_utcl2_vmsharedhvdec 7057 // base address: 0x3ea00 7058 #define regMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 7059 #define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 7060 #define regMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 7061 #define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 7062 #define regMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 7063 #define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 7064 #define regMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 7065 #define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 7066 #define regMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 7067 #define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 7068 #define regMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 7069 #define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 7070 #define regMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 7071 #define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 7072 #define regMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 7073 #define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 7074 #define regMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 7075 #define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 7076 #define regMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 7077 #define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 7078 #define regMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a 7079 #define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 7080 #define regMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b 7081 #define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 7082 #define regMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c 7083 #define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 7084 #define regMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d 7085 #define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 7086 #define regMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e 7087 #define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 7088 #define regMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f 7089 #define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 7090 #define regVM_IOMMU_MMIO_CNTRL_1 0x5a90 7091 #define regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 7092 #define regMC_VM_MARC_BASE_LO_0 0x5a91 7093 #define regMC_VM_MARC_BASE_LO_0_BASE_IDX 1 7094 #define regMC_VM_MARC_BASE_LO_1 0x5a92 7095 #define regMC_VM_MARC_BASE_LO_1_BASE_IDX 1 7096 #define regMC_VM_MARC_BASE_LO_2 0x5a93 7097 #define regMC_VM_MARC_BASE_LO_2_BASE_IDX 1 7098 #define regMC_VM_MARC_BASE_LO_3 0x5a94 7099 #define regMC_VM_MARC_BASE_LO_3_BASE_IDX 1 7100 #define regMC_VM_MARC_BASE_HI_0 0x5a95 7101 #define regMC_VM_MARC_BASE_HI_0_BASE_IDX 1 7102 #define regMC_VM_MARC_BASE_HI_1 0x5a96 7103 #define regMC_VM_MARC_BASE_HI_1_BASE_IDX 1 7104 #define regMC_VM_MARC_BASE_HI_2 0x5a97 7105 #define regMC_VM_MARC_BASE_HI_2_BASE_IDX 1 7106 #define regMC_VM_MARC_BASE_HI_3 0x5a98 7107 #define regMC_VM_MARC_BASE_HI_3_BASE_IDX 1 7108 #define regMC_VM_MARC_RELOC_LO_0 0x5a99 7109 #define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 7110 #define regMC_VM_MARC_RELOC_LO_1 0x5a9a 7111 #define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 7112 #define regMC_VM_MARC_RELOC_LO_2 0x5a9b 7113 #define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 7114 #define regMC_VM_MARC_RELOC_LO_3 0x5a9c 7115 #define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 7116 #define regMC_VM_MARC_RELOC_HI_0 0x5a9d 7117 #define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 7118 #define regMC_VM_MARC_RELOC_HI_1 0x5a9e 7119 #define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 7120 #define regMC_VM_MARC_RELOC_HI_2 0x5a9f 7121 #define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 7122 #define regMC_VM_MARC_RELOC_HI_3 0x5aa0 7123 #define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 7124 #define regMC_VM_MARC_LEN_LO_0 0x5aa1 7125 #define regMC_VM_MARC_LEN_LO_0_BASE_IDX 1 7126 #define regMC_VM_MARC_LEN_LO_1 0x5aa2 7127 #define regMC_VM_MARC_LEN_LO_1_BASE_IDX 1 7128 #define regMC_VM_MARC_LEN_LO_2 0x5aa3 7129 #define regMC_VM_MARC_LEN_LO_2_BASE_IDX 1 7130 #define regMC_VM_MARC_LEN_LO_3 0x5aa4 7131 #define regMC_VM_MARC_LEN_LO_3_BASE_IDX 1 7132 #define regMC_VM_MARC_LEN_HI_0 0x5aa5 7133 #define regMC_VM_MARC_LEN_HI_0_BASE_IDX 1 7134 #define regMC_VM_MARC_LEN_HI_1 0x5aa6 7135 #define regMC_VM_MARC_LEN_HI_1_BASE_IDX 1 7136 #define regMC_VM_MARC_LEN_HI_2 0x5aa7 7137 #define regMC_VM_MARC_LEN_HI_2_BASE_IDX 1 7138 #define regMC_VM_MARC_LEN_HI_3 0x5aa8 7139 #define regMC_VM_MARC_LEN_HI_3_BASE_IDX 1 7140 #define regVM_IOMMU_CONTROL_REGISTER 0x5aa9 7141 #define regVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 7142 #define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa 7143 #define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 7144 #define regVM_PCIE_ATS_CNTL 0x5aab 7145 #define regVM_PCIE_ATS_CNTL_BASE_IDX 1 7146 #define regVM_PCIE_ATS_CNTL_VF_0 0x5aac 7147 #define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 7148 #define regVM_PCIE_ATS_CNTL_VF_1 0x5aad 7149 #define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 7150 #define regVM_PCIE_ATS_CNTL_VF_2 0x5aae 7151 #define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 7152 #define regVM_PCIE_ATS_CNTL_VF_3 0x5aaf 7153 #define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 7154 #define regVM_PCIE_ATS_CNTL_VF_4 0x5ab0 7155 #define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 7156 #define regVM_PCIE_ATS_CNTL_VF_5 0x5ab1 7157 #define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 7158 #define regVM_PCIE_ATS_CNTL_VF_6 0x5ab2 7159 #define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 7160 #define regVM_PCIE_ATS_CNTL_VF_7 0x5ab3 7161 #define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 7162 #define regVM_PCIE_ATS_CNTL_VF_8 0x5ab4 7163 #define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 7164 #define regVM_PCIE_ATS_CNTL_VF_9 0x5ab5 7165 #define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 7166 #define regVM_PCIE_ATS_CNTL_VF_10 0x5ab6 7167 #define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 7168 #define regVM_PCIE_ATS_CNTL_VF_11 0x5ab7 7169 #define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 7170 #define regVM_PCIE_ATS_CNTL_VF_12 0x5ab8 7171 #define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 7172 #define regVM_PCIE_ATS_CNTL_VF_13 0x5ab9 7173 #define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 7174 #define regVM_PCIE_ATS_CNTL_VF_14 0x5aba 7175 #define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 7176 #define regVM_PCIE_ATS_CNTL_VF_15 0x5abb 7177 #define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 7178 #define regMC_SHARED_ACTIVE_FCN_ID 0x5abc 7179 #define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 7180 #define regMC_VM_XGMI_GPUIOV_ENABLE 0x5abd 7181 #define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 7182 7183 7184 // addressBlock: xcd0_gc_pspdec 7185 // base address: 0x3f000 7186 #define regCPG_PSP_DEBUG 0x5c30 7187 #define regCPG_PSP_DEBUG_BASE_IDX 1 7188 #define regCPC_PSP_DEBUG 0x5c31 7189 #define regCPC_PSP_DEBUG_BASE_IDX 1 7190 #define regCP_PSP_XCP_CTL 0x5c34 7191 #define regCP_PSP_XCP_CTL_BASE_IDX 1 7192 #define regGRBM_SEC_CNTL 0x5e0b 7193 #define regGRBM_SEC_CNTL_BASE_IDX 1 7194 #define regGRBM_IOV_ERROR_FIFO_DATA 0x5e12 7195 #define regGRBM_IOV_ERROR_FIFO_DATA_BASE_IDX 1 7196 #define regGRBM_DSM_BYPASS 0x5e13 7197 #define regGRBM_DSM_BYPASS_BASE_IDX 1 7198 #define regGRBM_CAM_INDEX 0x5e16 7199 #define regGRBM_CAM_INDEX_BASE_IDX 1 7200 #define regGRBM_HYP_CAM_INDEX 0x5e16 7201 #define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 7202 #define regGRBM_CAM_DATA 0x5e17 7203 #define regGRBM_CAM_DATA_BASE_IDX 1 7204 #define regGRBM_HYP_CAM_DATA 0x5e17 7205 #define regGRBM_HYP_CAM_DATA_BASE_IDX 1 7206 #define regRLC_FWL_FIRST_VIOL_ADDR 0x5f37 7207 #define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 7208 7209 7210 // addressBlock: sqind 7211 // base address: 0x0 7212 #define ixSQ_DEBUG_STS_LOCAL 0x0008 7213 #define ixSQ_DEBUG_CTRL_LOCAL 0x0009 7214 #define ixSQ_WAVE_VALID_AND_IDLE 0x000a 7215 #define ixSQ_WAVE_MODE 0x0011 7216 #define ixSQ_WAVE_STATUS 0x0012 7217 #define ixSQ_WAVE_TRAPSTS 0x0013 7218 #define ixSQ_WAVE_HW_ID 0x0014 7219 #define ixSQ_WAVE_GPR_ALLOC 0x0015 7220 #define ixSQ_WAVE_LDS_ALLOC 0x0016 7221 #define ixSQ_WAVE_IB_STS 0x0017 7222 #define ixSQ_WAVE_PC_LO 0x0018 7223 #define ixSQ_WAVE_PC_HI 0x0019 7224 #define ixSQ_WAVE_INST_DW0 0x001a 7225 #define ixSQ_WAVE_INST_DW1 0x001b 7226 #define ixSQ_WAVE_IB_DBG0 0x001c 7227 #define ixSQ_WAVE_IB_DBG1 0x001d 7228 #define ixSQ_WAVE_FLUSH_IB 0x001e 7229 #define ixSQ_WAVE_TTMP0 0x026c 7230 #define ixSQ_WAVE_TTMP1 0x026d 7231 #define ixSQ_WAVE_TTMP2 0x026e 7232 #define ixSQ_WAVE_TTMP3 0x026f 7233 #define ixSQ_WAVE_TTMP4 0x0270 7234 #define ixSQ_WAVE_TTMP5 0x0271 7235 #define ixSQ_WAVE_TTMP6 0x0272 7236 #define ixSQ_WAVE_TTMP7 0x0273 7237 #define ixSQ_WAVE_TTMP8 0x0274 7238 #define ixSQ_WAVE_TTMP9 0x0275 7239 #define ixSQ_WAVE_TTMP10 0x0276 7240 #define ixSQ_WAVE_TTMP11 0x0277 7241 #define ixSQ_WAVE_TTMP12 0x0278 7242 #define ixSQ_WAVE_TTMP13 0x0279 7243 #define ixSQ_WAVE_TTMP14 0x027a 7244 #define ixSQ_WAVE_TTMP15 0x027b 7245 #define ixSQ_WAVE_M0 0x027c 7246 #define ixSQ_WAVE_EXEC_LO 0x027e 7247 #define ixSQ_WAVE_EXEC_HI 0x027f 7248 #define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 7249 #define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 7250 #define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 7251 #define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 7252 #define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 7253 #define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 7254 #define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 7255 #define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 7256 7257 7258 #endif 7259