xref: /linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h (revision 2da68a77)

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _mmhub_1_7_SH_MASK_HEADER
#define _mmhub_1_7_SH_MASK_HEADER


// addressBlock: mmhub_dagb_dagbdec0
//DAGB0_RDCLI0
#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI1
#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI2
#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI3
#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI4
#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI5
#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI6
#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI7
#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI8
#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI9
#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI10
#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI11
#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI12
#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI13
#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI14
#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI15
#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RD_CNTL
#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB0_RD_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB0_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB0_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB0_RD_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB0_RD_GMI_CNTL
#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB0_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB0_RD_ADDR_DAGB
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB0_RD_CGTT_CLK_CTRL
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST1
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB0_RD_VC0_CNTL
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC1_CNTL
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC2_CNTL
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC3_CNTL
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC4_CNTL
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC5_CNTL
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC6_CNTL
#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC7_CNTL
#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_CNTL_MISC
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB0_RD_TLB_CREDIT
#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB0_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB0_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB0_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB0_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB0_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB0_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB0_RD_RDRET_CREDIT_CNTL
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
//DAGB0_RD_RDRET_CREDIT_CNTL2
#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT                                                         0x0
#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT                                                        0x6
#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0xc
#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK                                                           0x0000003FL
#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK                                                          0x00000FC0L
#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0007F000L
//DAGB0_RDCLI_ASK_PENDING
#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_RDCLI_GO_PENDING
#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB0_RDCLI_GBLSEND_PENDING
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_RDCLI_TLB_PENDING
#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_RDCLI_OARB_PENDING
#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB0_RDCLI_OSD_PENDING
#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI0
#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI1
#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI2
#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI3
#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI4
#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI5
#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI6
#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI7
#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI8
#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI9
#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI10
#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI11
#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI12
#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI13
#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI14
#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI15
#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WR_CNTL
#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB0_WR_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB0_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB0_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB0_WR_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB0_WR_GMI_CNTL
#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB0_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB0_WR_ADDR_DAGB
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB0_WR_CGTT_CLK_CTRL
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST1
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB0_WR_DATA_DAGB
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB0_WR_DATA_DAGB_MAX_BURST0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST1
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB0_WR_VC0_CNTL
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC1_CNTL
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC2_CNTL
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC3_CNTL
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC4_CNTL
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC5_CNTL
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC6_CNTL
#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC7_CNTL
#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_CNTL_MISC
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB0_WR_TLB_CREDIT
#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB0_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB0_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB0_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB0_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB0_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB0_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB0_WR_DATA_CREDIT
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB0_WR_MISC_CREDIT
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
//DAGB0_WR_OSD_CREDIT_CNTL1
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
//DAGB0_WR_OSD_CREDIT_CNTL2
#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB0_WRCLI_ASK_PENDING
#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI_GO_PENDING
#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB0_WRCLI_GBLSEND_PENDING
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_WRCLI_TLB_PENDING
#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI_OARB_PENDING
#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB0_WRCLI_OSD_PENDING
#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_ASK_PENDING
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_GO_PENDING
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_DAGB_DLY
#define DAGB0_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB0_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB0_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB0_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB0_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB0_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB0_CNTL_MISC
#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
//DAGB0_CNTL_MISC2
#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
#define DAGB0_CNTL_MISC2__HDP_CID__SHIFT                                                                      0xc
#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
#define DAGB0_CNTL_MISC2__HDP_CID_MASK                                                                        0x0001F000L
#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
//DAGB0_FATAL_ERROR_CNTL
#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT                                                             0x0
#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK                                                               0x000003FFL
//DAGB0_FATAL_ERROR_CLEAR
#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT                                                                 0x0
#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK                                                                   0x00000001L
//DAGB0_FATAL_ERROR_STATUS0
#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT                                                               0x0
#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT                                                                 0x1
#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT                                                             0x6
#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK                                                                 0x00000001L
#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK                                                                   0x0000003EL
#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK                                                               0xFFFFFFC0L
//DAGB0_FATAL_ERROR_STATUS1
#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT                                                             0x0
#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK                                                               0x0001FFFFL
//DAGB0_FATAL_ERROR_STATUS2
#define DAGB0_FATAL_ERROR_STATUS2__TAG__SHIFT                                                                 0x0
#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT                                                                0x10
#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT                                                                  0x14
#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT                                                               0x15
#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT                                                                  0x16
#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT                                                                0x17
#define DAGB0_FATAL_ERROR_STATUS2__FED__SHIFT                                                                 0x19
#define DAGB0_FATAL_ERROR_STATUS2__TAG_MASK                                                                   0x0000FFFFL
#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK                                                                  0x000F0000L
#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK                                                                    0x00100000L
#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK                                                                 0x00200000L
#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK                                                                    0x00400000L
#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK                                                                  0x00800000L
#define DAGB0_FATAL_ERROR_STATUS2__FED_MASK                                                                   0x02000000L
//DAGB0_FATAL_ERROR_STATUS3
#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT                                                                  0x6
#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT                                                               0x10
#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT                                                               0x11
#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT                                                               0x12
#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT                                                               0x13
#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT                                                                0x14
#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT                                                                  0x16
#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT                                                              0x17
#define DAGB0_FATAL_ERROR_STATUS3__EOP__SHIFT                                                                 0x18
#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK                                                                    0x00001FC0L
#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK                                                                 0x00010000L
#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK                                                                 0x00020000L
#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK                                                                 0x00040000L
#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK                                                                 0x00080000L
#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK                                                                  0x00300000L
#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK                                                                    0x00400000L
#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK                                                                0x00800000L
#define DAGB0_FATAL_ERROR_STATUS3__EOP_MASK                                                                   0x01000000L
//DAGB0_FIFO_EMPTY
#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB0_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
//DAGB0_FIFO_FULL
#define DAGB0_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB0_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
//DAGB0_WR_CREDITS_FULL
#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB0_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
//DAGB0_RD_CREDITS_FULL
#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB0_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
//DAGB0_PERFCOUNTER_LO
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB0_PERFCOUNTER_HI
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB0_PERFCOUNTER0_CFG
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB0_PERFCOUNTER1_CFG
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB0_PERFCOUNTER2_CFG
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB0_PERFCOUNTER_RSLT_CNTL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB0_L1TLB_REG_RW
#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT                                                        0x2
#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT                                                          0x4
#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT                                                        0x5
#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x6
#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK                                                          0x00000004L
#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK                                                            0x00000010L
#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK                                                          0x00000020L
#define DAGB0_L1TLB_REG_RW__RESERVE_MASK                                                                      0xFFFFFFC0L
//DAGB0_RESERVE1
#define DAGB0_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_RESERVE2
#define DAGB0_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_RESERVE3
#define DAGB0_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_RESERVE4
#define DAGB0_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL


// addressBlock: mmhub_dagb_dagbdec1
//DAGB1_RDCLI0
#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI1
#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI2
#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI3
#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI4
#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI5
#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI6
#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI7
#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI8
#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI9
#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_RDCLI10
#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_RDCLI11
#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_RDCLI12
#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_RDCLI13
#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_RDCLI14
#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_RDCLI15
#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_RD_CNTL
#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB1_RD_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB1_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB1_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB1_RD_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB1_RD_GMI_CNTL
#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB1_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB1_RD_ADDR_DAGB
#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB1_RD_CGTT_CLK_CTRL
#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB1_RD_ADDR_DAGB_MAX_BURST0
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB1_RD_ADDR_DAGB_MAX_BURST1
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB1_RD_VC0_CNTL
#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC1_CNTL
#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC2_CNTL
#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC3_CNTL
#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC4_CNTL
#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC5_CNTL
#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC6_CNTL
#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_VC7_CNTL
#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_RD_CNTL_MISC
#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB1_RD_TLB_CREDIT
#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB1_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB1_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB1_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB1_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB1_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB1_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB1_RD_RDRET_CREDIT_CNTL
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
//DAGB1_RD_RDRET_CREDIT_CNTL2
#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT                                                         0x0
#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT                                                        0x6
#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0xc
#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK                                                           0x0000003FL
#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK                                                          0x00000FC0L
#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0007F000L
//DAGB1_RDCLI_ASK_PENDING
#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB1_RDCLI_GO_PENDING
#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB1_RDCLI_GBLSEND_PENDING
#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB1_RDCLI_TLB_PENDING
#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB1_RDCLI_OARB_PENDING
#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB1_RDCLI_OSD_PENDING
#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB1_WRCLI0
#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI1
#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI2
#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI3
#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI4
#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI5
#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI6
#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI7
#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI8
#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI9
#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB1_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB1_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB1_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB1_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB1_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB1_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB1_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB1_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB1_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB1_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB1_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB1_WRCLI10
#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_WRCLI11
#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_WRCLI12
#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_WRCLI13
#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_WRCLI14
#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_WRCLI15
#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB1_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB1_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB1_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB1_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB1_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB1_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB1_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB1_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB1_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB1_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB1_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB1_WR_CNTL
#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB1_WR_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB1_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB1_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB1_WR_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB1_WR_GMI_CNTL
#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB1_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB1_WR_ADDR_DAGB
#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB1_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB1_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB1_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB1_WR_CGTT_CLK_CTRL
#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB1_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB1_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB1_WR_ADDR_DAGB_MAX_BURST0
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB1_WR_ADDR_DAGB_MAX_BURST1
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB1_WR_DATA_DAGB
#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB1_WR_DATA_DAGB_MAX_BURST0
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB1_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB1_WR_DATA_DAGB_MAX_BURST1
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB1_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB1_WR_VC0_CNTL
#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC1_CNTL
#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC2_CNTL
#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC3_CNTL
#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC4_CNTL
#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC5_CNTL
#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC6_CNTL
#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_VC7_CNTL
#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB1_WR_CNTL_MISC
#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB1_WR_TLB_CREDIT
#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB1_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB1_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB1_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB1_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB1_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB1_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB1_WR_DATA_CREDIT
#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB1_WR_MISC_CREDIT
#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
//DAGB1_WR_OSD_CREDIT_CNTL1
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
#define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
#define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
#define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
#define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
#define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
#define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
#define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
//DAGB1_WR_OSD_CREDIT_CNTL2
#define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
#define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
#define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
#define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
//DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB1_WRCLI_ASK_PENDING
#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB1_WRCLI_GO_PENDING
#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB1_WRCLI_GBLSEND_PENDING
#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB1_WRCLI_TLB_PENDING
#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB1_WRCLI_OARB_PENDING
#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB1_WRCLI_OSD_PENDING
#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB1_WRCLI_DBUS_ASK_PENDING
#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB1_WRCLI_DBUS_GO_PENDING
#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB1_DAGB_DLY
#define DAGB1_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB1_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB1_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB1_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB1_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB1_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB1_CNTL_MISC
#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
//DAGB1_CNTL_MISC2
#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
#define DAGB1_CNTL_MISC2__HDP_CID__SHIFT                                                                      0xc
#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
#define DAGB1_CNTL_MISC2__HDP_CID_MASK                                                                        0x0001F000L
#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
//DAGB1_FATAL_ERROR_CNTL
#define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT                                                             0x0
#define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM_MASK                                                               0x000003FFL
//DAGB1_FATAL_ERROR_CLEAR
#define DAGB1_FATAL_ERROR_CLEAR__CLEAR__SHIFT                                                                 0x0
#define DAGB1_FATAL_ERROR_CLEAR__CLEAR_MASK                                                                   0x00000001L
//DAGB1_FATAL_ERROR_STATUS0
#define DAGB1_FATAL_ERROR_STATUS0__VALID__SHIFT                                                               0x0
#define DAGB1_FATAL_ERROR_STATUS0__CID__SHIFT                                                                 0x1
#define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT                                                             0x6
#define DAGB1_FATAL_ERROR_STATUS0__VALID_MASK                                                                 0x00000001L
#define DAGB1_FATAL_ERROR_STATUS0__CID_MASK                                                                   0x0000003EL
#define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO_MASK                                                               0xFFFFFFC0L
//DAGB1_FATAL_ERROR_STATUS1
#define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT                                                             0x0
#define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI_MASK                                                               0x0001FFFFL
//DAGB1_FATAL_ERROR_STATUS2
#define DAGB1_FATAL_ERROR_STATUS2__TAG__SHIFT                                                                 0x0
#define DAGB1_FATAL_ERROR_STATUS2__VFID__SHIFT                                                                0x10
#define DAGB1_FATAL_ERROR_STATUS2__VF__SHIFT                                                                  0x14
#define DAGB1_FATAL_ERROR_STATUS2__SPACE__SHIFT                                                               0x15
#define DAGB1_FATAL_ERROR_STATUS2__IO__SHIFT                                                                  0x16
#define DAGB1_FATAL_ERROR_STATUS2__SIZE__SHIFT                                                                0x17
#define DAGB1_FATAL_ERROR_STATUS2__FED__SHIFT                                                                 0x19
#define DAGB1_FATAL_ERROR_STATUS2__TAG_MASK                                                                   0x0000FFFFL
#define DAGB1_FATAL_ERROR_STATUS2__VFID_MASK                                                                  0x000F0000L
#define DAGB1_FATAL_ERROR_STATUS2__VF_MASK                                                                    0x00100000L
#define DAGB1_FATAL_ERROR_STATUS2__SPACE_MASK                                                                 0x00200000L
#define DAGB1_FATAL_ERROR_STATUS2__IO_MASK                                                                    0x00400000L
#define DAGB1_FATAL_ERROR_STATUS2__SIZE_MASK                                                                  0x00800000L
#define DAGB1_FATAL_ERROR_STATUS2__FED_MASK                                                                   0x02000000L
//DAGB1_FATAL_ERROR_STATUS3
#define DAGB1_FATAL_ERROR_STATUS3__OP__SHIFT                                                                  0x6
#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ__SHIFT                                                               0x10
#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ__SHIFT                                                               0x11
#define DAGB1_FATAL_ERROR_STATUS3__SNOOP__SHIFT                                                               0x12
#define DAGB1_FATAL_ERROR_STATUS3__INVAL__SHIFT                                                               0x13
#define DAGB1_FATAL_ERROR_STATUS3__NACK__SHIFT                                                                0x14
#define DAGB1_FATAL_ERROR_STATUS3__RO__SHIFT                                                                  0x16
#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG__SHIFT                                                              0x17
#define DAGB1_FATAL_ERROR_STATUS3__EOP__SHIFT                                                                 0x18
#define DAGB1_FATAL_ERROR_STATUS3__OP_MASK                                                                    0x00001FC0L
#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ_MASK                                                                 0x00010000L
#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ_MASK                                                                 0x00020000L
#define DAGB1_FATAL_ERROR_STATUS3__SNOOP_MASK                                                                 0x00040000L
#define DAGB1_FATAL_ERROR_STATUS3__INVAL_MASK                                                                 0x00080000L
#define DAGB1_FATAL_ERROR_STATUS3__NACK_MASK                                                                  0x00300000L
#define DAGB1_FATAL_ERROR_STATUS3__RO_MASK                                                                    0x00400000L
#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG_MASK                                                                0x00800000L
#define DAGB1_FATAL_ERROR_STATUS3__EOP_MASK                                                                   0x01000000L
//DAGB1_FIFO_EMPTY
#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB1_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
//DAGB1_FIFO_FULL
#define DAGB1_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB1_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
//DAGB1_WR_CREDITS_FULL
#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB1_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
//DAGB1_RD_CREDITS_FULL
#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB1_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
//DAGB1_PERFCOUNTER_LO
#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB1_PERFCOUNTER_HI
#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB1_PERFCOUNTER0_CFG
#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB1_PERFCOUNTER1_CFG
#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB1_PERFCOUNTER2_CFG
#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB1_PERFCOUNTER_RSLT_CNTL
#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB1_L1TLB_REG_RW
#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT                                                        0x2
#define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT                                                          0x4
#define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT                                                        0x5
#define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x6
#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK                                                          0x00000004L
#define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK                                                            0x00000010L
#define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK                                                          0x00000020L
#define DAGB1_L1TLB_REG_RW__RESERVE_MASK                                                                      0xFFFFFFC0L
//DAGB1_RESERVE1
#define DAGB1_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB1_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB1_RESERVE2
#define DAGB1_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB1_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB1_RESERVE3
#define DAGB1_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB1_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB1_RESERVE4
#define DAGB1_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB1_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL


// addressBlock: mmhub_dagb_dagbdec2
//DAGB2_RDCLI0
#define DAGB2_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI1
#define DAGB2_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI2
#define DAGB2_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI3
#define DAGB2_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI4
#define DAGB2_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI5
#define DAGB2_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI6
#define DAGB2_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI7
#define DAGB2_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI8
#define DAGB2_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI9
#define DAGB2_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_RDCLI10
#define DAGB2_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_RDCLI11
#define DAGB2_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_RDCLI12
#define DAGB2_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_RDCLI13
#define DAGB2_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_RDCLI14
#define DAGB2_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_RDCLI15
#define DAGB2_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_RD_CNTL
#define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB2_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB2_RD_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB2_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB2_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB2_RD_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB2_RD_GMI_CNTL
#define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB2_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB2_RD_ADDR_DAGB
#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB2_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB2_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB2_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB2_RD_CGTT_CLK_CTRL
#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB2_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB2_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB2_RD_ADDR_DAGB_MAX_BURST0
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB2_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB2_RD_ADDR_DAGB_MAX_BURST1
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB2_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB2_RD_VC0_CNTL
#define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC1_CNTL
#define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC2_CNTL
#define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC3_CNTL
#define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC4_CNTL
#define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC5_CNTL
#define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC6_CNTL
#define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_VC7_CNTL
#define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_RD_CNTL_MISC
#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB2_RD_TLB_CREDIT
#define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB2_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB2_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB2_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB2_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB2_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB2_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB2_RD_RDRET_CREDIT_CNTL
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
#define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
#define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
#define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
//DAGB2_RD_RDRET_CREDIT_CNTL2
#define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT                                                         0x0
#define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT                                                        0x6
#define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0xc
#define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK                                                           0x0000003FL
#define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK                                                          0x00000FC0L
#define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0007F000L
//DAGB2_RDCLI_ASK_PENDING
#define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB2_RDCLI_GO_PENDING
#define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB2_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB2_RDCLI_GBLSEND_PENDING
#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB2_RDCLI_TLB_PENDING
#define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB2_RDCLI_OARB_PENDING
#define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB2_RDCLI_OSD_PENDING
#define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB2_WRCLI0
#define DAGB2_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI1
#define DAGB2_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI2
#define DAGB2_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI3
#define DAGB2_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI4
#define DAGB2_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI5
#define DAGB2_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI6
#define DAGB2_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI7
#define DAGB2_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI8
#define DAGB2_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI9
#define DAGB2_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB2_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB2_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB2_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB2_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB2_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB2_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB2_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB2_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB2_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB2_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB2_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB2_WRCLI10
#define DAGB2_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_WRCLI11
#define DAGB2_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_WRCLI12
#define DAGB2_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_WRCLI13
#define DAGB2_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_WRCLI14
#define DAGB2_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_WRCLI15
#define DAGB2_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB2_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB2_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB2_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB2_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB2_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB2_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB2_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB2_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB2_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB2_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB2_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB2_WR_CNTL
#define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB2_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB2_WR_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB2_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB2_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB2_WR_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB2_WR_GMI_CNTL
#define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB2_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB2_WR_ADDR_DAGB
#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB2_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB2_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB2_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB2_WR_CGTT_CLK_CTRL
#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB2_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB2_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB2_WR_ADDR_DAGB_MAX_BURST0
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB2_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB2_WR_ADDR_DAGB_MAX_BURST1
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB2_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB2_WR_DATA_DAGB
#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB2_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB2_WR_DATA_DAGB_MAX_BURST0
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB2_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB2_WR_DATA_DAGB_MAX_BURST1
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB2_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB2_WR_VC0_CNTL
#define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC1_CNTL
#define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC2_CNTL
#define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC3_CNTL
#define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC4_CNTL
#define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC5_CNTL
#define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC6_CNTL
#define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_VC7_CNTL
#define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB2_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB2_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB2_WR_CNTL_MISC
#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB2_WR_TLB_CREDIT
#define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB2_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB2_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB2_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB2_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB2_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB2_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB2_WR_DATA_CREDIT
#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB2_WR_MISC_CREDIT
#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
//DAGB2_WR_OSD_CREDIT_CNTL1
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
#define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
#define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
#define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
#define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
#define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
#define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
#define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
//DAGB2_WR_OSD_CREDIT_CNTL2
#define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
#define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
#define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
#define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
//DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
//DAGB2_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB2_WRCLI_ASK_PENDING
#define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB2_WRCLI_GO_PENDING
#define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB2_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB2_WRCLI_GBLSEND_PENDING
#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB2_WRCLI_TLB_PENDING
#define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB2_WRCLI_OARB_PENDING
#define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB2_WRCLI_OSD_PENDING
#define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB2_WRCLI_DBUS_ASK_PENDING
#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB2_WRCLI_DBUS_GO_PENDING
#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB2_DAGB_DLY
#define DAGB2_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB2_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB2_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB2_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB2_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB2_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB2_CNTL_MISC
#define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
#define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
#define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
#define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
#define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
#define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
#define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
#define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
#define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
#define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
#define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
#define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
#define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
#define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
#define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
#define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
#define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
#define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
//DAGB2_CNTL_MISC2
#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
#define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
#define DAGB2_CNTL_MISC2__HDP_CID__SHIFT                                                                      0xc
#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
#define DAGB2_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
#define DAGB2_CNTL_MISC2__HDP_CID_MASK                                                                        0x0001F000L
#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
//DAGB2_FATAL_ERROR_CNTL
#define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT                                                             0x0
#define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM_MASK                                                               0x000003FFL
//DAGB2_FATAL_ERROR_CLEAR
#define DAGB2_FATAL_ERROR_CLEAR__CLEAR__SHIFT                                                                 0x0
#define DAGB2_FATAL_ERROR_CLEAR__CLEAR_MASK                                                                   0x00000001L
//DAGB2_FATAL_ERROR_STATUS0
#define DAGB2_FATAL_ERROR_STATUS0__VALID__SHIFT                                                               0x0
#define DAGB2_FATAL_ERROR_STATUS0__CID__SHIFT                                                                 0x1
#define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT                                                             0x6
#define DAGB2_FATAL_ERROR_STATUS0__VALID_MASK                                                                 0x00000001L
#define DAGB2_FATAL_ERROR_STATUS0__CID_MASK                                                                   0x0000003EL
#define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO_MASK                                                               0xFFFFFFC0L
//DAGB2_FATAL_ERROR_STATUS1
#define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT                                                             0x0
#define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI_MASK                                                               0x0001FFFFL
//DAGB2_FATAL_ERROR_STATUS2
#define DAGB2_FATAL_ERROR_STATUS2__TAG__SHIFT                                                                 0x0
#define DAGB2_FATAL_ERROR_STATUS2__VFID__SHIFT                                                                0x10
#define DAGB2_FATAL_ERROR_STATUS2__VF__SHIFT                                                                  0x14
#define DAGB2_FATAL_ERROR_STATUS2__SPACE__SHIFT                                                               0x15
#define DAGB2_FATAL_ERROR_STATUS2__IO__SHIFT                                                                  0x16
#define DAGB2_FATAL_ERROR_STATUS2__SIZE__SHIFT                                                                0x17
#define DAGB2_FATAL_ERROR_STATUS2__FED__SHIFT                                                                 0x19
#define DAGB2_FATAL_ERROR_STATUS2__TAG_MASK                                                                   0x0000FFFFL
#define DAGB2_FATAL_ERROR_STATUS2__VFID_MASK                                                                  0x000F0000L
#define DAGB2_FATAL_ERROR_STATUS2__VF_MASK                                                                    0x00100000L
#define DAGB2_FATAL_ERROR_STATUS2__SPACE_MASK                                                                 0x00200000L
#define DAGB2_FATAL_ERROR_STATUS2__IO_MASK                                                                    0x00400000L
#define DAGB2_FATAL_ERROR_STATUS2__SIZE_MASK                                                                  0x00800000L
#define DAGB2_FATAL_ERROR_STATUS2__FED_MASK                                                                   0x02000000L
//DAGB2_FATAL_ERROR_STATUS3
#define DAGB2_FATAL_ERROR_STATUS3__OP__SHIFT                                                                  0x6
#define DAGB2_FATAL_ERROR_STATUS3__WRTMZ__SHIFT                                                               0x10
#define DAGB2_FATAL_ERROR_STATUS3__RDTMZ__SHIFT                                                               0x11
#define DAGB2_FATAL_ERROR_STATUS3__SNOOP__SHIFT                                                               0x12
#define DAGB2_FATAL_ERROR_STATUS3__INVAL__SHIFT                                                               0x13
#define DAGB2_FATAL_ERROR_STATUS3__NACK__SHIFT                                                                0x14
#define DAGB2_FATAL_ERROR_STATUS3__RO__SHIFT                                                                  0x16
#define DAGB2_FATAL_ERROR_STATUS3__MEMLOG__SHIFT                                                              0x17
#define DAGB2_FATAL_ERROR_STATUS3__EOP__SHIFT                                                                 0x18
#define DAGB2_FATAL_ERROR_STATUS3__OP_MASK                                                                    0x00001FC0L
#define DAGB2_FATAL_ERROR_STATUS3__WRTMZ_MASK                                                                 0x00010000L
#define DAGB2_FATAL_ERROR_STATUS3__RDTMZ_MASK                                                                 0x00020000L
#define DAGB2_FATAL_ERROR_STATUS3__SNOOP_MASK                                                                 0x00040000L
#define DAGB2_FATAL_ERROR_STATUS3__INVAL_MASK                                                                 0x00080000L
#define DAGB2_FATAL_ERROR_STATUS3__NACK_MASK                                                                  0x00300000L
#define DAGB2_FATAL_ERROR_STATUS3__RO_MASK                                                                    0x00400000L
#define DAGB2_FATAL_ERROR_STATUS3__MEMLOG_MASK                                                                0x00800000L
#define DAGB2_FATAL_ERROR_STATUS3__EOP_MASK                                                                   0x01000000L
//DAGB2_FIFO_EMPTY
#define DAGB2_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB2_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
//DAGB2_FIFO_FULL
#define DAGB2_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB2_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
//DAGB2_WR_CREDITS_FULL
#define DAGB2_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB2_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
//DAGB2_RD_CREDITS_FULL
#define DAGB2_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB2_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
//DAGB2_PERFCOUNTER_LO
#define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB2_PERFCOUNTER_HI
#define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB2_PERFCOUNTER0_CFG
#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB2_PERFCOUNTER1_CFG
#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB2_PERFCOUNTER2_CFG
#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB2_PERFCOUNTER_RSLT_CNTL
#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB2_L1TLB_REG_RW
#define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT                                                        0x2
#define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT                                                          0x4
#define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT                                                        0x5
#define DAGB2_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x6
#define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK                                                          0x00000004L
#define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK                                                            0x00000010L
#define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK                                                          0x00000020L
#define DAGB2_L1TLB_REG_RW__RESERVE_MASK                                                                      0xFFFFFFC0L
//DAGB2_RESERVE1
#define DAGB2_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB2_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB2_RESERVE2
#define DAGB2_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB2_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB2_RESERVE3
#define DAGB2_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB2_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB2_RESERVE4
#define DAGB2_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB2_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL


// addressBlock: mmhub_dagb_dagbdec3
//DAGB3_RDCLI0
#define DAGB3_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI1
#define DAGB3_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI2
#define DAGB3_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI3
#define DAGB3_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI4
#define DAGB3_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI5
#define DAGB3_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI6
#define DAGB3_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI7
#define DAGB3_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI8
#define DAGB3_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI9
#define DAGB3_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_RDCLI10
#define DAGB3_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_RDCLI11
#define DAGB3_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_RDCLI12
#define DAGB3_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_RDCLI13
#define DAGB3_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_RDCLI14
#define DAGB3_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_RDCLI15
#define DAGB3_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_RD_CNTL
#define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB3_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB3_RD_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB3_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB3_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB3_RD_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB3_RD_GMI_CNTL
#define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB3_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB3_RD_ADDR_DAGB
#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB3_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB3_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB3_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB3_RD_CGTT_CLK_CTRL
#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB3_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB3_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB3_RD_ADDR_DAGB_MAX_BURST0
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB3_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB3_RD_ADDR_DAGB_MAX_BURST1
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB3_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB3_RD_VC0_CNTL
#define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC1_CNTL
#define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC2_CNTL
#define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC3_CNTL
#define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC4_CNTL
#define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC5_CNTL
#define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC6_CNTL
#define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_VC7_CNTL
#define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_RD_CNTL_MISC
#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB3_RD_TLB_CREDIT
#define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB3_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB3_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB3_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB3_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB3_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB3_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB3_RD_RDRET_CREDIT_CNTL
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
#define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
#define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
#define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
//DAGB3_RD_RDRET_CREDIT_CNTL2
#define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT                                                         0x0
#define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT                                                        0x6
#define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0xc
#define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK                                                           0x0000003FL
#define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK                                                          0x00000FC0L
#define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0007F000L
//DAGB3_RDCLI_ASK_PENDING
#define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB3_RDCLI_GO_PENDING
#define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB3_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB3_RDCLI_GBLSEND_PENDING
#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB3_RDCLI_TLB_PENDING
#define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB3_RDCLI_OARB_PENDING
#define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB3_RDCLI_OSD_PENDING
#define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB3_WRCLI0
#define DAGB3_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI1
#define DAGB3_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI2
#define DAGB3_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI3
#define DAGB3_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI4
#define DAGB3_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI5
#define DAGB3_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI6
#define DAGB3_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI7
#define DAGB3_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI8
#define DAGB3_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI9
#define DAGB3_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB3_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB3_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB3_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB3_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB3_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB3_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB3_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB3_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB3_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB3_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB3_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB3_WRCLI10
#define DAGB3_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_WRCLI11
#define DAGB3_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_WRCLI12
#define DAGB3_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_WRCLI13
#define DAGB3_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_WRCLI14
#define DAGB3_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_WRCLI15
#define DAGB3_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB3_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB3_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB3_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB3_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB3_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB3_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB3_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB3_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB3_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB3_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB3_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB3_WR_CNTL
#define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB3_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB3_WR_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB3_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB3_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB3_WR_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB3_WR_GMI_CNTL
#define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB3_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB3_WR_ADDR_DAGB
#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB3_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB3_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB3_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB3_WR_CGTT_CLK_CTRL
#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB3_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB3_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB3_WR_ADDR_DAGB_MAX_BURST0
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB3_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB3_WR_ADDR_DAGB_MAX_BURST1
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB3_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB3_WR_DATA_DAGB
#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB3_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB3_WR_DATA_DAGB_MAX_BURST0
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB3_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB3_WR_DATA_DAGB_MAX_BURST1
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB3_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB3_WR_VC0_CNTL
#define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC1_CNTL
#define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC2_CNTL
#define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC3_CNTL
#define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC4_CNTL
#define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC5_CNTL
#define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC6_CNTL
#define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_VC7_CNTL
#define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB3_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB3_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB3_WR_CNTL_MISC
#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB3_WR_TLB_CREDIT
#define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB3_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB3_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB3_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB3_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB3_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB3_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB3_WR_DATA_CREDIT
#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB3_WR_MISC_CREDIT
#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
//DAGB3_WR_OSD_CREDIT_CNTL1
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
#define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
#define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
#define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
#define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
#define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
#define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
#define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
//DAGB3_WR_OSD_CREDIT_CNTL2
#define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
#define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
#define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
#define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
//DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
//DAGB3_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB3_WRCLI_ASK_PENDING
#define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB3_WRCLI_GO_PENDING
#define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB3_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB3_WRCLI_GBLSEND_PENDING
#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB3_WRCLI_TLB_PENDING
#define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB3_WRCLI_OARB_PENDING
#define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB3_WRCLI_OSD_PENDING
#define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB3_WRCLI_DBUS_ASK_PENDING
#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB3_WRCLI_DBUS_GO_PENDING
#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB3_DAGB_DLY
#define DAGB3_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB3_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB3_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB3_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB3_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB3_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB3_CNTL_MISC
#define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
#define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
#define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
#define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
#define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
#define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
#define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
#define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
#define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
#define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
#define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
#define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
#define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
#define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
#define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
#define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
#define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
#define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
//DAGB3_CNTL_MISC2
#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
#define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
#define DAGB3_CNTL_MISC2__HDP_CID__SHIFT                                                                      0xc
#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
#define DAGB3_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
#define DAGB3_CNTL_MISC2__HDP_CID_MASK                                                                        0x0001F000L
#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
//DAGB3_FATAL_ERROR_CNTL
#define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT                                                             0x0
#define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM_MASK                                                               0x000003FFL
//DAGB3_FATAL_ERROR_CLEAR
#define DAGB3_FATAL_ERROR_CLEAR__CLEAR__SHIFT                                                                 0x0
#define DAGB3_FATAL_ERROR_CLEAR__CLEAR_MASK                                                                   0x00000001L
//DAGB3_FATAL_ERROR_STATUS0
#define DAGB3_FATAL_ERROR_STATUS0__VALID__SHIFT                                                               0x0
#define DAGB3_FATAL_ERROR_STATUS0__CID__SHIFT                                                                 0x1
#define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT                                                             0x6
#define DAGB3_FATAL_ERROR_STATUS0__VALID_MASK                                                                 0x00000001L
#define DAGB3_FATAL_ERROR_STATUS0__CID_MASK                                                                   0x0000003EL
#define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO_MASK                                                               0xFFFFFFC0L
//DAGB3_FATAL_ERROR_STATUS1
#define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT                                                             0x0
#define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI_MASK                                                               0x0001FFFFL
//DAGB3_FATAL_ERROR_STATUS2
#define DAGB3_FATAL_ERROR_STATUS2__TAG__SHIFT                                                                 0x0
#define DAGB3_FATAL_ERROR_STATUS2__VFID__SHIFT                                                                0x10
#define DAGB3_FATAL_ERROR_STATUS2__VF__SHIFT                                                                  0x14
#define DAGB3_FATAL_ERROR_STATUS2__SPACE__SHIFT                                                               0x15
#define DAGB3_FATAL_ERROR_STATUS2__IO__SHIFT                                                                  0x16
#define DAGB3_FATAL_ERROR_STATUS2__SIZE__SHIFT                                                                0x17
#define DAGB3_FATAL_ERROR_STATUS2__FED__SHIFT                                                                 0x19
#define DAGB3_FATAL_ERROR_STATUS2__TAG_MASK                                                                   0x0000FFFFL
#define DAGB3_FATAL_ERROR_STATUS2__VFID_MASK                                                                  0x000F0000L
#define DAGB3_FATAL_ERROR_STATUS2__VF_MASK                                                                    0x00100000L
#define DAGB3_FATAL_ERROR_STATUS2__SPACE_MASK                                                                 0x00200000L
#define DAGB3_FATAL_ERROR_STATUS2__IO_MASK                                                                    0x00400000L
#define DAGB3_FATAL_ERROR_STATUS2__SIZE_MASK                                                                  0x00800000L
#define DAGB3_FATAL_ERROR_STATUS2__FED_MASK                                                                   0x02000000L
//DAGB3_FATAL_ERROR_STATUS3
#define DAGB3_FATAL_ERROR_STATUS3__OP__SHIFT                                                                  0x6
#define DAGB3_FATAL_ERROR_STATUS3__WRTMZ__SHIFT                                                               0x10
#define DAGB3_FATAL_ERROR_STATUS3__RDTMZ__SHIFT                                                               0x11
#define DAGB3_FATAL_ERROR_STATUS3__SNOOP__SHIFT                                                               0x12
#define DAGB3_FATAL_ERROR_STATUS3__INVAL__SHIFT                                                               0x13
#define DAGB3_FATAL_ERROR_STATUS3__NACK__SHIFT                                                                0x14
#define DAGB3_FATAL_ERROR_STATUS3__RO__SHIFT                                                                  0x16
#define DAGB3_FATAL_ERROR_STATUS3__MEMLOG__SHIFT                                                              0x17
#define DAGB3_FATAL_ERROR_STATUS3__EOP__SHIFT                                                                 0x18
#define DAGB3_FATAL_ERROR_STATUS3__OP_MASK                                                                    0x00001FC0L
#define DAGB3_FATAL_ERROR_STATUS3__WRTMZ_MASK                                                                 0x00010000L
#define DAGB3_FATAL_ERROR_STATUS3__RDTMZ_MASK                                                                 0x00020000L
#define DAGB3_FATAL_ERROR_STATUS3__SNOOP_MASK                                                                 0x00040000L
#define DAGB3_FATAL_ERROR_STATUS3__INVAL_MASK                                                                 0x00080000L
#define DAGB3_FATAL_ERROR_STATUS3__NACK_MASK                                                                  0x00300000L
#define DAGB3_FATAL_ERROR_STATUS3__RO_MASK                                                                    0x00400000L
#define DAGB3_FATAL_ERROR_STATUS3__MEMLOG_MASK                                                                0x00800000L
#define DAGB3_FATAL_ERROR_STATUS3__EOP_MASK                                                                   0x01000000L
//DAGB3_FIFO_EMPTY
#define DAGB3_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB3_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
//DAGB3_FIFO_FULL
#define DAGB3_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB3_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
//DAGB3_WR_CREDITS_FULL
#define DAGB3_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB3_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
//DAGB3_RD_CREDITS_FULL
#define DAGB3_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB3_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
//DAGB3_PERFCOUNTER_LO
#define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB3_PERFCOUNTER_HI
#define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB3_PERFCOUNTER0_CFG
#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB3_PERFCOUNTER1_CFG
#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB3_PERFCOUNTER2_CFG
#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB3_PERFCOUNTER_RSLT_CNTL
#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB3_L1TLB_REG_RW
#define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT                                                        0x2
#define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT                                                          0x4
#define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT                                                        0x5
#define DAGB3_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x6
#define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK                                                          0x00000004L
#define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK                                                            0x00000010L
#define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK                                                          0x00000020L
#define DAGB3_L1TLB_REG_RW__RESERVE_MASK                                                                      0xFFFFFFC0L
//DAGB3_RESERVE1
#define DAGB3_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB3_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB3_RESERVE2
#define DAGB3_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB3_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB3_RESERVE3
#define DAGB3_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB3_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB3_RESERVE4
#define DAGB3_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB3_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL


// addressBlock: mmhub_dagb_dagbdec4
//DAGB4_RDCLI0
#define DAGB4_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI1
#define DAGB4_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI2
#define DAGB4_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI3
#define DAGB4_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI4
#define DAGB4_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI5
#define DAGB4_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI6
#define DAGB4_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI7
#define DAGB4_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI8
#define DAGB4_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI9
#define DAGB4_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_RDCLI10
#define DAGB4_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_RDCLI11
#define DAGB4_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_RDCLI12
#define DAGB4_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_RDCLI13
#define DAGB4_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_RDCLI14
#define DAGB4_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_RDCLI15
#define DAGB4_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_RD_CNTL
#define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB4_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB4_RD_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB4_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB4_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB4_RD_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB4_RD_GMI_CNTL
#define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB4_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB4_RD_ADDR_DAGB
#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB4_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB4_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB4_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB4_RD_CGTT_CLK_CTRL
#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB4_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB4_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB4_RD_ADDR_DAGB_MAX_BURST0
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB4_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB4_RD_ADDR_DAGB_MAX_BURST1
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB4_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB4_RD_VC0_CNTL
#define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC1_CNTL
#define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC2_CNTL
#define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC3_CNTL
#define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC4_CNTL
#define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC5_CNTL
#define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC6_CNTL
#define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_VC7_CNTL
#define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_RD_CNTL_MISC
#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB4_RD_TLB_CREDIT
#define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB4_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB4_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB4_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB4_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB4_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB4_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB4_RD_RDRET_CREDIT_CNTL
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
#define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
#define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
#define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
//DAGB4_RD_RDRET_CREDIT_CNTL2
#define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT                                                         0x0
#define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT                                                        0x6
#define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0xc
#define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK                                                           0x0000003FL
#define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK                                                          0x00000FC0L
#define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0007F000L
//DAGB4_RDCLI_ASK_PENDING
#define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB4_RDCLI_GO_PENDING
#define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB4_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB4_RDCLI_GBLSEND_PENDING
#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB4_RDCLI_TLB_PENDING
#define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB4_RDCLI_OARB_PENDING
#define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB4_RDCLI_OSD_PENDING
#define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB4_WRCLI0
#define DAGB4_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI1
#define DAGB4_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI2
#define DAGB4_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI3
#define DAGB4_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI4
#define DAGB4_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI5
#define DAGB4_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI6
#define DAGB4_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI7
#define DAGB4_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI8
#define DAGB4_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI9
#define DAGB4_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB4_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB4_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB4_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB4_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB4_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB4_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB4_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB4_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB4_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB4_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB4_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB4_WRCLI10
#define DAGB4_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_WRCLI11
#define DAGB4_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_WRCLI12
#define DAGB4_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_WRCLI13
#define DAGB4_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_WRCLI14
#define DAGB4_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_WRCLI15
#define DAGB4_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB4_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB4_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB4_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB4_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB4_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB4_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB4_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB4_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB4_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB4_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB4_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB4_WR_CNTL
#define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB4_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB4_WR_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB4_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB4_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB4_WR_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB4_WR_GMI_CNTL
#define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB4_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB4_WR_ADDR_DAGB
#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB4_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB4_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB4_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB4_WR_CGTT_CLK_CTRL
#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB4_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB4_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB4_WR_ADDR_DAGB_MAX_BURST0
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB4_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB4_WR_ADDR_DAGB_MAX_BURST1
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB4_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB4_WR_DATA_DAGB
#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB4_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB4_WR_DATA_DAGB_MAX_BURST0
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB4_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB4_WR_DATA_DAGB_MAX_BURST1
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB4_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB4_WR_VC0_CNTL
#define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC1_CNTL
#define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC2_CNTL
#define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC3_CNTL
#define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC4_CNTL
#define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC5_CNTL
#define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC6_CNTL
#define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_VC7_CNTL
#define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB4_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB4_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB4_WR_CNTL_MISC
#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB4_WR_TLB_CREDIT
#define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB4_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB4_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB4_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB4_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB4_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB4_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB4_WR_DATA_CREDIT
#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB4_WR_MISC_CREDIT
#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
//DAGB4_WR_OSD_CREDIT_CNTL1
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
#define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
#define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
#define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
#define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
#define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
#define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
#define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
//DAGB4_WR_OSD_CREDIT_CNTL2
#define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
#define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
#define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
#define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
//DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
//DAGB4_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB4_WRCLI_ASK_PENDING
#define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB4_WRCLI_GO_PENDING
#define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB4_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB4_WRCLI_GBLSEND_PENDING
#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB4_WRCLI_TLB_PENDING
#define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB4_WRCLI_OARB_PENDING
#define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB4_WRCLI_OSD_PENDING
#define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB4_WRCLI_DBUS_ASK_PENDING
#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB4_WRCLI_DBUS_GO_PENDING
#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB4_DAGB_DLY
#define DAGB4_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB4_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB4_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB4_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB4_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB4_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB4_CNTL_MISC
#define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
#define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
#define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
#define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
#define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
#define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
#define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
#define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
#define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
#define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
#define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
#define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
#define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
#define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
#define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
#define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
#define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
#define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
//DAGB4_CNTL_MISC2
#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
#define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
#define DAGB4_CNTL_MISC2__HDP_CID__SHIFT                                                                      0xc
#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
#define DAGB4_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
#define DAGB4_CNTL_MISC2__HDP_CID_MASK                                                                        0x0001F000L
#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
//DAGB4_FATAL_ERROR_CNTL
#define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT                                                             0x0
#define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM_MASK                                                               0x000003FFL
//DAGB4_FATAL_ERROR_CLEAR
#define DAGB4_FATAL_ERROR_CLEAR__CLEAR__SHIFT                                                                 0x0
#define DAGB4_FATAL_ERROR_CLEAR__CLEAR_MASK                                                                   0x00000001L
//DAGB4_FATAL_ERROR_STATUS0
#define DAGB4_FATAL_ERROR_STATUS0__VALID__SHIFT                                                               0x0
#define DAGB4_FATAL_ERROR_STATUS0__CID__SHIFT                                                                 0x1
#define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT                                                             0x6
#define DAGB4_FATAL_ERROR_STATUS0__VALID_MASK                                                                 0x00000001L
#define DAGB4_FATAL_ERROR_STATUS0__CID_MASK                                                                   0x0000003EL
#define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO_MASK                                                               0xFFFFFFC0L
//DAGB4_FATAL_ERROR_STATUS1
#define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT                                                             0x0
#define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI_MASK                                                               0x0001FFFFL
//DAGB4_FATAL_ERROR_STATUS2
#define DAGB4_FATAL_ERROR_STATUS2__TAG__SHIFT                                                                 0x0
#define DAGB4_FATAL_ERROR_STATUS2__VFID__SHIFT                                                                0x10
#define DAGB4_FATAL_ERROR_STATUS2__VF__SHIFT                                                                  0x14
#define DAGB4_FATAL_ERROR_STATUS2__SPACE__SHIFT                                                               0x15
#define DAGB4_FATAL_ERROR_STATUS2__IO__SHIFT                                                                  0x16
#define DAGB4_FATAL_ERROR_STATUS2__SIZE__SHIFT                                                                0x17
#define DAGB4_FATAL_ERROR_STATUS2__FED__SHIFT                                                                 0x19
#define DAGB4_FATAL_ERROR_STATUS2__TAG_MASK                                                                   0x0000FFFFL
#define DAGB4_FATAL_ERROR_STATUS2__VFID_MASK                                                                  0x000F0000L
#define DAGB4_FATAL_ERROR_STATUS2__VF_MASK                                                                    0x00100000L
#define DAGB4_FATAL_ERROR_STATUS2__SPACE_MASK                                                                 0x00200000L
#define DAGB4_FATAL_ERROR_STATUS2__IO_MASK                                                                    0x00400000L
#define DAGB4_FATAL_ERROR_STATUS2__SIZE_MASK                                                                  0x00800000L
#define DAGB4_FATAL_ERROR_STATUS2__FED_MASK                                                                   0x02000000L
//DAGB4_FATAL_ERROR_STATUS3
#define DAGB4_FATAL_ERROR_STATUS3__OP__SHIFT                                                                  0x6
#define DAGB4_FATAL_ERROR_STATUS3__WRTMZ__SHIFT                                                               0x10
#define DAGB4_FATAL_ERROR_STATUS3__RDTMZ__SHIFT                                                               0x11
#define DAGB4_FATAL_ERROR_STATUS3__SNOOP__SHIFT                                                               0x12
#define DAGB4_FATAL_ERROR_STATUS3__INVAL__SHIFT                                                               0x13
#define DAGB4_FATAL_ERROR_STATUS3__NACK__SHIFT                                                                0x14
#define DAGB4_FATAL_ERROR_STATUS3__RO__SHIFT                                                                  0x16
#define DAGB4_FATAL_ERROR_STATUS3__MEMLOG__SHIFT                                                              0x17
#define DAGB4_FATAL_ERROR_STATUS3__EOP__SHIFT                                                                 0x18
#define DAGB4_FATAL_ERROR_STATUS3__OP_MASK                                                                    0x00001FC0L
#define DAGB4_FATAL_ERROR_STATUS3__WRTMZ_MASK                                                                 0x00010000L
#define DAGB4_FATAL_ERROR_STATUS3__RDTMZ_MASK                                                                 0x00020000L
#define DAGB4_FATAL_ERROR_STATUS3__SNOOP_MASK                                                                 0x00040000L
#define DAGB4_FATAL_ERROR_STATUS3__INVAL_MASK                                                                 0x00080000L
#define DAGB4_FATAL_ERROR_STATUS3__NACK_MASK                                                                  0x00300000L
#define DAGB4_FATAL_ERROR_STATUS3__RO_MASK                                                                    0x00400000L
#define DAGB4_FATAL_ERROR_STATUS3__MEMLOG_MASK                                                                0x00800000L
#define DAGB4_FATAL_ERROR_STATUS3__EOP_MASK                                                                   0x01000000L
//DAGB4_FIFO_EMPTY
#define DAGB4_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB4_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
//DAGB4_FIFO_FULL
#define DAGB4_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB4_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
//DAGB4_WR_CREDITS_FULL
#define DAGB4_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB4_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
//DAGB4_RD_CREDITS_FULL
#define DAGB4_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB4_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
//DAGB4_PERFCOUNTER_LO
#define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB4_PERFCOUNTER_HI
#define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB4_PERFCOUNTER0_CFG
#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB4_PERFCOUNTER1_CFG
#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB4_PERFCOUNTER2_CFG
#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB4_PERFCOUNTER_RSLT_CNTL
#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB4_L1TLB_REG_RW
#define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT                                                        0x2
#define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT                                                          0x4
#define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT                                                        0x5
#define DAGB4_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x6
#define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK                                                          0x00000004L
#define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK                                                            0x00000010L
#define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK                                                          0x00000020L
#define DAGB4_L1TLB_REG_RW__RESERVE_MASK                                                                      0xFFFFFFC0L
//DAGB4_RESERVE1
#define DAGB4_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB4_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB4_RESERVE2
#define DAGB4_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB4_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB4_RESERVE3
#define DAGB4_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB4_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB4_RESERVE4
#define DAGB4_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB4_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL


// addressBlock: mmhub_dagb_dagbdec5
//DAGB5_RDCLI0
#define DAGB5_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI1
#define DAGB5_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI2
#define DAGB5_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI3
#define DAGB5_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI4
#define DAGB5_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI5
#define DAGB5_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI6
#define DAGB5_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI7
#define DAGB5_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI8
#define DAGB5_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI9
#define DAGB5_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_RDCLI10
#define DAGB5_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_RDCLI11
#define DAGB5_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_RDCLI12
#define DAGB5_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_RDCLI13
#define DAGB5_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_RDCLI14
#define DAGB5_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_RDCLI15
#define DAGB5_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_RD_CNTL
#define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB5_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB5_RD_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB5_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB5_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB5_RD_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB5_RD_GMI_CNTL
#define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB5_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB5_RD_ADDR_DAGB
#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB5_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB5_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB5_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB5_RD_CGTT_CLK_CTRL
#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB5_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB5_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB5_RD_ADDR_DAGB_MAX_BURST0
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB5_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB5_RD_ADDR_DAGB_MAX_BURST1
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB5_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB5_RD_VC0_CNTL
#define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC1_CNTL
#define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC2_CNTL
#define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC3_CNTL
#define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC4_CNTL
#define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC5_CNTL
#define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC6_CNTL
#define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_VC7_CNTL
#define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_RD_CNTL_MISC
#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB5_RD_TLB_CREDIT
#define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB5_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB5_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB5_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB5_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB5_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB5_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB5_RD_RDRET_CREDIT_CNTL
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
#define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
#define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
#define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
//DAGB5_RD_RDRET_CREDIT_CNTL2
#define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT                                                         0x0
#define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT                                                        0x6
#define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0xc
#define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK                                                           0x0000003FL
#define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK                                                          0x00000FC0L
#define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0007F000L
//DAGB5_RDCLI_ASK_PENDING
#define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB5_RDCLI_GO_PENDING
#define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB5_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB5_RDCLI_GBLSEND_PENDING
#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB5_RDCLI_TLB_PENDING
#define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB5_RDCLI_OARB_PENDING
#define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB5_RDCLI_OSD_PENDING
#define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB5_WRCLI0
#define DAGB5_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI1
#define DAGB5_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI2
#define DAGB5_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI3
#define DAGB5_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI4
#define DAGB5_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI5
#define DAGB5_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI6
#define DAGB5_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI7
#define DAGB5_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI8
#define DAGB5_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI9
#define DAGB5_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB5_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB5_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB5_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB5_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB5_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB5_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB5_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB5_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB5_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB5_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB5_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB5_WRCLI10
#define DAGB5_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_WRCLI11
#define DAGB5_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_WRCLI12
#define DAGB5_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_WRCLI13
#define DAGB5_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_WRCLI14
#define DAGB5_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_WRCLI15
#define DAGB5_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB5_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB5_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB5_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB5_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB5_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB5_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB5_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB5_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB5_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB5_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB5_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB5_WR_CNTL
#define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
#define DAGB5_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
#define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
#define DAGB5_WR_CNTL__FIX_JUMP__SHIFT                                                                        0x1a
#define DAGB5_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
#define DAGB5_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
#define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
#define DAGB5_WR_CNTL__FIX_JUMP_MASK                                                                          0x04000000L
//DAGB5_WR_GMI_CNTL
#define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
#define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
#define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
#define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
#define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
#define DAGB5_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
#define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
#define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
//DAGB5_WR_ADDR_DAGB
#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB5_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB5_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB5_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
//DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
//DAGB5_WR_CGTT_CLK_CTRL
#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
//DAGB5_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB5_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
//DAGB5_WR_ADDR_DAGB_MAX_BURST0
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB5_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB5_WR_ADDR_DAGB_MAX_BURST1
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB5_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB5_WR_DATA_DAGB
#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB5_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB5_WR_DATA_DAGB_MAX_BURST0
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB5_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB5_WR_DATA_DAGB_MAX_BURST1
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB5_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB5_WR_VC0_CNTL
#define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC1_CNTL
#define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC2_CNTL
#define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC3_CNTL
#define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC4_CNTL
#define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC5_CNTL
#define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC6_CNTL
#define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_VC7_CNTL
#define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB5_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB5_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB5_WR_CNTL_MISC
#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
#define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
#define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
//DAGB5_WR_TLB_CREDIT
#define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB5_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB5_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB5_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB5_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB5_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB5_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB5_WR_DATA_CREDIT
#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB5_WR_MISC_CREDIT
#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
//DAGB5_WR_OSD_CREDIT_CNTL1
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
#define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
#define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
#define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
#define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
#define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
#define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
#define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
//DAGB5_WR_OSD_CREDIT_CNTL2
#define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
#define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
#define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
#define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
//DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
//DAGB5_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB5_WRCLI_ASK_PENDING
#define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB5_WRCLI_GO_PENDING
#define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB5_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB5_WRCLI_GBLSEND_PENDING
#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB5_WRCLI_TLB_PENDING
#define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB5_WRCLI_OARB_PENDING
#define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB5_WRCLI_OSD_PENDING
#define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB5_WRCLI_DBUS_ASK_PENDING
#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB5_WRCLI_DBUS_GO_PENDING
#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB5_DAGB_DLY
#define DAGB5_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB5_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB5_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB5_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB5_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB5_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB5_CNTL_MISC
#define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
#define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
#define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
#define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
#define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
#define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
#define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
#define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
#define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
#define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
#define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
#define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
#define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
#define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
#define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
#define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
#define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
#define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
//DAGB5_CNTL_MISC2
#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
#define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
#define DAGB5_CNTL_MISC2__HDP_CID__SHIFT                                                                      0xc
#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
#define DAGB5_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
#define DAGB5_CNTL_MISC2__HDP_CID_MASK                                                                        0x0001F000L
#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
//DAGB5_FATAL_ERROR_CNTL
#define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT                                                             0x0
#define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM_MASK                                                               0x000003FFL
//DAGB5_FATAL_ERROR_CLEAR
#define DAGB5_FATAL_ERROR_CLEAR__CLEAR__SHIFT                                                                 0x0
#define DAGB5_FATAL_ERROR_CLEAR__CLEAR_MASK                                                                   0x00000001L
//DAGB5_FATAL_ERROR_STATUS0
#define DAGB5_FATAL_ERROR_STATUS0__VALID__SHIFT                                                               0x0
#define DAGB5_FATAL_ERROR_STATUS0__CID__SHIFT                                                                 0x1
#define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT                                                             0x6
#define DAGB5_FATAL_ERROR_STATUS0__VALID_MASK                                                                 0x00000001L
#define DAGB5_FATAL_ERROR_STATUS0__CID_MASK                                                                   0x0000003EL
#define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO_MASK                                                               0xFFFFFFC0L
//DAGB5_FATAL_ERROR_STATUS1
#define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT                                                             0x0
#define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI_MASK                                                               0x0001FFFFL
//DAGB5_FATAL_ERROR_STATUS2
#define DAGB5_FATAL_ERROR_STATUS2__TAG__SHIFT                                                                 0x0
#define DAGB5_FATAL_ERROR_STATUS2__VFID__SHIFT                                                                0x10
#define DAGB5_FATAL_ERROR_STATUS2__VF__SHIFT                                                                  0x14
#define DAGB5_FATAL_ERROR_STATUS2__SPACE__SHIFT                                                               0x15
#define DAGB5_FATAL_ERROR_STATUS2__IO__SHIFT                                                                  0x16
#define DAGB5_FATAL_ERROR_STATUS2__SIZE__SHIFT                                                                0x17
#define DAGB5_FATAL_ERROR_STATUS2__FED__SHIFT                                                                 0x19
#define DAGB5_FATAL_ERROR_STATUS2__TAG_MASK                                                                   0x0000FFFFL
#define DAGB5_FATAL_ERROR_STATUS2__VFID_MASK                                                                  0x000F0000L
#define DAGB5_FATAL_ERROR_STATUS2__VF_MASK                                                                    0x00100000L
#define DAGB5_FATAL_ERROR_STATUS2__SPACE_MASK                                                                 0x00200000L
#define DAGB5_FATAL_ERROR_STATUS2__IO_MASK                                                                    0x00400000L
#define DAGB5_FATAL_ERROR_STATUS2__SIZE_MASK                                                                  0x00800000L
#define DAGB5_FATAL_ERROR_STATUS2__FED_MASK                                                                   0x02000000L
//DAGB5_FATAL_ERROR_STATUS3
#define DAGB5_FATAL_ERROR_STATUS3__OP__SHIFT                                                                  0x6
#define DAGB5_FATAL_ERROR_STATUS3__WRTMZ__SHIFT                                                               0x10
#define DAGB5_FATAL_ERROR_STATUS3__RDTMZ__SHIFT                                                               0x11
#define DAGB5_FATAL_ERROR_STATUS3__SNOOP__SHIFT                                                               0x12
#define DAGB5_FATAL_ERROR_STATUS3__INVAL__SHIFT                                                               0x13
#define DAGB5_FATAL_ERROR_STATUS3__NACK__SHIFT                                                                0x14
#define DAGB5_FATAL_ERROR_STATUS3__RO__SHIFT                                                                  0x16
#define DAGB5_FATAL_ERROR_STATUS3__MEMLOG__SHIFT                                                              0x17
#define DAGB5_FATAL_ERROR_STATUS3__EOP__SHIFT                                                                 0x18
#define DAGB5_FATAL_ERROR_STATUS3__OP_MASK                                                                    0x00001FC0L
#define DAGB5_FATAL_ERROR_STATUS3__WRTMZ_MASK                                                                 0x00010000L
#define DAGB5_FATAL_ERROR_STATUS3__RDTMZ_MASK                                                                 0x00020000L
#define DAGB5_FATAL_ERROR_STATUS3__SNOOP_MASK                                                                 0x00040000L
#define DAGB5_FATAL_ERROR_STATUS3__INVAL_MASK                                                                 0x00080000L
#define DAGB5_FATAL_ERROR_STATUS3__NACK_MASK                                                                  0x00300000L
#define DAGB5_FATAL_ERROR_STATUS3__RO_MASK                                                                    0x00400000L
#define DAGB5_FATAL_ERROR_STATUS3__MEMLOG_MASK                                                                0x00800000L
#define DAGB5_FATAL_ERROR_STATUS3__EOP_MASK                                                                   0x01000000L
//DAGB5_FIFO_EMPTY
#define DAGB5_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB5_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
//DAGB5_FIFO_FULL
#define DAGB5_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB5_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
//DAGB5_WR_CREDITS_FULL
#define DAGB5_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB5_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
//DAGB5_RD_CREDITS_FULL
#define DAGB5_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB5_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
//DAGB5_PERFCOUNTER_LO
#define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB5_PERFCOUNTER_HI
#define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB5_PERFCOUNTER0_CFG
#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB5_PERFCOUNTER1_CFG
#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB5_PERFCOUNTER2_CFG
#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB5_PERFCOUNTER_RSLT_CNTL
#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB5_L1TLB_REG_RW
#define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT                                                        0x2
#define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT                                                          0x4
#define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT                                                        0x5
#define DAGB5_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x6
#define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK                                                          0x00000004L
#define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK                                                            0x00000010L
#define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK                                                          0x00000020L
#define DAGB5_L1TLB_REG_RW__RESERVE_MASK                                                                      0xFFFFFFC0L
//DAGB5_RESERVE1
#define DAGB5_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB5_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB5_RESERVE2
#define DAGB5_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB5_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB5_RESERVE3
#define DAGB5_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB5_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB5_RESERVE4
#define DAGB5_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB5_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL


// addressBlock: mmhub_ea_mmeadec0
//MMEA0_DRAM_RD_CLI2GRP_MAP0
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA0_DRAM_RD_CLI2GRP_MAP1
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA0_DRAM_WR_CLI2GRP_MAP0
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA0_DRAM_WR_CLI2GRP_MAP1
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA0_DRAM_RD_GRP2VC_MAP
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA0_DRAM_WR_GRP2VC_MAP
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA0_DRAM_RD_LAZY
#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA0_DRAM_WR_LAZY
#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA0_DRAM_RD_CAM_CNTL
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA0_DRAM_WR_CAM_CNTL
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA0_DRAM_PAGE_BURST
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
//MMEA0_DRAM_RD_PRI_AGE
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA0_DRAM_WR_PRI_AGE
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA0_DRAM_RD_PRI_QUEUING
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA0_DRAM_WR_PRI_QUEUING
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA0_DRAM_RD_PRI_FIXED
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA0_DRAM_WR_PRI_FIXED
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA0_DRAM_RD_PRI_URGENCY
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA0_DRAM_WR_PRI_URGENCY
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA0_DRAM_RD_PRI_QUANT_PRI1
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA0_DRAM_RD_PRI_QUANT_PRI2
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA0_DRAM_RD_PRI_QUANT_PRI3
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA0_DRAM_WR_PRI_QUANT_PRI1
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA0_DRAM_WR_PRI_QUANT_PRI2
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA0_DRAM_WR_PRI_QUANT_PRI3
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA0_GMI_RD_CLI2GRP_MAP0
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA0_GMI_RD_CLI2GRP_MAP1
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA0_GMI_WR_CLI2GRP_MAP0
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA0_GMI_WR_CLI2GRP_MAP1
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA0_GMI_RD_GRP2VC_MAP
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA0_GMI_WR_GRP2VC_MAP
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA0_GMI_RD_LAZY
#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA0_GMI_WR_LAZY
#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA0_GMI_RD_CAM_CNTL
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA0_GMI_WR_CAM_CNTL
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA0_GMI_PAGE_BURST
#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA0_GMI_RD_PRI_AGE
#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA0_GMI_WR_PRI_AGE
#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA0_GMI_RD_PRI_QUEUING
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA0_GMI_WR_PRI_QUEUING
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA0_GMI_RD_PRI_FIXED
#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA0_GMI_WR_PRI_FIXED
#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA0_GMI_RD_PRI_URGENCY
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA0_GMI_WR_PRI_URGENCY
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA0_GMI_RD_PRI_URGENCY_MASKING
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA0_GMI_WR_PRI_URGENCY_MASKING
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA0_GMI_RD_PRI_QUANT_PRI1
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA0_GMI_RD_PRI_QUANT_PRI2
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA0_GMI_RD_PRI_QUANT_PRI3
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA0_GMI_WR_PRI_QUANT_PRI1
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA0_GMI_WR_PRI_QUANT_PRI2
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA0_GMI_WR_PRI_QUANT_PRI3
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA0_ADDRNORM_BASE_ADDR0
#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA0_ADDRNORM_LIMIT_ADDR0
#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA0_ADDRNORM_BASE_ADDR1
#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA0_ADDRNORM_LIMIT_ADDR1
#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA0_ADDRNORM_OFFSET_ADDR1
#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA0_ADDRNORM_BASE_ADDR2
#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA0_ADDRNORM_LIMIT_ADDR2
#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA0_ADDRNORM_BASE_ADDR3
#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA0_ADDRNORM_LIMIT_ADDR3
#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA0_ADDRNORM_OFFSET_ADDR3
#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA0_ADDRNORM_MEGABASE_ADDR0
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT                                                       0xc
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA0_ADDRNORM_MEGALIMIT_ADDR0
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA0_ADDRNORM_MEGABASE_ADDR1
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT                                                       0xc
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA0_ADDRNORM_MEGALIMIT_ADDR1
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA0_ADDRNORMDRAM_HOLE_CNTL
#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
//MMEA0_ADDRNORMGMI_HOLE_CNTL
#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG
#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
//MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG
#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
//MMEA0_ADDRDEC_BANK_CFG
#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
//MMEA0_ADDRDEC_MISC_CFG
#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
//MMEA0_ADDRDECGMI_HARVEST_ENABLE
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
//MMEA0_ADDRDEC0_BASE_ADDR_CS0
#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_CS1
#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_CS2
#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_CS3
#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC0_ADDR_MASK_CS01
#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA0_ADDRDEC0_ADDR_MASK_CS23
#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA0_ADDRDEC0_ADDR_CFG_CS01
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA0_ADDRDEC0_ADDR_CFG_CS23
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA0_ADDRDEC0_ADDR_SEL_CS01
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC0_ADDR_SEL_CS23
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC0_ADDR_SEL2_CS01
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA0_ADDRDEC0_ADDR_SEL2_CS23
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA0_ADDRDEC0_RM_SEL_CS01
#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA0_ADDRDEC0_RM_SEL_CS23
#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA0_ADDRDEC0_RM_SEL_SECCS01
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA0_ADDRDEC0_RM_SEL_SECCS23
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA0_ADDRDEC1_BASE_ADDR_CS0
#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_CS1
#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_CS2
#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_CS3
#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC1_ADDR_MASK_CS01
#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA0_ADDRDEC1_ADDR_MASK_CS23
#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA0_ADDRDEC1_ADDR_CFG_CS01
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA0_ADDRDEC1_ADDR_CFG_CS23
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA0_ADDRDEC1_ADDR_SEL_CS01
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC1_ADDR_SEL_CS23
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC1_ADDR_SEL2_CS01
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA0_ADDRDEC1_ADDR_SEL2_CS23
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA0_ADDRDEC1_RM_SEL_CS01
#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA0_ADDRDEC1_RM_SEL_CS23
#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA0_ADDRDEC1_RM_SEL_SECCS01
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA0_ADDRDEC1_RM_SEL_SECCS23
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA0_ADDRDEC2_BASE_ADDR_CS0
#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_CS1
#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_CS2
#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_CS3
#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_SECCS0
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_SECCS1
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_SECCS2
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC2_BASE_ADDR_SECCS3
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA0_ADDRDEC2_ADDR_MASK_CS01
#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA0_ADDRDEC2_ADDR_MASK_CS23
#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA0_ADDRDEC2_ADDR_MASK_SECCS01
#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA0_ADDRDEC2_ADDR_MASK_SECCS23
#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA0_ADDRDEC2_ADDR_CFG_CS01
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA0_ADDRDEC2_ADDR_CFG_CS23
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA0_ADDRDEC2_ADDR_SEL_CS01
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC2_ADDR_SEL_CS23
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC2_ADDR_SEL2_CS01
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA0_ADDRDEC2_ADDR_SEL2_CS23
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA0_ADDRDEC2_COL_SEL_LO_CS01
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC2_COL_SEL_LO_CS23
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA0_ADDRDEC2_COL_SEL_HI_CS01
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA0_ADDRDEC2_COL_SEL_HI_CS23
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA0_ADDRDEC2_RM_SEL_CS01
#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA0_ADDRDEC2_RM_SEL_CS23
#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA0_ADDRDEC2_RM_SEL_SECCS01
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA0_ADDRDEC2_RM_SEL_SECCS23
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA0_ADDRNORMDRAM_GLOBAL_CNTL
//MMEA0_ADDRNORMGMI_GLOBAL_CNTL
//MMEA0_ADDRNORM_MEGACONTROL_ADDR0
#define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA0_ADDRNORM_MEGACONTROL_ADDR1
#define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA0_ADDRNORMDRAM_MASKING
#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
//MMEA0_ADDRNORMGMI_MASKING
#define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT                                                         0x0
#define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK                                                           0x00000FFFL
//MMEA0_IO_RD_CLI2GRP_MAP0
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA0_IO_RD_CLI2GRP_MAP1
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA0_IO_WR_CLI2GRP_MAP0
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA0_IO_WR_CLI2GRP_MAP1
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA0_IO_RD_COMBINE_FLUSH
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA0_IO_WR_COMBINE_FLUSH
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA0_IO_GROUP_BURST
#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA0_IO_RD_PRI_AGE
#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA0_IO_WR_PRI_AGE
#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA0_IO_RD_PRI_QUEUING
#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA0_IO_WR_PRI_QUEUING
#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA0_IO_RD_PRI_FIXED
#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA0_IO_WR_PRI_FIXED
#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA0_IO_RD_PRI_URGENCY
#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA0_IO_WR_PRI_URGENCY
#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA0_IO_RD_PRI_URGENCY_MASKING
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA0_IO_WR_PRI_URGENCY_MASKING
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA0_IO_RD_PRI_QUANT_PRI1
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA0_IO_RD_PRI_QUANT_PRI2
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA0_IO_RD_PRI_QUANT_PRI3
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA0_IO_WR_PRI_QUANT_PRI1
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA0_IO_WR_PRI_QUANT_PRI2
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA0_IO_WR_PRI_QUANT_PRI3
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA0_SDP_ARB_DRAM
#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
//MMEA0_SDP_ARB_GMI
#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
//MMEA0_SDP_ARB_FINAL
#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
//MMEA0_SDP_DRAM_PRIORITY
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
//MMEA0_SDP_GMI_PRIORITY
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
//MMEA0_SDP_IO_PRIORITY
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
//MMEA0_SDP_CREDITS
#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
//MMEA0_SDP_TAG_RESERVE0
#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//MMEA0_SDP_TAG_RESERVE1
#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//MMEA0_SDP_VCC_RESERVE0
#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA0_SDP_VCC_RESERVE1
#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA0_SDP_VCD_RESERVE0
#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA0_SDP_VCD_RESERVE1
#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA0_SDP_REQ_CNTL
#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//MMEA0_MISC
#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
//MMEA0_LATENCY_SAMPLING
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
//MMEA0_PERFCOUNTER_LO
#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//MMEA0_PERFCOUNTER_HI
#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//MMEA0_PERFCOUNTER0_CFG
#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA0_PERFCOUNTER1_CFG
#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA0_PERFCOUNTER_RSLT_CNTL
#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//MMEA0_EDC_CNT
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
//MMEA0_EDC_CNT2
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
//MMEA0_DSM_CNTL
#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
//MMEA0_DSM_CNTLA
#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
//MMEA0_DSM_CNTLB
//MMEA0_DSM_CNTL2
#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
//MMEA0_DSM_CNTL2A
#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
//MMEA0_DSM_CNTL2B
//MMEA0_CGTT_CLK_CTRL
#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
//MMEA0_EDC_MODE
#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//MMEA0_ERR_STATUS
#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
#define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                     0x12
#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
#define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
#define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                       0x00040000L
//MMEA0_MISC2
#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
#define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
#define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
#define MMEA0_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
#define MMEA0_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
#define MMEA0_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
//MMEA0_ADDRDEC_SELECT
#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
//MMEA0_EDC_CNT3
#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
//MMEA0_MISC_AON
#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L


// addressBlock: mmhub_ea_mmeadec1
//MMEA1_DRAM_RD_CLI2GRP_MAP0
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA1_DRAM_RD_CLI2GRP_MAP1
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA1_DRAM_WR_CLI2GRP_MAP0
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA1_DRAM_WR_CLI2GRP_MAP1
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA1_DRAM_RD_GRP2VC_MAP
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA1_DRAM_WR_GRP2VC_MAP
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA1_DRAM_RD_LAZY
#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA1_DRAM_WR_LAZY
#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA1_DRAM_RD_CAM_CNTL
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA1_DRAM_WR_CAM_CNTL
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA1_DRAM_PAGE_BURST
#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
//MMEA1_DRAM_RD_PRI_AGE
#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA1_DRAM_WR_PRI_AGE
#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA1_DRAM_RD_PRI_QUEUING
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA1_DRAM_WR_PRI_QUEUING
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA1_DRAM_RD_PRI_FIXED
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA1_DRAM_WR_PRI_FIXED
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA1_DRAM_RD_PRI_URGENCY
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA1_DRAM_WR_PRI_URGENCY
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA1_DRAM_RD_PRI_QUANT_PRI1
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA1_DRAM_RD_PRI_QUANT_PRI2
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA1_DRAM_RD_PRI_QUANT_PRI3
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA1_DRAM_WR_PRI_QUANT_PRI1
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA1_DRAM_WR_PRI_QUANT_PRI2
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA1_DRAM_WR_PRI_QUANT_PRI3
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA1_GMI_RD_CLI2GRP_MAP0
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA1_GMI_RD_CLI2GRP_MAP1
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA1_GMI_WR_CLI2GRP_MAP0
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA1_GMI_WR_CLI2GRP_MAP1
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA1_GMI_RD_GRP2VC_MAP
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA1_GMI_WR_GRP2VC_MAP
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA1_GMI_RD_LAZY
#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA1_GMI_WR_LAZY
#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA1_GMI_RD_CAM_CNTL
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA1_GMI_WR_CAM_CNTL
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA1_GMI_PAGE_BURST
#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA1_GMI_RD_PRI_AGE
#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA1_GMI_WR_PRI_AGE
#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA1_GMI_RD_PRI_QUEUING
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA1_GMI_WR_PRI_QUEUING
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA1_GMI_RD_PRI_FIXED
#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA1_GMI_WR_PRI_FIXED
#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA1_GMI_RD_PRI_URGENCY
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA1_GMI_WR_PRI_URGENCY
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA1_GMI_RD_PRI_URGENCY_MASKING
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA1_GMI_WR_PRI_URGENCY_MASKING
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA1_GMI_RD_PRI_QUANT_PRI1
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA1_GMI_RD_PRI_QUANT_PRI2
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA1_GMI_RD_PRI_QUANT_PRI3
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA1_GMI_WR_PRI_QUANT_PRI1
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA1_GMI_WR_PRI_QUANT_PRI2
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA1_GMI_WR_PRI_QUANT_PRI3
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA1_ADDRNORM_BASE_ADDR0
#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA1_ADDRNORM_LIMIT_ADDR0
#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA1_ADDRNORM_BASE_ADDR1
#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA1_ADDRNORM_LIMIT_ADDR1
#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA1_ADDRNORM_OFFSET_ADDR1
#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA1_ADDRNORM_BASE_ADDR2
#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA1_ADDRNORM_LIMIT_ADDR2
#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA1_ADDRNORM_BASE_ADDR3
#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA1_ADDRNORM_LIMIT_ADDR3
#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA1_ADDRNORM_OFFSET_ADDR3
#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA1_ADDRNORM_MEGABASE_ADDR0
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT                                                       0xc
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA1_ADDRNORM_MEGALIMIT_ADDR0
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA1_ADDRNORM_MEGABASE_ADDR1
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT                                                       0xc
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA1_ADDRNORM_MEGALIMIT_ADDR1
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA1_ADDRNORMDRAM_HOLE_CNTL
#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
//MMEA1_ADDRNORMGMI_HOLE_CNTL
#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
//MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG
#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
//MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG
#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
//MMEA1_ADDRDEC_BANK_CFG
#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
//MMEA1_ADDRDEC_MISC_CFG
#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
//MMEA1_ADDRDECDRAM_HARVEST_ENABLE
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
//MMEA1_ADDRDECGMI_HARVEST_ENABLE
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
//MMEA1_ADDRDEC0_BASE_ADDR_CS0
#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_CS1
#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_CS2
#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_CS3
#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC0_ADDR_MASK_CS01
#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA1_ADDRDEC0_ADDR_MASK_CS23
#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01
#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23
#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA1_ADDRDEC0_ADDR_CFG_CS01
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA1_ADDRDEC0_ADDR_CFG_CS23
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA1_ADDRDEC0_ADDR_SEL_CS01
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC0_ADDR_SEL_CS23
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC0_ADDR_SEL2_CS01
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA1_ADDRDEC0_ADDR_SEL2_CS23
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA1_ADDRDEC0_COL_SEL_LO_CS01
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC0_COL_SEL_LO_CS23
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC0_COL_SEL_HI_CS01
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA1_ADDRDEC0_COL_SEL_HI_CS23
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA1_ADDRDEC0_RM_SEL_CS01
#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA1_ADDRDEC0_RM_SEL_CS23
#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA1_ADDRDEC0_RM_SEL_SECCS01
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA1_ADDRDEC0_RM_SEL_SECCS23
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA1_ADDRDEC1_BASE_ADDR_CS0
#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_CS1
#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_CS2
#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_CS3
#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC1_ADDR_MASK_CS01
#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA1_ADDRDEC1_ADDR_MASK_CS23
#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01
#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23
#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA1_ADDRDEC1_ADDR_CFG_CS01
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA1_ADDRDEC1_ADDR_CFG_CS23
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA1_ADDRDEC1_ADDR_SEL_CS01
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC1_ADDR_SEL_CS23
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC1_ADDR_SEL2_CS01
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA1_ADDRDEC1_ADDR_SEL2_CS23
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA1_ADDRDEC1_COL_SEL_LO_CS01
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC1_COL_SEL_LO_CS23
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC1_COL_SEL_HI_CS01
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA1_ADDRDEC1_COL_SEL_HI_CS23
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA1_ADDRDEC1_RM_SEL_CS01
#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA1_ADDRDEC1_RM_SEL_CS23
#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA1_ADDRDEC1_RM_SEL_SECCS01
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA1_ADDRDEC1_RM_SEL_SECCS23
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA1_ADDRDEC2_BASE_ADDR_CS0
#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_CS1
#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_CS2
#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_CS3
#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_SECCS0
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_SECCS1
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_SECCS2
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC2_BASE_ADDR_SECCS3
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA1_ADDRDEC2_ADDR_MASK_CS01
#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA1_ADDRDEC2_ADDR_MASK_CS23
#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA1_ADDRDEC2_ADDR_MASK_SECCS01
#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA1_ADDRDEC2_ADDR_MASK_SECCS23
#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA1_ADDRDEC2_ADDR_CFG_CS01
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA1_ADDRDEC2_ADDR_CFG_CS23
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA1_ADDRDEC2_ADDR_SEL_CS01
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC2_ADDR_SEL_CS23
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC2_ADDR_SEL2_CS01
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA1_ADDRDEC2_ADDR_SEL2_CS23
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA1_ADDRDEC2_COL_SEL_LO_CS01
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC2_COL_SEL_LO_CS23
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA1_ADDRDEC2_COL_SEL_HI_CS01
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA1_ADDRDEC2_COL_SEL_HI_CS23
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA1_ADDRDEC2_RM_SEL_CS01
#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA1_ADDRDEC2_RM_SEL_CS23
#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA1_ADDRDEC2_RM_SEL_SECCS01
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA1_ADDRDEC2_RM_SEL_SECCS23
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA1_ADDRNORMDRAM_GLOBAL_CNTL
//MMEA1_ADDRNORMGMI_GLOBAL_CNTL
//MMEA1_ADDRNORM_MEGACONTROL_ADDR0
#define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA1_ADDRNORM_MEGACONTROL_ADDR1
#define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA1_ADDRNORMDRAM_MASKING
#define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
#define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
//MMEA1_ADDRNORMGMI_MASKING
#define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT                                                         0x0
#define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK                                                           0x00000FFFL
//MMEA1_IO_RD_CLI2GRP_MAP0
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA1_IO_RD_CLI2GRP_MAP1
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA1_IO_WR_CLI2GRP_MAP0
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA1_IO_WR_CLI2GRP_MAP1
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA1_IO_RD_COMBINE_FLUSH
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA1_IO_WR_COMBINE_FLUSH
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA1_IO_GROUP_BURST
#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA1_IO_RD_PRI_AGE
#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA1_IO_WR_PRI_AGE
#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA1_IO_RD_PRI_QUEUING
#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA1_IO_WR_PRI_QUEUING
#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA1_IO_RD_PRI_FIXED
#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA1_IO_WR_PRI_FIXED
#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA1_IO_RD_PRI_URGENCY
#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA1_IO_WR_PRI_URGENCY
#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA1_IO_RD_PRI_URGENCY_MASKING
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA1_IO_WR_PRI_URGENCY_MASKING
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA1_IO_RD_PRI_QUANT_PRI1
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA1_IO_RD_PRI_QUANT_PRI2
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA1_IO_RD_PRI_QUANT_PRI3
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA1_IO_WR_PRI_QUANT_PRI1
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA1_IO_WR_PRI_QUANT_PRI2
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA1_IO_WR_PRI_QUANT_PRI3
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA1_SDP_ARB_DRAM
#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
//MMEA1_SDP_ARB_GMI
#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
//MMEA1_SDP_ARB_FINAL
#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
#define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
#define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
#define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
#define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
#define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
#define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
#define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
#define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
//MMEA1_SDP_DRAM_PRIORITY
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
//MMEA1_SDP_GMI_PRIORITY
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
//MMEA1_SDP_IO_PRIORITY
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
//MMEA1_SDP_CREDITS
#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
//MMEA1_SDP_TAG_RESERVE0
#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//MMEA1_SDP_TAG_RESERVE1
#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//MMEA1_SDP_VCC_RESERVE0
#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA1_SDP_VCC_RESERVE1
#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA1_SDP_VCD_RESERVE0
#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA1_SDP_VCD_RESERVE1
#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA1_SDP_REQ_CNTL
#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//MMEA1_MISC
#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
//MMEA1_LATENCY_SAMPLING
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
//MMEA1_PERFCOUNTER_LO
#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//MMEA1_PERFCOUNTER_HI
#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//MMEA1_PERFCOUNTER0_CFG
#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA1_PERFCOUNTER1_CFG
#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA1_PERFCOUNTER_RSLT_CNTL
#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//MMEA1_EDC_CNT
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
#define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
#define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
#define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
#define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
//MMEA1_EDC_CNT2
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
#define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
#define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
#define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
#define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
#define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
#define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
#define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
#define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
//MMEA1_DSM_CNTL
#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
//MMEA1_DSM_CNTLA
#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
//MMEA1_DSM_CNTLB
//MMEA1_DSM_CNTL2
#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
//MMEA1_DSM_CNTL2A
#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
//MMEA1_DSM_CNTL2B
//MMEA1_CGTT_CLK_CTRL
#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
#define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
#define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
//MMEA1_EDC_MODE
#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define MMEA1_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define MMEA1_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define MMEA1_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define MMEA1_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define MMEA1_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define MMEA1_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define MMEA1_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define MMEA1_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//MMEA1_ERR_STATUS
#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
#define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
#define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
#define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
#define MMEA1_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
#define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                     0x12
#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
#define MMEA1_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
#define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
#define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
#define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
#define MMEA1_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
#define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                       0x00040000L
//MMEA1_MISC2
#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
#define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
#define MMEA1_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
#define MMEA1_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
#define MMEA1_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
#define MMEA1_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
#define MMEA1_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
//MMEA1_ADDRDEC_SELECT
#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
//MMEA1_EDC_CNT3
#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
//MMEA1_MISC_AON
#define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
#define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
#define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
#define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L


// addressBlock: mmhub_ea_mmeadec2
//MMEA2_DRAM_RD_CLI2GRP_MAP0
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA2_DRAM_RD_CLI2GRP_MAP1
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA2_DRAM_WR_CLI2GRP_MAP0
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA2_DRAM_WR_CLI2GRP_MAP1
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA2_DRAM_RD_GRP2VC_MAP
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA2_DRAM_WR_GRP2VC_MAP
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA2_DRAM_RD_LAZY
#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA2_DRAM_WR_LAZY
#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA2_DRAM_RD_CAM_CNTL
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA2_DRAM_WR_CAM_CNTL
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA2_DRAM_PAGE_BURST
#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
//MMEA2_DRAM_RD_PRI_AGE
#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA2_DRAM_WR_PRI_AGE
#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA2_DRAM_RD_PRI_QUEUING
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA2_DRAM_WR_PRI_QUEUING
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA2_DRAM_RD_PRI_FIXED
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA2_DRAM_WR_PRI_FIXED
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA2_DRAM_RD_PRI_URGENCY
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA2_DRAM_WR_PRI_URGENCY
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA2_DRAM_RD_PRI_QUANT_PRI1
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA2_DRAM_RD_PRI_QUANT_PRI2
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA2_DRAM_RD_PRI_QUANT_PRI3
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA2_DRAM_WR_PRI_QUANT_PRI1
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA2_DRAM_WR_PRI_QUANT_PRI2
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA2_DRAM_WR_PRI_QUANT_PRI3
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA2_GMI_RD_CLI2GRP_MAP0
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA2_GMI_RD_CLI2GRP_MAP1
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA2_GMI_WR_CLI2GRP_MAP0
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA2_GMI_WR_CLI2GRP_MAP1
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA2_GMI_RD_GRP2VC_MAP
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA2_GMI_WR_GRP2VC_MAP
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA2_GMI_RD_LAZY
#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA2_GMI_WR_LAZY
#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA2_GMI_RD_CAM_CNTL
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA2_GMI_WR_CAM_CNTL
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA2_GMI_PAGE_BURST
#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA2_GMI_RD_PRI_AGE
#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA2_GMI_WR_PRI_AGE
#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA2_GMI_RD_PRI_QUEUING
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA2_GMI_WR_PRI_QUEUING
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA2_GMI_RD_PRI_FIXED
#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA2_GMI_WR_PRI_FIXED
#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA2_GMI_RD_PRI_URGENCY
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA2_GMI_WR_PRI_URGENCY
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA2_GMI_RD_PRI_URGENCY_MASKING
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA2_GMI_WR_PRI_URGENCY_MASKING
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA2_GMI_RD_PRI_QUANT_PRI1
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA2_GMI_RD_PRI_QUANT_PRI2
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA2_GMI_RD_PRI_QUANT_PRI3
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA2_GMI_WR_PRI_QUANT_PRI1
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA2_GMI_WR_PRI_QUANT_PRI2
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA2_GMI_WR_PRI_QUANT_PRI3
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA2_ADDRNORM_BASE_ADDR0
#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA2_ADDRNORM_LIMIT_ADDR0
#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA2_ADDRNORM_BASE_ADDR1
#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA2_ADDRNORM_LIMIT_ADDR1
#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA2_ADDRNORM_OFFSET_ADDR1
#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA2_ADDRNORM_BASE_ADDR2
#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA2_ADDRNORM_LIMIT_ADDR2
#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA2_ADDRNORM_BASE_ADDR3
#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA2_ADDRNORM_LIMIT_ADDR3
#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA2_ADDRNORM_OFFSET_ADDR3
#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA2_ADDRNORM_MEGABASE_ADDR0
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT                                                       0xc
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA2_ADDRNORM_MEGALIMIT_ADDR0
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA2_ADDRNORM_MEGABASE_ADDR1
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT                                                       0xc
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA2_ADDRNORM_MEGALIMIT_ADDR1
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA2_ADDRNORMDRAM_HOLE_CNTL
#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
//MMEA2_ADDRNORMGMI_HOLE_CNTL
#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
//MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG
#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
//MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG
#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
//MMEA2_ADDRDEC_BANK_CFG
#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
//MMEA2_ADDRDEC_MISC_CFG
#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
//MMEA2_ADDRDECDRAM_HARVEST_ENABLE
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
//MMEA2_ADDRDECGMI_HARVEST_ENABLE
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
//MMEA2_ADDRDEC0_BASE_ADDR_CS0
#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_CS1
#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_CS2
#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_CS3
#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_SECCS0
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_SECCS1
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_SECCS2
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC0_BASE_ADDR_SECCS3
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC0_ADDR_MASK_CS01
#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA2_ADDRDEC0_ADDR_MASK_CS23
#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA2_ADDRDEC0_ADDR_MASK_SECCS01
#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA2_ADDRDEC0_ADDR_MASK_SECCS23
#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA2_ADDRDEC0_ADDR_CFG_CS01
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA2_ADDRDEC0_ADDR_CFG_CS23
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA2_ADDRDEC0_ADDR_SEL_CS01
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC0_ADDR_SEL_CS23
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC0_ADDR_SEL2_CS01
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA2_ADDRDEC0_ADDR_SEL2_CS23
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA2_ADDRDEC0_COL_SEL_LO_CS01
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC0_COL_SEL_LO_CS23
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC0_COL_SEL_HI_CS01
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA2_ADDRDEC0_COL_SEL_HI_CS23
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA2_ADDRDEC0_RM_SEL_CS01
#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA2_ADDRDEC0_RM_SEL_CS23
#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA2_ADDRDEC0_RM_SEL_SECCS01
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA2_ADDRDEC0_RM_SEL_SECCS23
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA2_ADDRDEC1_BASE_ADDR_CS0
#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_CS1
#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_CS2
#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_CS3
#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_SECCS0
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_SECCS1
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_SECCS2
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC1_BASE_ADDR_SECCS3
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC1_ADDR_MASK_CS01
#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA2_ADDRDEC1_ADDR_MASK_CS23
#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA2_ADDRDEC1_ADDR_MASK_SECCS01
#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA2_ADDRDEC1_ADDR_MASK_SECCS23
#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA2_ADDRDEC1_ADDR_CFG_CS01
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA2_ADDRDEC1_ADDR_CFG_CS23
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA2_ADDRDEC1_ADDR_SEL_CS01
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC1_ADDR_SEL_CS23
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC1_ADDR_SEL2_CS01
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA2_ADDRDEC1_ADDR_SEL2_CS23
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA2_ADDRDEC1_COL_SEL_LO_CS01
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC1_COL_SEL_LO_CS23
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC1_COL_SEL_HI_CS01
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA2_ADDRDEC1_COL_SEL_HI_CS23
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA2_ADDRDEC1_RM_SEL_CS01
#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA2_ADDRDEC1_RM_SEL_CS23
#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA2_ADDRDEC1_RM_SEL_SECCS01
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA2_ADDRDEC1_RM_SEL_SECCS23
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA2_ADDRDEC2_BASE_ADDR_CS0
#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_CS1
#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_CS2
#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_CS3
#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_SECCS0
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_SECCS1
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_SECCS2
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC2_BASE_ADDR_SECCS3
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA2_ADDRDEC2_ADDR_MASK_CS01
#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA2_ADDRDEC2_ADDR_MASK_CS23
#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA2_ADDRDEC2_ADDR_MASK_SECCS01
#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA2_ADDRDEC2_ADDR_MASK_SECCS23
#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA2_ADDRDEC2_ADDR_CFG_CS01
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA2_ADDRDEC2_ADDR_CFG_CS23
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA2_ADDRDEC2_ADDR_SEL_CS01
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC2_ADDR_SEL_CS23
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC2_ADDR_SEL2_CS01
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA2_ADDRDEC2_ADDR_SEL2_CS23
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA2_ADDRDEC2_COL_SEL_LO_CS01
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC2_COL_SEL_LO_CS23
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA2_ADDRDEC2_COL_SEL_HI_CS01
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA2_ADDRDEC2_COL_SEL_HI_CS23
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA2_ADDRDEC2_RM_SEL_CS01
#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA2_ADDRDEC2_RM_SEL_CS23
#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA2_ADDRDEC2_RM_SEL_SECCS01
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA2_ADDRDEC2_RM_SEL_SECCS23
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA2_ADDRNORMDRAM_GLOBAL_CNTL
//MMEA2_ADDRNORMGMI_GLOBAL_CNTL
//MMEA2_ADDRNORM_MEGACONTROL_ADDR0
#define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA2_ADDRNORM_MEGACONTROL_ADDR1
#define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA2_ADDRNORMDRAM_MASKING
#define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
#define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
//MMEA2_ADDRNORMGMI_MASKING
#define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT                                                         0x0
#define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK                                                           0x00000FFFL
//MMEA2_IO_RD_CLI2GRP_MAP0
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA2_IO_RD_CLI2GRP_MAP1
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA2_IO_WR_CLI2GRP_MAP0
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA2_IO_WR_CLI2GRP_MAP1
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA2_IO_RD_COMBINE_FLUSH
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA2_IO_WR_COMBINE_FLUSH
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA2_IO_GROUP_BURST
#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA2_IO_RD_PRI_AGE
#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA2_IO_WR_PRI_AGE
#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA2_IO_RD_PRI_QUEUING
#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA2_IO_WR_PRI_QUEUING
#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA2_IO_RD_PRI_FIXED
#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA2_IO_WR_PRI_FIXED
#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA2_IO_RD_PRI_URGENCY
#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA2_IO_WR_PRI_URGENCY
#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA2_IO_RD_PRI_URGENCY_MASKING
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA2_IO_WR_PRI_URGENCY_MASKING
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA2_IO_RD_PRI_QUANT_PRI1
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA2_IO_RD_PRI_QUANT_PRI2
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA2_IO_RD_PRI_QUANT_PRI3
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA2_IO_WR_PRI_QUANT_PRI1
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA2_IO_WR_PRI_QUANT_PRI2
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA2_IO_WR_PRI_QUANT_PRI3
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA2_SDP_ARB_DRAM
#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
//MMEA2_SDP_ARB_GMI
#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
//MMEA2_SDP_ARB_FINAL
#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
#define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
#define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
#define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
#define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
#define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
#define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
#define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
#define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
//MMEA2_SDP_DRAM_PRIORITY
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
//MMEA2_SDP_GMI_PRIORITY
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
//MMEA2_SDP_IO_PRIORITY
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
//MMEA2_SDP_CREDITS
#define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
//MMEA2_SDP_TAG_RESERVE0
#define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define MMEA2_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define MMEA2_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define MMEA2_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define MMEA2_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//MMEA2_SDP_TAG_RESERVE1
#define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define MMEA2_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define MMEA2_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define MMEA2_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define MMEA2_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//MMEA2_SDP_VCC_RESERVE0
#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA2_SDP_VCC_RESERVE1
#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA2_SDP_VCD_RESERVE0
#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA2_SDP_VCD_RESERVE1
#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA2_SDP_REQ_CNTL
#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//MMEA2_MISC
#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
#define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
#define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
//MMEA2_LATENCY_SAMPLING
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
//MMEA2_PERFCOUNTER_LO
#define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//MMEA2_PERFCOUNTER_HI
#define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//MMEA2_PERFCOUNTER0_CFG
#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA2_PERFCOUNTER1_CFG
#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA2_PERFCOUNTER_RSLT_CNTL
#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//MMEA2_EDC_CNT
#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
#define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
#define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
#define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
#define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
//MMEA2_EDC_CNT2
#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
#define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
#define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
#define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
#define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
#define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
#define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
#define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
#define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
#define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
#define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
#define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
#define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
#define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
#define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
#define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
#define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
//MMEA2_DSM_CNTL
#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
//MMEA2_DSM_CNTLA
#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
//MMEA2_DSM_CNTLB
//MMEA2_DSM_CNTL2
#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
#define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
#define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
//MMEA2_DSM_CNTL2A
#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
//MMEA2_DSM_CNTL2B
//MMEA2_CGTT_CLK_CTRL
#define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
#define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
#define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
#define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
//MMEA2_EDC_MODE
#define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define MMEA2_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define MMEA2_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define MMEA2_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define MMEA2_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define MMEA2_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define MMEA2_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define MMEA2_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define MMEA2_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//MMEA2_ERR_STATUS
#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
#define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
#define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
#define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
#define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
#define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
#define MMEA2_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
#define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                     0x12
#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
#define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
#define MMEA2_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
#define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
#define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
#define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
#define MMEA2_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
#define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                       0x00040000L
//MMEA2_MISC2
#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
#define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
#define MMEA2_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
#define MMEA2_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
#define MMEA2_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
#define MMEA2_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
#define MMEA2_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
//MMEA2_ADDRDEC_SELECT
#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
//MMEA2_EDC_CNT3
#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
//MMEA2_MISC_AON
#define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
#define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
#define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
#define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L


// addressBlock: mmhub_ea_mmeadec3
//MMEA3_DRAM_RD_CLI2GRP_MAP0
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA3_DRAM_RD_CLI2GRP_MAP1
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA3_DRAM_WR_CLI2GRP_MAP0
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA3_DRAM_WR_CLI2GRP_MAP1
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA3_DRAM_RD_GRP2VC_MAP
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA3_DRAM_WR_GRP2VC_MAP
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA3_DRAM_RD_LAZY
#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA3_DRAM_WR_LAZY
#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA3_DRAM_RD_CAM_CNTL
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA3_DRAM_WR_CAM_CNTL
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA3_DRAM_PAGE_BURST
#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
//MMEA3_DRAM_RD_PRI_AGE
#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA3_DRAM_WR_PRI_AGE
#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA3_DRAM_RD_PRI_QUEUING
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA3_DRAM_WR_PRI_QUEUING
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA3_DRAM_RD_PRI_FIXED
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA3_DRAM_WR_PRI_FIXED
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA3_DRAM_RD_PRI_URGENCY
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA3_DRAM_WR_PRI_URGENCY
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA3_DRAM_RD_PRI_QUANT_PRI1
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA3_DRAM_RD_PRI_QUANT_PRI2
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA3_DRAM_RD_PRI_QUANT_PRI3
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA3_DRAM_WR_PRI_QUANT_PRI1
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA3_DRAM_WR_PRI_QUANT_PRI2
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA3_DRAM_WR_PRI_QUANT_PRI3
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA3_GMI_RD_CLI2GRP_MAP0
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA3_GMI_RD_CLI2GRP_MAP1
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA3_GMI_WR_CLI2GRP_MAP0
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA3_GMI_WR_CLI2GRP_MAP1
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA3_GMI_RD_GRP2VC_MAP
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA3_GMI_WR_GRP2VC_MAP
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA3_GMI_RD_LAZY
#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA3_GMI_WR_LAZY
#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA3_GMI_RD_CAM_CNTL
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA3_GMI_WR_CAM_CNTL
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA3_GMI_PAGE_BURST
#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA3_GMI_RD_PRI_AGE
#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA3_GMI_WR_PRI_AGE
#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA3_GMI_RD_PRI_QUEUING
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA3_GMI_WR_PRI_QUEUING
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA3_GMI_RD_PRI_FIXED
#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA3_GMI_WR_PRI_FIXED
#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA3_GMI_RD_PRI_URGENCY
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA3_GMI_WR_PRI_URGENCY
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA3_GMI_RD_PRI_URGENCY_MASKING
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA3_GMI_WR_PRI_URGENCY_MASKING
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA3_GMI_RD_PRI_QUANT_PRI1
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA3_GMI_RD_PRI_QUANT_PRI2
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA3_GMI_RD_PRI_QUANT_PRI3
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA3_GMI_WR_PRI_QUANT_PRI1
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA3_GMI_WR_PRI_QUANT_PRI2
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA3_GMI_WR_PRI_QUANT_PRI3
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA3_ADDRNORM_BASE_ADDR0
#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA3_ADDRNORM_LIMIT_ADDR0
#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA3_ADDRNORM_BASE_ADDR1
#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA3_ADDRNORM_LIMIT_ADDR1
#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA3_ADDRNORM_OFFSET_ADDR1
#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA3_ADDRNORM_BASE_ADDR2
#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA3_ADDRNORM_LIMIT_ADDR2
#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA3_ADDRNORM_BASE_ADDR3
#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA3_ADDRNORM_LIMIT_ADDR3
#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA3_ADDRNORM_OFFSET_ADDR3
#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA3_ADDRNORM_MEGABASE_ADDR0
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT                                                       0xc
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA3_ADDRNORM_MEGALIMIT_ADDR0
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA3_ADDRNORM_MEGABASE_ADDR1
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT                                                       0xc
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA3_ADDRNORM_MEGALIMIT_ADDR1
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA3_ADDRNORMDRAM_HOLE_CNTL
#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
//MMEA3_ADDRNORMGMI_HOLE_CNTL
#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
//MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG
#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
//MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG
#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
//MMEA3_ADDRDEC_BANK_CFG
#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
//MMEA3_ADDRDEC_MISC_CFG
#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
//MMEA3_ADDRDECDRAM_HARVEST_ENABLE
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
//MMEA3_ADDRDECGMI_HARVEST_ENABLE
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
//MMEA3_ADDRDEC0_BASE_ADDR_CS0
#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_CS1
#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_CS2
#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_CS3
#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_SECCS0
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_SECCS1
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_SECCS2
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC0_BASE_ADDR_SECCS3
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC0_ADDR_MASK_CS01
#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA3_ADDRDEC0_ADDR_MASK_CS23
#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA3_ADDRDEC0_ADDR_MASK_SECCS01
#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA3_ADDRDEC0_ADDR_MASK_SECCS23
#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA3_ADDRDEC0_ADDR_CFG_CS01
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA3_ADDRDEC0_ADDR_CFG_CS23
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA3_ADDRDEC0_ADDR_SEL_CS01
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC0_ADDR_SEL_CS23
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC0_ADDR_SEL2_CS01
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA3_ADDRDEC0_ADDR_SEL2_CS23
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA3_ADDRDEC0_COL_SEL_LO_CS01
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC0_COL_SEL_LO_CS23
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC0_COL_SEL_HI_CS01
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA3_ADDRDEC0_COL_SEL_HI_CS23
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA3_ADDRDEC0_RM_SEL_CS01
#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA3_ADDRDEC0_RM_SEL_CS23
#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA3_ADDRDEC0_RM_SEL_SECCS01
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA3_ADDRDEC0_RM_SEL_SECCS23
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA3_ADDRDEC1_BASE_ADDR_CS0
#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_CS1
#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_CS2
#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_CS3
#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_SECCS0
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_SECCS1
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_SECCS2
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC1_BASE_ADDR_SECCS3
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC1_ADDR_MASK_CS01
#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA3_ADDRDEC1_ADDR_MASK_CS23
#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA3_ADDRDEC1_ADDR_MASK_SECCS01
#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA3_ADDRDEC1_ADDR_MASK_SECCS23
#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA3_ADDRDEC1_ADDR_CFG_CS01
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA3_ADDRDEC1_ADDR_CFG_CS23
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA3_ADDRDEC1_ADDR_SEL_CS01
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC1_ADDR_SEL_CS23
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC1_ADDR_SEL2_CS01
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA3_ADDRDEC1_ADDR_SEL2_CS23
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA3_ADDRDEC1_COL_SEL_LO_CS01
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC1_COL_SEL_LO_CS23
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC1_COL_SEL_HI_CS01
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA3_ADDRDEC1_COL_SEL_HI_CS23
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA3_ADDRDEC1_RM_SEL_CS01
#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA3_ADDRDEC1_RM_SEL_CS23
#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA3_ADDRDEC1_RM_SEL_SECCS01
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA3_ADDRDEC1_RM_SEL_SECCS23
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA3_ADDRDEC2_BASE_ADDR_CS0
#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_CS1
#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_CS2
#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_CS3
#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_SECCS0
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_SECCS1
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_SECCS2
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC2_BASE_ADDR_SECCS3
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA3_ADDRDEC2_ADDR_MASK_CS01
#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA3_ADDRDEC2_ADDR_MASK_CS23
#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA3_ADDRDEC2_ADDR_MASK_SECCS01
#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA3_ADDRDEC2_ADDR_MASK_SECCS23
#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA3_ADDRDEC2_ADDR_CFG_CS01
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA3_ADDRDEC2_ADDR_CFG_CS23
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA3_ADDRDEC2_ADDR_SEL_CS01
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC2_ADDR_SEL_CS23
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC2_ADDR_SEL2_CS01
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA3_ADDRDEC2_ADDR_SEL2_CS23
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA3_ADDRDEC2_COL_SEL_LO_CS01
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC2_COL_SEL_LO_CS23
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA3_ADDRDEC2_COL_SEL_HI_CS01
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA3_ADDRDEC2_COL_SEL_HI_CS23
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA3_ADDRDEC2_RM_SEL_CS01
#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA3_ADDRDEC2_RM_SEL_CS23
#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA3_ADDRDEC2_RM_SEL_SECCS01
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA3_ADDRDEC2_RM_SEL_SECCS23
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA3_ADDRNORMDRAM_GLOBAL_CNTL
//MMEA3_ADDRNORMGMI_GLOBAL_CNTL
//MMEA3_ADDRNORM_MEGACONTROL_ADDR0
#define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA3_ADDRNORM_MEGACONTROL_ADDR1
#define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA3_ADDRNORMDRAM_MASKING
#define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
#define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
//MMEA3_ADDRNORMGMI_MASKING
#define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT                                                         0x0
#define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK                                                           0x00000FFFL
//MMEA3_IO_RD_CLI2GRP_MAP0
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA3_IO_RD_CLI2GRP_MAP1
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA3_IO_WR_CLI2GRP_MAP0
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA3_IO_WR_CLI2GRP_MAP1
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA3_IO_RD_COMBINE_FLUSH
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA3_IO_WR_COMBINE_FLUSH
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA3_IO_GROUP_BURST
#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA3_IO_RD_PRI_AGE
#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA3_IO_WR_PRI_AGE
#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA3_IO_RD_PRI_QUEUING
#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA3_IO_WR_PRI_QUEUING
#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA3_IO_RD_PRI_FIXED
#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA3_IO_WR_PRI_FIXED
#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA3_IO_RD_PRI_URGENCY
#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA3_IO_WR_PRI_URGENCY
#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA3_IO_RD_PRI_URGENCY_MASKING
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA3_IO_WR_PRI_URGENCY_MASKING
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA3_IO_RD_PRI_QUANT_PRI1
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA3_IO_RD_PRI_QUANT_PRI2
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA3_IO_RD_PRI_QUANT_PRI3
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA3_IO_WR_PRI_QUANT_PRI1
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA3_IO_WR_PRI_QUANT_PRI2
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA3_IO_WR_PRI_QUANT_PRI3
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA3_SDP_ARB_DRAM
#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
//MMEA3_SDP_ARB_GMI
#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
//MMEA3_SDP_ARB_FINAL
#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
#define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
#define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
#define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
#define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
#define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
#define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
#define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
#define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
//MMEA3_SDP_DRAM_PRIORITY
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
//MMEA3_SDP_GMI_PRIORITY
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
//MMEA3_SDP_IO_PRIORITY
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
//MMEA3_SDP_CREDITS
#define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
//MMEA3_SDP_TAG_RESERVE0
#define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define MMEA3_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define MMEA3_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define MMEA3_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define MMEA3_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//MMEA3_SDP_TAG_RESERVE1
#define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define MMEA3_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define MMEA3_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define MMEA3_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define MMEA3_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//MMEA3_SDP_VCC_RESERVE0
#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA3_SDP_VCC_RESERVE1
#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA3_SDP_VCD_RESERVE0
#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA3_SDP_VCD_RESERVE1
#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA3_SDP_REQ_CNTL
#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//MMEA3_MISC
#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
#define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
#define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
//MMEA3_LATENCY_SAMPLING
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
//MMEA3_PERFCOUNTER_LO
#define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//MMEA3_PERFCOUNTER_HI
#define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//MMEA3_PERFCOUNTER0_CFG
#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA3_PERFCOUNTER1_CFG
#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA3_PERFCOUNTER_RSLT_CNTL
#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//MMEA3_EDC_CNT
#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
#define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
#define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
#define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
#define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
//MMEA3_EDC_CNT2
#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
#define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
#define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
#define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
#define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
#define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
#define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
#define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
#define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
#define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
#define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
#define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
#define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
#define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
#define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
#define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
#define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
//MMEA3_DSM_CNTL
#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
//MMEA3_DSM_CNTLA
#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
//MMEA3_DSM_CNTLB
//MMEA3_DSM_CNTL2
#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
#define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
#define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
//MMEA3_DSM_CNTL2A
#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
//MMEA3_DSM_CNTL2B
//MMEA3_CGTT_CLK_CTRL
#define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
#define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
#define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
#define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
//MMEA3_EDC_MODE
#define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define MMEA3_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define MMEA3_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define MMEA3_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define MMEA3_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define MMEA3_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define MMEA3_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define MMEA3_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define MMEA3_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//MMEA3_ERR_STATUS
#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
#define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
#define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
#define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
#define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
#define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
#define MMEA3_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
#define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                     0x12
#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
#define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
#define MMEA3_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
#define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
#define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
#define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
#define MMEA3_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
#define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                       0x00040000L
//MMEA3_MISC2
#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
#define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
#define MMEA3_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
#define MMEA3_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
#define MMEA3_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
#define MMEA3_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
#define MMEA3_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
//MMEA3_ADDRDEC_SELECT
#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
//MMEA3_EDC_CNT3
#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
//MMEA3_MISC_AON
#define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
#define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
#define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
#define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L


// addressBlock: mmhub_ea_mmeadec4
//MMEA4_DRAM_RD_CLI2GRP_MAP0
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA4_DRAM_RD_CLI2GRP_MAP1
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA4_DRAM_WR_CLI2GRP_MAP0
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA4_DRAM_WR_CLI2GRP_MAP1
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA4_DRAM_RD_GRP2VC_MAP
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA4_DRAM_WR_GRP2VC_MAP
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA4_DRAM_RD_LAZY
#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA4_DRAM_WR_LAZY
#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA4_DRAM_RD_CAM_CNTL
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA4_DRAM_WR_CAM_CNTL
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA4_DRAM_PAGE_BURST
#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
//MMEA4_DRAM_RD_PRI_AGE
#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA4_DRAM_WR_PRI_AGE
#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA4_DRAM_RD_PRI_QUEUING
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA4_DRAM_WR_PRI_QUEUING
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA4_DRAM_RD_PRI_FIXED
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA4_DRAM_WR_PRI_FIXED
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA4_DRAM_RD_PRI_URGENCY
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA4_DRAM_WR_PRI_URGENCY
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA4_DRAM_RD_PRI_QUANT_PRI1
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA4_DRAM_RD_PRI_QUANT_PRI2
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA4_DRAM_RD_PRI_QUANT_PRI3
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA4_DRAM_WR_PRI_QUANT_PRI1
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA4_DRAM_WR_PRI_QUANT_PRI2
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA4_DRAM_WR_PRI_QUANT_PRI3
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA4_GMI_RD_CLI2GRP_MAP0
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA4_GMI_RD_CLI2GRP_MAP1
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA4_GMI_WR_CLI2GRP_MAP0
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA4_GMI_WR_CLI2GRP_MAP1
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA4_GMI_RD_GRP2VC_MAP
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA4_GMI_WR_GRP2VC_MAP
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA4_GMI_RD_LAZY
#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA4_GMI_WR_LAZY
#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA4_GMI_RD_CAM_CNTL
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA4_GMI_WR_CAM_CNTL
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA4_GMI_PAGE_BURST
#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA4_GMI_RD_PRI_AGE
#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA4_GMI_WR_PRI_AGE
#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA4_GMI_RD_PRI_QUEUING
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA4_GMI_WR_PRI_QUEUING
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA4_GMI_RD_PRI_FIXED
#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA4_GMI_WR_PRI_FIXED
#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA4_GMI_RD_PRI_URGENCY
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA4_GMI_WR_PRI_URGENCY
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA4_GMI_RD_PRI_URGENCY_MASKING
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA4_GMI_WR_PRI_URGENCY_MASKING
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA4_GMI_RD_PRI_QUANT_PRI1
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA4_GMI_RD_PRI_QUANT_PRI2
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA4_GMI_RD_PRI_QUANT_PRI3
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA4_GMI_WR_PRI_QUANT_PRI1
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA4_GMI_WR_PRI_QUANT_PRI2
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA4_GMI_WR_PRI_QUANT_PRI3
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA4_ADDRNORM_BASE_ADDR0
#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA4_ADDRNORM_LIMIT_ADDR0
#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA4_ADDRNORM_BASE_ADDR1
#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA4_ADDRNORM_LIMIT_ADDR1
#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA4_ADDRNORM_OFFSET_ADDR1
#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA4_ADDRNORM_BASE_ADDR2
#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA4_ADDRNORM_LIMIT_ADDR2
#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA4_ADDRNORM_BASE_ADDR3
#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA4_ADDRNORM_LIMIT_ADDR3
#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA4_ADDRNORM_OFFSET_ADDR3
#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA4_ADDRNORM_MEGABASE_ADDR0
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT                                                       0xc
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA4_ADDRNORM_MEGALIMIT_ADDR0
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA4_ADDRNORM_MEGABASE_ADDR1
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT                                                       0xc
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA4_ADDRNORM_MEGALIMIT_ADDR1
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA4_ADDRNORMDRAM_HOLE_CNTL
#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
//MMEA4_ADDRNORMGMI_HOLE_CNTL
#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
//MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG
#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
//MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG
#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
//MMEA4_ADDRDEC_BANK_CFG
#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
//MMEA4_ADDRDEC_MISC_CFG
#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
//MMEA4_ADDRDECDRAM_HARVEST_ENABLE
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
//MMEA4_ADDRDECGMI_HARVEST_ENABLE
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
//MMEA4_ADDRDEC0_BASE_ADDR_CS0
#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_CS1
#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_CS2
#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_CS3
#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_SECCS0
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_SECCS1
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_SECCS2
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC0_BASE_ADDR_SECCS3
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC0_ADDR_MASK_CS01
#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA4_ADDRDEC0_ADDR_MASK_CS23
#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA4_ADDRDEC0_ADDR_MASK_SECCS01
#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA4_ADDRDEC0_ADDR_MASK_SECCS23
#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA4_ADDRDEC0_ADDR_CFG_CS01
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA4_ADDRDEC0_ADDR_CFG_CS23
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA4_ADDRDEC0_ADDR_SEL_CS01
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC0_ADDR_SEL_CS23
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC0_ADDR_SEL2_CS01
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA4_ADDRDEC0_ADDR_SEL2_CS23
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA4_ADDRDEC0_COL_SEL_LO_CS01
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC0_COL_SEL_LO_CS23
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC0_COL_SEL_HI_CS01
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA4_ADDRDEC0_COL_SEL_HI_CS23
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA4_ADDRDEC0_RM_SEL_CS01
#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA4_ADDRDEC0_RM_SEL_CS23
#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA4_ADDRDEC0_RM_SEL_SECCS01
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA4_ADDRDEC0_RM_SEL_SECCS23
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA4_ADDRDEC1_BASE_ADDR_CS0
#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_CS1
#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_CS2
#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_CS3
#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_SECCS0
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_SECCS1
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_SECCS2
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC1_BASE_ADDR_SECCS3
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC1_ADDR_MASK_CS01
#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA4_ADDRDEC1_ADDR_MASK_CS23
#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA4_ADDRDEC1_ADDR_MASK_SECCS01
#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA4_ADDRDEC1_ADDR_MASK_SECCS23
#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA4_ADDRDEC1_ADDR_CFG_CS01
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA4_ADDRDEC1_ADDR_CFG_CS23
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA4_ADDRDEC1_ADDR_SEL_CS01
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC1_ADDR_SEL_CS23
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC1_ADDR_SEL2_CS01
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA4_ADDRDEC1_ADDR_SEL2_CS23
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA4_ADDRDEC1_COL_SEL_LO_CS01
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC1_COL_SEL_LO_CS23
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC1_COL_SEL_HI_CS01
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA4_ADDRDEC1_COL_SEL_HI_CS23
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA4_ADDRDEC1_RM_SEL_CS01
#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA4_ADDRDEC1_RM_SEL_CS23
#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA4_ADDRDEC1_RM_SEL_SECCS01
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA4_ADDRDEC1_RM_SEL_SECCS23
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA4_ADDRDEC2_BASE_ADDR_CS0
#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_CS1
#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_CS2
#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_CS3
#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_SECCS0
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_SECCS1
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_SECCS2
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC2_BASE_ADDR_SECCS3
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA4_ADDRDEC2_ADDR_MASK_CS01
#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA4_ADDRDEC2_ADDR_MASK_CS23
#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA4_ADDRDEC2_ADDR_MASK_SECCS01
#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA4_ADDRDEC2_ADDR_MASK_SECCS23
#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA4_ADDRDEC2_ADDR_CFG_CS01
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA4_ADDRDEC2_ADDR_CFG_CS23
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA4_ADDRDEC2_ADDR_SEL_CS01
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC2_ADDR_SEL_CS23
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC2_ADDR_SEL2_CS01
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA4_ADDRDEC2_ADDR_SEL2_CS23
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA4_ADDRDEC2_COL_SEL_LO_CS01
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC2_COL_SEL_LO_CS23
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA4_ADDRDEC2_COL_SEL_HI_CS01
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA4_ADDRDEC2_COL_SEL_HI_CS23
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA4_ADDRDEC2_RM_SEL_CS01
#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA4_ADDRDEC2_RM_SEL_CS23
#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA4_ADDRDEC2_RM_SEL_SECCS01
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA4_ADDRDEC2_RM_SEL_SECCS23
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA4_ADDRNORMDRAM_GLOBAL_CNTL
//MMEA4_ADDRNORMGMI_GLOBAL_CNTL
//MMEA4_ADDRNORM_MEGACONTROL_ADDR0
#define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA4_ADDRNORM_MEGACONTROL_ADDR1
#define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA4_ADDRNORMDRAM_MASKING
#define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
#define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
//MMEA4_ADDRNORMGMI_MASKING
#define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT                                                         0x0
#define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK                                                           0x00000FFFL
//MMEA4_IO_RD_CLI2GRP_MAP0
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA4_IO_RD_CLI2GRP_MAP1
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA4_IO_WR_CLI2GRP_MAP0
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA4_IO_WR_CLI2GRP_MAP1
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA4_IO_RD_COMBINE_FLUSH
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA4_IO_WR_COMBINE_FLUSH
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA4_IO_GROUP_BURST
#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA4_IO_RD_PRI_AGE
#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA4_IO_WR_PRI_AGE
#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA4_IO_RD_PRI_QUEUING
#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA4_IO_WR_PRI_QUEUING
#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA4_IO_RD_PRI_FIXED
#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA4_IO_WR_PRI_FIXED
#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA4_IO_RD_PRI_URGENCY
#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA4_IO_WR_PRI_URGENCY
#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA4_IO_RD_PRI_URGENCY_MASKING
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA4_IO_WR_PRI_URGENCY_MASKING
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA4_IO_RD_PRI_QUANT_PRI1
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA4_IO_RD_PRI_QUANT_PRI2
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA4_IO_RD_PRI_QUANT_PRI3
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA4_IO_WR_PRI_QUANT_PRI1
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA4_IO_WR_PRI_QUANT_PRI2
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA4_IO_WR_PRI_QUANT_PRI3
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA4_SDP_ARB_DRAM
#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
//MMEA4_SDP_ARB_GMI
#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
//MMEA4_SDP_ARB_FINAL
#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
#define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
#define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
#define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
#define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
#define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
#define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
#define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
#define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
//MMEA4_SDP_DRAM_PRIORITY
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
//MMEA4_SDP_GMI_PRIORITY
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
//MMEA4_SDP_IO_PRIORITY
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
//MMEA4_SDP_CREDITS
#define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
//MMEA4_SDP_TAG_RESERVE0
#define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define MMEA4_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define MMEA4_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define MMEA4_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define MMEA4_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//MMEA4_SDP_TAG_RESERVE1
#define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define MMEA4_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define MMEA4_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define MMEA4_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define MMEA4_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//MMEA4_SDP_VCC_RESERVE0
#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA4_SDP_VCC_RESERVE1
#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA4_SDP_VCD_RESERVE0
#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA4_SDP_VCD_RESERVE1
#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA4_SDP_REQ_CNTL
#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//MMEA4_MISC
#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
#define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
#define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
//MMEA4_LATENCY_SAMPLING
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
//MMEA4_PERFCOUNTER_LO
#define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//MMEA4_PERFCOUNTER_HI
#define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//MMEA4_PERFCOUNTER0_CFG
#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA4_PERFCOUNTER1_CFG
#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA4_PERFCOUNTER_RSLT_CNTL
#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//MMEA4_EDC_CNT
#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
#define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
#define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
#define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
#define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
//MMEA4_EDC_CNT2
#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
#define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
#define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
#define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
#define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
#define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
#define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
#define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
#define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
#define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
#define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
#define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
#define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
#define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
#define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
#define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
#define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
//MMEA4_DSM_CNTL
#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
//MMEA4_DSM_CNTLA
#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
//MMEA4_DSM_CNTLB
//MMEA4_DSM_CNTL2
#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
#define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
#define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
//MMEA4_DSM_CNTL2A
#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
//MMEA4_DSM_CNTL2B
//MMEA4_CGTT_CLK_CTRL
#define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
#define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
#define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
#define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
//MMEA4_EDC_MODE
#define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define MMEA4_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define MMEA4_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define MMEA4_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define MMEA4_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define MMEA4_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define MMEA4_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define MMEA4_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define MMEA4_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//MMEA4_ERR_STATUS
#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
#define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
#define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
#define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
#define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
#define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
#define MMEA4_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
#define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                     0x12
#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
#define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
#define MMEA4_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
#define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
#define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
#define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
#define MMEA4_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
#define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                       0x00040000L
//MMEA4_MISC2
#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
#define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
#define MMEA4_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
#define MMEA4_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
#define MMEA4_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
#define MMEA4_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
#define MMEA4_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
//MMEA4_ADDRDEC_SELECT
#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
//MMEA4_EDC_CNT3
#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
//MMEA4_MISC_AON
#define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
#define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
#define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
#define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L


// addressBlock: mmhub_ea_mmeadec5
//MMEA5_DRAM_RD_CLI2GRP_MAP0
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA5_DRAM_RD_CLI2GRP_MAP1
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA5_DRAM_WR_CLI2GRP_MAP0
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
//MMEA5_DRAM_WR_CLI2GRP_MAP1
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
//MMEA5_DRAM_RD_GRP2VC_MAP
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA5_DRAM_WR_GRP2VC_MAP
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
//MMEA5_DRAM_RD_LAZY
#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA5_DRAM_WR_LAZY
#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
//MMEA5_DRAM_RD_CAM_CNTL
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA5_DRAM_WR_CAM_CNTL
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
//MMEA5_DRAM_PAGE_BURST
#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
//MMEA5_DRAM_RD_PRI_AGE
#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA5_DRAM_WR_PRI_AGE
#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
//MMEA5_DRAM_RD_PRI_QUEUING
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA5_DRAM_WR_PRI_QUEUING
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
//MMEA5_DRAM_RD_PRI_FIXED
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA5_DRAM_WR_PRI_FIXED
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
//MMEA5_DRAM_RD_PRI_URGENCY
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA5_DRAM_WR_PRI_URGENCY
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
//MMEA5_DRAM_RD_PRI_QUANT_PRI1
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA5_DRAM_RD_PRI_QUANT_PRI2
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA5_DRAM_RD_PRI_QUANT_PRI3
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA5_DRAM_WR_PRI_QUANT_PRI1
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA5_DRAM_WR_PRI_QUANT_PRI2
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA5_DRAM_WR_PRI_QUANT_PRI3
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
//MMEA5_GMI_RD_CLI2GRP_MAP0
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA5_GMI_RD_CLI2GRP_MAP1
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA5_GMI_WR_CLI2GRP_MAP0
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//MMEA5_GMI_WR_CLI2GRP_MAP1
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//MMEA5_GMI_RD_GRP2VC_MAP
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA5_GMI_WR_GRP2VC_MAP
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//MMEA5_GMI_RD_LAZY
#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA5_GMI_WR_LAZY
#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//MMEA5_GMI_RD_CAM_CNTL
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA5_GMI_WR_CAM_CNTL
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
//MMEA5_GMI_PAGE_BURST
#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA5_GMI_RD_PRI_AGE
#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA5_GMI_WR_PRI_AGE
#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//MMEA5_GMI_RD_PRI_QUEUING
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA5_GMI_WR_PRI_QUEUING
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//MMEA5_GMI_RD_PRI_FIXED
#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA5_GMI_WR_PRI_FIXED
#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//MMEA5_GMI_RD_PRI_URGENCY
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA5_GMI_WR_PRI_URGENCY
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//MMEA5_GMI_RD_PRI_URGENCY_MASKING
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA5_GMI_WR_PRI_URGENCY_MASKING
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
//MMEA5_GMI_RD_PRI_QUANT_PRI1
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA5_GMI_RD_PRI_QUANT_PRI2
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA5_GMI_RD_PRI_QUANT_PRI3
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA5_GMI_WR_PRI_QUANT_PRI1
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA5_GMI_WR_PRI_QUANT_PRI2
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA5_GMI_WR_PRI_QUANT_PRI3
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//MMEA5_ADDRNORM_BASE_ADDR0
#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA5_ADDRNORM_LIMIT_ADDR0
#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA5_ADDRNORM_BASE_ADDR1
#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA5_ADDRNORM_LIMIT_ADDR1
#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA5_ADDRNORM_OFFSET_ADDR1
#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA5_ADDRNORM_BASE_ADDR2
#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA5_ADDRNORM_LIMIT_ADDR2
#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA5_ADDRNORM_BASE_ADDR3
#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x7
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000007CL
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x00000080L
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
//MMEA5_ADDRNORM_LIMIT_ADDR3
#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
//MMEA5_ADDRNORM_OFFSET_ADDR3
#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0xc
#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0x00FFF000L
//MMEA5_ADDRNORM_MEGABASE_ADDR0
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT                                                       0xc
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA5_ADDRNORM_MEGALIMIT_ADDR0
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA5_ADDRNORM_MEGABASE_ADDR1
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                    0x0
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                               0x1
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                  0x2
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                  0x7
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                               0x8
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                  0x9
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT                                                       0xc
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK                                                      0x00000001L
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                 0x00000002L
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK                                                    0x0000007CL
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK                                                    0x00000080L
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                 0x00000100L
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK                                                    0x00000E00L
#define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK                                                         0xFFFFF000L
//MMEA5_ADDRNORM_MEGALIMIT_ADDR1
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                  0x0
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                     0xc
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK                                                    0x0000001FL
#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK                                                       0xFFFFF000L
//MMEA5_ADDRNORMDRAM_HOLE_CNTL
#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
//MMEA5_ADDRNORMGMI_HOLE_CNTL
#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
//MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG
#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
//MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG
#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
//MMEA5_ADDRDEC_BANK_CFG
#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
//MMEA5_ADDRDEC_MISC_CFG
#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
//MMEA5_ADDRDECDRAM_HARVEST_ENABLE
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
//MMEA5_ADDRDECGMI_HARVEST_ENABLE
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
//MMEA5_ADDRDEC0_BASE_ADDR_CS0
#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_CS1
#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_CS2
#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_CS3
#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_SECCS0
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_SECCS1
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_SECCS2
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC0_BASE_ADDR_SECCS3
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC0_ADDR_MASK_CS01
#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA5_ADDRDEC0_ADDR_MASK_CS23
#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA5_ADDRDEC0_ADDR_MASK_SECCS01
#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA5_ADDRDEC0_ADDR_MASK_SECCS23
#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA5_ADDRDEC0_ADDR_CFG_CS01
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA5_ADDRDEC0_ADDR_CFG_CS23
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA5_ADDRDEC0_ADDR_SEL_CS01
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC0_ADDR_SEL_CS23
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC0_ADDR_SEL2_CS01
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA5_ADDRDEC0_ADDR_SEL2_CS23
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA5_ADDRDEC0_COL_SEL_LO_CS01
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC0_COL_SEL_LO_CS23
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC0_COL_SEL_HI_CS01
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA5_ADDRDEC0_COL_SEL_HI_CS23
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA5_ADDRDEC0_RM_SEL_CS01
#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA5_ADDRDEC0_RM_SEL_CS23
#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA5_ADDRDEC0_RM_SEL_SECCS01
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA5_ADDRDEC0_RM_SEL_SECCS23
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA5_ADDRDEC1_BASE_ADDR_CS0
#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_CS1
#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_CS2
#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_CS3
#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_SECCS0
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_SECCS1
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_SECCS2
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC1_BASE_ADDR_SECCS3
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC1_ADDR_MASK_CS01
#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA5_ADDRDEC1_ADDR_MASK_CS23
#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA5_ADDRDEC1_ADDR_MASK_SECCS01
#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA5_ADDRDEC1_ADDR_MASK_SECCS23
#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA5_ADDRDEC1_ADDR_CFG_CS01
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA5_ADDRDEC1_ADDR_CFG_CS23
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA5_ADDRDEC1_ADDR_SEL_CS01
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC1_ADDR_SEL_CS23
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC1_ADDR_SEL2_CS01
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA5_ADDRDEC1_ADDR_SEL2_CS23
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA5_ADDRDEC1_COL_SEL_LO_CS01
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC1_COL_SEL_LO_CS23
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC1_COL_SEL_HI_CS01
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA5_ADDRDEC1_COL_SEL_HI_CS23
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA5_ADDRDEC1_RM_SEL_CS01
#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA5_ADDRDEC1_RM_SEL_CS23
#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA5_ADDRDEC1_RM_SEL_SECCS01
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA5_ADDRDEC1_RM_SEL_SECCS23
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA5_ADDRDEC2_BASE_ADDR_CS0
#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_CS1
#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_CS2
#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_CS3
#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_SECCS0
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_SECCS1
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_SECCS2
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC2_BASE_ADDR_SECCS3
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
//MMEA5_ADDRDEC2_ADDR_MASK_CS01
#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA5_ADDRDEC2_ADDR_MASK_CS23
#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
//MMEA5_ADDRDEC2_ADDR_MASK_SECCS01
#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA5_ADDRDEC2_ADDR_MASK_SECCS23
#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
//MMEA5_ADDRDEC2_ADDR_CFG_CS01
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
//MMEA5_ADDRDEC2_ADDR_CFG_CS23
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
//MMEA5_ADDRDEC2_ADDR_SEL_CS01
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC2_ADDR_SEL_CS23
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC2_ADDR_SEL2_CS01
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA5_ADDRDEC2_ADDR_SEL2_CS23
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
//MMEA5_ADDRDEC2_COL_SEL_LO_CS01
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC2_COL_SEL_LO_CS23
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
//MMEA5_ADDRDEC2_COL_SEL_HI_CS01
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
//MMEA5_ADDRDEC2_COL_SEL_HI_CS23
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
//MMEA5_ADDRDEC2_RM_SEL_CS01
#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA5_ADDRDEC2_RM_SEL_CS23
#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
//MMEA5_ADDRDEC2_RM_SEL_SECCS01
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA5_ADDRDEC2_RM_SEL_SECCS23
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
//MMEA5_ADDRNORMDRAM_GLOBAL_CNTL
//MMEA5_ADDRNORMGMI_GLOBAL_CNTL
//MMEA5_ADDRNORM_MEGACONTROL_ADDR0
#define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA5_ADDRNORM_MEGACONTROL_ADDR1
#define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT                                       0x0
#define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK                                         0x0000003FL
//MMEA5_ADDRNORMDRAM_MASKING
#define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
#define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
//MMEA5_ADDRNORMGMI_MASKING
#define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT                                                         0x0
#define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK                                                           0x00000FFFL
//MMEA5_IO_RD_CLI2GRP_MAP0
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA5_IO_RD_CLI2GRP_MAP1
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA5_IO_WR_CLI2GRP_MAP0
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
//MMEA5_IO_WR_CLI2GRP_MAP1
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
//MMEA5_IO_RD_COMBINE_FLUSH
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA5_IO_WR_COMBINE_FLUSH
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
#define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
#define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
//MMEA5_IO_GROUP_BURST
#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//MMEA5_IO_RD_PRI_AGE
#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA5_IO_WR_PRI_AGE
#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
//MMEA5_IO_RD_PRI_QUEUING
#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA5_IO_WR_PRI_QUEUING
#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
//MMEA5_IO_RD_PRI_FIXED
#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA5_IO_WR_PRI_FIXED
#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
//MMEA5_IO_RD_PRI_URGENCY
#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA5_IO_WR_PRI_URGENCY
#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
//MMEA5_IO_RD_PRI_URGENCY_MASKING
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA5_IO_WR_PRI_URGENCY_MASKING
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
//MMEA5_IO_RD_PRI_QUANT_PRI1
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA5_IO_RD_PRI_QUANT_PRI2
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA5_IO_RD_PRI_QUANT_PRI3
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA5_IO_WR_PRI_QUANT_PRI1
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA5_IO_WR_PRI_QUANT_PRI2
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA5_IO_WR_PRI_QUANT_PRI3
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
//MMEA5_SDP_ARB_DRAM
#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
//MMEA5_SDP_ARB_GMI
#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
//MMEA5_SDP_ARB_FINAL
#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
#define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
#define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
#define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
#define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
#define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
#define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
#define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
#define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
//MMEA5_SDP_DRAM_PRIORITY
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
//MMEA5_SDP_GMI_PRIORITY
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
//MMEA5_SDP_IO_PRIORITY
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
//MMEA5_SDP_CREDITS
#define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
//MMEA5_SDP_TAG_RESERVE0
#define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define MMEA5_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define MMEA5_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define MMEA5_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define MMEA5_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//MMEA5_SDP_TAG_RESERVE1
#define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define MMEA5_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define MMEA5_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define MMEA5_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define MMEA5_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//MMEA5_SDP_VCC_RESERVE0
#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA5_SDP_VCC_RESERVE1
#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA5_SDP_VCD_RESERVE0
#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//MMEA5_SDP_VCD_RESERVE1
#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//MMEA5_SDP_REQ_CNTL
#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//MMEA5_MISC
#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
#define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
#define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
//MMEA5_LATENCY_SAMPLING
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
//MMEA5_PERFCOUNTER_LO
#define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//MMEA5_PERFCOUNTER_HI
#define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//MMEA5_PERFCOUNTER0_CFG
#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA5_PERFCOUNTER1_CFG
#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//MMEA5_PERFCOUNTER_RSLT_CNTL
#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//MMEA5_EDC_CNT
#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
#define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
#define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
#define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
#define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
//MMEA5_EDC_CNT2
#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
#define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
#define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
#define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
#define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
#define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
#define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
#define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
#define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
#define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
#define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
#define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
#define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
#define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
#define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
#define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
#define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
//MMEA5_DSM_CNTL
#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
//MMEA5_DSM_CNTLA
#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
//MMEA5_DSM_CNTLB
//MMEA5_DSM_CNTL2
#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
#define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
#define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
//MMEA5_DSM_CNTL2A
#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
//MMEA5_DSM_CNTL2B
//MMEA5_CGTT_CLK_CTRL
#define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
#define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
#define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
#define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
//MMEA5_EDC_MODE
#define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define MMEA5_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define MMEA5_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define MMEA5_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define MMEA5_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define MMEA5_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define MMEA5_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define MMEA5_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define MMEA5_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//MMEA5_ERR_STATUS
#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
#define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
#define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
#define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
#define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
#define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
#define MMEA5_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
#define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                     0x12
#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
#define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
#define MMEA5_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
#define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
#define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
#define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
#define MMEA5_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
#define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                       0x00040000L
//MMEA5_MISC2
#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
#define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
#define MMEA5_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
#define MMEA5_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
#define MMEA5_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
#define MMEA5_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
#define MMEA5_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
//MMEA5_ADDRDEC_SELECT
#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
//MMEA5_EDC_CNT3
#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
//MMEA5_MISC_AON
#define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
#define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
#define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
#define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L


// addressBlock: mmhub_l1tlb_vml1dec
//MC_VM_MX_L1_TLB0_STATUS
#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB1_STATUS
#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB2_STATUS
#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB3_STATUS
#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB4_STATUS
#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB5_STATUS
#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB6_STATUS
#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L
//MC_VM_MX_L1_TLB7_STATUS
#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                                  0x0
#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                   0x1
#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                                    0x00000001L
#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                                     0x00000002L


// addressBlock: mmhub_l1tlb_vml1pldec
//MC_VM_MX_L1_PERFCOUNTER0_CFG
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                     0x8
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                        0x18
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                           0x1c
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                            0x1d
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                           0x000000FFL
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                       0x0000FF00L
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                          0x0F000000L
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                             0x10000000L
#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                              0x20000000L
//MC_VM_MX_L1_PERFCOUNTER1_CFG
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                     0x8
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                        0x18
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                           0x1c
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                            0x1d
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                           0x000000FFL
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                       0x0000FF00L
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                          0x0F000000L
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                             0x10000000L
#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                              0x20000000L
//MC_VM_MX_L1_PERFCOUNTER2_CFG
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                     0x8
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                        0x18
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                           0x1c
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                            0x1d
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                           0x000000FFL
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                       0x0000FF00L
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                          0x0F000000L
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                             0x10000000L
#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                              0x20000000L
//MC_VM_MX_L1_PERFCOUNTER3_CFG
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                     0x8
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                        0x18
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                           0x1c
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                            0x1d
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                           0x000000FFL
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                       0x0000FF00L
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                          0x0F000000L
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                             0x10000000L
#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                              0x20000000L
//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                               0x8
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                0x10
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                  0x18
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                   0x19
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                        0x1a
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                           0x0000000FL
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                 0x0000FF00L
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                  0x00FF0000L
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                    0x01000000L
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                     0x02000000L
#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                          0x04000000L


// addressBlock: mmhub_l1tlb_vml1prdec
//MC_VM_MX_L1_PERFCOUNTER_LO
#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                           0xFFFFFFFFL
//MC_VM_MX_L1_PERFCOUNTER_HI
#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                         0x0
#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                      0x10
#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                           0x0000FFFFL
#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                        0xFFFF0000L


// addressBlock: mmhub_pctldec0
//PCTL0_CTRL
#define PCTL0_CTRL__PG_ENABLE__SHIFT                                                                          0x0
#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                              0x1
#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                     0x10
#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT                                                                0x11
#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT                                                                0x12
#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT                                                                0x13
#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT                                                                0x14
#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT                                                                0x15
#define PCTL0_CTRL__OVR_EA5_SDP_PARTACK__SHIFT                                                                0x16
#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT                                                                0x17
#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT                                                                0x18
#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT                                                                0x19
#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT                                                                0x1a
#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT                                                                0x1b
#define PCTL0_CTRL__OVR_EA5_SDP_FULLACK__SHIFT                                                                0x1c
#define PCTL0_CTRL__PG_ENABLE_MASK                                                                            0x00000001L
#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                0x0000000EL
#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                           0x0000F800L
#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                       0x00010000L
#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK                                                                  0x00020000L
#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK                                                                  0x00040000L
#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK                                                                  0x00080000L
#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK                                                                  0x00100000L
#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK                                                                  0x00200000L
#define PCTL0_CTRL__OVR_EA5_SDP_PARTACK_MASK                                                                  0x00400000L
#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK                                                                  0x00800000L
#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK                                                                  0x01000000L
#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK                                                                  0x02000000L
#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK                                                                  0x04000000L
#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK                                                                  0x08000000L
#define PCTL0_CTRL__OVR_EA5_SDP_FULLACK_MASK                                                                  0x10000000L
//PCTL0_MMHUB_DEEPSLEEP_IB
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                  0x0
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                  0x1
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                  0x2
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                  0x3
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                  0x4
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                  0x5
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                  0x6
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                  0x7
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                  0x8
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                  0x9
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                 0xa
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                 0xb
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                 0xc
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                 0xd
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                 0xe
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                 0xf
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                 0x10
#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                             0x1f
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                    0x00000001L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                    0x00000002L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                    0x00000004L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                    0x00000008L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                    0x00000010L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                    0x00000020L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                    0x00000040L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                    0x00000080L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                    0x00000100L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                    0x00000200L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                   0x00000400L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                   0x00000800L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                   0x00001000L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                   0x00002000L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                   0x00004000L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                   0x00008000L
#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                   0x00010000L
#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                               0x80000000L
//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                            0x0
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                            0x1
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                            0x2
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                            0x3
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                            0x4
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                            0x5
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                            0x6
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                            0x7
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                            0x8
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                            0x9
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                           0xa
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                           0xb
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                           0xc
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                           0xd
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                           0xe
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                           0xf
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                           0x10
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                       0x11
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                              0x00000001L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                              0x00000002L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                              0x00000004L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                              0x00000008L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                              0x00000010L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                              0x00000020L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                              0x00000040L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                              0x00000080L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                              0x00000100L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                              0x00000200L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                             0x00000400L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                             0x00000800L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                             0x00001000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                             0x00002000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                             0x00004000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                             0x00008000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                             0x00010000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                         0x00020000L
//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                         0x0
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                         0x1
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                         0x2
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                         0x3
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                         0x4
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                         0x5
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                         0x6
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                         0x7
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                         0x8
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                         0x9
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                        0xa
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                        0xb
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                        0xc
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                        0xd
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                        0xe
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                        0xf
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                        0x10
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                           0x00000001L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                           0x00000002L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                           0x00000004L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                           0x00000008L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                           0x00000010L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                           0x00000020L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                           0x00000040L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                           0x00000080L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                           0x00000100L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                           0x00000200L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                          0x00000400L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                          0x00000800L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                          0x00001000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                          0x00002000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                          0x00004000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                          0x00008000L
#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                          0x00010000L
//PCTL0_PG_IGNORE_DEEPSLEEP
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                 0x0
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                 0x1
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                 0x2
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                 0x3
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                 0x4
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                 0x5
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                 0x6
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                 0x7
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                 0x8
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                 0x9
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                0xa
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                0xb
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                0xc
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                0xd
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                0xe
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                0xf
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                0x10
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                            0x11
#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                              0x12
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                   0x00000001L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                   0x00000002L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                   0x00000004L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                   0x00000008L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                   0x00000010L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                   0x00000020L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                   0x00000040L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                   0x00000080L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                   0x00000100L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                   0x00000200L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                  0x00000400L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                  0x00000800L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                  0x00001000L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                  0x00002000L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                  0x00004000L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                  0x00008000L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                  0x00010000L
#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                              0x00020000L
#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                0x00040000L
//PCTL0_PG_IGNORE_DEEPSLEEP_IB
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                              0x0
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                              0x1
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                              0x2
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                              0x3
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                              0x4
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                              0x5
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                              0x6
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                              0x7
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                              0x8
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                              0x9
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                             0xa
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                             0xb
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                             0xc
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                             0xd
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                             0xe
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                             0xf
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                             0x10
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                           0x11
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                               0x00010000L
#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                             0x00020000L
//PCTL0_SLICE0_CFG_DAGB_BUSY
#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
//PCTL0_SLICE0_CFG_DS_ALLOW
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
//PCTL0_SLICE0_CFG_DS_ALLOW_IB
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
//PCTL0_SLICE1_CFG_DAGB_BUSY
#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
//PCTL0_SLICE1_CFG_DS_ALLOW
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
//PCTL0_SLICE1_CFG_DS_ALLOW_IB
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
//PCTL0_SLICE2_CFG_DAGB_BUSY
#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
//PCTL0_SLICE2_CFG_DS_ALLOW
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
//PCTL0_SLICE2_CFG_DS_ALLOW_IB
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
//PCTL0_SLICE3_CFG_DAGB_BUSY
#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
//PCTL0_SLICE3_CFG_DS_ALLOW
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
//PCTL0_SLICE3_CFG_DS_ALLOW_IB
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
//PCTL0_SLICE4_CFG_DAGB_BUSY
#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
//PCTL0_SLICE4_CFG_DS_ALLOW
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
//PCTL0_SLICE4_CFG_DS_ALLOW_IB
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
//PCTL0_SLICE5_CFG_DAGB_BUSY
#define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
#define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
//PCTL0_SLICE5_CFG_DS_ALLOW
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
#define PCTL0_SLICE5_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
//PCTL0_SLICE5_CFG_DS_ALLOW_IB
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
//PCTL0_UTCL2_MISC
#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xb
#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xc
#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xf
#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0x10
#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000800L
#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00007000L
#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00008000L
#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00010000L
#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
//PCTL0_SLICE0_MISC
#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
//PCTL0_SLICE1_MISC
#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
//PCTL0_SLICE2_MISC
#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
//PCTL0_SLICE3_MISC
#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
//PCTL0_SLICE4_MISC
#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
//PCTL0_SLICE5_MISC
#define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
#define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
#define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
#define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
#define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
#define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
#define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
#define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
#define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
#define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
#define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
#define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
#define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
#define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L


// addressBlock: mmhub_utcl2_atcl2dec
//ATC_L2_CNTL
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                               0x0
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                              0x3
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                   0x6
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                                  0x7
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                          0x8
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                         0xb
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                              0xe
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                             0xf
#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                             0x10
#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                          0x13
#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                               0x14
#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT                                                             0x16
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                                 0x00000003L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                                0x00000018L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                     0x00000040L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                    0x00000080L
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                            0x00000300L
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                           0x00001800L
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                0x00004000L
#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                               0x00008000L
#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                               0x00070000L
#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                            0x00080000L
#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK                                                                 0x00300000L
#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK                                                               0x0FC00000L
//ATC_L2_CNTL2
#define ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                      0x0
#define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT                                                                   0x6
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                             0x9
#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                              0xb
#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                     0xc
#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                               0xf
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                         0x12
#define ATC_L2_CNTL2__BANK_SELECT_MASK                                                                        0x0000003FL
#define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK                                                                     0x000001C0L
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                               0x00000600L
#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                                0x00000800L
#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                       0x00007000L
#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                                 0x00038000L
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                           0x00FC0000L
//ATC_L2_CACHE_DATA0
#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                        0x0
#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                          0x1
#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                          0x2
#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                                  0x17
#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                          0x00000001L
#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                            0x00000002L
#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                            0x007FFFFCL
#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                    0x07800000L
//ATC_L2_CACHE_DATA1
#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                   0x0
#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                     0xFFFFFFFFL
//ATC_L2_CACHE_DATA2
#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                      0x0
#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                        0xFFFFFFFFL
//ATC_L2_CACHE_DATA3
#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT                                                      0x0
#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK                                                        0xFFFFFFFFL
//ATC_L2_CNTL3
#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT                                                          0x0
#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT                                                            0x6
#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT                                                            0xc
#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                                  0x12
#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                        0x15
#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                        0x1b
#define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT                                                                0x1e
#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK                                                            0x0000003FL
#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK                                                              0x00000FC0L
#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK                                                              0x0003F000L
#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                    0x001C0000L
#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                          0x07E00000L
#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                          0x38000000L
#define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK                                                                  0x40000000L
//ATC_L2_STATUS
#define ATC_L2_STATUS__BUSY__SHIFT                                                                            0x0
#define ATC_L2_STATUS__BUSY_MASK                                                                              0x00000001L
//ATC_L2_STATUS2
#define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT                                                                   0x0
#define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT                                                                   0xc
#define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT                                                                  0x12
#define ATC_L2_STATUS2__UCE__SHIFT                                                                            0x13
#define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK                                                                     0x00000FFFL
#define ATC_L2_STATUS2__UCE_MEM_INST_MASK                                                                     0x0003F000L
#define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK                                                                    0x00040000L
#define ATC_L2_STATUS2__UCE_MASK                                                                              0x00080000L
//ATC_L2_MISC_CG
#define ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                         0x6
#define ATC_L2_MISC_CG__ENABLE__SHIFT                                                                         0x12
#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                                  0x13
#define ATC_L2_MISC_CG__OFFDLY_MASK                                                                           0x00000FC0L
#define ATC_L2_MISC_CG__ENABLE_MASK                                                                           0x00040000L
#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                    0x00080000L
//ATC_L2_MEM_POWER_LS
#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                                  0x0
#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                   0x6
#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                    0x0000003FL
#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                     0x00000FC0L
//ATC_L2_CGTT_CLK_CTRL
#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                            0xf
#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                      0x10
#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                            0x18
#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                              0x00008000L
#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                        0x00FF0000L
#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                              0xFF000000L
//ATC_L2_CACHE_4K_DSM_INDEX
#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT                                                               0x0
#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK                                                                 0x000000FFL
//ATC_L2_CACHE_32K_DSM_INDEX
#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT                                                              0x0
#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK                                                                0x000000FFL
//ATC_L2_CACHE_2M_DSM_INDEX
#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT                                                               0x0
#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK                                                                 0x000000FFL
//ATC_L2_CACHE_4K_DSM_CNTL
#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT                                                         0x0
#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                   0x6
#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                  0x9
#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                                  0xb
#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                                       0xc
#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT                                                            0xd
#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT                                                            0xf
#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT                                                             0x11
#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK                                                           0x0000003FL
#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                                    0x00000800L
#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK                                                         0x00001000L
#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK                                                              0x00006000L
#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK                                                              0x00018000L
#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK                                                               0x00020000L
//ATC_L2_CACHE_32K_DSM_CNTL
#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT                                                        0x0
#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                  0x6
#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                 0x8
#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                 0x9
#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                                 0xb
#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                                      0xc
#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT                                                           0xd
#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT                                                           0xf
#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT                                                            0x11
#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK                                                          0x0000003FL
#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                                    0x000000C0L
#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                                   0x00000100L
#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                                   0x00000600L
#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                                   0x00000800L
#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK                                                        0x00001000L
#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK                                                             0x00006000L
#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK                                                             0x00018000L
#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK                                                              0x00020000L
//ATC_L2_CACHE_2M_DSM_CNTL
#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT                                                         0x0
#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                   0x6
#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                  0x9
#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                                  0xb
#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT                                                       0xc
#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT                                                            0xd
#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT                                                            0xf
#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT                                                             0x11
#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK                                                           0x0000003FL
#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                                    0x00000800L
#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK                                                         0x00001000L
#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK                                                              0x00006000L
#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK                                                              0x00018000L
#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK                                                               0x00020000L
//ATC_L2_CNTL4
#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                          0x0
#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0xa
#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                            0x000003FFL
#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x000FFC00L
//ATC_L2_MM_GROUP_RT_CLASSES
#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                                     0x0
#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                                       0xFFFFFFFFL


// addressBlock: mmhub_utcl2_atcl2pfcntldec
//ATC_L2_PERFCOUNTER0_CFG
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                              0x0
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                          0x8
#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                             0x18
#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                0x1c
#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                 0x1d
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                0x000000FFL
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                               0x0F000000L
#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                  0x10000000L
#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                   0x20000000L
//ATC_L2_PERFCOUNTER1_CFG
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                              0x0
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                          0x8
#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                             0x18
#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                0x1c
#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                 0x1d
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                0x000000FFL
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                               0x0F000000L
#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                  0x10000000L
#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                   0x20000000L
//ATC_L2_PERFCOUNTER_RSLT_CNTL
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                              0x0
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                    0x8
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                     0x10
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                       0x18
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                        0x19
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                             0x1a
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                0x0000000FL
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                      0x0000FF00L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                       0x00FF0000L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                         0x01000000L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                          0x02000000L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                               0x04000000L


// addressBlock: mmhub_utcl2_atcl2pfcntrdec
//ATC_L2_PERFCOUNTER_LO
#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                              0x0
#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                0xFFFFFFFFL
//ATC_L2_PERFCOUNTER_HI
#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                              0x0
#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                           0x10
#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                0x0000FFFFL
#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                             0xFFFF0000L


// addressBlock: mmhub_utcl2_l2tlbdec
//L2TLB_TLB0_STATUS
#define L2TLB_TLB0_STATUS__BUSY__SHIFT                                                                        0x0
#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                         0x1
#define L2TLB_TLB0_STATUS__BUSY_MASK                                                                          0x00000001L
#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                           0x00000002L
//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT                                             0x0
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK                                               0xFFFFFFFFL
//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT                                             0x0
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT                                             0x4
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT                                             0x9
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT                                               0xd
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT                                              0xe
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT                                          0x10
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT                                          0x11
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT                                          0x12
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT                                        0x13
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT                                              0x1f
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK                                               0x0000000FL
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK                                               0x000000F0L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK                                               0x00001E00L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK                                                 0x00002000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK                                                0x0000C000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK                                            0x00010000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK                                            0x00020000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK                                            0x00040000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK                                          0x0FF80000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK                                                0x80000000L
//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT                                            0x0
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK                                              0xFFFFFFFFL
//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT                                            0x0
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT                                           0x4
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT                                   0x7
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT                                           0xd
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT                                             0xe
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT                                              0xf
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT                                         0x10
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT                                          0x11
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT                                           0x12
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT                                          0x14
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT                                            0x15
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT                                             0x1e
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK                                              0x0000000FL
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK                                             0x00000070L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK                                     0x00001F80L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK                                             0x00002000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK                                               0x00004000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK                                                0x00008000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK                                           0x00010000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK                                            0x00020000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK                                             0x000C0000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK                                            0x00100000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK                                              0x00600000L
#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK                                               0x40000000L


// addressBlock: mmhub_utcl2_l2tlbpldec
//L2TLB_PERFCOUNTER0_CFG
#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//L2TLB_PERFCOUNTER1_CFG
#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//L2TLB_PERFCOUNTER2_CFG
#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//L2TLB_PERFCOUNTER3_CFG
#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                               0x0
#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                              0x18
#define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                                 0x1c
#define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                  0x1d
#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK                                                                   0x10000000L
#define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK                                                                    0x20000000L
//L2TLB_PERFCOUNTER_RSLT_CNTL
#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L


// addressBlock: mmhub_utcl2_l2tlbprdec
//L2TLB_PERFCOUNTER_LO
#define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//L2TLB_PERFCOUNTER_HI
#define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L


// addressBlock: mmhub_utcl2_vml2pfdec
//VM_L2_CNTL
#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                    0x0
#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                      0x1
#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                      0x2
#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                      0x4
#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                  0x8
#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                            0x9
#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0xa
#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                           0xb
#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                           0xc
#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                            0xf
#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                           0x12
#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                      0x13
#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                        0x15
#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                             0x1a
#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                      0x00000001L
#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                        0x00000002L
#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                        0x0000000CL
#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                        0x00000030L
#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                    0x00000100L
#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                              0x00000200L
#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000400L
#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                             0x00000800L
#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                             0x00007000L
#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                              0x00038000L
#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                             0x00040000L
#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                        0x00180000L
#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                          0x03E00000L
#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                               0x0C000000L
//VM_L2_CNTL2
#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                            0x0
#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                               0x1
#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                     0x15
#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                   0x16
#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                            0x17
#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                             0x1a
#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                              0x00000001L
#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                                 0x00000002L
#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                       0x00200000L
#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                     0x00400000L
#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                              0x03800000L
#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                               0x0C000000L
#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                            0x70000000L
//VM_L2_CNTL3
#define VM_L2_CNTL3__BANK_SELECT__SHIFT                                                                       0x0
#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                              0x6
#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                          0x8
#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                       0xf
#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                       0x14
#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                      0x18
#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                            0x1c
#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                          0x1d
#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                              0x1e
#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                         0x1f
#define VM_L2_CNTL3__BANK_SELECT_MASK                                                                         0x0000003FL
#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                                0x000000C0L
#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                            0x00001F00L
#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                         0x000F8000L
#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                         0x00100000L
#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                              0x10000000L
#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                            0x20000000L
#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                                0x40000000L
#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                           0x80000000L
//VM_L2_STATUS
#define VM_L2_STATUS__L2_BUSY__SHIFT                                                                          0x0
#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                              0x1
#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                                 0x11
#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x12
#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                   0x13
#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                   0x14
#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                   0x15
#define VM_L2_STATUS__L2_BUSY_MASK                                                                            0x00000001L
#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                                0x0001FFFEL
#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                   0x00020000L
#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00040000L
#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                     0x00080000L
#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                     0x00100000L
#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                     0x00200000L
//VM_DUMMY_PAGE_FAULT_CNTL
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                              0x0
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                           0x1
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                              0x2
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                                0x00000001L
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                             0x00000002L
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                                0x000000FCL
//VM_DUMMY_PAGE_FAULT_ADDR_LO32
#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                            0x0
#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                              0xFFFFFFFFL
//VM_DUMMY_PAGE_FAULT_ADDR_HI32
#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                             0x0
#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                               0x0000000FL
//VM_L2_PROTECTION_FAULT_CNTL
#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                0x0
#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT             0x1
#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x2
#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x3
#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x4
#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x5
#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                 0x6
#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x7
#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                        0x8
#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x9
#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0xa
#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0xb
#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                                0xd
#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                          0x1d
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                           0x1e
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                              0x1f
#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                  0x00000001L
#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK               0x00000002L
#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000004L
#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000008L
#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000010L
#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000020L
#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                   0x00000040L
#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000080L
#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                          0x00000100L
#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000200L
#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000400L
#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000800L
#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                  0x1FFFE000L
#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                            0x20000000L
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                             0x40000000L
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                                0x80000000L
//VM_L2_PROTECTION_FAULT_CNTL2
#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                    0x0
#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                              0x10
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                        0x11
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                             0x12
#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                     0x13
#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                      0x0000FFFFL
#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                0x00010000L
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                          0x00020000L
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                               0x00040000L
#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                       0x00080000L
//VM_L2_PROTECTION_FAULT_MM_CNTL3
#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x0
#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_MM_CNTL4
#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                 0x0
#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                   0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_STATUS
#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                     0x0
#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                    0x1
#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                               0x4
#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                   0x8
#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                             0x9
#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                              0x12
#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                          0x13
#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                            0x14
#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                              0x18
#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                            0x19
#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT                                                             0x1d
#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT                                                             0x1e
#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                       0x00000001L
#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                      0x0000000EL
#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                                 0x000000F0L
#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                     0x00000100L
#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                               0x0003FE00L
#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                                0x00040000L
#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                            0x00080000L
#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                              0x00F00000L
#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                                0x01000000L
#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                              0x1E000000L
#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK                                                               0x20000000L
#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK                                                               0x40000000L
//VM_L2_PROTECTION_FAULT_ADDR_LO32
#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                       0x0
#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                         0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_ADDR_HI32
#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                        0x0
#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                          0x0000000FL
//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                              0x0
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                                0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                               0x0
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                                 0x0000000FL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                         0x0
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                           0xFFFFFFFFL
//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                          0x0
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                            0x0000000FL
//VM_L2_CNTL4
#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                       0x0
#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                      0x6
#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                      0x7
#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                           0x8
#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                          0x12
#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                               0x1c
#define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                    0x1d
#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT                                                               0x1e
#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                         0x0000003FL
#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                        0x00000040L
#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                        0x00000080L
#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                             0x0003FF00L
#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                            0x0FFC0000L
#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                                 0x10000000L
#define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                      0x20000000L
#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK                                                                 0x40000000L
//VM_L2_MM_GROUP_RT_CLASSES
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                    0x0
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                    0x1
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                    0x2
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                    0x3
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                    0x4
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                    0x5
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                    0x6
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                    0x7
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                    0x8
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                    0x9
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                   0xa
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                   0xb
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                   0xc
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                   0xd
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                   0xe
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                   0xf
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                   0x10
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                   0x11
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                   0x12
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                   0x13
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                   0x14
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                   0x15
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                   0x16
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                   0x17
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                   0x18
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                   0x19
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                   0x1a
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                   0x1b
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                   0x1c
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                   0x1d
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                   0x1e
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                   0x1f
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                      0x00000001L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                      0x00000002L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                      0x00000004L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                      0x00000008L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                      0x00000010L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                      0x00000020L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                      0x00000040L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                      0x00000080L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                      0x00000100L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                      0x00000200L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                     0x00000400L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                     0x00000800L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                     0x00001000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                     0x00002000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                     0x00004000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                     0x00008000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                     0x00010000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                     0x00020000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                     0x00040000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                     0x00080000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                     0x00100000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                     0x00200000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                     0x00400000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                     0x00800000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                     0x01000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                     0x02000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                     0x04000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                     0x08000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                     0x10000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                     0x20000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                     0x40000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                     0x80000000L
//VM_L2_BANK_SELECT_RESERVED_CID
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                        0x0
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                       0xa
#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                         0x14
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                               0x18
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                            0x19
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                          0x000001FFL
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                         0x0007FC00L
#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                           0x00100000L
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                                 0x01000000L
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                              0x02000000L
//VM_L2_BANK_SELECT_RESERVED_CID2
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                       0x0
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                      0xa
#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                        0x14
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                              0x18
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                           0x19
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                         0x000001FFL
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                        0x0007FC00L
#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                          0x00100000L
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                                0x01000000L
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                             0x02000000L
//VM_L2_CACHE_PARITY_CNTL
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                                 0x0
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                               0x1
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                    0x2
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                                 0x3
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                               0x4
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                    0x5
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                      0x6
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                    0x9
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                     0xc
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                   0x00000001L
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                                 0x00000002L
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                      0x00000004L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                   0x00000008L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                                 0x00000010L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                      0x00000020L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                        0x000001C0L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                      0x00000E00L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                       0x0000F000L
//VM_L2_CGTT_CLK_CTRL
#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
//VM_L2_CGTT_BUSY_CTRL
#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                               0x0
#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                              0x4
#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                                 0x0000000FL
#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                                0x00000010L
//VML2_MEM_ECC_INDEX
#define VML2_MEM_ECC_INDEX__INDEX__SHIFT                                                                      0x0
#define VML2_MEM_ECC_INDEX__INDEX_MASK                                                                        0x000000FFL
//VML2_WALKER_MEM_ECC_INDEX
#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT                                                               0x0
#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK                                                                 0x000000FFL
//UTCL2_MEM_ECC_INDEX
#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT                                                                     0x0
#define UTCL2_MEM_ECC_INDEX__INDEX_MASK                                                                       0x000000FFL
//VML2_MEM_ECC_CNTL
#define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT                                                                0x0
#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                          0x6
#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                         0x8
#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                         0x9
#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT                                                         0xb
#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT                                                                   0xc
#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT                                                                   0xe
#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT                                                              0x10
#define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT                                                                    0x11
#define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK                                                                  0x0000003FL
#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK                                                            0x000000C0L
#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK                                                           0x00000100L
#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK                                                           0x00000600L
#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK                                                           0x00000800L
#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK                                                                     0x00003000L
#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK                                                                     0x0000C000L
#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK                                                                0x00010000L
#define VML2_MEM_ECC_CNTL__TEST_FUE_MASK                                                                      0x00020000L
//VML2_WALKER_MEM_ECC_CNTL
#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT                                                         0x0
#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                   0x6
#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                  0x8
#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                  0x9
#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT                                                  0xb
#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT                                                            0xc
#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT                                                            0xe
#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT                                                       0x10
#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT                                                             0x11
#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK                                                           0x0000003FL
#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK                                                     0x000000C0L
#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK                                                    0x00000100L
#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK                                                    0x00000600L
#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK                                                    0x00000800L
#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK                                                              0x00003000L
#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK                                                              0x0000C000L
#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK                                                         0x00010000L
#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK                                                               0x00020000L
//UTCL2_MEM_ECC_CNTL
#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT                                                               0x0
#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT                                                         0x6
#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                                        0x8
#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT                                                        0x9
#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT                                                        0xb
#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT                                                                  0xc
#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT                                                                  0xe
#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT                                                             0x10
#define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT                                                                   0x11
#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK                                                                 0x0000003FL
#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK                                                           0x000000C0L
#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK                                                          0x00000100L
#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK                                                          0x00000600L
#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK                                                          0x00000800L
#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK                                                                    0x00003000L
#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK                                                                    0x0000C000L
#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK                                                               0x00010000L
#define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK                                                                     0x00020000L
//VML2_MEM_ECC_STATUS
#define VML2_MEM_ECC_STATUS__UCE__SHIFT                                                                       0x0
#define VML2_MEM_ECC_STATUS__FED__SHIFT                                                                       0x1
#define VML2_MEM_ECC_STATUS__UCE_MASK                                                                         0x00000001L
#define VML2_MEM_ECC_STATUS__FED_MASK                                                                         0x00000002L
//VML2_WALKER_MEM_ECC_STATUS
#define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT                                                                0x0
#define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT                                                                0x1
#define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK                                                                  0x00000001L
#define VML2_WALKER_MEM_ECC_STATUS__FED_MASK                                                                  0x00000002L
//UTCL2_MEM_ECC_STATUS
#define UTCL2_MEM_ECC_STATUS__UCE__SHIFT                                                                      0x0
#define UTCL2_MEM_ECC_STATUS__FED__SHIFT                                                                      0x1
#define UTCL2_MEM_ECC_STATUS__UCE_MASK                                                                        0x00000001L
#define UTCL2_MEM_ECC_STATUS__FED_MASK                                                                        0x00000002L
//UTCL2_EDC_MODE
#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                               0xf
#define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
#define UTCL2_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
#define UTCL2_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
#define UTCL2_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
#define UTCL2_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                 0x00008000L
#define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
#define UTCL2_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
#define UTCL2_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
#define UTCL2_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
#define UTCL2_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
//UTCL2_EDC_CONFIG
#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
#define UTCL2_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L


// addressBlock: mmhub_utcl2_vml2pldec
//MC_VM_L2_PERFCOUNTER0_CFG
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER1_CFG
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER2_CFG
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER3_CFG
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER4_CFG
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER5_CFG
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER6_CFG
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER7_CFG
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                        0x8
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                           0x18
#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                              0x1c
#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                               0x1d
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                              0x000000FFL
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                             0x0F000000L
#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                                0x10000000L
#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                                 0x20000000L
//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                            0x0
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                  0x8
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                   0x10
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                     0x18
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                      0x19
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                           0x1a
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                              0x0000000FL
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                    0x0000FF00L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                     0x00FF0000L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                       0x01000000L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                        0x02000000L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                             0x04000000L


// addressBlock: mmhub_utcl2_vml2prdec
//MC_VM_L2_PERFCOUNTER_LO
#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                              0xFFFFFFFFL
//MC_VM_L2_PERFCOUNTER_HI
#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                            0x0
#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                         0x10
#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                              0x0000FFFFL
#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                           0xFFFF0000L


// addressBlock: mmhub_utcl2_vml2vcdec
//VM_CONTEXT0_CNTL
#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT1_CNTL
#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT2_CNTL
#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT3_CNTL
#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT4_CNTL
#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT5_CNTL
#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT6_CNTL
#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT7_CNTL
#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT8_CNTL
#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT9_CNTL
#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
//VM_CONTEXT10_CNTL
#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
//VM_CONTEXT11_CNTL
#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
//VM_CONTEXT12_CNTL
#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
//VM_CONTEXT13_CNTL
#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
//VM_CONTEXT14_CNTL
#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
//VM_CONTEXT15_CNTL
#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
//VM_CONTEXTS_DISABLE
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                         0x0
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                         0x1
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                         0x2
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                         0x3
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                         0x4
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                         0x5
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                         0x6
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                         0x7
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                         0x8
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                         0x9
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                        0xa
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                        0xb
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                        0xc
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                        0xd
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                        0xe
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                        0xf
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                           0x00000001L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                           0x00000002L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                           0x00000004L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                           0x00000008L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                           0x00000010L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                           0x00000020L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                           0x00000040L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                           0x00000080L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                           0x00000100L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                           0x00000200L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                          0x00000400L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                          0x00000800L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                          0x00001000L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                          0x00002000L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                          0x00004000L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                          0x00008000L
//VM_INVALIDATE_ENG0_SEM
#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG1_SEM
#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG2_SEM
#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG3_SEM
#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG4_SEM
#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG5_SEM
#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG6_SEM
#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG7_SEM
#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG8_SEM
#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG9_SEM
#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                              0x0
#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                                0x00000001L
//VM_INVALIDATE_ENG10_SEM
#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG11_SEM
#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG12_SEM
#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG13_SEM
#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG14_SEM
#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG15_SEM
#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG16_SEM
#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG17_SEM
#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                             0x0
#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                               0x00000001L
//VM_INVALIDATE_ENG0_REQ
#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG1_REQ
#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG2_REQ
#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG3_REQ
#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG4_REQ
#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG5_REQ
#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG6_REQ
#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG7_REQ
#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG8_REQ
#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG9_REQ
#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT                                                            0x18
#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK                                                              0x01000000L
//VM_INVALIDATE_ENG10_REQ
#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG11_REQ
#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG12_REQ
#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG13_REQ
#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG14_REQ
#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG15_REQ
#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG16_REQ
#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG17_REQ
#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                            0x10
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT                                                           0x18
#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK                                                             0x01000000L
//VM_INVALIDATE_ENG0_ACK
#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG1_ACK
#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG2_ACK
#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG3_ACK
#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG4_ACK
#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG5_ACK
#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG6_ACK
#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG7_ACK
#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG8_ACK
#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG9_ACK
#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                              0x10
#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                                0x00010000L
//VM_INVALIDATE_ENG10_ACK
#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG11_ACK
#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG12_ACK
#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG13_ACK
#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG14_ACK
#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG15_ACK
#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG16_ACK
#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG17_ACK
#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                             0x10
#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                               0x00010000L
//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL


// addressBlock: mmhub_utcl2_vmsharedhvdec
//MC_VM_FB_SIZE_OFFSET_VF0
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF1
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF2
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF3
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF4
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF5
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF6
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF7
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF8
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF9
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                           0x0
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                         0x10
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                             0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF10
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                          0x0
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                        0x10
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                            0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF11
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                          0x0
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                        0x10
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                            0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF12
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                          0x0
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                        0x10
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                            0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF13
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                          0x0
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                        0x10
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                            0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF14
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                          0x0
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                        0x10
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                            0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF15
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                          0x0
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                        0x10
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                            0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
//MC_VM_MARC_BASE_LO_0
#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                           0xc
#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                             0xFFFFF000L
//MC_VM_MARC_BASE_LO_1
#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                           0xc
#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                             0xFFFFF000L
//MC_VM_MARC_BASE_LO_2
#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                           0xc
#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                             0xFFFFF000L
//MC_VM_MARC_BASE_LO_3
#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                           0xc
#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                             0xFFFFF000L
//MC_VM_MARC_BASE_HI_0
#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                           0x0
#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                             0x000FFFFFL
//MC_VM_MARC_BASE_HI_1
#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                           0x0
#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                             0x000FFFFFL
//MC_VM_MARC_BASE_HI_2
#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                           0x0
#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                             0x000FFFFFL
//MC_VM_MARC_BASE_HI_3
#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                           0x0
#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                             0x000FFFFFL
//MC_VM_MARC_RELOC_LO_0
#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                           0x0
#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                         0x1
#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                         0xc
#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                             0x00000001L
#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                           0x00000002L
#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                           0xFFFFF000L
//MC_VM_MARC_RELOC_LO_1
#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                           0x0
#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                         0x1
#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                         0xc
#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                             0x00000001L
#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                           0x00000002L
#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                           0xFFFFF000L
//MC_VM_MARC_RELOC_LO_2
#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                           0x0
#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                         0x1
#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                         0xc
#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                             0x00000001L
#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                           0x00000002L
#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                           0xFFFFF000L
//MC_VM_MARC_RELOC_LO_3
#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                           0x0
#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                         0x1
#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                         0xc
#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                             0x00000001L
#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                           0x00000002L
#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                           0xFFFFF000L
//MC_VM_MARC_RELOC_HI_0
#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                         0x0
#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                           0x000FFFFFL
//MC_VM_MARC_RELOC_HI_1
#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                         0x0
#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                           0x000FFFFFL
//MC_VM_MARC_RELOC_HI_2
#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                         0x0
#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                           0x000FFFFFL
//MC_VM_MARC_RELOC_HI_3
#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                         0x0
#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                           0x000FFFFFL
//MC_VM_MARC_LEN_LO_0
#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                             0xc
#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                               0xFFFFF000L
//MC_VM_MARC_LEN_LO_1
#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                             0xc
#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                               0xFFFFF000L
//MC_VM_MARC_LEN_LO_2
#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                             0xc
#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                               0xFFFFF000L
//MC_VM_MARC_LEN_LO_3
#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                             0xc
#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                               0xFFFFF000L
//MC_VM_MARC_LEN_HI_0
#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                             0x0
#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                               0x000FFFFFL
//MC_VM_MARC_LEN_HI_1
#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                             0x0
#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                               0x000FFFFFL
//MC_VM_MARC_LEN_HI_2
#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                             0x0
#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                               0x000FFFFFL
//MC_VM_MARC_LEN_HI_3
#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                             0x0
#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                               0x000FFFFFL
//VM_PCIE_ATS_CNTL
#define VM_PCIE_ATS_CNTL__STU__SHIFT                                                                          0x10
#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                   0x1f
#define VM_PCIE_ATS_CNTL__STU_MASK                                                                            0x001F0000L
#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                     0x80000000L
//VM_PCIE_ATS_CNTL_VF_0
#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_1
#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_2
#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_3
#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_4
#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_5
#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_6
#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_7
#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_8
#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_9
#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                              0x1f
#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                                0x80000000L
//VM_PCIE_ATS_CNTL_VF_10
#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                             0x1f
#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                               0x80000000L
//VM_PCIE_ATS_CNTL_VF_11
#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                             0x1f
#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                               0x80000000L
//VM_PCIE_ATS_CNTL_VF_12
#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                             0x1f
#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                               0x80000000L
//VM_PCIE_ATS_CNTL_VF_13
#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                             0x1f
#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                               0x80000000L
//VM_PCIE_ATS_CNTL_VF_14
#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                             0x1f
#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                               0x80000000L
//VM_PCIE_ATS_CNTL_VF_15
#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                             0x1f
#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                               0x80000000L
//MC_SHARED_ACTIVE_FCN_ID
#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                  0x0
#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                    0x1f
#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                    0x0000000FL
#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                      0x80000000L
//MC_VM_XGMI_GPUIOV_ENABLE
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                                           0x0
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                                           0x1
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                                           0x2
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                                           0x3
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                                           0x4
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                                           0x5
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                                           0x6
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                                           0x7
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                                           0x8
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                                           0x9
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                                          0xa
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                                          0xb
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                                          0xc
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                                          0xd
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                                          0xe
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                                          0xf
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                            0x1f
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                             0x00000001L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                             0x00000002L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                             0x00000004L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                             0x00000008L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                             0x00000010L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                             0x00000020L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                             0x00000040L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                             0x00000080L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                             0x00000100L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                             0x00000200L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                            0x00000400L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                            0x00000800L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                            0x00001000L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                            0x00002000L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                            0x00004000L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                            0x00008000L
#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                              0x80000000L


// addressBlock: mmhub_utcl2_vmsharedpfdec
//MC_VM_FB_OFFSET
#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                     0x0
#define MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                       0x00FFFFFFL
//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                               0x0
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                                 0xFFFFFFFFL
//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                               0x0
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                                 0x0000000FL
//MC_VM_STEERING
#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                               0x0
#define MC_VM_STEERING__DEFAULT_STEERING_MASK                                                                 0x00000003L
//MC_SHARED_VIRT_RESET_REQ
#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                   0x0
#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                   0x1f
#define MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                     0x0000FFFFL
#define MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                     0x80000000L
//MC_MEM_POWER_LS
#define MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                      0x0
#define MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                       0x6
#define MC_MEM_POWER_LS__LS_SETUP_MASK                                                                        0x0000003FL
#define MC_MEM_POWER_LS__LS_HOLD_MASK                                                                         0x00000FC0L
//MC_VM_CACHEABLE_DRAM_ADDRESS_START
#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                    0x0
#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                      0x00FFFFFFL
//MC_VM_CACHEABLE_DRAM_ADDRESS_END
#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                      0x0
#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                        0x00FFFFFFL
//MC_VM_APT_CNTL
#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                                 0x0
#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                               0x1
#define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT                                                                 0x2
#define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT                                                                  0x3
#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                   0x00000001L
#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                                 0x00000002L
#define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK                                                                   0x00000004L
#define MC_VM_APT_CNTL__PERMS_GRANTED_MASK                                                                    0x00000008L
//MC_VM_LOCAL_HBM_ADDRESS_START
#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                         0x0
#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                           0x00FFFFFFL
//MC_VM_LOCAL_HBM_ADDRESS_END
#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                           0x0
#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                             0x00FFFFFFL
//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                        0x0
#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                          0x00000001L
//UTCL2_CGTT_CLK_CTRL
#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                                       0xc
#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                                         0x00007000L
#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
//MC_VM_XGMI_LFB_CNTL
#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                             0x0
#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                             0x4
#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                               0x0000000FL
#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                               0x000000F0L
//MC_VM_XGMI_LFB_SIZE
#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                               0x0
#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                                 0x0001FFFFL
//MC_VM_CACHEABLE_DRAM_CNTL
#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT                              0x0
#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK                                0x00000001L
//MC_VM_HOST_MAPPING
#define MC_VM_HOST_MAPPING__MODE__SHIFT                                                                       0x0
#define MC_VM_HOST_MAPPING__MODE_MASK                                                                         0x00000001L


// addressBlock: mmhub_utcl2_vmsharedvcdec
//MC_VM_FB_LOCATION_BASE
#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                                0x0
#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                  0x00FFFFFFL
//MC_VM_FB_LOCATION_TOP
#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                  0x0
#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                    0x00FFFFFFL
//MC_VM_AGP_TOP
#define MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                         0x0
#define MC_VM_AGP_TOP__AGP_TOP_MASK                                                                           0x00FFFFFFL
//MC_VM_AGP_BOT
#define MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                         0x0
#define MC_VM_AGP_BOT__AGP_BOT_MASK                                                                           0x00FFFFFFL
//MC_VM_AGP_BASE
#define MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                       0x0
#define MC_VM_AGP_BASE__AGP_BASE_MASK                                                                         0x00FFFFFFL
//MC_VM_SYSTEM_APERTURE_LOW_ADDR
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                   0x0
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                     0x3FFFFFFFL
//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                  0x0
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                    0x3FFFFFFFL
//MC_VM_MX_L1_TLB_CNTL
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                            0x0
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                       0x3
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                          0x5
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                             0x6
#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                                 0x7
#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                    0xb
#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                                   0xd
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                              0x00000001L
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                         0x00000018L
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                            0x00000020L
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                               0x00000040L
#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                   0x00000780L
#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                      0x00001800L
#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                                     0x00002000L

#endif