1 /*
2  * Copyright (C) 2020  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _mp_11_5_0_SH_MASK_HEADER
22 #define _mp_11_5_0_SH_MASK_HEADER
23 
24 
25 // addressBlock: mp_SmuMp0_SmnDec
26 //MP0_SMN_C2PMSG_32
27 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
28 #define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
29 //MP0_SMN_C2PMSG_33
30 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
31 #define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
32 //MP0_SMN_C2PMSG_34
33 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
34 #define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
35 //MP0_SMN_C2PMSG_35
36 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
37 #define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
38 //MP0_SMN_C2PMSG_36
39 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
40 #define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
41 //MP0_SMN_C2PMSG_37
42 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
43 #define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
44 //MP0_SMN_C2PMSG_38
45 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
46 #define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
47 //MP0_SMN_C2PMSG_39
48 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
49 #define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
50 //MP0_SMN_C2PMSG_40
51 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
52 #define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
53 //MP0_SMN_C2PMSG_41
54 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
55 #define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
56 //MP0_SMN_C2PMSG_42
57 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
58 #define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
59 //MP0_SMN_C2PMSG_43
60 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
61 #define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
62 //MP0_SMN_C2PMSG_44
63 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
64 #define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
65 //MP0_SMN_C2PMSG_45
66 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
67 #define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
68 //MP0_SMN_C2PMSG_46
69 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
70 #define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
71 //MP0_SMN_C2PMSG_47
72 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
73 #define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
74 //MP0_SMN_C2PMSG_48
75 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
76 #define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
77 //MP0_SMN_C2PMSG_49
78 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
79 #define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
80 //MP0_SMN_C2PMSG_50
81 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
82 #define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
83 //MP0_SMN_C2PMSG_51
84 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
85 #define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
86 //MP0_SMN_C2PMSG_52
87 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
88 #define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
89 //MP0_SMN_C2PMSG_53
90 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
91 #define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
92 //MP0_SMN_C2PMSG_54
93 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
94 #define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
95 //MP0_SMN_C2PMSG_55
96 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
97 #define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
98 //MP0_SMN_C2PMSG_56
99 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
100 #define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
101 //MP0_SMN_C2PMSG_57
102 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
103 #define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
104 //MP0_SMN_C2PMSG_58
105 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
106 #define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
107 //MP0_SMN_C2PMSG_59
108 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
109 #define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
110 //MP0_SMN_C2PMSG_60
111 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
112 #define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
113 //MP0_SMN_C2PMSG_61
114 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
115 #define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
116 //MP0_SMN_C2PMSG_62
117 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
118 #define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
119 //MP0_SMN_C2PMSG_63
120 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
121 #define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
122 //MP0_SMN_C2PMSG_64
123 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
124 #define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
125 //MP0_SMN_C2PMSG_65
126 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
127 #define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
128 //MP0_SMN_C2PMSG_66
129 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
130 #define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
131 //MP0_SMN_C2PMSG_67
132 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
133 #define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
134 //MP0_SMN_C2PMSG_68
135 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
136 #define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
137 //MP0_SMN_C2PMSG_69
138 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
139 #define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
140 //MP0_SMN_C2PMSG_70
141 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
142 #define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
143 //MP0_SMN_C2PMSG_71
144 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
145 #define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
146 //MP0_SMN_C2PMSG_72
147 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
148 #define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
149 //MP0_SMN_C2PMSG_73
150 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
151 #define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
152 //MP0_SMN_C2PMSG_74
153 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
154 #define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
155 //MP0_SMN_C2PMSG_75
156 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
157 #define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
158 //MP0_SMN_C2PMSG_76
159 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
160 #define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
161 //MP0_SMN_C2PMSG_77
162 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
163 #define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
164 //MP0_SMN_C2PMSG_78
165 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
166 #define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
167 //MP0_SMN_C2PMSG_79
168 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
169 #define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
170 //MP0_SMN_C2PMSG_80
171 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
172 #define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
173 //MP0_SMN_C2PMSG_81
174 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
175 #define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
176 //MP0_SMN_C2PMSG_82
177 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
178 #define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
179 //MP0_SMN_C2PMSG_83
180 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
181 #define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
182 //MP0_SMN_C2PMSG_84
183 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
184 #define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
185 //MP0_SMN_C2PMSG_85
186 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
187 #define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
188 //MP0_SMN_C2PMSG_86
189 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
190 #define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
191 //MP0_SMN_C2PMSG_87
192 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
193 #define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
194 //MP0_SMN_C2PMSG_88
195 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
196 #define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
197 //MP0_SMN_C2PMSG_89
198 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
199 #define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
200 //MP0_SMN_C2PMSG_90
201 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
202 #define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
203 //MP0_SMN_C2PMSG_91
204 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
205 #define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
206 //MP0_SMN_C2PMSG_92
207 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
208 #define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
209 //MP0_SMN_C2PMSG_93
210 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
211 #define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
212 //MP0_SMN_C2PMSG_94
213 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
214 #define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
215 //MP0_SMN_C2PMSG_95
216 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
217 #define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
218 //MP0_SMN_C2PMSG_96
219 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
220 #define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
221 //MP0_SMN_C2PMSG_97
222 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
223 #define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
224 //MP0_SMN_C2PMSG_98
225 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
226 #define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
227 //MP0_SMN_C2PMSG_99
228 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
229 #define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
230 //MP0_SMN_C2PMSG_100
231 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
232 #define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
233 //MP0_SMN_C2PMSG_101
234 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
235 #define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
236 //MP0_SMN_C2PMSG_102
237 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
238 #define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
239 //MP0_SMN_C2PMSG_103
240 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
241 #define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
242 //MP0_SMN_IH_CREDIT
243 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
244 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
245 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
246 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
247 //MP0_SMN_IH_SW_INT
248 #define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
249 #define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
250 #define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
251 #define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
252 //MP0_SMN_IH_SW_INT_CTRL
253 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
254 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
255 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
256 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
257 
258 
259 // addressBlock: mp_SmuMp1_SmnDec
260 //MP1_SMN_C2PMSG_32
261 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
262 #define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
263 //MP1_SMN_C2PMSG_33
264 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
265 #define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
266 //MP1_SMN_C2PMSG_34
267 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
268 #define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
269 //MP1_SMN_C2PMSG_35
270 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
271 #define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
272 //MP1_SMN_C2PMSG_36
273 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
274 #define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
275 //MP1_SMN_C2PMSG_37
276 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
277 #define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
278 //MP1_SMN_C2PMSG_38
279 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
280 #define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
281 //MP1_SMN_C2PMSG_39
282 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
283 #define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
284 //MP1_SMN_C2PMSG_40
285 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
286 #define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
287 //MP1_SMN_C2PMSG_41
288 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
289 #define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
290 //MP1_SMN_C2PMSG_42
291 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
292 #define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
293 //MP1_SMN_C2PMSG_43
294 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
295 #define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
296 //MP1_SMN_C2PMSG_44
297 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
298 #define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
299 //MP1_SMN_C2PMSG_45
300 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
301 #define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
302 //MP1_SMN_C2PMSG_46
303 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
304 #define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
305 //MP1_SMN_C2PMSG_47
306 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
307 #define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
308 //MP1_SMN_C2PMSG_48
309 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
310 #define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
311 //MP1_SMN_C2PMSG_49
312 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
313 #define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
314 //MP1_SMN_C2PMSG_50
315 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
316 #define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
317 //MP1_SMN_C2PMSG_51
318 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
319 #define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
320 //MP1_SMN_C2PMSG_52
321 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
322 #define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
323 //MP1_SMN_C2PMSG_53
324 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
325 #define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
326 //MP1_SMN_C2PMSG_54
327 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
328 #define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
329 //MP1_SMN_C2PMSG_55
330 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
331 #define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
332 //MP1_SMN_C2PMSG_56
333 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
334 #define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
335 //MP1_SMN_C2PMSG_57
336 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
337 #define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
338 //MP1_SMN_C2PMSG_58
339 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
340 #define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
341 //MP1_SMN_C2PMSG_59
342 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
343 #define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
344 //MP1_SMN_C2PMSG_60
345 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
346 #define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
347 //MP1_SMN_C2PMSG_61
348 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
349 #define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
350 //MP1_SMN_C2PMSG_62
351 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
352 #define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
353 //MP1_SMN_C2PMSG_63
354 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
355 #define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
356 //MP1_SMN_C2PMSG_64
357 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
358 #define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
359 //MP1_SMN_C2PMSG_65
360 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
361 #define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
362 //MP1_SMN_C2PMSG_66
363 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
364 #define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
365 //MP1_SMN_C2PMSG_67
366 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
367 #define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
368 //MP1_SMN_C2PMSG_68
369 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
370 #define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
371 //MP1_SMN_C2PMSG_69
372 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
373 #define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
374 //MP1_SMN_C2PMSG_70
375 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
376 #define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
377 //MP1_SMN_C2PMSG_71
378 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
379 #define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
380 //MP1_SMN_C2PMSG_72
381 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
382 #define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
383 //MP1_SMN_C2PMSG_73
384 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
385 #define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
386 //MP1_SMN_C2PMSG_74
387 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
388 #define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
389 //MP1_SMN_C2PMSG_75
390 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
391 #define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
392 //MP1_SMN_C2PMSG_76
393 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
394 #define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
395 //MP1_SMN_C2PMSG_77
396 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
397 #define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
398 //MP1_SMN_C2PMSG_78
399 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
400 #define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
401 //MP1_SMN_C2PMSG_79
402 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
403 #define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
404 //MP1_SMN_C2PMSG_80
405 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
406 #define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
407 //MP1_SMN_C2PMSG_81
408 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
409 #define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
410 //MP1_SMN_C2PMSG_82
411 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
412 #define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
413 //MP1_SMN_C2PMSG_83
414 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
415 #define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
416 //MP1_SMN_C2PMSG_84
417 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
418 #define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
419 //MP1_SMN_C2PMSG_85
420 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
421 #define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
422 //MP1_SMN_C2PMSG_86
423 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
424 #define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
425 //MP1_SMN_C2PMSG_87
426 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
427 #define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
428 //MP1_SMN_C2PMSG_88
429 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
430 #define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
431 //MP1_SMN_C2PMSG_89
432 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
433 #define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
434 //MP1_SMN_C2PMSG_90
435 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
436 #define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
437 //MP1_SMN_C2PMSG_91
438 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
439 #define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
440 //MP1_SMN_C2PMSG_92
441 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
442 #define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
443 //MP1_SMN_C2PMSG_93
444 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
445 #define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
446 //MP1_SMN_C2PMSG_94
447 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
448 #define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
449 //MP1_SMN_C2PMSG_95
450 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
451 #define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
452 //MP1_SMN_C2PMSG_96
453 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
454 #define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
455 //MP1_SMN_C2PMSG_97
456 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
457 #define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
458 //MP1_SMN_C2PMSG_98
459 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
460 #define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
461 //MP1_SMN_C2PMSG_99
462 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
463 #define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
464 //MP1_SMN_C2PMSG_100
465 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
466 #define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
467 //MP1_SMN_C2PMSG_101
468 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
469 #define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
470 //MP1_SMN_C2PMSG_102
471 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
472 #define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
473 //MP1_SMN_C2PMSG_103
474 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
475 #define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
476 //MP1_SMN_IH_CREDIT
477 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
478 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
479 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
480 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
481 //MP1_SMN_IH_SW_INT
482 #define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
483 #define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
484 #define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
485 #define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
486 //MP1_SMN_IH_SW_INT_CTRL
487 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
488 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
489 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
490 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
491 //MP1_SMN_FPS_CNT
492 #define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
493 #define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
494 //MP1_SMN_EXT_SCRATCH0
495 #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
496 #define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
497 //MP1_SMN_EXT_SCRATCH1
498 #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
499 #define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
500 //MP1_SMN_EXT_SCRATCH2
501 #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
502 #define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
503 //MP1_SMN_EXT_SCRATCH3
504 #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
505 #define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
506 //MP1_SMN_EXT_SCRATCH4
507 #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
508 #define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
509 //MP1_SMN_EXT_SCRATCH5
510 #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
511 #define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
512 //MP1_SMN_EXT_SCRATCH6
513 #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
514 #define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
515 //MP1_SMN_EXT_SCRATCH7
516 #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
517 #define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
518 
519 
520 // addressBlock: mp_SmuMp1Pub_CruDec
521 //MP1_CRU1_MP1_FIRMWARE_FLAGS
522 #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                0x0
523 #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                          0x1
524 #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                  0x00000001L
525 #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                            0xFFFFFFFEL
526 //MP1_CRU1_MP1_PUB_SCRATCH0
527 #define MP1_CRU1_MP1_PUB_SCRATCH0__DATA__SHIFT                                                                0x0
528 #define MP1_CRU1_MP1_PUB_SCRATCH0__DATA_MASK                                                                  0xFFFFFFFFL
529 //MP1_CRU1_MP1_PUB_SCRATCH1
530 #define MP1_CRU1_MP1_PUB_SCRATCH1__DATA__SHIFT                                                                0x0
531 #define MP1_CRU1_MP1_PUB_SCRATCH1__DATA_MASK                                                                  0xFFFFFFFFL
532 //MP1_CRU1_MP1_PUB_SCRATCH2
533 #define MP1_CRU1_MP1_PUB_SCRATCH2__DATA__SHIFT                                                                0x0
534 #define MP1_CRU1_MP1_PUB_SCRATCH2__DATA_MASK                                                                  0xFFFFFFFFL
535 //MP1_CRU1_MP1_PUB_SCRATCH3
536 #define MP1_CRU1_MP1_PUB_SCRATCH3__DATA__SHIFT                                                                0x0
537 #define MP1_CRU1_MP1_PUB_SCRATCH3__DATA_MASK                                                                  0xFFFFFFFFL
538 //MP1_CRU1_MP1_C2PMSG_0
539 #define MP1_CRU1_MP1_C2PMSG_0__CONTENT__SHIFT                                                                 0x0
540 #define MP1_CRU1_MP1_C2PMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
541 //MP1_CRU1_MP1_C2PMSG_1
542 #define MP1_CRU1_MP1_C2PMSG_1__CONTENT__SHIFT                                                                 0x0
543 #define MP1_CRU1_MP1_C2PMSG_1__CONTENT_MASK                                                                   0xFFFFFFFFL
544 //MP1_CRU1_MP1_C2PMSG_2
545 #define MP1_CRU1_MP1_C2PMSG_2__CONTENT__SHIFT                                                                 0x0
546 #define MP1_CRU1_MP1_C2PMSG_2__CONTENT_MASK                                                                   0xFFFFFFFFL
547 //MP1_CRU1_MP1_C2PMSG_3
548 #define MP1_CRU1_MP1_C2PMSG_3__CONTENT__SHIFT                                                                 0x0
549 #define MP1_CRU1_MP1_C2PMSG_3__CONTENT_MASK                                                                   0xFFFFFFFFL
550 //MP1_CRU1_MP1_C2PMSG_4
551 #define MP1_CRU1_MP1_C2PMSG_4__CONTENT__SHIFT                                                                 0x0
552 #define MP1_CRU1_MP1_C2PMSG_4__CONTENT_MASK                                                                   0xFFFFFFFFL
553 //MP1_CRU1_MP1_C2PMSG_5
554 #define MP1_CRU1_MP1_C2PMSG_5__CONTENT__SHIFT                                                                 0x0
555 #define MP1_CRU1_MP1_C2PMSG_5__CONTENT_MASK                                                                   0xFFFFFFFFL
556 //MP1_CRU1_MP1_C2PMSG_6
557 #define MP1_CRU1_MP1_C2PMSG_6__CONTENT__SHIFT                                                                 0x0
558 #define MP1_CRU1_MP1_C2PMSG_6__CONTENT_MASK                                                                   0xFFFFFFFFL
559 //MP1_CRU1_MP1_C2PMSG_7
560 #define MP1_CRU1_MP1_C2PMSG_7__CONTENT__SHIFT                                                                 0x0
561 #define MP1_CRU1_MP1_C2PMSG_7__CONTENT_MASK                                                                   0xFFFFFFFFL
562 //MP1_CRU1_MP1_C2PMSG_8
563 #define MP1_CRU1_MP1_C2PMSG_8__CONTENT__SHIFT                                                                 0x0
564 #define MP1_CRU1_MP1_C2PMSG_8__CONTENT_MASK                                                                   0xFFFFFFFFL
565 //MP1_CRU1_MP1_C2PMSG_9
566 #define MP1_CRU1_MP1_C2PMSG_9__CONTENT__SHIFT                                                                 0x0
567 #define MP1_CRU1_MP1_C2PMSG_9__CONTENT_MASK                                                                   0xFFFFFFFFL
568 //MP1_CRU1_MP1_C2PMSG_10
569 #define MP1_CRU1_MP1_C2PMSG_10__CONTENT__SHIFT                                                                0x0
570 #define MP1_CRU1_MP1_C2PMSG_10__CONTENT_MASK                                                                  0xFFFFFFFFL
571 //MP1_CRU1_MP1_C2PMSG_11
572 #define MP1_CRU1_MP1_C2PMSG_11__CONTENT__SHIFT                                                                0x0
573 #define MP1_CRU1_MP1_C2PMSG_11__CONTENT_MASK                                                                  0xFFFFFFFFL
574 //MP1_CRU1_MP1_C2PMSG_12
575 #define MP1_CRU1_MP1_C2PMSG_12__CONTENT__SHIFT                                                                0x0
576 #define MP1_CRU1_MP1_C2PMSG_12__CONTENT_MASK                                                                  0xFFFFFFFFL
577 //MP1_CRU1_MP1_C2PMSG_13
578 #define MP1_CRU1_MP1_C2PMSG_13__CONTENT__SHIFT                                                                0x0
579 #define MP1_CRU1_MP1_C2PMSG_13__CONTENT_MASK                                                                  0xFFFFFFFFL
580 //MP1_CRU1_MP1_C2PMSG_14
581 #define MP1_CRU1_MP1_C2PMSG_14__CONTENT__SHIFT                                                                0x0
582 #define MP1_CRU1_MP1_C2PMSG_14__CONTENT_MASK                                                                  0xFFFFFFFFL
583 //MP1_CRU1_MP1_C2PMSG_15
584 #define MP1_CRU1_MP1_C2PMSG_15__CONTENT__SHIFT                                                                0x0
585 #define MP1_CRU1_MP1_C2PMSG_15__CONTENT_MASK                                                                  0xFFFFFFFFL
586 //MP1_CRU1_MP1_C2PMSG_16
587 #define MP1_CRU1_MP1_C2PMSG_16__CONTENT__SHIFT                                                                0x0
588 #define MP1_CRU1_MP1_C2PMSG_16__CONTENT_MASK                                                                  0xFFFFFFFFL
589 //MP1_CRU1_MP1_C2PMSG_17
590 #define MP1_CRU1_MP1_C2PMSG_17__CONTENT__SHIFT                                                                0x0
591 #define MP1_CRU1_MP1_C2PMSG_17__CONTENT_MASK                                                                  0xFFFFFFFFL
592 //MP1_CRU1_MP1_C2PMSG_18
593 #define MP1_CRU1_MP1_C2PMSG_18__CONTENT__SHIFT                                                                0x0
594 #define MP1_CRU1_MP1_C2PMSG_18__CONTENT_MASK                                                                  0xFFFFFFFFL
595 //MP1_CRU1_MP1_C2PMSG_19
596 #define MP1_CRU1_MP1_C2PMSG_19__CONTENT__SHIFT                                                                0x0
597 #define MP1_CRU1_MP1_C2PMSG_19__CONTENT_MASK                                                                  0xFFFFFFFFL
598 //MP1_CRU1_MP1_C2PMSG_20
599 #define MP1_CRU1_MP1_C2PMSG_20__CONTENT__SHIFT                                                                0x0
600 #define MP1_CRU1_MP1_C2PMSG_20__CONTENT_MASK                                                                  0xFFFFFFFFL
601 //MP1_CRU1_MP1_C2PMSG_21
602 #define MP1_CRU1_MP1_C2PMSG_21__CONTENT__SHIFT                                                                0x0
603 #define MP1_CRU1_MP1_C2PMSG_21__CONTENT_MASK                                                                  0xFFFFFFFFL
604 //MP1_CRU1_MP1_C2PMSG_22
605 #define MP1_CRU1_MP1_C2PMSG_22__CONTENT__SHIFT                                                                0x0
606 #define MP1_CRU1_MP1_C2PMSG_22__CONTENT_MASK                                                                  0xFFFFFFFFL
607 //MP1_CRU1_MP1_C2PMSG_23
608 #define MP1_CRU1_MP1_C2PMSG_23__CONTENT__SHIFT                                                                0x0
609 #define MP1_CRU1_MP1_C2PMSG_23__CONTENT_MASK                                                                  0xFFFFFFFFL
610 //MP1_CRU1_MP1_C2PMSG_24
611 #define MP1_CRU1_MP1_C2PMSG_24__CONTENT__SHIFT                                                                0x0
612 #define MP1_CRU1_MP1_C2PMSG_24__CONTENT_MASK                                                                  0xFFFFFFFFL
613 //MP1_CRU1_MP1_C2PMSG_25
614 #define MP1_CRU1_MP1_C2PMSG_25__CONTENT__SHIFT                                                                0x0
615 #define MP1_CRU1_MP1_C2PMSG_25__CONTENT_MASK                                                                  0xFFFFFFFFL
616 //MP1_CRU1_MP1_C2PMSG_26
617 #define MP1_CRU1_MP1_C2PMSG_26__CONTENT__SHIFT                                                                0x0
618 #define MP1_CRU1_MP1_C2PMSG_26__CONTENT_MASK                                                                  0xFFFFFFFFL
619 //MP1_CRU1_MP1_C2PMSG_27
620 #define MP1_CRU1_MP1_C2PMSG_27__CONTENT__SHIFT                                                                0x0
621 #define MP1_CRU1_MP1_C2PMSG_27__CONTENT_MASK                                                                  0xFFFFFFFFL
622 //MP1_CRU1_MP1_C2PMSG_28
623 #define MP1_CRU1_MP1_C2PMSG_28__CONTENT__SHIFT                                                                0x0
624 #define MP1_CRU1_MP1_C2PMSG_28__CONTENT_MASK                                                                  0xFFFFFFFFL
625 //MP1_CRU1_MP1_C2PMSG_29
626 #define MP1_CRU1_MP1_C2PMSG_29__CONTENT__SHIFT                                                                0x0
627 #define MP1_CRU1_MP1_C2PMSG_29__CONTENT_MASK                                                                  0xFFFFFFFFL
628 //MP1_CRU1_MP1_C2PMSG_30
629 #define MP1_CRU1_MP1_C2PMSG_30__CONTENT__SHIFT                                                                0x0
630 #define MP1_CRU1_MP1_C2PMSG_30__CONTENT_MASK                                                                  0xFFFFFFFFL
631 //MP1_CRU1_MP1_C2PMSG_31
632 #define MP1_CRU1_MP1_C2PMSG_31__CONTENT__SHIFT                                                                0x0
633 #define MP1_CRU1_MP1_C2PMSG_31__CONTENT_MASK                                                                  0xFFFFFFFFL
634 //MP1_CRU1_MP1_P2CMSG_0
635 #define MP1_CRU1_MP1_P2CMSG_0__CONTENT__SHIFT                                                                 0x0
636 #define MP1_CRU1_MP1_P2CMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
637 //MP1_CRU1_MP1_P2CMSG_1
638 #define MP1_CRU1_MP1_P2CMSG_1__CONTENT__SHIFT                                                                 0x0
639 #define MP1_CRU1_MP1_P2CMSG_1__CONTENT_MASK                                                                   0xFFFFFFFFL
640 //MP1_CRU1_MP1_P2CMSG_2
641 #define MP1_CRU1_MP1_P2CMSG_2__CONTENT__SHIFT                                                                 0x0
642 #define MP1_CRU1_MP1_P2CMSG_2__CONTENT_MASK                                                                   0xFFFFFFFFL
643 //MP1_CRU1_MP1_P2CMSG_3
644 #define MP1_CRU1_MP1_P2CMSG_3__CONTENT__SHIFT                                                                 0x0
645 #define MP1_CRU1_MP1_P2CMSG_3__CONTENT_MASK                                                                   0xFFFFFFFFL
646 //MP1_CRU1_MP1_P2CMSG_INTEN
647 #define MP1_CRU1_MP1_P2CMSG_INTEN__INTEN__SHIFT                                                               0x0
648 #define MP1_CRU1_MP1_P2CMSG_INTEN__INTEN_MASK                                                                 0x0000000FL
649 //MP1_CRU1_MP1_P2CMSG_INTSTS
650 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                            0x0
651 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                            0x1
652 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                            0x2
653 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                            0x3
654 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS0_MASK                                                              0x00000001L
655 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS1_MASK                                                              0x00000002L
656 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS2_MASK                                                              0x00000004L
657 #define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS3_MASK                                                              0x00000008L
658 //MP1_CRU1_MP1_P2SMSG_0
659 #define MP1_CRU1_MP1_P2SMSG_0__CONTENT__SHIFT                                                                 0x0
660 #define MP1_CRU1_MP1_P2SMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
661 //MP1_CRU1_MP1_P2SMSG_1
662 #define MP1_CRU1_MP1_P2SMSG_1__CONTENT__SHIFT                                                                 0x0
663 #define MP1_CRU1_MP1_P2SMSG_1__CONTENT_MASK                                                                   0xFFFFFFFFL
664 //MP1_CRU1_MP1_P2SMSG_2
665 #define MP1_CRU1_MP1_P2SMSG_2__CONTENT__SHIFT                                                                 0x0
666 #define MP1_CRU1_MP1_P2SMSG_2__CONTENT_MASK                                                                   0xFFFFFFFFL
667 //MP1_CRU1_MP1_P2SMSG_3
668 #define MP1_CRU1_MP1_P2SMSG_3__CONTENT__SHIFT                                                                 0x0
669 #define MP1_CRU1_MP1_P2SMSG_3__CONTENT_MASK                                                                   0xFFFFFFFFL
670 //MP1_CRU1_MP1_P2SMSG_INTSTS
671 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS0__SHIFT                                                            0x0
672 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS1__SHIFT                                                            0x1
673 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS2__SHIFT                                                            0x2
674 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS3__SHIFT                                                            0x3
675 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS0_MASK                                                              0x00000001L
676 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS1_MASK                                                              0x00000002L
677 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS2_MASK                                                              0x00000004L
678 #define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS3_MASK                                                              0x00000008L
679 //MP1_CRU1_MP1_S2PMSG_0
680 #define MP1_CRU1_MP1_S2PMSG_0__CONTENT__SHIFT                                                                 0x0
681 #define MP1_CRU1_MP1_S2PMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
682 //MP1_CRU1_MP1_C2PMSG_32
683 #define MP1_CRU1_MP1_C2PMSG_32__CONTENT__SHIFT                                                                0x0
684 #define MP1_CRU1_MP1_C2PMSG_32__CONTENT_MASK                                                                  0xFFFFFFFFL
685 //MP1_CRU1_MP1_C2PMSG_33
686 #define MP1_CRU1_MP1_C2PMSG_33__CONTENT__SHIFT                                                                0x0
687 #define MP1_CRU1_MP1_C2PMSG_33__CONTENT_MASK                                                                  0xFFFFFFFFL
688 //MP1_CRU1_MP1_C2PMSG_34
689 #define MP1_CRU1_MP1_C2PMSG_34__CONTENT__SHIFT                                                                0x0
690 #define MP1_CRU1_MP1_C2PMSG_34__CONTENT_MASK                                                                  0xFFFFFFFFL
691 //MP1_CRU1_MP1_C2PMSG_35
692 #define MP1_CRU1_MP1_C2PMSG_35__CONTENT__SHIFT                                                                0x0
693 #define MP1_CRU1_MP1_C2PMSG_35__CONTENT_MASK                                                                  0xFFFFFFFFL
694 //MP1_CRU1_MP1_C2PMSG_36
695 #define MP1_CRU1_MP1_C2PMSG_36__CONTENT__SHIFT                                                                0x0
696 #define MP1_CRU1_MP1_C2PMSG_36__CONTENT_MASK                                                                  0xFFFFFFFFL
697 //MP1_CRU1_MP1_C2PMSG_37
698 #define MP1_CRU1_MP1_C2PMSG_37__CONTENT__SHIFT                                                                0x0
699 #define MP1_CRU1_MP1_C2PMSG_37__CONTENT_MASK                                                                  0xFFFFFFFFL
700 //MP1_CRU1_MP1_C2PMSG_38
701 #define MP1_CRU1_MP1_C2PMSG_38__CONTENT__SHIFT                                                                0x0
702 #define MP1_CRU1_MP1_C2PMSG_38__CONTENT_MASK                                                                  0xFFFFFFFFL
703 //MP1_CRU1_MP1_C2PMSG_39
704 #define MP1_CRU1_MP1_C2PMSG_39__CONTENT__SHIFT                                                                0x0
705 #define MP1_CRU1_MP1_C2PMSG_39__CONTENT_MASK                                                                  0xFFFFFFFFL
706 //MP1_CRU1_MP1_C2PMSG_40
707 #define MP1_CRU1_MP1_C2PMSG_40__CONTENT__SHIFT                                                                0x0
708 #define MP1_CRU1_MP1_C2PMSG_40__CONTENT_MASK                                                                  0xFFFFFFFFL
709 //MP1_CRU1_MP1_C2PMSG_41
710 #define MP1_CRU1_MP1_C2PMSG_41__CONTENT__SHIFT                                                                0x0
711 #define MP1_CRU1_MP1_C2PMSG_41__CONTENT_MASK                                                                  0xFFFFFFFFL
712 //MP1_CRU1_MP1_C2PMSG_42
713 #define MP1_CRU1_MP1_C2PMSG_42__CONTENT__SHIFT                                                                0x0
714 #define MP1_CRU1_MP1_C2PMSG_42__CONTENT_MASK                                                                  0xFFFFFFFFL
715 //MP1_CRU1_MP1_C2PMSG_43
716 #define MP1_CRU1_MP1_C2PMSG_43__CONTENT__SHIFT                                                                0x0
717 #define MP1_CRU1_MP1_C2PMSG_43__CONTENT_MASK                                                                  0xFFFFFFFFL
718 //MP1_CRU1_MP1_C2PMSG_44
719 #define MP1_CRU1_MP1_C2PMSG_44__CONTENT__SHIFT                                                                0x0
720 #define MP1_CRU1_MP1_C2PMSG_44__CONTENT_MASK                                                                  0xFFFFFFFFL
721 //MP1_CRU1_MP1_C2PMSG_45
722 #define MP1_CRU1_MP1_C2PMSG_45__CONTENT__SHIFT                                                                0x0
723 #define MP1_CRU1_MP1_C2PMSG_45__CONTENT_MASK                                                                  0xFFFFFFFFL
724 //MP1_CRU1_MP1_C2PMSG_46
725 #define MP1_CRU1_MP1_C2PMSG_46__CONTENT__SHIFT                                                                0x0
726 #define MP1_CRU1_MP1_C2PMSG_46__CONTENT_MASK                                                                  0xFFFFFFFFL
727 //MP1_CRU1_MP1_C2PMSG_47
728 #define MP1_CRU1_MP1_C2PMSG_47__CONTENT__SHIFT                                                                0x0
729 #define MP1_CRU1_MP1_C2PMSG_47__CONTENT_MASK                                                                  0xFFFFFFFFL
730 //MP1_CRU1_MP1_C2PMSG_48
731 #define MP1_CRU1_MP1_C2PMSG_48__CONTENT__SHIFT                                                                0x0
732 #define MP1_CRU1_MP1_C2PMSG_48__CONTENT_MASK                                                                  0xFFFFFFFFL
733 //MP1_CRU1_MP1_C2PMSG_49
734 #define MP1_CRU1_MP1_C2PMSG_49__CONTENT__SHIFT                                                                0x0
735 #define MP1_CRU1_MP1_C2PMSG_49__CONTENT_MASK                                                                  0xFFFFFFFFL
736 //MP1_CRU1_MP1_C2PMSG_50
737 #define MP1_CRU1_MP1_C2PMSG_50__CONTENT__SHIFT                                                                0x0
738 #define MP1_CRU1_MP1_C2PMSG_50__CONTENT_MASK                                                                  0xFFFFFFFFL
739 //MP1_CRU1_MP1_C2PMSG_51
740 #define MP1_CRU1_MP1_C2PMSG_51__CONTENT__SHIFT                                                                0x0
741 #define MP1_CRU1_MP1_C2PMSG_51__CONTENT_MASK                                                                  0xFFFFFFFFL
742 //MP1_CRU1_MP1_C2PMSG_52
743 #define MP1_CRU1_MP1_C2PMSG_52__CONTENT__SHIFT                                                                0x0
744 #define MP1_CRU1_MP1_C2PMSG_52__CONTENT_MASK                                                                  0xFFFFFFFFL
745 //MP1_CRU1_MP1_C2PMSG_53
746 #define MP1_CRU1_MP1_C2PMSG_53__CONTENT__SHIFT                                                                0x0
747 #define MP1_CRU1_MP1_C2PMSG_53__CONTENT_MASK                                                                  0xFFFFFFFFL
748 //MP1_CRU1_MP1_C2PMSG_54
749 #define MP1_CRU1_MP1_C2PMSG_54__CONTENT__SHIFT                                                                0x0
750 #define MP1_CRU1_MP1_C2PMSG_54__CONTENT_MASK                                                                  0xFFFFFFFFL
751 //MP1_CRU1_MP1_C2PMSG_55
752 #define MP1_CRU1_MP1_C2PMSG_55__CONTENT__SHIFT                                                                0x0
753 #define MP1_CRU1_MP1_C2PMSG_55__CONTENT_MASK                                                                  0xFFFFFFFFL
754 //MP1_CRU1_MP1_C2PMSG_56
755 #define MP1_CRU1_MP1_C2PMSG_56__CONTENT__SHIFT                                                                0x0
756 #define MP1_CRU1_MP1_C2PMSG_56__CONTENT_MASK                                                                  0xFFFFFFFFL
757 //MP1_CRU1_MP1_C2PMSG_57
758 #define MP1_CRU1_MP1_C2PMSG_57__CONTENT__SHIFT                                                                0x0
759 #define MP1_CRU1_MP1_C2PMSG_57__CONTENT_MASK                                                                  0xFFFFFFFFL
760 //MP1_CRU1_MP1_C2PMSG_58
761 #define MP1_CRU1_MP1_C2PMSG_58__CONTENT__SHIFT                                                                0x0
762 #define MP1_CRU1_MP1_C2PMSG_58__CONTENT_MASK                                                                  0xFFFFFFFFL
763 //MP1_CRU1_MP1_C2PMSG_59
764 #define MP1_CRU1_MP1_C2PMSG_59__CONTENT__SHIFT                                                                0x0
765 #define MP1_CRU1_MP1_C2PMSG_59__CONTENT_MASK                                                                  0xFFFFFFFFL
766 //MP1_CRU1_MP1_C2PMSG_60
767 #define MP1_CRU1_MP1_C2PMSG_60__CONTENT__SHIFT                                                                0x0
768 #define MP1_CRU1_MP1_C2PMSG_60__CONTENT_MASK                                                                  0xFFFFFFFFL
769 //MP1_CRU1_MP1_C2PMSG_61
770 #define MP1_CRU1_MP1_C2PMSG_61__CONTENT__SHIFT                                                                0x0
771 #define MP1_CRU1_MP1_C2PMSG_61__CONTENT_MASK                                                                  0xFFFFFFFFL
772 //MP1_CRU1_MP1_C2PMSG_62
773 #define MP1_CRU1_MP1_C2PMSG_62__CONTENT__SHIFT                                                                0x0
774 #define MP1_CRU1_MP1_C2PMSG_62__CONTENT_MASK                                                                  0xFFFFFFFFL
775 //MP1_CRU1_MP1_C2PMSG_63
776 #define MP1_CRU1_MP1_C2PMSG_63__CONTENT__SHIFT                                                                0x0
777 #define MP1_CRU1_MP1_C2PMSG_63__CONTENT_MASK                                                                  0xFFFFFFFFL
778 //MP1_CRU1_MP1_C2PMSG_64
779 #define MP1_CRU1_MP1_C2PMSG_64__CONTENT__SHIFT                                                                0x0
780 #define MP1_CRU1_MP1_C2PMSG_64__CONTENT_MASK                                                                  0xFFFFFFFFL
781 //MP1_CRU1_MP1_C2PMSG_65
782 #define MP1_CRU1_MP1_C2PMSG_65__CONTENT__SHIFT                                                                0x0
783 #define MP1_CRU1_MP1_C2PMSG_65__CONTENT_MASK                                                                  0xFFFFFFFFL
784 //MP1_CRU1_MP1_C2PMSG_66
785 #define MP1_CRU1_MP1_C2PMSG_66__CONTENT__SHIFT                                                                0x0
786 #define MP1_CRU1_MP1_C2PMSG_66__CONTENT_MASK                                                                  0xFFFFFFFFL
787 //MP1_CRU1_MP1_C2PMSG_67
788 #define MP1_CRU1_MP1_C2PMSG_67__CONTENT__SHIFT                                                                0x0
789 #define MP1_CRU1_MP1_C2PMSG_67__CONTENT_MASK                                                                  0xFFFFFFFFL
790 //MP1_CRU1_MP1_C2PMSG_68
791 #define MP1_CRU1_MP1_C2PMSG_68__CONTENT__SHIFT                                                                0x0
792 #define MP1_CRU1_MP1_C2PMSG_68__CONTENT_MASK                                                                  0xFFFFFFFFL
793 //MP1_CRU1_MP1_C2PMSG_69
794 #define MP1_CRU1_MP1_C2PMSG_69__CONTENT__SHIFT                                                                0x0
795 #define MP1_CRU1_MP1_C2PMSG_69__CONTENT_MASK                                                                  0xFFFFFFFFL
796 //MP1_CRU1_MP1_C2PMSG_70
797 #define MP1_CRU1_MP1_C2PMSG_70__CONTENT__SHIFT                                                                0x0
798 #define MP1_CRU1_MP1_C2PMSG_70__CONTENT_MASK                                                                  0xFFFFFFFFL
799 //MP1_CRU1_MP1_C2PMSG_71
800 #define MP1_CRU1_MP1_C2PMSG_71__CONTENT__SHIFT                                                                0x0
801 #define MP1_CRU1_MP1_C2PMSG_71__CONTENT_MASK                                                                  0xFFFFFFFFL
802 //MP1_CRU1_MP1_C2PMSG_72
803 #define MP1_CRU1_MP1_C2PMSG_72__CONTENT__SHIFT                                                                0x0
804 #define MP1_CRU1_MP1_C2PMSG_72__CONTENT_MASK                                                                  0xFFFFFFFFL
805 //MP1_CRU1_MP1_C2PMSG_73
806 #define MP1_CRU1_MP1_C2PMSG_73__CONTENT__SHIFT                                                                0x0
807 #define MP1_CRU1_MP1_C2PMSG_73__CONTENT_MASK                                                                  0xFFFFFFFFL
808 //MP1_CRU1_MP1_C2PMSG_74
809 #define MP1_CRU1_MP1_C2PMSG_74__CONTENT__SHIFT                                                                0x0
810 #define MP1_CRU1_MP1_C2PMSG_74__CONTENT_MASK                                                                  0xFFFFFFFFL
811 //MP1_CRU1_MP1_C2PMSG_75
812 #define MP1_CRU1_MP1_C2PMSG_75__CONTENT__SHIFT                                                                0x0
813 #define MP1_CRU1_MP1_C2PMSG_75__CONTENT_MASK                                                                  0xFFFFFFFFL
814 //MP1_CRU1_MP1_C2PMSG_76
815 #define MP1_CRU1_MP1_C2PMSG_76__CONTENT__SHIFT                                                                0x0
816 #define MP1_CRU1_MP1_C2PMSG_76__CONTENT_MASK                                                                  0xFFFFFFFFL
817 //MP1_CRU1_MP1_C2PMSG_77
818 #define MP1_CRU1_MP1_C2PMSG_77__CONTENT__SHIFT                                                                0x0
819 #define MP1_CRU1_MP1_C2PMSG_77__CONTENT_MASK                                                                  0xFFFFFFFFL
820 //MP1_CRU1_MP1_C2PMSG_78
821 #define MP1_CRU1_MP1_C2PMSG_78__CONTENT__SHIFT                                                                0x0
822 #define MP1_CRU1_MP1_C2PMSG_78__CONTENT_MASK                                                                  0xFFFFFFFFL
823 //MP1_CRU1_MP1_C2PMSG_79
824 #define MP1_CRU1_MP1_C2PMSG_79__CONTENT__SHIFT                                                                0x0
825 #define MP1_CRU1_MP1_C2PMSG_79__CONTENT_MASK                                                                  0xFFFFFFFFL
826 //MP1_CRU1_MP1_C2PMSG_80
827 #define MP1_CRU1_MP1_C2PMSG_80__CONTENT__SHIFT                                                                0x0
828 #define MP1_CRU1_MP1_C2PMSG_80__CONTENT_MASK                                                                  0xFFFFFFFFL
829 //MP1_CRU1_MP1_C2PMSG_81
830 #define MP1_CRU1_MP1_C2PMSG_81__CONTENT__SHIFT                                                                0x0
831 #define MP1_CRU1_MP1_C2PMSG_81__CONTENT_MASK                                                                  0xFFFFFFFFL
832 //MP1_CRU1_MP1_C2PMSG_82
833 #define MP1_CRU1_MP1_C2PMSG_82__CONTENT__SHIFT                                                                0x0
834 #define MP1_CRU1_MP1_C2PMSG_82__CONTENT_MASK                                                                  0xFFFFFFFFL
835 //MP1_CRU1_MP1_C2PMSG_83
836 #define MP1_CRU1_MP1_C2PMSG_83__CONTENT__SHIFT                                                                0x0
837 #define MP1_CRU1_MP1_C2PMSG_83__CONTENT_MASK                                                                  0xFFFFFFFFL
838 //MP1_CRU1_MP1_C2PMSG_84
839 #define MP1_CRU1_MP1_C2PMSG_84__CONTENT__SHIFT                                                                0x0
840 #define MP1_CRU1_MP1_C2PMSG_84__CONTENT_MASK                                                                  0xFFFFFFFFL
841 //MP1_CRU1_MP1_C2PMSG_85
842 #define MP1_CRU1_MP1_C2PMSG_85__CONTENT__SHIFT                                                                0x0
843 #define MP1_CRU1_MP1_C2PMSG_85__CONTENT_MASK                                                                  0xFFFFFFFFL
844 //MP1_CRU1_MP1_C2PMSG_86
845 #define MP1_CRU1_MP1_C2PMSG_86__CONTENT__SHIFT                                                                0x0
846 #define MP1_CRU1_MP1_C2PMSG_86__CONTENT_MASK                                                                  0xFFFFFFFFL
847 //MP1_CRU1_MP1_C2PMSG_87
848 #define MP1_CRU1_MP1_C2PMSG_87__CONTENT__SHIFT                                                                0x0
849 #define MP1_CRU1_MP1_C2PMSG_87__CONTENT_MASK                                                                  0xFFFFFFFFL
850 //MP1_CRU1_MP1_C2PMSG_88
851 #define MP1_CRU1_MP1_C2PMSG_88__CONTENT__SHIFT                                                                0x0
852 #define MP1_CRU1_MP1_C2PMSG_88__CONTENT_MASK                                                                  0xFFFFFFFFL
853 //MP1_CRU1_MP1_C2PMSG_89
854 #define MP1_CRU1_MP1_C2PMSG_89__CONTENT__SHIFT                                                                0x0
855 #define MP1_CRU1_MP1_C2PMSG_89__CONTENT_MASK                                                                  0xFFFFFFFFL
856 //MP1_CRU1_MP1_C2PMSG_90
857 #define MP1_CRU1_MP1_C2PMSG_90__CONTENT__SHIFT                                                                0x0
858 #define MP1_CRU1_MP1_C2PMSG_90__CONTENT_MASK                                                                  0xFFFFFFFFL
859 //MP1_CRU1_MP1_C2PMSG_91
860 #define MP1_CRU1_MP1_C2PMSG_91__CONTENT__SHIFT                                                                0x0
861 #define MP1_CRU1_MP1_C2PMSG_91__CONTENT_MASK                                                                  0xFFFFFFFFL
862 //MP1_CRU1_MP1_C2PMSG_92
863 #define MP1_CRU1_MP1_C2PMSG_92__CONTENT__SHIFT                                                                0x0
864 #define MP1_CRU1_MP1_C2PMSG_92__CONTENT_MASK                                                                  0xFFFFFFFFL
865 //MP1_CRU1_MP1_C2PMSG_93
866 #define MP1_CRU1_MP1_C2PMSG_93__CONTENT__SHIFT                                                                0x0
867 #define MP1_CRU1_MP1_C2PMSG_93__CONTENT_MASK                                                                  0xFFFFFFFFL
868 //MP1_CRU1_MP1_C2PMSG_94
869 #define MP1_CRU1_MP1_C2PMSG_94__CONTENT__SHIFT                                                                0x0
870 #define MP1_CRU1_MP1_C2PMSG_94__CONTENT_MASK                                                                  0xFFFFFFFFL
871 //MP1_CRU1_MP1_C2PMSG_95
872 #define MP1_CRU1_MP1_C2PMSG_95__CONTENT__SHIFT                                                                0x0
873 #define MP1_CRU1_MP1_C2PMSG_95__CONTENT_MASK                                                                  0xFFFFFFFFL
874 //MP1_CRU1_MP1_C2PMSG_96
875 #define MP1_CRU1_MP1_C2PMSG_96__CONTENT__SHIFT                                                                0x0
876 #define MP1_CRU1_MP1_C2PMSG_96__CONTENT_MASK                                                                  0xFFFFFFFFL
877 //MP1_CRU1_MP1_C2PMSG_97
878 #define MP1_CRU1_MP1_C2PMSG_97__CONTENT__SHIFT                                                                0x0
879 #define MP1_CRU1_MP1_C2PMSG_97__CONTENT_MASK                                                                  0xFFFFFFFFL
880 //MP1_CRU1_MP1_C2PMSG_98
881 #define MP1_CRU1_MP1_C2PMSG_98__CONTENT__SHIFT                                                                0x0
882 #define MP1_CRU1_MP1_C2PMSG_98__CONTENT_MASK                                                                  0xFFFFFFFFL
883 //MP1_CRU1_MP1_C2PMSG_99
884 #define MP1_CRU1_MP1_C2PMSG_99__CONTENT__SHIFT                                                                0x0
885 #define MP1_CRU1_MP1_C2PMSG_99__CONTENT_MASK                                                                  0xFFFFFFFFL
886 //MP1_CRU1_MP1_C2PMSG_100
887 #define MP1_CRU1_MP1_C2PMSG_100__CONTENT__SHIFT                                                               0x0
888 #define MP1_CRU1_MP1_C2PMSG_100__CONTENT_MASK                                                                 0xFFFFFFFFL
889 //MP1_CRU1_MP1_C2PMSG_101
890 #define MP1_CRU1_MP1_C2PMSG_101__CONTENT__SHIFT                                                               0x0
891 #define MP1_CRU1_MP1_C2PMSG_101__CONTENT_MASK                                                                 0xFFFFFFFFL
892 //MP1_CRU1_MP1_C2PMSG_102
893 #define MP1_CRU1_MP1_C2PMSG_102__CONTENT__SHIFT                                                               0x0
894 #define MP1_CRU1_MP1_C2PMSG_102__CONTENT_MASK                                                                 0xFFFFFFFFL
895 //MP1_CRU1_MP1_C2PMSG_103
896 #define MP1_CRU1_MP1_C2PMSG_103__CONTENT__SHIFT                                                               0x0
897 #define MP1_CRU1_MP1_C2PMSG_103__CONTENT_MASK                                                                 0xFFFFFFFFL
898 //MP1_CRU1_MP1_IH_CREDIT
899 #define MP1_CRU1_MP1_IH_CREDIT__CREDIT_VALUE__SHIFT                                                           0x0
900 #define MP1_CRU1_MP1_IH_CREDIT__CLIENT_ID__SHIFT                                                              0x10
901 #define MP1_CRU1_MP1_IH_CREDIT__CREDIT_VALUE_MASK                                                             0x00000003L
902 #define MP1_CRU1_MP1_IH_CREDIT__CLIENT_ID_MASK                                                                0x00FF0000L
903 //MP1_CRU1_MP1_IH_SW_INT
904 #define MP1_CRU1_MP1_IH_SW_INT__ID__SHIFT                                                                     0x0
905 #define MP1_CRU1_MP1_IH_SW_INT__VALID__SHIFT                                                                  0x8
906 #define MP1_CRU1_MP1_IH_SW_INT__ID_MASK                                                                       0x000000FFL
907 #define MP1_CRU1_MP1_IH_SW_INT__VALID_MASK                                                                    0x00000100L
908 //MP1_CRU1_MP1_IH_SW_INT_CTRL
909 #define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                          0x0
910 #define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                           0x8
911 #define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_MASK_MASK                                                            0x00000001L
912 #define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_ACK_MASK                                                             0x00000100L
913 //MP1_CRU1_MP1_FPS_CNT
914 #define MP1_CRU1_MP1_FPS_CNT__COUNT__SHIFT                                                                    0x0
915 #define MP1_CRU1_MP1_FPS_CNT__COUNT_MASK                                                                      0xFFFFFFFFL
916 //MP1_CRU1_MP1_EXT_SCRATCH0
917 #define MP1_CRU1_MP1_EXT_SCRATCH0__DATA__SHIFT                                                                0x0
918 #define MP1_CRU1_MP1_EXT_SCRATCH0__DATA_MASK                                                                  0xFFFFFFFFL
919 //MP1_CRU1_MP1_EXT_SCRATCH1
920 #define MP1_CRU1_MP1_EXT_SCRATCH1__DATA__SHIFT                                                                0x0
921 #define MP1_CRU1_MP1_EXT_SCRATCH1__DATA_MASK                                                                  0xFFFFFFFFL
922 //MP1_CRU1_MP1_EXT_SCRATCH2
923 #define MP1_CRU1_MP1_EXT_SCRATCH2__DATA__SHIFT                                                                0x0
924 #define MP1_CRU1_MP1_EXT_SCRATCH2__DATA_MASK                                                                  0xFFFFFFFFL
925 //MP1_CRU1_MP1_EXT_SCRATCH3
926 #define MP1_CRU1_MP1_EXT_SCRATCH3__DATA__SHIFT                                                                0x0
927 #define MP1_CRU1_MP1_EXT_SCRATCH3__DATA_MASK                                                                  0xFFFFFFFFL
928 //MP1_CRU1_MP1_EXT_SCRATCH4
929 #define MP1_CRU1_MP1_EXT_SCRATCH4__DATA__SHIFT                                                                0x0
930 #define MP1_CRU1_MP1_EXT_SCRATCH4__DATA_MASK                                                                  0xFFFFFFFFL
931 //MP1_CRU1_MP1_EXT_SCRATCH5
932 #define MP1_CRU1_MP1_EXT_SCRATCH5__DATA__SHIFT                                                                0x0
933 #define MP1_CRU1_MP1_EXT_SCRATCH5__DATA_MASK                                                                  0xFFFFFFFFL
934 //MP1_CRU1_MP1_EXT_SCRATCH6
935 #define MP1_CRU1_MP1_EXT_SCRATCH6__DATA__SHIFT                                                                0x0
936 #define MP1_CRU1_MP1_EXT_SCRATCH6__DATA_MASK                                                                  0xFFFFFFFFL
937 //MP1_CRU1_MP1_EXT_SCRATCH7
938 #define MP1_CRU1_MP1_EXT_SCRATCH7__DATA__SHIFT                                                                0x0
939 #define MP1_CRU1_MP1_EXT_SCRATCH7__DATA_MASK                                                                  0xFFFFFFFFL
940 
941 
942 #endif
943