1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _mp_13_0_2_SH_MASK_HEADER 25 #define _mp_13_0_2_SH_MASK_HEADER 26 27 28 // addressBlock: mp_SmuMp0_SmnDec 29 //MP0_SMN_C2PMSG_32 30 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 31 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 32 //MP0_SMN_C2PMSG_33 33 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 34 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 35 //MP0_SMN_C2PMSG_34 36 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 37 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 38 //MP0_SMN_C2PMSG_35 39 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 40 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 41 //MP0_SMN_C2PMSG_36 42 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 43 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 44 //MP0_SMN_C2PMSG_37 45 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 46 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 47 //MP0_SMN_C2PMSG_38 48 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 49 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 50 //MP0_SMN_C2PMSG_39 51 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 52 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 53 //MP0_SMN_C2PMSG_40 54 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 55 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 56 //MP0_SMN_C2PMSG_41 57 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 58 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 59 //MP0_SMN_C2PMSG_42 60 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 61 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 62 //MP0_SMN_C2PMSG_43 63 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 64 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 65 //MP0_SMN_C2PMSG_44 66 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 67 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 68 //MP0_SMN_C2PMSG_45 69 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 70 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 71 //MP0_SMN_C2PMSG_46 72 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 73 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 74 //MP0_SMN_C2PMSG_47 75 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 76 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 77 //MP0_SMN_C2PMSG_48 78 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 79 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 80 //MP0_SMN_C2PMSG_49 81 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 82 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 83 //MP0_SMN_C2PMSG_50 84 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 85 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 86 //MP0_SMN_C2PMSG_51 87 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 88 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 89 //MP0_SMN_C2PMSG_52 90 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 91 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 92 //MP0_SMN_C2PMSG_53 93 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 94 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 95 //MP0_SMN_C2PMSG_54 96 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 97 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 98 //MP0_SMN_C2PMSG_55 99 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 100 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 101 //MP0_SMN_C2PMSG_56 102 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 103 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 104 //MP0_SMN_C2PMSG_57 105 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 106 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 107 //MP0_SMN_C2PMSG_58 108 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 109 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 110 //MP0_SMN_C2PMSG_59 111 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 112 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 113 //MP0_SMN_C2PMSG_60 114 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 115 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 116 //MP0_SMN_C2PMSG_61 117 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 118 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 119 //MP0_SMN_C2PMSG_62 120 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 121 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 122 //MP0_SMN_C2PMSG_63 123 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 124 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 125 //MP0_SMN_C2PMSG_64 126 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 127 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 128 //MP0_SMN_C2PMSG_65 129 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 130 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 131 //MP0_SMN_C2PMSG_66 132 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 133 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 134 //MP0_SMN_C2PMSG_67 135 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 136 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 137 //MP0_SMN_C2PMSG_68 138 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 139 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 140 //MP0_SMN_C2PMSG_69 141 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 142 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 143 //MP0_SMN_C2PMSG_70 144 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 145 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 146 //MP0_SMN_C2PMSG_71 147 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 148 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 149 //MP0_SMN_C2PMSG_72 150 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 151 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 152 //MP0_SMN_C2PMSG_73 153 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 154 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 155 //MP0_SMN_C2PMSG_74 156 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 157 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 158 //MP0_SMN_C2PMSG_75 159 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 160 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 161 //MP0_SMN_C2PMSG_76 162 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 163 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 164 //MP0_SMN_C2PMSG_77 165 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 166 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 167 //MP0_SMN_C2PMSG_78 168 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 169 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 170 //MP0_SMN_C2PMSG_79 171 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 172 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 173 //MP0_SMN_C2PMSG_80 174 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 175 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 176 //MP0_SMN_C2PMSG_81 177 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 178 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 179 //MP0_SMN_C2PMSG_82 180 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 181 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 182 //MP0_SMN_C2PMSG_83 183 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 184 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 185 //MP0_SMN_C2PMSG_84 186 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 187 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 188 //MP0_SMN_C2PMSG_85 189 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 190 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 191 //MP0_SMN_C2PMSG_86 192 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 193 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 194 //MP0_SMN_C2PMSG_87 195 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 196 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 197 //MP0_SMN_C2PMSG_88 198 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 199 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 200 //MP0_SMN_C2PMSG_89 201 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 202 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 203 //MP0_SMN_C2PMSG_90 204 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 205 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 206 //MP0_SMN_C2PMSG_91 207 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 208 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 209 //MP0_SMN_C2PMSG_92 210 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 211 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 212 //MP0_SMN_C2PMSG_93 213 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 214 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 215 //MP0_SMN_C2PMSG_94 216 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 217 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 218 //MP0_SMN_C2PMSG_95 219 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 220 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 221 //MP0_SMN_C2PMSG_96 222 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 223 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 224 //MP0_SMN_C2PMSG_97 225 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 226 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 227 //MP0_SMN_C2PMSG_98 228 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 229 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 230 //MP0_SMN_C2PMSG_99 231 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 232 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 233 //MP0_SMN_C2PMSG_100 234 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 235 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 236 //MP0_SMN_C2PMSG_101 237 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 238 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 239 //MP0_SMN_C2PMSG_102 240 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 241 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 242 //MP0_SMN_C2PMSG_103 243 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 244 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 245 //MP0_SMN_IH_CREDIT 246 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 247 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 248 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 249 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 250 //MP0_SMN_IH_SW_INT 251 #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 252 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 253 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL 254 #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L 255 //MP0_SMN_IH_SW_INT_CTRL 256 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 257 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 258 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 259 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 260 261 262 // addressBlock: mp_SmuMp1Pub_CruDec 263 //MP1_FIRMWARE_FLAGS 264 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 265 #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 266 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 267 #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 268 269 270 // addressBlock: mp_SmuMp1_SmnDec 271 //MP1_SMN_C2PMSG_32 272 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 273 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 274 //MP1_SMN_C2PMSG_33 275 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 276 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 277 //MP1_SMN_C2PMSG_34 278 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 279 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 280 //MP1_SMN_C2PMSG_35 281 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 282 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 283 //MP1_SMN_C2PMSG_36 284 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 285 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 286 //MP1_SMN_C2PMSG_37 287 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 288 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 289 //MP1_SMN_C2PMSG_38 290 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 291 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 292 //MP1_SMN_C2PMSG_39 293 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 294 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 295 //MP1_SMN_C2PMSG_40 296 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 297 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 298 //MP1_SMN_C2PMSG_41 299 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 300 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 301 //MP1_SMN_C2PMSG_42 302 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 303 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 304 //MP1_SMN_C2PMSG_43 305 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 306 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 307 //MP1_SMN_C2PMSG_44 308 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 309 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 310 //MP1_SMN_C2PMSG_45 311 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 312 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 313 //MP1_SMN_C2PMSG_46 314 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 315 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 316 //MP1_SMN_C2PMSG_47 317 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 318 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 319 //MP1_SMN_C2PMSG_48 320 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 321 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 322 //MP1_SMN_C2PMSG_49 323 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 324 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 325 //MP1_SMN_C2PMSG_50 326 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 327 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 328 //MP1_SMN_C2PMSG_51 329 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 330 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 331 //MP1_SMN_C2PMSG_52 332 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 333 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 334 //MP1_SMN_C2PMSG_53 335 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 336 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 337 //MP1_SMN_C2PMSG_54 338 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 339 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 340 //MP1_SMN_C2PMSG_55 341 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 342 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 343 //MP1_SMN_C2PMSG_56 344 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 345 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 346 //MP1_SMN_C2PMSG_57 347 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 348 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 349 //MP1_SMN_C2PMSG_58 350 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 351 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 352 //MP1_SMN_C2PMSG_59 353 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 354 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 355 //MP1_SMN_C2PMSG_60 356 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 357 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 358 //MP1_SMN_C2PMSG_61 359 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 360 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 361 //MP1_SMN_C2PMSG_62 362 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 363 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 364 //MP1_SMN_C2PMSG_63 365 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 366 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 367 //MP1_SMN_C2PMSG_64 368 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 369 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 370 //MP1_SMN_C2PMSG_65 371 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 372 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 373 //MP1_SMN_C2PMSG_66 374 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 375 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 376 //MP1_SMN_C2PMSG_67 377 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 378 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 379 //MP1_SMN_C2PMSG_68 380 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 381 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 382 //MP1_SMN_C2PMSG_69 383 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 384 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 385 //MP1_SMN_C2PMSG_70 386 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 387 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 388 //MP1_SMN_C2PMSG_71 389 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 390 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 391 //MP1_SMN_C2PMSG_72 392 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 393 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 394 //MP1_SMN_C2PMSG_73 395 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 396 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 397 //MP1_SMN_C2PMSG_74 398 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 399 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 400 //MP1_SMN_C2PMSG_75 401 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 402 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 403 //MP1_SMN_C2PMSG_76 404 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 405 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 406 //MP1_SMN_C2PMSG_77 407 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 408 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 409 //MP1_SMN_C2PMSG_78 410 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 411 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 412 //MP1_SMN_C2PMSG_79 413 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 414 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 415 //MP1_SMN_C2PMSG_80 416 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 417 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 418 //MP1_SMN_C2PMSG_81 419 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 420 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 421 //MP1_SMN_C2PMSG_82 422 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 423 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 424 //MP1_SMN_C2PMSG_83 425 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 426 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 427 //MP1_SMN_C2PMSG_84 428 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 429 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 430 //MP1_SMN_C2PMSG_85 431 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 432 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 433 //MP1_SMN_C2PMSG_86 434 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 435 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 436 //MP1_SMN_C2PMSG_87 437 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 438 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 439 //MP1_SMN_C2PMSG_88 440 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 441 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 442 //MP1_SMN_C2PMSG_89 443 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 444 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 445 //MP1_SMN_C2PMSG_90 446 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 447 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 448 //MP1_SMN_C2PMSG_91 449 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 450 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 451 //MP1_SMN_C2PMSG_92 452 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 453 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 454 //MP1_SMN_C2PMSG_93 455 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 456 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 457 //MP1_SMN_C2PMSG_94 458 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 459 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 460 //MP1_SMN_C2PMSG_95 461 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 462 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 463 //MP1_SMN_C2PMSG_96 464 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 465 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 466 //MP1_SMN_C2PMSG_97 467 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 468 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 469 //MP1_SMN_C2PMSG_98 470 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 471 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 472 //MP1_SMN_C2PMSG_99 473 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 474 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 475 //MP1_SMN_C2PMSG_100 476 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 477 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 478 //MP1_SMN_C2PMSG_101 479 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 480 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 481 //MP1_SMN_C2PMSG_102 482 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 483 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 484 //MP1_SMN_C2PMSG_103 485 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 486 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 487 //MP1_SMN_C2PMSG_104 488 #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 489 #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 490 //MP1_SMN_C2PMSG_105 491 #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 492 #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 493 //MP1_SMN_C2PMSG_106 494 #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 495 #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 496 //MP1_SMN_C2PMSG_107 497 #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 498 #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 499 //MP1_SMN_C2PMSG_108 500 #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 501 #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 502 //MP1_SMN_C2PMSG_109 503 #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 504 #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 505 //MP1_SMN_C2PMSG_110 506 #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 507 #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 508 //MP1_SMN_C2PMSG_111 509 #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 510 #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 511 //MP1_SMN_C2PMSG_112 512 #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 513 #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 514 //MP1_SMN_C2PMSG_113 515 #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 516 #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 517 //MP1_SMN_C2PMSG_114 518 #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 519 #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 520 //MP1_SMN_C2PMSG_115 521 #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 522 #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 523 //MP1_SMN_C2PMSG_116 524 #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 525 #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 526 //MP1_SMN_C2PMSG_117 527 #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 528 #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 529 //MP1_SMN_C2PMSG_118 530 #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 531 #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 532 //MP1_SMN_C2PMSG_119 533 #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 534 #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 535 //MP1_SMN_C2PMSG_120 536 #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 537 #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 538 //MP1_SMN_C2PMSG_121 539 #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 540 #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 541 //MP1_SMN_C2PMSG_122 542 #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 543 #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 544 //MP1_SMN_C2PMSG_123 545 #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 546 #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 547 //MP1_SMN_C2PMSG_124 548 #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 549 #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 550 //MP1_SMN_C2PMSG_125 551 #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 552 #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 553 //MP1_SMN_C2PMSG_126 554 #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 555 #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 556 //MP1_SMN_C2PMSG_127 557 #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 558 #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 559 //MP1_SMN_IH_CREDIT 560 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 561 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 562 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 563 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 564 //MP1_SMN_IH_SW_INT 565 #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 566 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 567 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 568 #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 569 //MP1_SMN_IH_SW_INT_CTRL 570 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 571 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 572 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 573 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 574 //MP1_SMN_FPS_CNT 575 #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 576 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 577 //MP1_SMN_EXT_SCRATCH0 578 #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 579 #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 580 //MP1_SMN_EXT_SCRATCH1 581 #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 582 #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 583 //MP1_SMN_EXT_SCRATCH2 584 #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 585 #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 586 //MP1_SMN_EXT_SCRATCH3 587 #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 588 #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 589 //MP1_SMN_EXT_SCRATCH4 590 #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 591 #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 592 //MP1_SMN_EXT_SCRATCH5 593 #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 594 #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 595 //MP1_SMN_EXT_SCRATCH6 596 #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 597 #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 598 //MP1_SMN_EXT_SCRATCH7 599 #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 600 #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 601 602 603 #endif 604