1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 
22 #ifndef _nbio_6_1_SMN_HEADER
23 #define _nbio_6_1_SMN_HEADER
24 
25 
26 #define smnCPM_CONTROL					0x11180460
27 #define smnPCIE_CNTL2					0x11180070
28 #define smnPCIE_CONFIG_CNTL				0x11180044
29 #define smnPCIE_CI_CNTL					0x11180080
30 
31 
32 #define smnPCIE_PERF_COUNT_CNTL				0x11180200
33 #define smnPCIE_PERF_CNTL_TXCLK				0x11180204
34 #define smnPCIE_PERF_COUNT0_TXCLK			0x11180208
35 #define smnPCIE_PERF_COUNT1_TXCLK			0x1118020c
36 #define smnPCIE_PERF_CNTL_MST_R_CLK			0x11180210
37 #define smnPCIE_PERF_COUNT0_MST_R_CLK			0x11180214
38 #define smnPCIE_PERF_COUNT1_MST_R_CLK			0x11180218
39 #define smnPCIE_PERF_CNTL_MST_C_CLK			0x1118021c
40 #define smnPCIE_PERF_COUNT0_MST_C_CLK			0x11180220
41 #define smnPCIE_PERF_COUNT1_MST_C_CLK			0x11180224
42 #define smnPCIE_PERF_CNTL_SLV_R_CLK			0x11180228
43 #define smnPCIE_PERF_COUNT0_SLV_R_CLK			0x1118022c
44 #define smnPCIE_PERF_COUNT1_SLV_R_CLK			0x11180230
45 #define smnPCIE_PERF_CNTL_SLV_S_C_CLK			0x11180234
46 #define smnPCIE_PERF_COUNT0_SLV_S_C_CLK			0x11180238
47 #define smnPCIE_PERF_COUNT1_SLV_S_C_CLK			0x1118023c
48 #define smnPCIE_PERF_CNTL_SLV_NS_C_CLK			0x11180240
49 #define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK		0x11180244
50 #define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK		0x11180248
51 #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL		0x1118024c
52 #define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL		0x11180250
53 #define smnPCIE_PERF_CNTL_TXCLK2			0x11180254
54 #define smnPCIE_PERF_COUNT0_TXCLK2			0x11180258
55 #define smnPCIE_PERF_COUNT1_TXCLK2			0x1118025c
56 
57 #define smnPCIE_RX_NUM_NAK				0x11180038
58 #define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c
59 
60 #endif	// _nbio_6_1_SMN_HEADER
61 
62