11f902edeSFeifei Xu /* 21f902edeSFeifei Xu * Copyright (C) 2018 Advanced Micro Devices, Inc. 31f902edeSFeifei Xu * 41f902edeSFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 51f902edeSFeifei Xu * copy of this software and associated documentation files (the "Software"), 61f902edeSFeifei Xu * to deal in the Software without restriction, including without limitation 71f902edeSFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 81f902edeSFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 91f902edeSFeifei Xu * Software is furnished to do so, subject to the following conditions: 101f902edeSFeifei Xu * 111f902edeSFeifei Xu * The above copyright notice and this permission notice shall be included 121f902edeSFeifei Xu * in all copies or substantial portions of the Software. 131f902edeSFeifei Xu * 141f902edeSFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 151f902edeSFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 161f902edeSFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 171f902edeSFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 181f902edeSFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 191f902edeSFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 201f902edeSFeifei Xu */ 211f902edeSFeifei Xu #ifndef _nbio_7_4_OFFSET_HEADER 221f902edeSFeifei Xu #define _nbio_7_4_OFFSET_HEADER 231f902edeSFeifei Xu 241f902edeSFeifei Xu 251f902edeSFeifei Xu 261f902edeSFeifei Xu // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 271f902edeSFeifei Xu // base address: 0x0 281f902edeSFeifei Xu #define cfgPSWUSCFG0_VENDOR_ID 0x0000 291f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_ID 0x0002 301f902edeSFeifei Xu #define cfgPSWUSCFG0_COMMAND 0x0004 311f902edeSFeifei Xu #define cfgPSWUSCFG0_STATUS 0x0006 321f902edeSFeifei Xu #define cfgPSWUSCFG0_REVISION_ID 0x0008 331f902edeSFeifei Xu #define cfgPSWUSCFG0_PROG_INTERFACE 0x0009 341f902edeSFeifei Xu #define cfgPSWUSCFG0_SUB_CLASS 0x000a 351f902edeSFeifei Xu #define cfgPSWUSCFG0_BASE_CLASS 0x000b 361f902edeSFeifei Xu #define cfgPSWUSCFG0_CACHE_LINE 0x000c 371f902edeSFeifei Xu #define cfgPSWUSCFG0_LATENCY 0x000d 381f902edeSFeifei Xu #define cfgPSWUSCFG0_HEADER 0x000e 391f902edeSFeifei Xu #define cfgPSWUSCFG0_BIST 0x000f 401f902edeSFeifei Xu #define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018 411f902edeSFeifei Xu #define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c 421f902edeSFeifei Xu #define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e 431f902edeSFeifei Xu #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020 441f902edeSFeifei Xu #define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024 451f902edeSFeifei Xu #define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028 461f902edeSFeifei Xu #define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c 471f902edeSFeifei Xu #define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030 481f902edeSFeifei Xu #define cfgPSWUSCFG0_CAP_PTR 0x0034 491f902edeSFeifei Xu #define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c 501f902edeSFeifei Xu #define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d 511f902edeSFeifei Xu #define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e 521f902edeSFeifei Xu #define cfgEXT_BRIDGE_CNTL 0x0040 531f902edeSFeifei Xu #define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048 541f902edeSFeifei Xu #define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c 551f902edeSFeifei Xu #define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050 561f902edeSFeifei Xu #define cfgPSWUSCFG0_PMI_CAP 0x0052 571f902edeSFeifei Xu #define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054 581f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058 591f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_CAP 0x005a 601f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_CAP 0x005c 611f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_CNTL 0x0060 621f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_STATUS 0x0062 631f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_CAP 0x0064 641f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_CNTL 0x0068 651f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_STATUS 0x006a 661f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_CAP2 0x007c 671f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080 681f902edeSFeifei Xu #define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082 691f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_CAP2 0x0084 701f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_CNTL2 0x0088 711f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_STATUS2 0x008a 721f902edeSFeifei Xu #define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0 731f902edeSFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2 741f902edeSFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4 751f902edeSFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8 761f902edeSFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8 771f902edeSFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac 781f902edeSFeifei Xu #define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0 791f902edeSFeifei Xu #define cfgPSWUSCFG0_SSID_CAP 0x00c4 801f902edeSFeifei Xu #define cfgMSI_MAP_CAP_LIST 0x00c8 811f902edeSFeifei Xu #define cfgMSI_MAP_CAP 0x00ca 821f902edeSFeifei Xu #define cfgMSI_MAP_ADDR_LO 0x00cc 831f902edeSFeifei Xu #define cfgMSI_MAP_ADDR_HI 0x00d0 841f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 851f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 861f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108 871f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c 881f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110 891f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114 901f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118 911f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c 921f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e 931f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120 941f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124 951f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a 961f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c 971f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130 981f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136 991f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 1001f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 1011f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 1021f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1031f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154 1041f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158 1051f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1061f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160 1071f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164 1081f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1091f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c 1101f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170 1111f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174 1121f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178 1131f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188 1141f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c 1151f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190 1161f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194 1171f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 1181f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274 1191f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278 1201f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 1211f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 1221f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 1231f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 1241f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 1251f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 1261f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 1271f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 1281f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 1291f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 1301f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 1311f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 1321f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 1331f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 1341f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 1351f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 1361f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0 1371f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4 1381f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6 1391f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0 1401f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4 1411f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6 1421f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8 1431f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc 1441f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300 1451f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304 1461f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308 1471f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c 1481f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 1491f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 1501f902edeSFeifei Xu #define cfgPCIE_MC_OVERLAY_BAR0 0x0318 1511f902edeSFeifei Xu #define cfgPCIE_MC_OVERLAY_BAR1 0x031c 1521f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320 1531f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324 1541f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328 1551f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c 1561f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e 1571f902edeSFeifei Xu #define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370 1581f902edeSFeifei Xu #define cfgPCIE_L1_PM_SUB_CAP 0x0374 1591f902edeSFeifei Xu #define cfgPCIE_L1_PM_SUB_CNTL 0x0378 1601f902edeSFeifei Xu #define cfgPCIE_L1_PM_SUB_CNTL2 0x037c 1611f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_LIST 0x03c4 1621f902edeSFeifei Xu #define cfgPCIE_ESM_HEADER_1 0x03c8 1631f902edeSFeifei Xu #define cfgPCIE_ESM_HEADER_2 0x03cc 1641f902edeSFeifei Xu #define cfgPCIE_ESM_STATUS 0x03ce 1651f902edeSFeifei Xu #define cfgPCIE_ESM_CTRL 0x03d0 1661f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_1 0x03d4 1671f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_2 0x03d8 1681f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_3 0x03dc 1691f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_4 0x03e0 1701f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_5 0x03e4 1711f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_6 0x03e8 1721f902edeSFeifei Xu #define cfgPCIE_ESM_CAP_7 0x03ec 1731f902edeSFeifei Xu #define cfgPSWUSCFG0_PCIE_DLF_ENH_CAP_LIST 0x0400 1741f902edeSFeifei Xu #define cfgPSWUSCFG0_DATA_LINK_FEATURE_CAP 0x0404 1751f902edeSFeifei Xu #define cfgPSWUSCFG0_DATA_LINK_FEATURE_STATUS 0x0408 1761f902edeSFeifei Xu #define cfgPCIE_PHY_16GT_ENH_CAP_LIST 0x0410 1771f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_CAP_16GT 0x0414 1781f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_CNTL_16GT 0x0418 1791f902edeSFeifei Xu #define cfgPSWUSCFG0_LINK_STATUS_16GT 0x041c 1801f902edeSFeifei Xu #define cfgPSWUSCFG0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 1811f902edeSFeifei Xu #define cfgPSWUSCFG0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 1821f902edeSFeifei Xu #define cfgPSWUSCFG0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 1831f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 1841f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 1851f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 1861f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 1871f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 1881f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 1891f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 1901f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 1911f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 1921f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 1931f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 1941f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 1951f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 1961f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 1971f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 1981f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 1991f902edeSFeifei Xu #define cfgPCIE_MARGINING_ENH_CAP_LIST 0x0440 2001f902edeSFeifei Xu #define cfgPSWUSCFG0_MARGINING_PORT_CAP 0x0444 2011f902edeSFeifei Xu #define cfgPSWUSCFG0_MARGINING_PORT_STATUS 0x0446 2021f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_0_MARGINING_LANE_CNTL 0x0448 2031f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_0_MARGINING_LANE_STATUS 0x044a 2041f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_1_MARGINING_LANE_CNTL 0x044c 2051f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_1_MARGINING_LANE_STATUS 0x044e 2061f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_2_MARGINING_LANE_CNTL 0x0450 2071f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_2_MARGINING_LANE_STATUS 0x0452 2081f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_3_MARGINING_LANE_CNTL 0x0454 2091f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_3_MARGINING_LANE_STATUS 0x0456 2101f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_4_MARGINING_LANE_CNTL 0x0458 2111f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_4_MARGINING_LANE_STATUS 0x045a 2121f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_5_MARGINING_LANE_CNTL 0x045c 2131f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_5_MARGINING_LANE_STATUS 0x045e 2141f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_6_MARGINING_LANE_CNTL 0x0460 2151f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_6_MARGINING_LANE_STATUS 0x0462 2161f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_7_MARGINING_LANE_CNTL 0x0464 2171f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_7_MARGINING_LANE_STATUS 0x0466 2181f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_8_MARGINING_LANE_CNTL 0x0468 2191f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_8_MARGINING_LANE_STATUS 0x046a 2201f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_9_MARGINING_LANE_CNTL 0x046c 2211f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_9_MARGINING_LANE_STATUS 0x046e 2221f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_10_MARGINING_LANE_CNTL 0x0470 2231f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_10_MARGINING_LANE_STATUS 0x0472 2241f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_11_MARGINING_LANE_CNTL 0x0474 2251f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_11_MARGINING_LANE_STATUS 0x0476 2261f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_12_MARGINING_LANE_CNTL 0x0478 2271f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_12_MARGINING_LANE_STATUS 0x047a 2281f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_13_MARGINING_LANE_CNTL 0x047c 2291f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_13_MARGINING_LANE_STATUS 0x047e 2301f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_14_MARGINING_LANE_CNTL 0x0480 2311f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_14_MARGINING_LANE_STATUS 0x0482 2321f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_15_MARGINING_LANE_CNTL 0x0484 2331f902edeSFeifei Xu #define cfgPSWUSCFG0_LANE_15_MARGINING_LANE_STATUS 0x0486 2341f902edeSFeifei Xu 2351f902edeSFeifei Xu 2361f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 2371f902edeSFeifei Xu // base address: 0x0 2381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 2391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 2401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 2411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 2421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 2431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 2441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a 2451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b 2461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c 2471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d 2481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e 2491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f 2501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 2511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 2521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 2531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c 2541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 2551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 2561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c 2571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 2581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 2591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c 2601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d 2611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e 2621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f 2631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 2641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c 2651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 2661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 2671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 2681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 2691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 2701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 2711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c 2721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e 2731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 2741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 2751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 2761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 2771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c 2781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e 2791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 2801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 2811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 2821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098 2831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c 2841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e 2851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 2861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 2871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 2881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 2891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 2901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac 2911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac 2921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 2931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 2941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 2951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 2961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 2971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 2981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 2991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 3001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 3011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 3021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 3031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 3041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 3051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 3061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c 3071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e 3081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 3091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 3101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 3111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c 3121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 3131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 3141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 3151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 3161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 3171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 3181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 3191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 3201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 3211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 3221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 3231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 3241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c 3251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 3261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 3271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 3281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 3291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 3301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 3311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 3321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 3331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 3341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 3351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c 3361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 3371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 3381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 3391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c 3401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 3411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 3421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 3431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c 3441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 3451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 3461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 3471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 3481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c 3491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 3501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 3511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 3521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c 3531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e 3541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 3551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 3561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 3571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 3581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 3591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 3601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 3611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 3621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 3631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 3641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 3651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 3661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 3671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 3681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 3691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 3701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 3711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 3721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 3731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 3741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 3751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 3761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 3771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 3781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 3791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 3801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 3811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 3821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 3831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 3841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 3851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 3861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 3871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 3881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 3891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 3901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 3911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 3921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 3931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 3941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 3951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 3961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 3971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 3981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 3991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc 4001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 4011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 4021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 4031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c 4041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 4051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 4061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 4071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 4081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 4091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c 4101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e 4111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 4121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 4131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 4141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a 4151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c 4161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e 4171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 4181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 4191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 4201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 4211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 4221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 4231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 4241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 4251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 4261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 4271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 4281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 4291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 4301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 4311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 4321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x0374 4331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x0378 4341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 4351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x0404 4361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x0408 4371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST 0x0410 4381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x0414 4391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x0418 4401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x041c 4411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 4421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 4431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 4441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 4451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 4461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 4471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 4481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 4491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 4501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 4511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 4521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 4531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 4541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 4551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 4561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 4571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 4581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 4591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 4601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST 0x0440 4611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x0444 4621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x0446 4631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 4641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x044a 4651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x044c 4661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x044e 4671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 4681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 4691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 4701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 4711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 4721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x045a 4731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x045c 4741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x045e 4751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 4761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 4771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 4781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 4791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 4801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x046a 4811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x046c 4821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x046e 4831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 4841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 4851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 4861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 4871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 4881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x047a 4891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x047c 4901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x047e 4911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 4921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 4931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 4941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 4951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 4961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 4971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 4981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 4991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 5001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 5011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 5021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 5031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 5041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 5051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 5061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 5071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 5081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 5091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 5101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 5111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c 5121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 5131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 5141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 5151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c 5161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 5171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 5181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 5191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c 5201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0530 5211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0534 5221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0538 5231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x053c 5241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0540 5251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0544 5261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0548 5271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x054c 5281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0550 5291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0554 5301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0558 5311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x055c 5321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0560 5331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0564 5341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0568 5351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x056c 5361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0570 5371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0574 5381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x0578 5391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x057c 5401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0580 5411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0584 5421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x0588 5431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x058c 5441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0590 5451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0594 5461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x0598 5471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x059c 5481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a0 5491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a4 5501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05a8 5511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05ac 5521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05b0 5531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05b4 5541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05b8 5551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05bc 5561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05c0 5571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05c4 5581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05c8 5591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05cc 5601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05d0 5611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05e0 5621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05e4 5631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05e8 5641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05ec 5651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x05f0 5661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x05f4 5671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x05f8 5681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x05fc 5691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0600 5701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0610 5711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0614 5721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0618 5731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x061c 5741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0620 5751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0624 5761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0628 5771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x062c 5781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0630 5791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0640 5801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0644 5811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0648 5821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x064c 5831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0650 5841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0654 5851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0658 5861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x065c 5871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0660 5881f902edeSFeifei Xu 5891f902edeSFeifei Xu 5901f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 5911f902edeSFeifei Xu // base address: 0x0 5921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 5931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 5941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 5951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 5961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 5971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 5981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a 5991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b 6001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c 6011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d 6021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e 6031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f 6041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 6051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 6061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 6071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c 6081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 6091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 6101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c 6111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 6121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 6131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c 6141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d 6151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e 6161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f 6171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 6181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c 6191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 6201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 6211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 6221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 6231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 6241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 6251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c 6261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e 6271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 6281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 6291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 6301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 6311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c 6321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e 6331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 6341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 6351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 6361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 6371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c 6381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e 6391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 6401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 6411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 6421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 6431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 6441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac 6451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac 6461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 6471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 6481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 6491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 6501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 6511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 6521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 6531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 6541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 6551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 6561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 6571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 6581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 6591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 6601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c 6611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e 6621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 6631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 6641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 6651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c 6661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 6671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 6681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 6691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 6701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 6711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 6721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 6731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 6741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 6751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 6761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 6771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 6781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c 6791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 6801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 6811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 6821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 6831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 6841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 6851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 6861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 6871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 6881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 6891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c 6901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 6911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 6921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 6931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c 6941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 6951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 6961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 6971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c 6981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 6991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 7001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 7011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 7021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 7031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 7041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 7051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 7061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c 7071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e 7081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 7091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 7101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 7111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 7121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 7131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 7141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 7151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 7161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 7171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 7181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 7191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 7201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 7211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 7221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 7231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 7241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 7251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 7261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 7271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 7281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 7291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 7301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 7311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 7321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 7331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 7341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 7351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 7361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 7371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 7381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 7391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 7401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 7411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 7421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 7431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 7441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 7451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 7461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 7471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 7481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 7491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 7501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 7511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 7521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 7531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc 7541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 7551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 7561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 7571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c 7581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 7591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 7601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 7611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 7621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 7631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c 7641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e 7651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 7661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 7671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 7681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a 7691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c 7701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e 7711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 7721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 7731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 7741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 7751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 7761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 7771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 7781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 7791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 7801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 7811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 7821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 7831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 7841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 7851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 7861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x0374 7871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x0378 7881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x0400 7891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x0404 7901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x0408 7911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST 0x0410 7921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x0414 7931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x0418 7941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x041c 7951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 7961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 7971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 7981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 7991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 8001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 8011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 8021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 8031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 8041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 8051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 8061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 8071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 8081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 8091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 8101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 8111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 8121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 8131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 8141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST 0x0440 8151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x0444 8161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x0446 8171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x0448 8181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x044a 8191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x044c 8201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x044e 8211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x0450 8221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x0452 8231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x0454 8241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x0456 8251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x0458 8261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x045a 8271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x045c 8281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x045e 8291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x0460 8301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x0462 8311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x0464 8321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x0466 8331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x0468 8341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x046a 8351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x046c 8361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x046e 8371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x0470 8381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x0472 8391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x0474 8401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x0476 8411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x0478 8421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x047a 8431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x047c 8441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x047e 8451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x0480 8461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x0482 8471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x0484 8481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x0486 8491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 8501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 8511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 8521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 8531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 8541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 8551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 8561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 8571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 8581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 8591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 8601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 8611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 8621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 8631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 8641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 8651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c 8661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 8671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 8681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 8691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c 8701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 8711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 8721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 8731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c 8741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0530 8751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0534 8761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0538 8771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x053c 8781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0540 8791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0544 8801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0548 8811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x054c 8821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0550 8831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0554 8841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0558 8851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x055c 8861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0560 8871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0564 8881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0568 8891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x056c 8901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0570 8911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0574 8921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x0578 8931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x057c 8941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0580 8951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0584 8961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x0588 8971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x058c 8981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0590 8991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0594 9001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x0598 9011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x059c 9021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a0 9031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a4 9041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05a8 9051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05ac 9061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05b0 9071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05b4 9081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05b8 9091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05bc 9101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05c0 9111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05c4 9121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05c8 9131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05cc 9141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05d0 9151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05e0 9161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05e4 9171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05e8 9181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05ec 9191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x05f0 9201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x05f4 9211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x05f8 9221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x05fc 9231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0600 9241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0610 9251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0614 9261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0618 9271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x061c 9281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0620 9291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0624 9301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0628 9311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x062c 9321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0630 9331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0640 9341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0644 9351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0648 9361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x064c 9371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0650 9381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0654 9391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0658 9401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x065c 9411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0660 9421f902edeSFeifei Xu 9431f902edeSFeifei Xu 9441f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp 9451f902edeSFeifei Xu // base address: 0x0 9461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 9471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 9481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 9491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 9501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 9511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 9521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a 9531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b 9541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c 9551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d 9561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e 9571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f 9581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 9591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 9601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c 9611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e 9621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 9631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 9641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 9651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c 9661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 9671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 9681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c 9691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d 9701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e 9711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 9721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 9731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 9741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 9751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a 9761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c 9771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 9781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 9791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 9801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 9811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a 9821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c 9831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 9841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 9851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c 9861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 9871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 9881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 9891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 9901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a 9911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c 9921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 9931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 9941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 9951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 9961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 9971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 9981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 9991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac 10001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 10011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 10021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 10031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 10041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 10051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c 10061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 10071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 10081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 10091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c 10101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e 10111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 10121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 10131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a 10141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c 10151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 10161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 10171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 10181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 10191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 10201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 10211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 10221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 10231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c 10241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 10251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 10261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 10271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c 10281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 10291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 10301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 10311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 10321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c 10331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 10341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 10351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 10361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 10371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 10381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 10391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 10401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 10411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 10421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 10431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 10441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 10451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 10461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 10471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 10481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 10491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 10501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 10511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 10521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 10531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 10541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 10551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 10561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 10571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 0x0400 10581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 0x0404 10591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 0x0408 10601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST 0x0410 10611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 0x0414 10621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 0x0418 10631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 0x041c 10641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 10651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 10661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 10671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 10681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 10691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 10701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 10711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 10721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 10731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 10741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 10751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 10761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 10771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 10781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 10791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 10801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 10811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 10821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 10831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST 0x0440 10841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 0x0444 10851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 0x0446 10861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 0x0448 10871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 0x044a 10881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 0x044c 10891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 0x044e 10901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 0x0450 10911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 0x0452 10921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 0x0454 10931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 0x0456 10941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 0x0458 10951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 0x045a 10961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 0x045c 10971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 0x045e 10981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 0x0460 10991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 0x0462 11001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 0x0464 11011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 0x0466 11021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 0x0468 11031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 0x046a 11041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 0x046c 11051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 0x046e 11061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 0x0470 11071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 0x0472 11081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 11091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 0x0476 11101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 0x0478 11111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 0x047a 11121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 0x047c 11131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 0x047e 11141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 0x0480 11151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 0x0482 11161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 0x0484 11171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 0x0486 11181f902edeSFeifei Xu 11191f902edeSFeifei Xu 11201f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 11211f902edeSFeifei Xu // base address: 0x0 11221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 11231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 11241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 11251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 11261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 11271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 11281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a 11291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b 11301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c 11311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d 11321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e 11331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f 11341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 11351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 11361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 11371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c 11381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 11391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 11401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c 11411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 11421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 11431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c 11441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d 11451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 11461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 11471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 11481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c 11491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e 11501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 11511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 11521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 11531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 11541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c 11551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e 11561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 11571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 11581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 11591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098 11601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c 11611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e 11621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 11631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 11641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 11651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 11661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 11671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac 11681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac 11691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 11701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 11711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 11721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 11731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 11741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 11751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 11761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 11771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 11781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 11791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 11801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 11811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 11821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 11831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 11841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 11851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 11861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 11871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c 11881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 11891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 11901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 11911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 11921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 11931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 11941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 11951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 11961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 11971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 11981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 11991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c 12001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e 12011f902edeSFeifei Xu 12021f902edeSFeifei Xu 12031f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 12041f902edeSFeifei Xu // base address: 0x0 12051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 12061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 12071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 12081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 12091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 12101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 12111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a 12121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b 12131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c 12141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d 12151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e 12161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f 12171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 12181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 12191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 12201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c 12211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 12221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 12231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c 12241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 12251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 12261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c 12271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d 12281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 12291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 12301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 12311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c 12321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e 12331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 12341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 12351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 12361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 12371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c 12381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e 12391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 12401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 12411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 12421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098 12431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c 12441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e 12451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 12461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 12471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 12481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 12491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 12501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac 12511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac 12521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 12531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 12541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 12551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 12561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 12571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 12581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 12591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 12601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 12611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 12621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 12631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 12641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 12651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 12661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 12671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 12681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 12691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 12701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c 12711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 12721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 12731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 12741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 12751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 12761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 12771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 12781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 12791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 12801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 12811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 12821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c 12831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e 12841f902edeSFeifei Xu 12851f902edeSFeifei Xu 12861f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 12871f902edeSFeifei Xu // base address: 0x0 12881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 12891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 12901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 12911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 12921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 12931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 12941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a 12951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b 12961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c 12971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d 12981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e 12991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f 13001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 13011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 13021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 13031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c 13041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 13051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 13061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c 13071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 13081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 13091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c 13101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d 13111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 13121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 13131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 13141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c 13151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e 13161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 13171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 13181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 13191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 13201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c 13211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e 13221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 13231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 13241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 13251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098 13261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c 13271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e 13281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 13291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 13301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 13311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 13321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 13331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac 13341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac 13351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 13361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 13371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 13381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 13391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 13401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 13411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 13421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 13431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 13441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 13451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 13461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 13471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 13481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 13491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 13501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 13511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 13521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 13531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c 13541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 13551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 13561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 13571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 13581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 13591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 13601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 13611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 13621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 13631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 13641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 13651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c 13661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e 13671f902edeSFeifei Xu 13681f902edeSFeifei Xu 13691f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 13701f902edeSFeifei Xu // base address: 0x0 13711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 13721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 13731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 13741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 13751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 13761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 13771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a 13781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b 13791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c 13801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d 13811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e 13821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f 13831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 13841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 13851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 13861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c 13871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 13881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 13891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c 13901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 13911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 13921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c 13931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d 13941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 13951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 13961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 13971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c 13981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e 13991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 14001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 14011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 14021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 14031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c 14041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e 14051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 14061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 14071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 14081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098 14091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c 14101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e 14111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 14121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 14131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 14141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 14151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 14161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac 14171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac 14181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 14191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 14201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 14211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 14221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 14231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 14241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 14251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 14261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 14271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 14281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c 14291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 14301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 14311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 14321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 14331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 14341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 14351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 14361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c 14371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 14381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 14391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 14401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 14411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c 14421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 14431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 14441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 14451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 14461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 14471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 14481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c 14491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e 14501f902edeSFeifei Xu 14511f902edeSFeifei Xu 14521f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 14531f902edeSFeifei Xu // base address: 0x0 14541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 14551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 14561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 14571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 14581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 14591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 14601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a 14611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b 14621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c 14631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d 14641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e 14651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f 14661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 14671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 14681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 14691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c 14701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 14711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 14721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c 14731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 14741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 14751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c 14761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d 14771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 14781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 14791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 14801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c 14811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e 14821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 14831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 14841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 14851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 14861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c 14871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e 14881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 14891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 14901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 14911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098 14921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c 14931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e 14941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 14951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 14961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 14971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 14981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 14991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac 15001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac 15011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 15021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 15031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 15041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 15051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 15061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 15071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 15081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 15111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c 15121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 15141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 15151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 15161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 15171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 15181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 15191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c 15201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 15211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 15221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 15231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 15241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c 15251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 15261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 15271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 15281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 15291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 15301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 15311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c 15321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e 15331f902edeSFeifei Xu 15341f902edeSFeifei Xu 15351f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 15361f902edeSFeifei Xu // base address: 0x0 15371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 15381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 15391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 15401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 15411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 15421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 15431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a 15441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b 15451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c 15461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d 15471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e 15481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f 15491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 15501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 15511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 15521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c 15531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 15541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 15551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c 15561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 15571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 15581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c 15591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d 15601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 15611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 15621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 15631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c 15641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e 15651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 15661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 15671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 15681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 15691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c 15701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e 15711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 15721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 15731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 15741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098 15751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c 15761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e 15771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 15781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 15791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 15801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 15811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 15821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac 15831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac 15841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 15851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 15861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 15871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 15881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 15891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 15901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 15911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 15921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 15931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 15941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c 15951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 15961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 15971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 15981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 15991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 16001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 16011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 16021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c 16031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 16041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 16051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 16061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 16071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c 16081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 16091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 16101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 16111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 16121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 16131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 16141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c 16151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e 16161f902edeSFeifei Xu 16171f902edeSFeifei Xu 16181f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 16191f902edeSFeifei Xu // base address: 0x0 16201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 16211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 16221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 16231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 16241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 16251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 16261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a 16271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b 16281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c 16291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d 16301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e 16311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f 16321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 16331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 16341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 16351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c 16361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 16371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 16381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c 16391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 16401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 16411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c 16421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d 16431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 16441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 16451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 16461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c 16471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e 16481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 16491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 16501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 16511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 16521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c 16531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e 16541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 16551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 16561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 16571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098 16581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c 16591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e 16601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 16611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 16621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 16631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 16641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 16651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac 16661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac 16671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 16681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 16691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 16701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 16711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 16721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 16731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 16741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 16751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 16761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 16771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c 16781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 16791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 16801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 16811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 16821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 16831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 16841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 16851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c 16861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 16871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 16881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 16891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 16901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c 16911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 16921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 16931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 16941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 16951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 16961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 16971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c 16981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e 16991f902edeSFeifei Xu 17001f902edeSFeifei Xu 17011f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 17021f902edeSFeifei Xu // base address: 0x0 17031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 17041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 17051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 17061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 17071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 17081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 17091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a 17101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b 17111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c 17121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d 17131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e 17141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f 17151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 17161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 17171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 17181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c 17191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 17201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 17211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c 17221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 17231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 17241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c 17251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d 17261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 17271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 17281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 17291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c 17301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e 17311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 17321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 17331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 17341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 17351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c 17361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e 17371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 17381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 17391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 17401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098 17411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c 17421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e 17431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 17441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 17451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 17461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 17471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 17481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac 17491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac 17501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 17511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 17521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 17531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 17541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 17551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 17561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 17571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 17581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 17591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 17601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c 17611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 17621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 17631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 17641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 17651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 17661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 17671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 17681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c 17691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 17701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 17711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 17721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 17731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c 17741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 17751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 17761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 17771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 17781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 17791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 17801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c 17811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e 17821f902edeSFeifei Xu 17831f902edeSFeifei Xu 17841f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 17851f902edeSFeifei Xu // base address: 0x0 17861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 17871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 17881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 17891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 17901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 17911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 17921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a 17931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b 17941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c 17951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d 17961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e 17971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f 17981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 17991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 18001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 18011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c 18021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 18031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 18041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c 18051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 18061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 18071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c 18081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d 18091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 18101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 18111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 18121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c 18131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e 18141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 18151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 18161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 18171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 18181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c 18191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e 18201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 18211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 18221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 18231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098 18241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c 18251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e 18261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 18271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 18281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 18291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 18301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 18311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac 18321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac 18331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 18341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 18351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 18361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 18371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 18381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 18391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 18401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 18411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 18421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 18431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c 18441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 18451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 18461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 18471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 18481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 18491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 18501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 18511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c 18521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 18531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 18541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 18551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 18561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c 18571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 18581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 18591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 18601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 18611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 18621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 18631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c 18641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e 18651f902edeSFeifei Xu 18661f902edeSFeifei Xu 18671f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 18681f902edeSFeifei Xu // base address: 0x0 18691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 18701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 18711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 18721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 18731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 18741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 18751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a 18761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b 18771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c 18781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d 18791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e 18801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f 18811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 18821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 18831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 18841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c 18851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 18861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 18871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c 18881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 18891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 18901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c 18911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d 18921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 18931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 18941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 18951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c 18961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e 18971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 18981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 18991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 19001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 19011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c 19021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e 19031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 19041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 19051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 19061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098 19071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c 19081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e 19091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 19101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 19111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 19121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 19131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 19141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac 19151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac 19161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 19171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 19181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 19191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 19201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 19211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 19221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 19231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 19241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 19251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 19261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c 19271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 19281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 19291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 19301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 19311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 19321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 19331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 19341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c 19351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 19361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 19371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 19381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 19391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c 19401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 19411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 19421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 19431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 19441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 19451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 19461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c 19471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e 19481f902edeSFeifei Xu 19491f902edeSFeifei Xu 19501f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 19511f902edeSFeifei Xu // base address: 0x0 19521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 19531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 19541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 19551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 19561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 19571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 19581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a 19591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b 19601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c 19611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d 19621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e 19631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f 19641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 19651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 19661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 19671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c 19681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 19691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 19701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c 19711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 19721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 19731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c 19741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d 19751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 19761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 19771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 19781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c 19791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e 19801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 19811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 19821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 19831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 19841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c 19851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e 19861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 19871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 19881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 19891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098 19901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c 19911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e 19921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 19931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 19941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 19951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 19961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 19971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac 19981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac 19991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 20001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 20011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 20021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 20031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 20041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 20051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 20061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 20071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 20081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 20091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c 20101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 20111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 20121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 20131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 20141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 20151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 20161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 20171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c 20181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 20191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 20201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 20211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 20221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c 20231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 20241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 20251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 20261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 20271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 20281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 20291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c 20301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e 20311f902edeSFeifei Xu 20321f902edeSFeifei Xu 20331f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 20341f902edeSFeifei Xu // base address: 0x0 20351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 20361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 20371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 20381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 20391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 20401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 20411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a 20421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b 20431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c 20441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d 20451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e 20461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f 20471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 20481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 20491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 20501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c 20511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 20521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 20531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c 20541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 20551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 20561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c 20571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d 20581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 20591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 20601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 20611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c 20621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e 20631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 20641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 20651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 20661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 20671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c 20681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e 20691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 20701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 20711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 20721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098 20731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c 20741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e 20751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 20761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 20771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 20781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 20791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 20801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac 20811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac 20821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 20831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 20841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 20851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 20861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 20871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 20881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 20891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 20901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 20911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 20921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c 20931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 20941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 20951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 20961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 20971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 20981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 20991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 21001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c 21011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 21021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 21031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 21041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 21051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c 21061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 21071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 21081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 21091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 21101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 21111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 21121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c 21131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e 21141f902edeSFeifei Xu 21151f902edeSFeifei Xu 21161f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 21171f902edeSFeifei Xu // base address: 0x0 21181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 21191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 21201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 21211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 21221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 21231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 21241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a 21251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b 21261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c 21271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d 21281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e 21291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f 21301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 21311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 21321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 21331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c 21341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 21351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 21361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c 21371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 21381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 21391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c 21401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d 21411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 21421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 21431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 21441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c 21451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e 21461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 21471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 21481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 21491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 21501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c 21511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e 21521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 21531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 21541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 21551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098 21561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c 21571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e 21581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 21591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 21601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 21611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 21621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 21631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac 21641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac 21651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 21661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 21671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 21681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 21691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 21701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 21711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 21721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 21731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 21741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 21751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c 21761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 21771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 21781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 21791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 21801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 21811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 21821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 21831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c 21841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 21851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 21861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 21871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 21881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c 21891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 21901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 21911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 21921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 21931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 21941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 21951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c 21961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e 21971f902edeSFeifei Xu 21981f902edeSFeifei Xu 21991f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 22001f902edeSFeifei Xu // base address: 0x0 22011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 22021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 22031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 22041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 22051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 22061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 22071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a 22081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b 22091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c 22101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d 22111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e 22121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f 22131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 22141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 22151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 22161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c 22171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 22181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 22191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c 22201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 22211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 22221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c 22231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d 22241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 22251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 22261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 22271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c 22281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e 22291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 22301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 22311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 22321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 22331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c 22341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e 22351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 22361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 22371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 22381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098 22391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c 22401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e 22411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 22421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 22431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 22441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 22451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 22461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac 22471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac 22481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 22491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 22501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 22511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 22521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 22531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 22541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 22551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 22561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 22571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 22581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c 22591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 22601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 22611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 22621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 22631f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 22641f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 22651f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 22661f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c 22671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 22681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 22691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 22701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 22711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c 22721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 22731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 22741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 22751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 22761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 22771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 22781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c 22791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e 22801f902edeSFeifei Xu 22811f902edeSFeifei Xu 22821f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 22831f902edeSFeifei Xu // base address: 0x0 22841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 22851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 22861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 22871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 22881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 22891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 22901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a 22911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b 22921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c 22931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d 22941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e 22951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f 22961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 22971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 22981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 22991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c 23001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 23011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 23021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c 23031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 23041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 23051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c 23061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d 23071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 23081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 23091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 23101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c 23111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e 23121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 23131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 23141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 23151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 23161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c 23171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e 23181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 23191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 23201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 23211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098 23221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c 23231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e 23241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 23251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 23261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 23271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 23281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 23291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac 23301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac 23311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 23321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 23331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 23341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 23351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 23361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 23371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 23381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 23391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 23401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 23411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c 23421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 23431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 23441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 23451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 23461f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 23471f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 23481f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 23491f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c 23501f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 23511f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 23521f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 23531f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 23541f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c 23551f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 23561f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 23571f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 23581f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 23591f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 23601f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 23611f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c 23621f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e 23631f902edeSFeifei Xu 23641f902edeSFeifei Xu 23651f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 23661f902edeSFeifei Xu // base address: 0x0 23671f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 23681f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 23691f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 23701f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 23711f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 23721f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 23731f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a 23741f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b 23751f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c 23761f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d 23771f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e 23781f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f 23791f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 23801f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 23811f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 23821f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c 23831f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 23841f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 23851f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c 23861f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 23871f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 23881f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c 23891f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d 23901f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 23911f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 23921f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 23931f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c 23941f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e 23951f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 23961f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 23971f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 23981f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 23991f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c 24001f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e 24011f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 24021f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 24031f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 24041f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098 24051f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c 24061f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e 24071f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 24081f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 24091f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 24101f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 24111f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 24121f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac 24131f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac 24141f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 24151f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 24161f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 24171f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 24181f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 24191f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 24201f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 24211f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 24221f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 24231f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 24241f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c 24251f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 24261f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 24271f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 24281f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 24291f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 24301f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 24311f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 24321f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c 24331f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 24341f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 24351f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 24361f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 24371f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c 24381f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 24391f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 24401f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 24411f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 24421f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 24431f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 24441f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c 24451f902edeSFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e 24461f902edeSFeifei Xu 24471f902edeSFeifei Xu 24481f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 24491f902edeSFeifei Xu // base address: 0x0 24501f902edeSFeifei Xu #define mmMM_INDEX 0x0000 24511f902edeSFeifei Xu #define mmMM_INDEX_BASE_IDX 0 24521f902edeSFeifei Xu #define mmMM_DATA 0x0001 24531f902edeSFeifei Xu #define mmMM_DATA_BASE_IDX 0 24541f902edeSFeifei Xu #define mmMM_INDEX_HI 0x0006 24551f902edeSFeifei Xu #define mmMM_INDEX_HI_BASE_IDX 0 24561f902edeSFeifei Xu 24571f902edeSFeifei Xu 24581f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_SYSDEC 24591f902edeSFeifei Xu // base address: 0x0 24601f902edeSFeifei Xu #define mmSYSHUB_INDEX_OVLP 0x0008 24611f902edeSFeifei Xu #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 24621f902edeSFeifei Xu #define mmSYSHUB_DATA_OVLP 0x0009 24631f902edeSFeifei Xu #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 24641f902edeSFeifei Xu #define mmPCIE_INDEX 0x000c 24651f902edeSFeifei Xu #define mmPCIE_INDEX_BASE_IDX 0 24661f902edeSFeifei Xu #define mmPCIE_DATA 0x000d 24671f902edeSFeifei Xu #define mmPCIE_DATA_BASE_IDX 0 24681f902edeSFeifei Xu #define mmPCIE_INDEX2 0x000e 24691f902edeSFeifei Xu #define mmPCIE_INDEX2_BASE_IDX 0 24701f902edeSFeifei Xu #define mmPCIE_DATA2 0x000f 24711f902edeSFeifei Xu #define mmPCIE_DATA2_BASE_IDX 0 24721f902edeSFeifei Xu #define mmSBIOS_SCRATCH_0 0x0034 24731f902edeSFeifei Xu #define mmSBIOS_SCRATCH_0_BASE_IDX 1 24741f902edeSFeifei Xu #define mmSBIOS_SCRATCH_1 0x0035 24751f902edeSFeifei Xu #define mmSBIOS_SCRATCH_1_BASE_IDX 1 24761f902edeSFeifei Xu #define mmSBIOS_SCRATCH_2 0x0036 24771f902edeSFeifei Xu #define mmSBIOS_SCRATCH_2_BASE_IDX 1 24781f902edeSFeifei Xu #define mmSBIOS_SCRATCH_3 0x0037 24791f902edeSFeifei Xu #define mmSBIOS_SCRATCH_3_BASE_IDX 1 24801f902edeSFeifei Xu #define mmBIOS_SCRATCH_0 0x0038 24811f902edeSFeifei Xu #define mmBIOS_SCRATCH_0_BASE_IDX 1 24821f902edeSFeifei Xu #define mmBIOS_SCRATCH_1 0x0039 24831f902edeSFeifei Xu #define mmBIOS_SCRATCH_1_BASE_IDX 1 24841f902edeSFeifei Xu #define mmBIOS_SCRATCH_2 0x003a 24851f902edeSFeifei Xu #define mmBIOS_SCRATCH_2_BASE_IDX 1 24861f902edeSFeifei Xu #define mmBIOS_SCRATCH_3 0x003b 24871f902edeSFeifei Xu #define mmBIOS_SCRATCH_3_BASE_IDX 1 24881f902edeSFeifei Xu #define mmBIOS_SCRATCH_4 0x003c 24891f902edeSFeifei Xu #define mmBIOS_SCRATCH_4_BASE_IDX 1 24901f902edeSFeifei Xu #define mmBIOS_SCRATCH_5 0x003d 24911f902edeSFeifei Xu #define mmBIOS_SCRATCH_5_BASE_IDX 1 24921f902edeSFeifei Xu #define mmBIOS_SCRATCH_6 0x003e 24931f902edeSFeifei Xu #define mmBIOS_SCRATCH_6_BASE_IDX 1 24941f902edeSFeifei Xu #define mmBIOS_SCRATCH_7 0x003f 24951f902edeSFeifei Xu #define mmBIOS_SCRATCH_7_BASE_IDX 1 24961f902edeSFeifei Xu #define mmBIOS_SCRATCH_8 0x0040 24971f902edeSFeifei Xu #define mmBIOS_SCRATCH_8_BASE_IDX 1 24981f902edeSFeifei Xu #define mmBIOS_SCRATCH_9 0x0041 24991f902edeSFeifei Xu #define mmBIOS_SCRATCH_9_BASE_IDX 1 25001f902edeSFeifei Xu #define mmBIOS_SCRATCH_10 0x0042 25011f902edeSFeifei Xu #define mmBIOS_SCRATCH_10_BASE_IDX 1 25021f902edeSFeifei Xu #define mmBIOS_SCRATCH_11 0x0043 25031f902edeSFeifei Xu #define mmBIOS_SCRATCH_11_BASE_IDX 1 25041f902edeSFeifei Xu #define mmBIOS_SCRATCH_12 0x0044 25051f902edeSFeifei Xu #define mmBIOS_SCRATCH_12_BASE_IDX 1 25061f902edeSFeifei Xu #define mmBIOS_SCRATCH_13 0x0045 25071f902edeSFeifei Xu #define mmBIOS_SCRATCH_13_BASE_IDX 1 25081f902edeSFeifei Xu #define mmBIOS_SCRATCH_14 0x0046 25091f902edeSFeifei Xu #define mmBIOS_SCRATCH_14_BASE_IDX 1 25101f902edeSFeifei Xu #define mmBIOS_SCRATCH_15 0x0047 25111f902edeSFeifei Xu #define mmBIOS_SCRATCH_15_BASE_IDX 1 25121f902edeSFeifei Xu #define mmBIF_RLC_INTR_CNTL 0x004c 25131f902edeSFeifei Xu #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 25141f902edeSFeifei Xu #define mmBIF_VCE_INTR_CNTL 0x004d 25151f902edeSFeifei Xu #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 25161f902edeSFeifei Xu #define mmBIF_UVD_INTR_CNTL 0x004e 25171f902edeSFeifei Xu #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 25181f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0 0x006c 25191f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 25201f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 25211f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 25221f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1 0x006e 25231f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 25241f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 25251f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 25261f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 25271f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 25281f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 25291f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 25301f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 25311f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 25321f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 25331f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 25341f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 25351f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 25361f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 25371f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 25381f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 25391f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 25401f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 25411f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 25421f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 25431f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 25441f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 25451f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 25461f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7 0x007a 25471f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 25481f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 25491f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 25501f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL 0x007c 25511f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 25521f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d 25531f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 25541f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e 25551f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 25561f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 25571f902edeSFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 25581f902edeSFeifei Xu 25591f902edeSFeifei Xu 25601f902edeSFeifei Xu // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec 25611f902edeSFeifei Xu // base address: 0x0 25621f902edeSFeifei Xu #define mmSYSHUB_INDEX 0x0008 25631f902edeSFeifei Xu #define mmSYSHUB_INDEX_BASE_IDX 0 25641f902edeSFeifei Xu #define mmSYSHUB_DATA 0x0009 25651f902edeSFeifei Xu #define mmSYSHUB_DATA_BASE_IDX 0 25661f902edeSFeifei Xu 25671f902edeSFeifei Xu 25681f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 25691f902edeSFeifei Xu // base address: 0x0 2570f5d9e9b9SJim Qu #define mmRCC_BIF_STRAP0 0x0000 2571f5d9e9b9SJim Qu #define mmRCC_BIF_STRAP0_BASE_IDX 2 25721f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0 0x0011 25731f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 25741f902edeSFeifei Xu 25751f902edeSFeifei Xu 25761f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 25771f902edeSFeifei Xu // base address: 0x0 25781f902edeSFeifei Xu #define mmEP_PCIE_SCRATCH 0x0025 25791f902edeSFeifei Xu #define mmEP_PCIE_SCRATCH_BASE_IDX 2 25801f902edeSFeifei Xu #define mmEP_PCIE_CNTL 0x0027 25811f902edeSFeifei Xu #define mmEP_PCIE_CNTL_BASE_IDX 2 25821f902edeSFeifei Xu #define mmEP_PCIE_INT_CNTL 0x0028 25831f902edeSFeifei Xu #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 25841f902edeSFeifei Xu #define mmEP_PCIE_INT_STATUS 0x0029 25851f902edeSFeifei Xu #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 25861f902edeSFeifei Xu #define mmEP_PCIE_RX_CNTL2 0x002a 25871f902edeSFeifei Xu #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 25881f902edeSFeifei Xu #define mmEP_PCIE_BUS_CNTL 0x002b 25891f902edeSFeifei Xu #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 25901f902edeSFeifei Xu #define mmEP_PCIE_CFG_CNTL 0x002c 25911f902edeSFeifei Xu #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 25921f902edeSFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL 0x002e 25931f902edeSFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 25941f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002f 25951f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 25961f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002f 25971f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 25981f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002f 25991f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 26001f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002f 26011f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 26021f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0030 26031f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 26041f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0030 26051f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 26061f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0030 26071f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 26081f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0030 26091f902edeSFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 26101f902edeSFeifei Xu #define mmEP_PCIE_F0_DPA_CAP 0x0034 26111f902edeSFeifei Xu #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 26121f902edeSFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0035 26131f902edeSFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 26141f902edeSFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL 0x0035 26151f902edeSFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 26161f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0035 26171f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 26181f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0036 26191f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 26201f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0036 26211f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 26221f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0036 26231f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 26241f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0036 26251f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 26261f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0037 26271f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 26281f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0037 26291f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 26301f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0037 26311f902edeSFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 26321f902edeSFeifei Xu #define mmEP_PCIE_PME_CONTROL 0x0037 26331f902edeSFeifei Xu #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 26341f902edeSFeifei Xu #define mmEP_PCIEP_RESERVED 0x0038 26351f902edeSFeifei Xu #define mmEP_PCIEP_RESERVED_BASE_IDX 2 26361f902edeSFeifei Xu #define mmEP_PCIE_TX_CNTL 0x003a 26371f902edeSFeifei Xu #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 26381f902edeSFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID 0x003b 26391f902edeSFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 26401f902edeSFeifei Xu #define mmEP_PCIE_ERR_CNTL 0x003c 26411f902edeSFeifei Xu #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 26421f902edeSFeifei Xu #define mmEP_PCIE_RX_CNTL 0x003d 26431f902edeSFeifei Xu #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 26441f902edeSFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL 0x003e 26451f902edeSFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 26461f902edeSFeifei Xu 26471f902edeSFeifei Xu 26481f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 26491f902edeSFeifei Xu // base address: 0x0 26501f902edeSFeifei Xu #define mmDN_PCIE_RESERVED 0x0040 26511f902edeSFeifei Xu #define mmDN_PCIE_RESERVED_BASE_IDX 2 26521f902edeSFeifei Xu #define mmDN_PCIE_SCRATCH 0x0041 26531f902edeSFeifei Xu #define mmDN_PCIE_SCRATCH_BASE_IDX 2 26541f902edeSFeifei Xu #define mmDN_PCIE_CNTL 0x0043 26551f902edeSFeifei Xu #define mmDN_PCIE_CNTL_BASE_IDX 2 26561f902edeSFeifei Xu #define mmDN_PCIE_CONFIG_CNTL 0x0044 26571f902edeSFeifei Xu #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 26581f902edeSFeifei Xu #define mmDN_PCIE_RX_CNTL2 0x0045 26591f902edeSFeifei Xu #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 26601f902edeSFeifei Xu #define mmDN_PCIE_BUS_CNTL 0x0046 26611f902edeSFeifei Xu #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 26621f902edeSFeifei Xu #define mmDN_PCIE_CFG_CNTL 0x0047 26631f902edeSFeifei Xu #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 26641f902edeSFeifei Xu 26651f902edeSFeifei Xu 26661f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 26671f902edeSFeifei Xu // base address: 0x0 26681f902edeSFeifei Xu #define mmPCIE_ERR_CNTL 0x004f 26691f902edeSFeifei Xu #define mmPCIE_ERR_CNTL_BASE_IDX 2 26701f902edeSFeifei Xu #define mmPCIE_RX_CNTL 0x0050 26711f902edeSFeifei Xu #define mmPCIE_RX_CNTL_BASE_IDX 2 26721f902edeSFeifei Xu #define mmPCIE_LC_SPEED_CNTL 0x0051 26731f902edeSFeifei Xu #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 26741f902edeSFeifei Xu #define mmPCIE_LC_CNTL2 0x0052 26751f902edeSFeifei Xu #define mmPCIE_LC_CNTL2_BASE_IDX 2 26761f902edeSFeifei Xu #define mmLTR_MSG_INFO_FROM_EP 0x0054 26771f902edeSFeifei Xu #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 26781f902edeSFeifei Xu 26791f902edeSFeifei Xu 26801f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 26811f902edeSFeifei Xu // base address: 0x3480 26821f902edeSFeifei Xu #define mmRCC_ERR_LOG 0x0085 26831f902edeSFeifei Xu #define mmRCC_ERR_LOG_BASE_IDX 2 26841f902edeSFeifei Xu #define mmRCC_DOORBELL_APER_EN 0x00c0 26851f902edeSFeifei Xu #define mmRCC_DOORBELL_APER_EN_BASE_IDX 2 26861f902edeSFeifei Xu #define mmRCC_CONFIG_MEMSIZE 0x00c3 26871f902edeSFeifei Xu #define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2 26881f902edeSFeifei Xu #define mmRCC_CONFIG_RESERVED 0x00c4 26891f902edeSFeifei Xu #define mmRCC_CONFIG_RESERVED_BASE_IDX 2 2690*3aa0115dSMonk Liu #ifndef mmRCC_IOV_FUNC_IDENTIFIER 26911f902edeSFeifei Xu #define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5 26921f902edeSFeifei Xu #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2693*3aa0115dSMonk Liu #endif 26941f902edeSFeifei Xu 26951f902edeSFeifei Xu 26961f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 26971f902edeSFeifei Xu // base address: 0x0 26981f902edeSFeifei Xu #define mmRCC_ERR_INT_CNTL 0x0086 26991f902edeSFeifei Xu #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 27001f902edeSFeifei Xu #define mmRCC_BACO_CNTL_MISC 0x0087 27011f902edeSFeifei Xu #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 27021f902edeSFeifei Xu #define mmRCC_RESET_EN 0x0088 27031f902edeSFeifei Xu #define mmRCC_RESET_EN_BASE_IDX 2 27041f902edeSFeifei Xu #define mmRCC_VDM_SUPPORT 0x0089 27051f902edeSFeifei Xu #define mmRCC_VDM_SUPPORT_BASE_IDX 2 27061f902edeSFeifei Xu #define mmRCC_MARGIN_PARAM_CNTL0 0x008a 27071f902edeSFeifei Xu #define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 27081f902edeSFeifei Xu #define mmRCC_MARGIN_PARAM_CNTL1 0x008b 27091f902edeSFeifei Xu #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 27101f902edeSFeifei Xu #define mmRCC_PEER_REG_RANGE0 0x00be 27111f902edeSFeifei Xu #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 27121f902edeSFeifei Xu #define mmRCC_PEER_REG_RANGE1 0x00bf 27131f902edeSFeifei Xu #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 27141f902edeSFeifei Xu #define mmRCC_BUS_CNTL 0x00c1 27151f902edeSFeifei Xu #define mmRCC_BUS_CNTL_BASE_IDX 2 27161f902edeSFeifei Xu #define mmRCC_CONFIG_CNTL 0x00c2 27171f902edeSFeifei Xu #define mmRCC_CONFIG_CNTL_BASE_IDX 2 27181f902edeSFeifei Xu #define mmRCC_CONFIG_F0_BASE 0x00c6 27191f902edeSFeifei Xu #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 27201f902edeSFeifei Xu #define mmRCC_CONFIG_APER_SIZE 0x00c7 27211f902edeSFeifei Xu #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 27221f902edeSFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 27231f902edeSFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 27241f902edeSFeifei Xu #define mmRCC_XDMA_LO 0x00c9 27251f902edeSFeifei Xu #define mmRCC_XDMA_LO_BASE_IDX 2 27261f902edeSFeifei Xu #define mmRCC_XDMA_HI 0x00ca 27271f902edeSFeifei Xu #define mmRCC_XDMA_HI_BASE_IDX 2 27281f902edeSFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC 0x00cb 27291f902edeSFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 27301f902edeSFeifei Xu #define mmRCC_BUSNUM_CNTL1 0x00cc 27311f902edeSFeifei Xu #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 27321f902edeSFeifei Xu #define mmRCC_BUSNUM_LIST0 0x00cd 27331f902edeSFeifei Xu #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 27341f902edeSFeifei Xu #define mmRCC_BUSNUM_LIST1 0x00ce 27351f902edeSFeifei Xu #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 27361f902edeSFeifei Xu #define mmRCC_BUSNUM_CNTL2 0x00cf 27371f902edeSFeifei Xu #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 27381f902edeSFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 27391f902edeSFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 27401f902edeSFeifei Xu #define mmRCC_HOST_BUSNUM 0x00d1 27411f902edeSFeifei Xu #define mmRCC_HOST_BUSNUM_BASE_IDX 2 27421f902edeSFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 27431f902edeSFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 27441f902edeSFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 27451f902edeSFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 27461f902edeSFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 27471f902edeSFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 27481f902edeSFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 27491f902edeSFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 27501f902edeSFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 27511f902edeSFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 27521f902edeSFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 27531f902edeSFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 27541f902edeSFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 27551f902edeSFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 27561f902edeSFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 27571f902edeSFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 27581f902edeSFeifei Xu #define mmRCC_CMN_LINK_CNTL 0x00de 27591f902edeSFeifei Xu #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 27601f902edeSFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE 0x00df 27611f902edeSFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 27621f902edeSFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 27631f902edeSFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 27641f902edeSFeifei Xu #define mmRCC_MH_ARB_CNTL 0x00e1 27651f902edeSFeifei Xu #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 27661f902edeSFeifei Xu 27671f902edeSFeifei Xu 27681f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 27691f902edeSFeifei Xu // base address: 0x0 27701f902edeSFeifei Xu #define mmBIF_MM_INDACCESS_CNTL 0x00e6 27711f902edeSFeifei Xu #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 27721f902edeSFeifei Xu #define mmBUS_CNTL 0x00e7 27731f902edeSFeifei Xu #define mmBUS_CNTL_BASE_IDX 2 27741f902edeSFeifei Xu #define mmBIF_SCRATCH0 0x00e8 27751f902edeSFeifei Xu #define mmBIF_SCRATCH0_BASE_IDX 2 27761f902edeSFeifei Xu #define mmBIF_SCRATCH1 0x00e9 27771f902edeSFeifei Xu #define mmBIF_SCRATCH1_BASE_IDX 2 27781f902edeSFeifei Xu #define mmBX_RESET_EN 0x00ed 27791f902edeSFeifei Xu #define mmBX_RESET_EN_BASE_IDX 2 27801f902edeSFeifei Xu #define mmMM_CFGREGS_CNTL 0x00ee 27811f902edeSFeifei Xu #define mmMM_CFGREGS_CNTL_BASE_IDX 2 27821f902edeSFeifei Xu #define mmBX_RESET_CNTL 0x00f0 27831f902edeSFeifei Xu #define mmBX_RESET_CNTL_BASE_IDX 2 27841f902edeSFeifei Xu #define mmINTERRUPT_CNTL 0x00f1 27851f902edeSFeifei Xu #define mmINTERRUPT_CNTL_BASE_IDX 2 27861f902edeSFeifei Xu #define mmINTERRUPT_CNTL2 0x00f2 27871f902edeSFeifei Xu #define mmINTERRUPT_CNTL2_BASE_IDX 2 27881f902edeSFeifei Xu #define mmCLKREQB_PAD_CNTL 0x00f8 27891f902edeSFeifei Xu #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 27901f902edeSFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC 0x00fb 27911f902edeSFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 27921f902edeSFeifei Xu #define mmBIF_DOORBELL_CNTL 0x00fc 27931f902edeSFeifei Xu #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 27941f902edeSFeifei Xu #define mmBIF_DOORBELL_INT_CNTL 0x00fd 27951f902edeSFeifei Xu #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 27961f902edeSFeifei Xu #define mmBIF_FB_EN 0x00ff 27971f902edeSFeifei Xu #define mmBIF_FB_EN_BASE_IDX 2 2798fc098fb4SHawking Zhang #define mmBIF_INTR_CNTL 0x0100 2799fc098fb4SHawking Zhang #define mmBIF_INTR_CNTL_BASE_IDX 2 28001f902edeSFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF 0x0109 28011f902edeSFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 28021f902edeSFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF 0x010a 28031f902edeSFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 28041f902edeSFeifei Xu #define mmBACO_CNTL 0x010b 28051f902edeSFeifei Xu #define mmBACO_CNTL_BASE_IDX 2 28061f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIME0 0x010c 28071f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 28081f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER1 0x010d 28091f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 28101f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER2 0x010e 28111f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 28121f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER3 0x010f 28131f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 28141f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER4 0x0110 28151f902edeSFeifei Xu #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 28161f902edeSFeifei Xu #define mmMEM_TYPE_CNTL 0x0111 28171f902edeSFeifei Xu #define mmMEM_TYPE_CNTL_BASE_IDX 2 28181f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_CNTL 0x0113 28191f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 28201f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_0 0x0114 28211f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX 2 28221f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_1 0x0115 28231f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX 2 28241f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_2 0x0116 28251f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX 2 28261f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_3 0x0117 28271f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX 2 28281f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_4 0x0118 28291f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX 2 28301f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_5 0x0119 28311f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX 2 28321f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_6 0x011a 28331f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX 2 28341f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_7 0x011b 28351f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX 2 28361f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_8 0x011c 28371f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX 2 28381f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_9 0x011d 28391f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX 2 28401f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_10 0x011e 28411f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX 2 28421f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_11 0x011f 28431f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX 2 28441f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_12 0x0120 28451f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX 2 28461f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_13 0x0121 28471f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX 2 28481f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_14 0x0122 28491f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX 2 28501f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_15 0x0123 28511f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX 2 28521f902edeSFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d 28531f902edeSFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 28541f902edeSFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e 28551f902edeSFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 28561f902edeSFeifei Xu #define mmBIF_RB_CNTL 0x012f 28571f902edeSFeifei Xu #define mmBIF_RB_CNTL_BASE_IDX 2 28581f902edeSFeifei Xu #define mmBIF_RB_BASE 0x0130 28591f902edeSFeifei Xu #define mmBIF_RB_BASE_BASE_IDX 2 28601f902edeSFeifei Xu #define mmBIF_RB_RPTR 0x0131 28611f902edeSFeifei Xu #define mmBIF_RB_RPTR_BASE_IDX 2 28621f902edeSFeifei Xu #define mmBIF_RB_WPTR 0x0132 28631f902edeSFeifei Xu #define mmBIF_RB_WPTR_BASE_IDX 2 28641f902edeSFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI 0x0133 28651f902edeSFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 28661f902edeSFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO 0x0134 28671f902edeSFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 28681f902edeSFeifei Xu #define mmMAILBOX_INDEX 0x0135 28691f902edeSFeifei Xu #define mmMAILBOX_INDEX_BASE_IDX 2 28701f902edeSFeifei Xu #define mmBIF_MP1_INTR_CTRL 0x0142 28711f902edeSFeifei Xu #define mmBIF_MP1_INTR_CTRL_BASE_IDX 2 28721f902edeSFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 28731f902edeSFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 28741f902edeSFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 28751f902edeSFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 28761f902edeSFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 28771f902edeSFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 28781f902edeSFeifei Xu #define mmBIF_PERSTB_PAD_CNTL 0x0148 28791f902edeSFeifei Xu #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 28801f902edeSFeifei Xu #define mmBIF_PX_EN_PAD_CNTL 0x0149 28811f902edeSFeifei Xu #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 28821f902edeSFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL 0x014a 28831f902edeSFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 28841f902edeSFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL 0x014b 28851f902edeSFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 28861f902edeSFeifei Xu #define mmBIF_PWRBRK_PAD_CNTL 0x014c 28871f902edeSFeifei Xu #define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX 2 28881f902edeSFeifei Xu #define mmBIF_WAKEB_PAD_CNTL 0x014d 28891f902edeSFeifei Xu #define mmBIF_WAKEB_PAD_CNTL_BASE_IDX 2 28901f902edeSFeifei Xu 28911f902edeSFeifei Xu 28921f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 28931f902edeSFeifei Xu // base address: 0x0 28941f902edeSFeifei Xu #define mmBIF_BME_STATUS 0x00eb 28951f902edeSFeifei Xu #define mmBIF_BME_STATUS_BASE_IDX 2 28961f902edeSFeifei Xu #define mmBIF_ATOMIC_ERR_LOG 0x00ec 28971f902edeSFeifei Xu #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 2 28981f902edeSFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 28991f902edeSFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 29001f902edeSFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 29011f902edeSFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 29021f902edeSFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 29031f902edeSFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 29041f902edeSFeifei Xu #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 29051f902edeSFeifei Xu #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 29061f902edeSFeifei Xu #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 29071f902edeSFeifei Xu #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 29081f902edeSFeifei Xu #define mmGPU_HDP_FLUSH_REQ 0x0106 29091f902edeSFeifei Xu #define mmGPU_HDP_FLUSH_REQ_BASE_IDX 2 29101f902edeSFeifei Xu #define mmGPU_HDP_FLUSH_DONE 0x0107 29111f902edeSFeifei Xu #define mmGPU_HDP_FLUSH_DONE_BASE_IDX 2 29121f902edeSFeifei Xu #define mmBIF_TRANS_PENDING 0x0108 29131f902edeSFeifei Xu #define mmBIF_TRANS_PENDING_BASE_IDX 2 29141f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_BYPASS 0x0112 29151f902edeSFeifei Xu #define mmNBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 29161f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 29171f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 29181f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW1 0x0137 29191f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 29201f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW2 0x0138 29211f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 29221f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW3 0x0139 29231f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 29241f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW0 0x013a 29251f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 29261f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW1 0x013b 29271f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 29281f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW2 0x013c 29291f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 29301f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW3 0x013d 29311f902edeSFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 29321f902edeSFeifei Xu #define mmMAILBOX_CONTROL 0x013e 29331f902edeSFeifei Xu #define mmMAILBOX_CONTROL_BASE_IDX 2 29341f902edeSFeifei Xu #define mmMAILBOX_INT_CNTL 0x013f 29351f902edeSFeifei Xu #define mmMAILBOX_INT_CNTL_BASE_IDX 2 29361f902edeSFeifei Xu #define mmBIF_VMHV_MAILBOX 0x0140 29371f902edeSFeifei Xu #define mmBIF_VMHV_MAILBOX_BASE_IDX 2 29381f902edeSFeifei Xu 29391f902edeSFeifei Xu 29401f902edeSFeifei Xu // addressBlock: nbio_nbif0_gdc_GDCDEC 29411f902edeSFeifei Xu // base address: 0x0 29421f902edeSFeifei Xu #define mmNGDC_SDP_PORT_CTRL 0x01c2 29431f902edeSFeifei Xu #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 29441f902edeSFeifei Xu #define mmSHUB_REGS_IF_CTL 0x01c3 29451f902edeSFeifei Xu #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 29461f902edeSFeifei Xu #define mmNGDC_MGCG_CTRL 0x01ca 29471f902edeSFeifei Xu #define mmNGDC_MGCG_CTRL_BASE_IDX 2 29481f902edeSFeifei Xu #define mmNGDC_RESERVED_0 0x01cb 29491f902edeSFeifei Xu #define mmNGDC_RESERVED_0_BASE_IDX 2 29501f902edeSFeifei Xu #define mmNGDC_RESERVED_1 0x01cc 29511f902edeSFeifei Xu #define mmNGDC_RESERVED_1_BASE_IDX 2 29521f902edeSFeifei Xu #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd 29531f902edeSFeifei Xu #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 29541f902edeSFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 29551f902edeSFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 29561f902edeSFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 29571f902edeSFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 29581f902edeSFeifei Xu #define mmBIF_IH_DOORBELL_RANGE 0x01d2 29591f902edeSFeifei Xu #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 29601f902edeSFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 29611f902edeSFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 29621f902edeSFeifei Xu #define mmBIF_ACV_DOORBELL_RANGE 0x01d4 29631f902edeSFeifei Xu #define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX 2 29641f902edeSFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL 0x01de 29651f902edeSFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 29661f902edeSFeifei Xu #define mmS2A_MISC_CNTL 0x01df 29671f902edeSFeifei Xu #define mmS2A_MISC_CNTL_BASE_IDX 2 29681f902edeSFeifei Xu 29691f902edeSFeifei Xu 29701f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 29711f902edeSFeifei Xu // base address: 0x0 29721f902edeSFeifei Xu #define mmGFXMSIX_VECT0_ADDR_LO 0x0400 29731f902edeSFeifei Xu #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 29741f902edeSFeifei Xu #define mmGFXMSIX_VECT0_ADDR_HI 0x0401 29751f902edeSFeifei Xu #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 29761f902edeSFeifei Xu #define mmGFXMSIX_VECT0_MSG_DATA 0x0402 29771f902edeSFeifei Xu #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 29781f902edeSFeifei Xu #define mmGFXMSIX_VECT0_CONTROL 0x0403 29791f902edeSFeifei Xu #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 3 29801f902edeSFeifei Xu #define mmGFXMSIX_VECT1_ADDR_LO 0x0404 29811f902edeSFeifei Xu #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 29821f902edeSFeifei Xu #define mmGFXMSIX_VECT1_ADDR_HI 0x0405 29831f902edeSFeifei Xu #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 29841f902edeSFeifei Xu #define mmGFXMSIX_VECT1_MSG_DATA 0x0406 29851f902edeSFeifei Xu #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 29861f902edeSFeifei Xu #define mmGFXMSIX_VECT1_CONTROL 0x0407 29871f902edeSFeifei Xu #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 3 29881f902edeSFeifei Xu #define mmGFXMSIX_VECT2_ADDR_LO 0x0408 29891f902edeSFeifei Xu #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 29901f902edeSFeifei Xu #define mmGFXMSIX_VECT2_ADDR_HI 0x0409 29911f902edeSFeifei Xu #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 29921f902edeSFeifei Xu #define mmGFXMSIX_VECT2_MSG_DATA 0x040a 29931f902edeSFeifei Xu #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 29941f902edeSFeifei Xu #define mmGFXMSIX_VECT2_CONTROL 0x040b 29951f902edeSFeifei Xu #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 3 29961f902edeSFeifei Xu #define mmGFXMSIX_PBA 0x0800 29971f902edeSFeifei Xu #define mmGFXMSIX_PBA_BASE_IDX 3 29981f902edeSFeifei Xu 29991f902edeSFeifei Xu 30001f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 30011f902edeSFeifei Xu // base address: 0x0 30021f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 30031f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 30041f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 30051f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 30061f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 30071f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 30081f902edeSFeifei Xu 30091f902edeSFeifei Xu 30101f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 30111f902edeSFeifei Xu // base address: 0x0 30121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 30131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 30141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 30151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 30161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 30171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 30181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 30191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 30201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 30211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 30221f902edeSFeifei Xu 30231f902edeSFeifei Xu 30241f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 30251f902edeSFeifei Xu // base address: 0x0 30261f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 30271f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 30281f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 30291f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 30301f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 30311f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 30321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 30331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 30341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 30351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 30361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 30371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 30381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 30391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 30401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 30411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 30421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 30431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 30441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 30451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 30461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 30471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 30481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 30491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 30501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 30511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 30521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 30531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 30541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 30551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 30561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 30571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 30581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 30591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 30601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 30611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 30621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 30631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 30641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 30651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 30661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 30671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 30681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 30691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 30701f902edeSFeifei Xu 30711f902edeSFeifei Xu 30721f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 30731f902edeSFeifei Xu // base address: 0x0 30741f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 30751f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 30761f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 30771f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 30781f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 30791f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 30801f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 30811f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 30821f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 30831f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 30841f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 30851f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 30861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 30871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 30881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 30891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 30901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 30911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 30921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 30931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 30941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a 30951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 30961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b 30971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 30981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 30991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 31001f902edeSFeifei Xu 31011f902edeSFeifei Xu 31021f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 31031f902edeSFeifei Xu // base address: 0x0 31041f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 31051f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 31061f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 31071f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 31081f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 31091f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 31101f902edeSFeifei Xu 31111f902edeSFeifei Xu 31121f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 31131f902edeSFeifei Xu // base address: 0x0 31141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 31151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 31161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 31171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 31181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 31191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 31201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 31211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 31221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 31231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 31241f902edeSFeifei Xu 31251f902edeSFeifei Xu 31261f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 31271f902edeSFeifei Xu // base address: 0x0 31281f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 31291f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 31301f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 31311f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 31321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 31331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 31341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 31351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 31361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 31371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 31381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 31391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 31401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 31411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 31421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 31431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 31441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 31451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 31461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 31471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 31481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 31491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 31501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 31511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 31521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 31531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 31541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 31551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 31561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 31571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 31581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 31591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 31601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 31611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 31621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 31631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 31641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 31651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 31661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 31671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 31681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 31691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 31701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 31711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 31721f902edeSFeifei Xu 31731f902edeSFeifei Xu 31741f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 31751f902edeSFeifei Xu // base address: 0x0 31761f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 31771f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 31781f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 31791f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 31801f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 31811f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 31821f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 31831f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 31841f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 31851f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 31861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 31871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 31881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 31891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 31901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 31911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 31921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 31931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 31941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 31951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 31961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a 31971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 31981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b 31991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 32001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 32011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 32021f902edeSFeifei Xu 32031f902edeSFeifei Xu 32041f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 32051f902edeSFeifei Xu // base address: 0x0 32061f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 32071f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 32081f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 32091f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 32101f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 32111f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 32121f902edeSFeifei Xu 32131f902edeSFeifei Xu 32141f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 32151f902edeSFeifei Xu // base address: 0x0 32161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 32171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 32181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 32191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 32201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 32211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 32221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 32231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 32241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 32251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 32261f902edeSFeifei Xu 32271f902edeSFeifei Xu 32281f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 32291f902edeSFeifei Xu // base address: 0x0 32301f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 32311f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 32321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 32331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 32341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 32351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 32361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 32371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 32381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 32391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 32401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 32411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 32421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 32431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 32441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 32451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 32461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 32471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 32481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 32491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 32501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 32511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 32521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 32531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 32541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 32551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 32561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 32571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 32581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 32591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 32601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 32611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 32621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 32631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 32641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 32651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 32661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 32671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 32681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 32691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 32701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 32711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 32721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 32731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 32741f902edeSFeifei Xu 32751f902edeSFeifei Xu 32761f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 32771f902edeSFeifei Xu // base address: 0x0 32781f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 32791f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 32801f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 32811f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 32821f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 32831f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 32841f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 32851f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 32861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 32871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 32881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 32891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 32901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 32911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 32921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 32931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 32941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 32951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 32961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 32971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 32981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a 32991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 33001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b 33011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 33021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 33031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 33041f902edeSFeifei Xu 33051f902edeSFeifei Xu 33061f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 33071f902edeSFeifei Xu // base address: 0x0 33081f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 33091f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 33101f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 33111f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 33121f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 33131f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 33141f902edeSFeifei Xu 33151f902edeSFeifei Xu 33161f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 33171f902edeSFeifei Xu // base address: 0x0 33181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 33191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 33201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 33211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 33221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 33231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 33241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 33251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 33261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 33271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 33281f902edeSFeifei Xu 33291f902edeSFeifei Xu 33301f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 33311f902edeSFeifei Xu // base address: 0x0 33321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 33331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 33341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 33351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 33361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 33371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 33381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 33391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 33401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 33411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 33421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 33431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 33441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 33451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 33461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 33471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 33481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 33491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 33501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 33511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 33521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 33531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 33541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 33551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 33561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 33571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 33581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 33591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 33601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 33611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 33621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 33631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 33641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 33651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 33661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 33671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 33681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 33691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 33701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 33711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 33721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 33731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 33741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 33751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 33761f902edeSFeifei Xu 33771f902edeSFeifei Xu 33781f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 33791f902edeSFeifei Xu // base address: 0x0 33801f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 33811f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 33821f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 33831f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 33841f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 33851f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 33861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 33871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 33881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 33891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 33901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 33911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 33921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 33931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 33941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 33951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 33961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 33971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 33981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 33991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 34001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a 34011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 34021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b 34031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 34041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 34051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 34061f902edeSFeifei Xu 34071f902edeSFeifei Xu 34081f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 34091f902edeSFeifei Xu // base address: 0x0 34101f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 34111f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 34121f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 34131f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 34141f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 34151f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 34161f902edeSFeifei Xu 34171f902edeSFeifei Xu 34181f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 34191f902edeSFeifei Xu // base address: 0x0 34201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 34211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 34221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 34231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 34241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 34251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 34261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 34271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 34281f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 34291f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 34301f902edeSFeifei Xu 34311f902edeSFeifei Xu 34321f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 34331f902edeSFeifei Xu // base address: 0x0 34341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 34351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 34361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 34371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 34381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 34391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 34401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 34411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 34421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 34431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 34441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 34451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 34461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 34471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 34481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 34491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 34501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 34511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 34521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 34531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 34541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 34551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 34561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 34571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 34581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 34591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 34601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 34611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 34621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 34631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 34641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 34651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 34661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 34671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 34681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 34691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 34701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 34711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 34721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 34731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 34741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 34751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 34761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 34771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 34781f902edeSFeifei Xu 34791f902edeSFeifei Xu 34801f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 34811f902edeSFeifei Xu // base address: 0x0 34821f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 34831f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 34841f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 34851f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 34861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 34871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 34881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 34891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 34901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 34911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 34921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 34931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 34941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 34951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 34961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 34971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 34981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 34991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 35001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 35011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 35021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a 35031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 35041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b 35051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 35061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 35071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 35081f902edeSFeifei Xu 35091f902edeSFeifei Xu 35101f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 35111f902edeSFeifei Xu // base address: 0x0 35121f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 35131f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 35141f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 35151f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 35161f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 35171f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 35181f902edeSFeifei Xu 35191f902edeSFeifei Xu 35201f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 35211f902edeSFeifei Xu // base address: 0x0 35221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 35231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 35241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 35251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 35261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 35271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 35281f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 35291f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 35301f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 35311f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 35321f902edeSFeifei Xu 35331f902edeSFeifei Xu 35341f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 35351f902edeSFeifei Xu // base address: 0x0 35361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 35371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 35381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 35391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 35401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 35411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 35421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 35431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 35441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 35451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 35461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 35471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 35481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 35491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 35501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 35511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 35521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 35531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 35541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 35551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 35561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 35571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 35581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 35591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 35601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 35611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 35621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 35631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 35641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 35651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 35661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 35671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 35681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 35691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 35701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 35711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 35721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 35731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 35741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 35751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 35761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 35771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 35781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 35791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 35801f902edeSFeifei Xu 35811f902edeSFeifei Xu 35821f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 35831f902edeSFeifei Xu // base address: 0x0 35841f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 35851f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 35861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 35871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 35881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 35891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 35901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 35911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 35921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 35931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 35941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 35951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 35961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 35971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 35981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 35991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 36001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 36011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 36021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 36031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 36041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a 36051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 36061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b 36071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 36081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 36091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 36101f902edeSFeifei Xu 36111f902edeSFeifei Xu 36121f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 36131f902edeSFeifei Xu // base address: 0x0 36141f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 36151f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 36161f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 36171f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 36181f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 36191f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 36201f902edeSFeifei Xu 36211f902edeSFeifei Xu 36221f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 36231f902edeSFeifei Xu // base address: 0x0 36241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 36251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 36261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 36271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 36281f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 36291f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 36301f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 36311f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 36321f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 36331f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 36341f902edeSFeifei Xu 36351f902edeSFeifei Xu 36361f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 36371f902edeSFeifei Xu // base address: 0x0 36381f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 36391f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 36401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 36411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 36421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 36431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 36441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 36451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 36461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 36471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 36481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 36491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 36501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 36511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 36521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 36531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 36541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 36551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 36561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 36571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 36581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 36591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 36601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 36611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 36621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 36631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 36641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 36651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 36661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 36671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 36681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 36691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 36701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 36711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 36721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 36731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 36741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 36751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 36761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 36771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 36781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 36791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 36801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 36811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 36821f902edeSFeifei Xu 36831f902edeSFeifei Xu 36841f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 36851f902edeSFeifei Xu // base address: 0x0 36861f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 36871f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 36881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 36891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 36901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 36911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 36921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 36931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 36941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 36951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 36961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 36971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 36981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 36991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 37001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 37011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 37021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 37031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 37041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 37051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 37061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a 37071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 37081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b 37091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 37101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 37111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 37121f902edeSFeifei Xu 37131f902edeSFeifei Xu 37141f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 37151f902edeSFeifei Xu // base address: 0x0 37161f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 37171f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 37181f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 37191f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 37201f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 37211f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 37221f902edeSFeifei Xu 37231f902edeSFeifei Xu 37241f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 37251f902edeSFeifei Xu // base address: 0x0 37261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 37271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 37281f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 37291f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 37301f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 37311f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 37321f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 37331f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 37341f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 37351f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 37361f902edeSFeifei Xu 37371f902edeSFeifei Xu 37381f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 37391f902edeSFeifei Xu // base address: 0x0 37401f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 37411f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 37421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 37431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 37441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 37451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 37461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 37471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 37481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 37491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 37501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 37511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 37521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 37531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 37541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 37551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 37561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 37571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 37581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 37591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 37601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 37611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 37621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 37631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 37641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 37651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 37661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 37671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 37681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 37691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 37701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 37711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 37721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 37731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 37741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 37751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 37761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 37771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 37781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 37791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 37801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 37811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 37821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 37831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 37841f902edeSFeifei Xu 37851f902edeSFeifei Xu 37861f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 37871f902edeSFeifei Xu // base address: 0x0 37881f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 37891f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 37901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 37911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 37921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 37931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 37941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 37951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 37961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 37971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 37981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 37991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 38001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 38011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 38021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 38031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 38041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 38051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 38061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 38071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 38081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a 38091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 38101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b 38111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 38121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 38131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 38141f902edeSFeifei Xu 38151f902edeSFeifei Xu 38161f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 38171f902edeSFeifei Xu // base address: 0x0 38181f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 38191f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 38201f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 38211f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 38221f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 38231f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 38241f902edeSFeifei Xu 38251f902edeSFeifei Xu 38261f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 38271f902edeSFeifei Xu // base address: 0x0 38281f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 38291f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 38301f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 38311f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 38321f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 38331f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 38341f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 38351f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 38361f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 38371f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 38381f902edeSFeifei Xu 38391f902edeSFeifei Xu 38401f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 38411f902edeSFeifei Xu // base address: 0x0 38421f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 38431f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 38441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 38451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 38461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 38471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 38481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 38491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 38501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 38511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 38521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 38531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 38541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 38551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 38561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 38571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 38581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 38591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 38601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 38611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 38621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 38631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 38641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 38651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 38661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 38671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 38681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 38691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 38701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 38711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 38721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 38731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 38741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 38751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 38761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 38771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 38781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 38791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 38801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 38811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 38821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 38831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 38841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 38851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 38861f902edeSFeifei Xu 38871f902edeSFeifei Xu 38881f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 38891f902edeSFeifei Xu // base address: 0x0 38901f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 38911f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 38921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 38931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 38941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 38951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 38961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 38971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 38981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 38991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 39001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 39011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 39021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 39031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 39041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 39051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 39061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 39071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 39081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 39091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 39101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a 39111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 39121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b 39131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 39141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 39151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 39161f902edeSFeifei Xu 39171f902edeSFeifei Xu 39181f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 39191f902edeSFeifei Xu // base address: 0x0 39201f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 39211f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 39221f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 39231f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 39241f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 39251f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 39261f902edeSFeifei Xu 39271f902edeSFeifei Xu 39281f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 39291f902edeSFeifei Xu // base address: 0x0 39301f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 39311f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 39321f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 39331f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 39341f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 39351f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 39361f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 39371f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 39381f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 39391f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 39401f902edeSFeifei Xu 39411f902edeSFeifei Xu 39421f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 39431f902edeSFeifei Xu // base address: 0x0 39441f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 39451f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 39461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 39471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 39481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 39491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 39501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 39511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 39521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 39531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 39541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 39551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 39561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 39571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 39581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 39591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 39601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 39611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 39621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 39631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 39641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 39651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 39661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 39671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 39681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 39691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 39701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 39711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 39721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 39731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 39741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 39751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 39761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 39771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 39781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 39791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 39801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 39811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 39821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 39831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 39841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 39851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 39861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 39871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 39881f902edeSFeifei Xu 39891f902edeSFeifei Xu 39901f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 39911f902edeSFeifei Xu // base address: 0x0 39921f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 39931f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 39941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 39951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 39961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 39971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 39981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 39991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 40001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 40011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 40021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 40031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 40041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 40051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 40061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 40071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 40081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 40091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 40101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 40111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 40121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a 40131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 40141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b 40151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 40161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 40171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 40181f902edeSFeifei Xu 40191f902edeSFeifei Xu 40201f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 40211f902edeSFeifei Xu // base address: 0x0 40221f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 40231f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 40241f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 40251f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 40261f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 40271f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 40281f902edeSFeifei Xu 40291f902edeSFeifei Xu 40301f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 40311f902edeSFeifei Xu // base address: 0x0 40321f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 40331f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 40341f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 40351f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 40361f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 40371f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 40381f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 40391f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 40401f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 40411f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 40421f902edeSFeifei Xu 40431f902edeSFeifei Xu 40441f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 40451f902edeSFeifei Xu // base address: 0x0 40461f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 40471f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 40481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 40491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 40501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 40511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 40521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 40531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 40541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 40551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 40561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 40571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 40581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 40591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 40601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 40611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 40621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 40631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 40641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 40651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 40661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 40671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 40681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 40691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 40701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 40711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 40721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 40731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 40741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 40751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 40761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 40771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 40781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 40791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 40801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 40811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 40821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 40831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 40841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 40851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 40861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 40871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 40881f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 40891f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 40901f902edeSFeifei Xu 40911f902edeSFeifei Xu 40921f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 40931f902edeSFeifei Xu // base address: 0x0 40941f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 40951f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 40961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 40971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 40981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 40991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 41001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 41011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 41021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 41031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 41041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 41051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 41061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 41071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 41081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 41091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 41101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 41111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 41121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 41131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 41141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a 41151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 41161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b 41171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 41181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 41191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 41201f902edeSFeifei Xu 41211f902edeSFeifei Xu 41221f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 41231f902edeSFeifei Xu // base address: 0x0 41241f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 41251f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 41261f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 41271f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 41281f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 41291f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 41301f902edeSFeifei Xu 41311f902edeSFeifei Xu 41321f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 41331f902edeSFeifei Xu // base address: 0x0 41341f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 41351f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 41361f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 41371f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 41381f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 41391f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 41401f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 41411f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 41421f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 41431f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 41441f902edeSFeifei Xu 41451f902edeSFeifei Xu 41461f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 41471f902edeSFeifei Xu // base address: 0x0 41481f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 41491f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 41501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 41511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 41521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 41531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 41541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 41551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 41561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 41571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 41581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 41591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 41601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 41611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 41621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 41631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 41641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 41651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 41661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 41671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 41681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 41691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 41701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 41711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 41721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 41731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 41741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 41751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 41761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 41771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 41781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 41791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 41801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 41811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 41821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 41831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 41841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 41851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 41861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 41871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 41881f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 41891f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 41901f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 41911f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 41921f902edeSFeifei Xu 41931f902edeSFeifei Xu 41941f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 41951f902edeSFeifei Xu // base address: 0x0 41961f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 41971f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 41981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 41991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 42001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 42011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 42021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 42031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 42041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 42051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 42061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 42071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 42081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 42091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 42101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 42111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 42121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 42131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 42141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 42151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 42161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a 42171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 42181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b 42191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 42201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 42211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 42221f902edeSFeifei Xu 42231f902edeSFeifei Xu 42241f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 42251f902edeSFeifei Xu // base address: 0x0 42261f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 42271f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 42281f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 42291f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 42301f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 42311f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 42321f902edeSFeifei Xu 42331f902edeSFeifei Xu 42341f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 42351f902edeSFeifei Xu // base address: 0x0 42361f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 42371f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 42381f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 42391f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 42401f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 42411f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 42421f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 42431f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 42441f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 42451f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 42461f902edeSFeifei Xu 42471f902edeSFeifei Xu 42481f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 42491f902edeSFeifei Xu // base address: 0x0 42501f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 42511f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 42521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 42531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 42541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 42551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 42561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 42571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 42581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 42591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 42601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 42611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 42621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 42631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 42641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 42651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 42661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 42671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 42681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 42691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 42701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 42711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 42721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 42731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 42741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 42751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 42761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 42771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 42781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 42791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 42801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 42811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 42821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 42831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 42841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 42851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 42861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 42871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 42881f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 42891f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 42901f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 42911f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 42921f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 42931f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 42941f902edeSFeifei Xu 42951f902edeSFeifei Xu 42961f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 42971f902edeSFeifei Xu // base address: 0x0 42981f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 42991f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 43001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 43011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 43021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 43031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 43041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 43051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 43061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 43071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 43081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 43091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 43101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 43111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 43121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 43131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 43141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 43151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 43161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 43171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 43181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a 43191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 43201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b 43211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 43221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 43231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 43241f902edeSFeifei Xu 43251f902edeSFeifei Xu 43261f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 43271f902edeSFeifei Xu // base address: 0x0 43281f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 43291f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 43301f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 43311f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 43321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 43331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 43341f902edeSFeifei Xu 43351f902edeSFeifei Xu 43361f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 43371f902edeSFeifei Xu // base address: 0x0 43381f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 43391f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 43401f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 43411f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 43421f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 43431f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 43441f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 43451f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 43461f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 43471f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 43481f902edeSFeifei Xu 43491f902edeSFeifei Xu 43501f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 43511f902edeSFeifei Xu // base address: 0x0 43521f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 43531f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 43541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 43551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 43561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 43571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 43581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 43591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 43601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 43611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 43621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 43631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 43641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 43651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 43661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 43671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 43681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 43691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 43701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 43711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 43721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 43731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 43741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 43751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 43761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 43771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 43781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 43791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 43801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 43811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 43821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 43831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 43841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 43851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 43861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 43871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 43881f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 43891f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 43901f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 43911f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 43921f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 43931f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 43941f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 43951f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 43961f902edeSFeifei Xu 43971f902edeSFeifei Xu 43981f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 43991f902edeSFeifei Xu // base address: 0x0 44001f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 44011f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 44021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 44031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 44041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 44051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 44061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 44071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 44081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 44091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 44101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 44111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 44121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 44131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 44141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 44151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 44161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 44171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 44181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 44191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 44201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a 44211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 44221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b 44231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 44241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 44251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 44261f902edeSFeifei Xu 44271f902edeSFeifei Xu 44281f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 44291f902edeSFeifei Xu // base address: 0x0 44301f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 44311f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 44321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 44331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 44341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 44351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 44361f902edeSFeifei Xu 44371f902edeSFeifei Xu 44381f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 44391f902edeSFeifei Xu // base address: 0x0 44401f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 44411f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 44421f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 44431f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 44441f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 44451f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 44461f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 44471f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 44481f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 44491f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 44501f902edeSFeifei Xu 44511f902edeSFeifei Xu 44521f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 44531f902edeSFeifei Xu // base address: 0x0 44541f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 44551f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 44561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 44571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 44581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 44591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 44601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 44611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 44621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 44631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 44641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 44651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 44661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 44671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 44681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 44691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 44701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 44711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 44721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 44731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 44741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 44751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 44761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 44771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 44781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 44791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 44801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 44811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 44821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 44831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 44841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 44851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 44861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 44871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 44881f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 44891f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 44901f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 44911f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 44921f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 44931f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 44941f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 44951f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 44961f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 44971f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 44981f902edeSFeifei Xu 44991f902edeSFeifei Xu 45001f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 45011f902edeSFeifei Xu // base address: 0x0 45021f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 45031f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 45041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 45051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 45061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 45071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 45081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 45091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 45101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 45111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 45121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 45131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 45141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 45151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 45161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 45171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 45181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 45191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 45201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 45211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 45221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a 45231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 45241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b 45251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 45261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 45271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 45281f902edeSFeifei Xu 45291f902edeSFeifei Xu 45301f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 45311f902edeSFeifei Xu // base address: 0x0 45321f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 45331f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 45341f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 45351f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 45361f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 45371f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 45381f902edeSFeifei Xu 45391f902edeSFeifei Xu 45401f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 45411f902edeSFeifei Xu // base address: 0x0 45421f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 45431f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 45441f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 45451f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 45461f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 45471f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 45481f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 45491f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 45501f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 45511f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 45521f902edeSFeifei Xu 45531f902edeSFeifei Xu 45541f902edeSFeifei Xu // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 45551f902edeSFeifei Xu // base address: 0x0 45561f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 45571f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 45581f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 45591f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 45601f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 45611f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 45621f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 45631f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 45641f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 45651f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 45661f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 45671f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 45681f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 45691f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 45701f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 45711f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 45721f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 45731f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 45741f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 45751f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 45761f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 45771f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 45781f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 45791f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 45801f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 45811f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 45821f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 45831f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 45841f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 45851f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 45861f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 45871f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 45881f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 45891f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 45901f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 45911f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 45921f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 45931f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 45941f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 45951f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 45961f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 45971f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 45981f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 45991f902edeSFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 46001f902edeSFeifei Xu 46011f902edeSFeifei Xu 46021f902edeSFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 46031f902edeSFeifei Xu // base address: 0x0 46041f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 46051f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 46061f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 46071f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 46081f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 46091f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 46101f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 46111f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 46121f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 46131f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 46141f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 46151f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 46161f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 46171f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 46181f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 46191f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 46201f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 46211f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 46221f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 46231f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 46241f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a 46251f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 46261f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b 46271f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 46281f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 46291f902edeSFeifei Xu #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 46301f902edeSFeifei Xu 46311f902edeSFeifei Xu #endif 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