1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _nbio_7_4_OFFSET_HEADER 22 #define _nbio_7_4_OFFSET_HEADER 23 24 25 26 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 27 // base address: 0x0 28 #define cfgPSWUSCFG0_VENDOR_ID 0x0000 29 #define cfgPSWUSCFG0_DEVICE_ID 0x0002 30 #define cfgPSWUSCFG0_COMMAND 0x0004 31 #define cfgPSWUSCFG0_STATUS 0x0006 32 #define cfgPSWUSCFG0_REVISION_ID 0x0008 33 #define cfgPSWUSCFG0_PROG_INTERFACE 0x0009 34 #define cfgPSWUSCFG0_SUB_CLASS 0x000a 35 #define cfgPSWUSCFG0_BASE_CLASS 0x000b 36 #define cfgPSWUSCFG0_CACHE_LINE 0x000c 37 #define cfgPSWUSCFG0_LATENCY 0x000d 38 #define cfgPSWUSCFG0_HEADER 0x000e 39 #define cfgPSWUSCFG0_BIST 0x000f 40 #define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018 41 #define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c 42 #define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e 43 #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020 44 #define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024 45 #define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028 46 #define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c 47 #define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030 48 #define cfgPSWUSCFG0_CAP_PTR 0x0034 49 #define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c 50 #define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d 51 #define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e 52 #define cfgEXT_BRIDGE_CNTL 0x0040 53 #define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048 54 #define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c 55 #define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050 56 #define cfgPSWUSCFG0_PMI_CAP 0x0052 57 #define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054 58 #define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058 59 #define cfgPSWUSCFG0_PCIE_CAP 0x005a 60 #define cfgPSWUSCFG0_DEVICE_CAP 0x005c 61 #define cfgPSWUSCFG0_DEVICE_CNTL 0x0060 62 #define cfgPSWUSCFG0_DEVICE_STATUS 0x0062 63 #define cfgPSWUSCFG0_LINK_CAP 0x0064 64 #define cfgPSWUSCFG0_LINK_CNTL 0x0068 65 #define cfgPSWUSCFG0_LINK_STATUS 0x006a 66 #define cfgPSWUSCFG0_DEVICE_CAP2 0x007c 67 #define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080 68 #define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082 69 #define cfgPSWUSCFG0_LINK_CAP2 0x0084 70 #define cfgPSWUSCFG0_LINK_CNTL2 0x0088 71 #define cfgPSWUSCFG0_LINK_STATUS2 0x008a 72 #define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0 73 #define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2 74 #define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4 75 #define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8 76 #define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8 77 #define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac 78 #define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0 79 #define cfgPSWUSCFG0_SSID_CAP 0x00c4 80 #define cfgMSI_MAP_CAP_LIST 0x00c8 81 #define cfgMSI_MAP_CAP 0x00ca 82 #define cfgMSI_MAP_ADDR_LO 0x00cc 83 #define cfgMSI_MAP_ADDR_HI 0x00d0 84 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 85 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 86 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108 87 #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c 88 #define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110 89 #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114 90 #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118 91 #define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c 92 #define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e 93 #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120 94 #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124 95 #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a 96 #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c 97 #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130 98 #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136 99 #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 100 #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 101 #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 102 #define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 103 #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154 104 #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158 105 #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c 106 #define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160 107 #define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164 108 #define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168 109 #define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c 110 #define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170 111 #define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174 112 #define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178 113 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188 114 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c 115 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190 116 #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194 117 #define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 118 #define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274 119 #define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278 120 #define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 121 #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 122 #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 123 #define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 124 #define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 125 #define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 126 #define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 127 #define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 128 #define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 129 #define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 130 #define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 131 #define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 132 #define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 133 #define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 134 #define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 135 #define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 136 #define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0 137 #define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4 138 #define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6 139 #define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0 140 #define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4 141 #define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6 142 #define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8 143 #define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc 144 #define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300 145 #define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304 146 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308 147 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c 148 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 149 #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 150 #define cfgPCIE_MC_OVERLAY_BAR0 0x0318 151 #define cfgPCIE_MC_OVERLAY_BAR1 0x031c 152 #define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320 153 #define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324 154 #define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328 155 #define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c 156 #define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e 157 #define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370 158 #define cfgPCIE_L1_PM_SUB_CAP 0x0374 159 #define cfgPCIE_L1_PM_SUB_CNTL 0x0378 160 #define cfgPCIE_L1_PM_SUB_CNTL2 0x037c 161 #define cfgPCIE_ESM_CAP_LIST 0x03c4 162 #define cfgPCIE_ESM_HEADER_1 0x03c8 163 #define cfgPCIE_ESM_HEADER_2 0x03cc 164 #define cfgPCIE_ESM_STATUS 0x03ce 165 #define cfgPCIE_ESM_CTRL 0x03d0 166 #define cfgPCIE_ESM_CAP_1 0x03d4 167 #define cfgPCIE_ESM_CAP_2 0x03d8 168 #define cfgPCIE_ESM_CAP_3 0x03dc 169 #define cfgPCIE_ESM_CAP_4 0x03e0 170 #define cfgPCIE_ESM_CAP_5 0x03e4 171 #define cfgPCIE_ESM_CAP_6 0x03e8 172 #define cfgPCIE_ESM_CAP_7 0x03ec 173 #define cfgPSWUSCFG0_PCIE_DLF_ENH_CAP_LIST 0x0400 174 #define cfgPSWUSCFG0_DATA_LINK_FEATURE_CAP 0x0404 175 #define cfgPSWUSCFG0_DATA_LINK_FEATURE_STATUS 0x0408 176 #define cfgPCIE_PHY_16GT_ENH_CAP_LIST 0x0410 177 #define cfgPSWUSCFG0_LINK_CAP_16GT 0x0414 178 #define cfgPSWUSCFG0_LINK_CNTL_16GT 0x0418 179 #define cfgPSWUSCFG0_LINK_STATUS_16GT 0x041c 180 #define cfgPSWUSCFG0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 181 #define cfgPSWUSCFG0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 182 #define cfgPSWUSCFG0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 183 #define cfgPSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 184 #define cfgPSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 185 #define cfgPSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 186 #define cfgPSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 187 #define cfgPSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 188 #define cfgPSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 189 #define cfgPSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 190 #define cfgPSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 191 #define cfgPSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 192 #define cfgPSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 193 #define cfgPSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 194 #define cfgPSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 195 #define cfgPSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 196 #define cfgPSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 197 #define cfgPSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 198 #define cfgPSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 199 #define cfgPCIE_MARGINING_ENH_CAP_LIST 0x0440 200 #define cfgPSWUSCFG0_MARGINING_PORT_CAP 0x0444 201 #define cfgPSWUSCFG0_MARGINING_PORT_STATUS 0x0446 202 #define cfgPSWUSCFG0_LANE_0_MARGINING_LANE_CNTL 0x0448 203 #define cfgPSWUSCFG0_LANE_0_MARGINING_LANE_STATUS 0x044a 204 #define cfgPSWUSCFG0_LANE_1_MARGINING_LANE_CNTL 0x044c 205 #define cfgPSWUSCFG0_LANE_1_MARGINING_LANE_STATUS 0x044e 206 #define cfgPSWUSCFG0_LANE_2_MARGINING_LANE_CNTL 0x0450 207 #define cfgPSWUSCFG0_LANE_2_MARGINING_LANE_STATUS 0x0452 208 #define cfgPSWUSCFG0_LANE_3_MARGINING_LANE_CNTL 0x0454 209 #define cfgPSWUSCFG0_LANE_3_MARGINING_LANE_STATUS 0x0456 210 #define cfgPSWUSCFG0_LANE_4_MARGINING_LANE_CNTL 0x0458 211 #define cfgPSWUSCFG0_LANE_4_MARGINING_LANE_STATUS 0x045a 212 #define cfgPSWUSCFG0_LANE_5_MARGINING_LANE_CNTL 0x045c 213 #define cfgPSWUSCFG0_LANE_5_MARGINING_LANE_STATUS 0x045e 214 #define cfgPSWUSCFG0_LANE_6_MARGINING_LANE_CNTL 0x0460 215 #define cfgPSWUSCFG0_LANE_6_MARGINING_LANE_STATUS 0x0462 216 #define cfgPSWUSCFG0_LANE_7_MARGINING_LANE_CNTL 0x0464 217 #define cfgPSWUSCFG0_LANE_7_MARGINING_LANE_STATUS 0x0466 218 #define cfgPSWUSCFG0_LANE_8_MARGINING_LANE_CNTL 0x0468 219 #define cfgPSWUSCFG0_LANE_8_MARGINING_LANE_STATUS 0x046a 220 #define cfgPSWUSCFG0_LANE_9_MARGINING_LANE_CNTL 0x046c 221 #define cfgPSWUSCFG0_LANE_9_MARGINING_LANE_STATUS 0x046e 222 #define cfgPSWUSCFG0_LANE_10_MARGINING_LANE_CNTL 0x0470 223 #define cfgPSWUSCFG0_LANE_10_MARGINING_LANE_STATUS 0x0472 224 #define cfgPSWUSCFG0_LANE_11_MARGINING_LANE_CNTL 0x0474 225 #define cfgPSWUSCFG0_LANE_11_MARGINING_LANE_STATUS 0x0476 226 #define cfgPSWUSCFG0_LANE_12_MARGINING_LANE_CNTL 0x0478 227 #define cfgPSWUSCFG0_LANE_12_MARGINING_LANE_STATUS 0x047a 228 #define cfgPSWUSCFG0_LANE_13_MARGINING_LANE_CNTL 0x047c 229 #define cfgPSWUSCFG0_LANE_13_MARGINING_LANE_STATUS 0x047e 230 #define cfgPSWUSCFG0_LANE_14_MARGINING_LANE_CNTL 0x0480 231 #define cfgPSWUSCFG0_LANE_14_MARGINING_LANE_STATUS 0x0482 232 #define cfgPSWUSCFG0_LANE_15_MARGINING_LANE_CNTL 0x0484 233 #define cfgPSWUSCFG0_LANE_15_MARGINING_LANE_STATUS 0x0486 234 235 236 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 237 // base address: 0x0 238 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 239 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 240 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 241 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 242 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 243 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 244 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a 245 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b 246 #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c 247 #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d 248 #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e 249 #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f 250 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 251 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 252 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 253 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c 254 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 255 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 256 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c 257 #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 258 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 259 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c 260 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d 261 #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e 262 #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f 263 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 264 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c 265 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 266 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 267 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 268 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 269 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 270 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 271 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c 272 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e 273 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 274 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 275 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 276 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 277 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c 278 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e 279 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 280 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 281 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 282 #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098 283 #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c 284 #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e 285 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 286 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 287 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 288 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 289 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 290 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac 291 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac 292 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 293 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 294 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 295 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 296 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 297 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 298 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 299 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 300 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 301 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 302 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 303 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 304 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 305 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 306 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c 307 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e 308 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 309 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 310 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 311 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c 312 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 313 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 314 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 315 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 316 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 317 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 318 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 319 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 320 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 321 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 322 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 323 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 324 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c 325 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 326 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 327 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 328 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 329 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 330 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 331 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 332 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 333 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 334 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 335 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c 336 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 337 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 338 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 339 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c 340 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 341 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 342 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 343 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c 344 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 345 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 346 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 347 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 348 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c 349 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 350 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 351 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 352 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c 353 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e 354 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 355 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 356 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 357 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 358 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 359 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 360 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 361 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 362 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 363 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 364 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 365 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 366 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 367 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 368 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 369 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 370 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 371 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 372 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 373 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 374 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 375 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 376 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 377 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 378 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 379 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 380 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 381 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 382 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 383 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 384 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 385 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 386 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 387 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 388 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 389 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 390 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 391 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 392 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 393 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 394 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 395 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 396 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 397 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 398 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 399 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc 400 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 401 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 402 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 403 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c 404 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 405 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 406 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 407 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 408 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 409 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c 410 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e 411 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 412 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 413 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 414 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a 415 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c 416 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e 417 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 418 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 419 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 420 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 421 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 422 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 423 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 424 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 425 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 426 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 427 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 428 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 429 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 430 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 431 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 432 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x0374 433 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x0378 434 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 435 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x0404 436 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x0408 437 #define cfgBIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST 0x0410 438 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x0414 439 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x0418 440 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x041c 441 #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 442 #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 443 #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 444 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 445 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 446 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 447 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 448 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 449 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 450 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 451 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 452 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 453 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 454 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 455 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 456 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 457 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 458 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 459 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 460 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST 0x0440 461 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x0444 462 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x0446 463 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 464 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x044a 465 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x044c 466 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x044e 467 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 468 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 469 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 470 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 471 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 472 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x045a 473 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x045c 474 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x045e 475 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 476 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 477 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 478 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 479 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 480 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x046a 481 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x046c 482 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x046e 483 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 484 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 485 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 486 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 487 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 488 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x047a 489 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x047c 490 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x047e 491 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 492 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 493 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 494 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 495 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 496 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 497 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 498 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 499 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 500 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 501 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 502 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 503 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 504 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 505 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 506 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 507 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 508 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 509 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 510 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 511 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c 512 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 513 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 514 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 515 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c 516 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 517 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 518 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 519 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c 520 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0530 521 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0534 522 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0538 523 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x053c 524 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0540 525 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0544 526 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0548 527 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x054c 528 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0550 529 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0554 530 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0558 531 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x055c 532 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0560 533 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0564 534 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0568 535 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x056c 536 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0570 537 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0574 538 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x0578 539 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x057c 540 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0580 541 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0584 542 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x0588 543 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x058c 544 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0590 545 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0594 546 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x0598 547 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x059c 548 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a0 549 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a4 550 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05a8 551 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05ac 552 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05b0 553 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05b4 554 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05b8 555 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05bc 556 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05c0 557 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05c4 558 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05c8 559 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05cc 560 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05d0 561 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05e0 562 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05e4 563 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05e8 564 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05ec 565 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x05f0 566 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x05f4 567 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x05f8 568 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x05fc 569 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0600 570 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0610 571 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0614 572 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0618 573 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x061c 574 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0620 575 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0624 576 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0628 577 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x062c 578 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0630 579 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0640 580 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0644 581 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0648 582 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x064c 583 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0650 584 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0654 585 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0658 586 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x065c 587 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0660 588 589 590 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 591 // base address: 0x0 592 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 593 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 594 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 595 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 596 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 597 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 598 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a 599 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b 600 #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c 601 #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d 602 #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e 603 #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f 604 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 605 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 606 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 607 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c 608 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 609 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 610 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c 611 #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 612 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 613 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c 614 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d 615 #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e 616 #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f 617 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 618 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c 619 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 620 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 621 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 622 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 623 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 624 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 625 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c 626 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e 627 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 628 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 629 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 630 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 631 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c 632 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e 633 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 634 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 635 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 636 #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 637 #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c 638 #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e 639 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 640 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 641 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 642 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 643 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 644 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac 645 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac 646 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 647 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 648 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 649 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 650 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 651 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 652 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 653 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 654 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 655 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 656 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 657 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 658 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 659 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 660 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c 661 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e 662 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 663 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 664 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 665 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c 666 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 667 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 668 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 669 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 670 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 671 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 672 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 673 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 674 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 675 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 676 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 677 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 678 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c 679 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 680 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 681 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 682 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 683 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 684 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 685 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 686 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 687 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 688 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 689 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c 690 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 691 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 692 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 693 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c 694 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 695 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 696 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 697 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c 698 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 699 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 700 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 701 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 702 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 703 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 704 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 705 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 706 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c 707 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e 708 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 709 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 710 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 711 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 712 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 713 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 714 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 715 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 716 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 717 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 718 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 719 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 720 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 721 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 722 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 723 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 724 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 725 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 726 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 727 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 728 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 729 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 730 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 731 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 732 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 733 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 734 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 735 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 736 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 737 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 738 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 739 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 740 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 741 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 742 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 743 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 744 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 745 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 746 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 747 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 748 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 749 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 750 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 751 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 752 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 753 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc 754 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 755 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 756 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 757 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c 758 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 759 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 760 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 761 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 762 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 763 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c 764 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e 765 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 766 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 767 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 768 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a 769 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c 770 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e 771 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 772 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 773 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 774 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 775 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 776 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 777 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 778 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 779 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 780 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 781 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 782 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 783 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 784 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 785 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 786 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x0374 787 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x0378 788 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x0400 789 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x0404 790 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x0408 791 #define cfgBIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST 0x0410 792 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x0414 793 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x0418 794 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x041c 795 #define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 796 #define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 797 #define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 798 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 799 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 800 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 801 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 802 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 803 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 804 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 805 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 806 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 807 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 808 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 809 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 810 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 811 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 812 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 813 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 814 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST 0x0440 815 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x0444 816 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x0446 817 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x0448 818 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x044a 819 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x044c 820 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x044e 821 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x0450 822 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x0452 823 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x0454 824 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x0456 825 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x0458 826 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x045a 827 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x045c 828 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x045e 829 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x0460 830 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x0462 831 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x0464 832 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x0466 833 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x0468 834 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x046a 835 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x046c 836 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x046e 837 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x0470 838 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x0472 839 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x0474 840 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x0476 841 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x0478 842 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x047a 843 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x047c 844 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x047e 845 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x0480 846 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x0482 847 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x0484 848 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x0486 849 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 850 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 851 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 852 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 853 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 854 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 855 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 856 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 857 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 858 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 859 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 860 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 861 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 862 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 863 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 864 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 865 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c 866 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 867 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 868 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 869 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c 870 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 871 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 872 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 873 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c 874 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0530 875 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0534 876 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0538 877 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x053c 878 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0540 879 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0544 880 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0548 881 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x054c 882 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0550 883 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0554 884 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0558 885 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x055c 886 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0560 887 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0564 888 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0568 889 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x056c 890 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0570 891 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0574 892 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x0578 893 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x057c 894 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0580 895 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0584 896 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x0588 897 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x058c 898 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0590 899 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0594 900 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x0598 901 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x059c 902 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a0 903 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a4 904 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05a8 905 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05ac 906 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05b0 907 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05b4 908 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05b8 909 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05bc 910 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05c0 911 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05c4 912 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05c8 913 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05cc 914 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05d0 915 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05e0 916 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05e4 917 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05e8 918 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05ec 919 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x05f0 920 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x05f4 921 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x05f8 922 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x05fc 923 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0600 924 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0610 925 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0614 926 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0618 927 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x061c 928 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0620 929 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0624 930 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0628 931 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x062c 932 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0630 933 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0640 934 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0644 935 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0648 936 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x064c 937 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0650 938 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0654 939 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0658 940 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x065c 941 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0660 942 943 944 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp 945 // base address: 0x0 946 #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 947 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 948 #define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 949 #define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 950 #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 951 #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 952 #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a 953 #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b 954 #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c 955 #define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d 956 #define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e 957 #define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f 958 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 959 #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 960 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c 961 #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e 962 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 963 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 964 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 965 #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c 966 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 967 #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 968 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c 969 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d 970 #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e 971 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 972 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 973 #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 974 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 975 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a 976 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c 977 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 978 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 979 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 980 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 981 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a 982 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c 983 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 984 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 985 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c 986 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 987 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 988 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 989 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 990 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a 991 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c 992 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 993 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 994 #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 995 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 996 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 997 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 998 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 999 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac 1000 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 1001 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 1002 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1003 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1004 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 1005 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c 1006 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 1007 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 1008 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 1009 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c 1010 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e 1011 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 1012 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 1013 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a 1014 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c 1015 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 1016 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 1017 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 1018 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 1019 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 1020 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1021 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 1022 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 1023 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1024 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 1025 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 1026 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1027 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c 1028 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 1029 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 1030 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 1031 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 1032 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c 1033 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 1034 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 1035 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 1036 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 1037 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 1038 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 1039 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 1040 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 1041 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 1042 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 1043 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 1044 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 1045 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 1046 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 1047 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 1048 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 1049 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 1050 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 1051 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 1052 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 1053 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 1054 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 1055 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 1056 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 1057 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 0x0400 1058 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 0x0404 1059 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 0x0408 1060 #define cfgBIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST 0x0410 1061 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 0x0414 1062 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 0x0418 1063 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 0x041c 1064 #define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 1065 #define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 1066 #define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 1067 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 1068 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 1069 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 1070 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 1071 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 1072 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 1073 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 1074 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 1075 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 1076 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 1077 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 1078 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 1079 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 1080 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 1081 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 1082 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 1083 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST 0x0440 1084 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 0x0444 1085 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 0x0446 1086 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 0x0448 1087 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 0x044a 1088 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 0x044c 1089 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 0x044e 1090 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 0x0450 1091 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 0x0452 1092 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 0x0454 1093 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 0x0456 1094 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 0x0458 1095 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 0x045a 1096 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 0x045c 1097 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 0x045e 1098 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 0x0460 1099 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 0x0462 1100 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 0x0464 1101 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 0x0466 1102 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 0x0468 1103 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 0x046a 1104 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 0x046c 1105 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 0x046e 1106 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 0x0470 1107 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 0x0472 1108 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 1109 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 0x0476 1110 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 0x0478 1111 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 0x047a 1112 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 0x047c 1113 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 0x047e 1114 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 0x0480 1115 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 0x0482 1116 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 0x0484 1117 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 0x0486 1118 1119 1120 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 1121 // base address: 0x0 1122 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 1123 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 1124 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 1125 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 1126 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 1127 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 1128 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a 1129 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b 1130 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c 1131 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d 1132 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e 1133 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f 1134 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 1135 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 1136 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 1137 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c 1138 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 1139 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 1140 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c 1141 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 1142 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 1143 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c 1144 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d 1145 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 1146 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 1147 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 1148 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c 1149 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e 1150 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 1151 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 1152 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 1153 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 1154 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c 1155 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e 1156 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 1157 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 1158 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 1159 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098 1160 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c 1161 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e 1162 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 1163 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 1164 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 1165 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 1166 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 1167 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac 1168 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac 1169 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 1170 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 1171 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 1172 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 1173 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 1174 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 1175 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 1176 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1177 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1178 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 1179 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 1180 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1181 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 1182 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 1183 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1184 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 1185 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 1186 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1187 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c 1188 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 1189 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 1190 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 1191 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 1192 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 1193 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 1194 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 1195 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1196 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 1197 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 1198 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1199 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c 1200 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e 1201 1202 1203 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 1204 // base address: 0x0 1205 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 1206 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 1207 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 1208 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 1209 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 1210 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 1211 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a 1212 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b 1213 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c 1214 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d 1215 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e 1216 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f 1217 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 1218 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 1219 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 1220 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c 1221 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 1222 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 1223 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c 1224 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 1225 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 1226 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c 1227 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d 1228 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 1229 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 1230 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 1231 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c 1232 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e 1233 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 1234 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 1235 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 1236 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 1237 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c 1238 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e 1239 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 1240 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 1241 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 1242 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098 1243 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c 1244 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e 1245 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 1246 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 1247 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 1248 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 1249 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 1250 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac 1251 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac 1252 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 1253 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 1254 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 1255 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 1256 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 1257 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 1258 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 1259 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1260 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1261 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 1262 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 1263 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1264 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 1265 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 1266 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1267 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 1268 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 1269 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1270 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c 1271 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 1272 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 1273 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 1274 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 1275 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 1276 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 1277 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 1278 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1279 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 1280 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 1281 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1282 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c 1283 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e 1284 1285 1286 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 1287 // base address: 0x0 1288 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 1289 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 1290 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 1291 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 1292 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 1293 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 1294 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a 1295 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b 1296 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c 1297 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d 1298 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e 1299 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f 1300 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 1301 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 1302 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 1303 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c 1304 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 1305 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 1306 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c 1307 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 1308 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 1309 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c 1310 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d 1311 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 1312 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 1313 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 1314 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c 1315 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e 1316 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 1317 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 1318 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 1319 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 1320 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c 1321 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e 1322 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 1323 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 1324 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 1325 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098 1326 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c 1327 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e 1328 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 1329 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 1330 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 1331 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 1332 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 1333 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac 1334 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac 1335 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 1336 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 1337 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 1338 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 1339 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 1340 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 1341 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 1342 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1343 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1344 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 1345 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 1346 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1347 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 1348 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 1349 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1350 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 1351 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 1352 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1353 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c 1354 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 1355 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 1356 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 1357 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 1358 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 1359 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 1360 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 1361 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1362 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 1363 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 1364 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1365 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c 1366 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e 1367 1368 1369 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 1370 // base address: 0x0 1371 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 1372 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 1373 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 1374 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 1375 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 1376 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 1377 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a 1378 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b 1379 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c 1380 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d 1381 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e 1382 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f 1383 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 1384 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 1385 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 1386 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c 1387 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 1388 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 1389 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c 1390 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 1391 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 1392 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c 1393 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d 1394 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 1395 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 1396 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 1397 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c 1398 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e 1399 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 1400 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 1401 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 1402 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 1403 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c 1404 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e 1405 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 1406 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 1407 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 1408 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098 1409 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c 1410 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e 1411 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 1412 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 1413 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 1414 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 1415 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 1416 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac 1417 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac 1418 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 1419 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 1420 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 1421 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 1422 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 1423 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 1424 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 1425 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1426 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1427 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 1428 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c 1429 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1430 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 1431 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 1432 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1433 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 1434 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 1435 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1436 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c 1437 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 1438 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 1439 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 1440 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 1441 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c 1442 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 1443 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 1444 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1445 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 1446 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 1447 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1448 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c 1449 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e 1450 1451 1452 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 1453 // base address: 0x0 1454 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 1455 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 1456 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 1457 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 1458 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 1459 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 1460 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a 1461 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b 1462 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c 1463 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d 1464 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e 1465 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f 1466 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 1467 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 1468 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 1469 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c 1470 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 1471 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 1472 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c 1473 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 1474 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 1475 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c 1476 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d 1477 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 1478 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 1479 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 1480 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c 1481 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e 1482 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 1483 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 1484 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 1485 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 1486 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c 1487 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e 1488 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 1489 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 1490 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 1491 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098 1492 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c 1493 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e 1494 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 1495 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 1496 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 1497 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 1498 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 1499 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac 1500 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac 1501 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 1502 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 1503 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 1504 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 1505 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 1506 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 1507 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 1508 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1509 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1510 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 1511 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c 1512 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1513 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 1514 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 1515 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1516 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 1517 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 1518 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1519 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c 1520 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 1521 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 1522 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 1523 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 1524 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c 1525 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 1526 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 1527 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1528 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 1529 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 1530 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1531 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c 1532 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e 1533 1534 1535 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 1536 // base address: 0x0 1537 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 1538 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 1539 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 1540 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 1541 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 1542 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 1543 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a 1544 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b 1545 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c 1546 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d 1547 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e 1548 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f 1549 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 1550 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 1551 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 1552 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c 1553 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 1554 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 1555 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c 1556 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 1557 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 1558 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c 1559 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d 1560 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 1561 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 1562 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 1563 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c 1564 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e 1565 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 1566 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 1567 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 1568 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 1569 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c 1570 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e 1571 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 1572 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 1573 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 1574 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098 1575 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c 1576 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e 1577 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 1578 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 1579 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 1580 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 1581 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 1582 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac 1583 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac 1584 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 1585 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 1586 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 1587 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 1588 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 1589 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 1590 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 1591 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1592 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1593 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 1594 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c 1595 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1596 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 1597 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 1598 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1599 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 1600 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 1601 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1602 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c 1603 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 1604 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 1605 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 1606 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 1607 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c 1608 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 1609 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 1610 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1611 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 1612 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 1613 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1614 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c 1615 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e 1616 1617 1618 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 1619 // base address: 0x0 1620 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 1621 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 1622 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 1623 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 1624 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 1625 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 1626 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a 1627 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b 1628 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c 1629 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d 1630 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e 1631 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f 1632 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 1633 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 1634 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 1635 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c 1636 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 1637 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 1638 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c 1639 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 1640 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 1641 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c 1642 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d 1643 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 1644 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 1645 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 1646 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c 1647 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e 1648 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 1649 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 1650 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 1651 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 1652 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c 1653 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e 1654 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 1655 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 1656 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 1657 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098 1658 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c 1659 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e 1660 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 1661 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 1662 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 1663 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 1664 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 1665 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac 1666 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac 1667 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 1668 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 1669 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 1670 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 1671 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 1672 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 1673 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 1674 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1675 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1676 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 1677 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c 1678 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1679 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 1680 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 1681 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1682 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 1683 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 1684 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1685 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c 1686 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 1687 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 1688 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 1689 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 1690 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c 1691 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 1692 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 1693 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1694 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 1695 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 1696 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1697 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c 1698 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e 1699 1700 1701 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 1702 // base address: 0x0 1703 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 1704 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 1705 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 1706 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 1707 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 1708 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 1709 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a 1710 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b 1711 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c 1712 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d 1713 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e 1714 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f 1715 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 1716 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 1717 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 1718 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c 1719 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 1720 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 1721 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c 1722 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 1723 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 1724 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c 1725 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d 1726 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 1727 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 1728 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 1729 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c 1730 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e 1731 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 1732 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 1733 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 1734 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 1735 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c 1736 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e 1737 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 1738 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 1739 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 1740 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098 1741 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c 1742 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e 1743 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 1744 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 1745 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 1746 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 1747 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 1748 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac 1749 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac 1750 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 1751 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 1752 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 1753 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 1754 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 1755 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 1756 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 1757 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1758 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1759 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 1760 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c 1761 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1762 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 1763 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 1764 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1765 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 1766 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 1767 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1768 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c 1769 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 1770 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 1771 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 1772 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 1773 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c 1774 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 1775 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 1776 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1777 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 1778 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 1779 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1780 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c 1781 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e 1782 1783 1784 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 1785 // base address: 0x0 1786 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 1787 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 1788 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 1789 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 1790 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 1791 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 1792 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a 1793 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b 1794 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c 1795 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d 1796 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e 1797 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f 1798 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 1799 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 1800 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 1801 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c 1802 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 1803 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 1804 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c 1805 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 1806 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 1807 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c 1808 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d 1809 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 1810 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 1811 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 1812 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c 1813 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e 1814 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 1815 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 1816 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 1817 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 1818 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c 1819 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e 1820 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 1821 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 1822 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 1823 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098 1824 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c 1825 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e 1826 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 1827 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 1828 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 1829 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 1830 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 1831 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac 1832 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac 1833 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 1834 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 1835 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 1836 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 1837 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 1838 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 1839 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 1840 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1841 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1842 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 1843 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c 1844 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1845 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 1846 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 1847 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1848 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 1849 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 1850 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1851 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c 1852 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 1853 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 1854 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 1855 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 1856 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c 1857 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 1858 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 1859 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1860 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 1861 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 1862 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1863 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c 1864 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e 1865 1866 1867 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 1868 // base address: 0x0 1869 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 1870 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 1871 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 1872 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 1873 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 1874 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 1875 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a 1876 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b 1877 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c 1878 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d 1879 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e 1880 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f 1881 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 1882 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 1883 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 1884 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c 1885 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 1886 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 1887 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c 1888 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 1889 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 1890 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c 1891 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d 1892 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 1893 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 1894 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 1895 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c 1896 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e 1897 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 1898 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 1899 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 1900 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 1901 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c 1902 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e 1903 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 1904 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 1905 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 1906 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098 1907 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c 1908 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e 1909 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 1910 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 1911 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 1912 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 1913 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 1914 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac 1915 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac 1916 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 1917 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 1918 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 1919 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 1920 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 1921 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 1922 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 1923 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1924 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1925 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 1926 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c 1927 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1928 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 1929 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 1930 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1931 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 1932 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 1933 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1934 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c 1935 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 1936 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 1937 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 1938 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 1939 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c 1940 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 1941 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 1942 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1943 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 1944 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 1945 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1946 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c 1947 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e 1948 1949 1950 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 1951 // base address: 0x0 1952 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 1953 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 1954 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 1955 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 1956 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 1957 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 1958 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a 1959 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b 1960 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c 1961 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d 1962 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e 1963 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f 1964 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 1965 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 1966 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 1967 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c 1968 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 1969 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 1970 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c 1971 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 1972 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 1973 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c 1974 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d 1975 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 1976 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 1977 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 1978 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c 1979 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e 1980 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 1981 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 1982 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 1983 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 1984 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c 1985 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e 1986 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 1987 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 1988 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 1989 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098 1990 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c 1991 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e 1992 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 1993 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 1994 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 1995 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 1996 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 1997 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac 1998 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac 1999 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 2000 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 2001 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 2002 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 2003 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 2004 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 2005 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 2006 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2007 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2008 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 2009 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c 2010 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2011 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 2012 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 2013 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2014 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 2015 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 2016 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2017 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c 2018 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 2019 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 2020 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 2021 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 2022 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c 2023 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 2024 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 2025 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2026 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 2027 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 2028 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2029 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c 2030 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e 2031 2032 2033 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 2034 // base address: 0x0 2035 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 2036 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 2037 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 2038 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 2039 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 2040 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 2041 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a 2042 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b 2043 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c 2044 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d 2045 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e 2046 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f 2047 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 2048 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 2049 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 2050 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c 2051 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 2052 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 2053 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c 2054 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 2055 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 2056 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c 2057 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d 2058 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 2059 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 2060 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 2061 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c 2062 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e 2063 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 2064 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 2065 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 2066 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 2067 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c 2068 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e 2069 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 2070 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 2071 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 2072 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098 2073 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c 2074 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e 2075 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 2076 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 2077 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 2078 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 2079 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 2080 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac 2081 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac 2082 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 2083 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 2084 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 2085 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 2086 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 2087 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 2088 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 2089 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2090 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2091 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 2092 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c 2093 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2094 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 2095 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 2096 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2097 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 2098 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 2099 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2100 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c 2101 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 2102 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 2103 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 2104 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 2105 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c 2106 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 2107 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 2108 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2109 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 2110 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 2111 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2112 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c 2113 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e 2114 2115 2116 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 2117 // base address: 0x0 2118 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 2119 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 2120 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 2121 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 2122 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 2123 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 2124 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a 2125 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b 2126 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c 2127 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d 2128 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e 2129 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f 2130 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 2131 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 2132 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 2133 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c 2134 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 2135 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 2136 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c 2137 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 2138 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 2139 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c 2140 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d 2141 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 2142 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 2143 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 2144 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c 2145 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e 2146 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 2147 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 2148 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 2149 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 2150 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c 2151 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e 2152 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 2153 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 2154 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 2155 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098 2156 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c 2157 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e 2158 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 2159 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 2160 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 2161 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 2162 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 2163 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac 2164 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac 2165 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 2166 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 2167 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 2168 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 2169 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 2170 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 2171 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 2172 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2173 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2174 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 2175 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c 2176 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2177 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 2178 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 2179 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2180 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 2181 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 2182 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2183 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c 2184 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 2185 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 2186 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 2187 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 2188 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c 2189 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 2190 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 2191 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2192 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 2193 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 2194 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2195 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c 2196 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e 2197 2198 2199 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 2200 // base address: 0x0 2201 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 2202 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 2203 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 2204 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 2205 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 2206 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 2207 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a 2208 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b 2209 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c 2210 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d 2211 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e 2212 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f 2213 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 2214 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 2215 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 2216 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c 2217 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 2218 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 2219 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c 2220 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 2221 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 2222 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c 2223 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d 2224 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 2225 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 2226 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 2227 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c 2228 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e 2229 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 2230 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 2231 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 2232 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 2233 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c 2234 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e 2235 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 2236 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 2237 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 2238 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098 2239 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c 2240 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e 2241 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 2242 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 2243 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 2244 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 2245 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 2246 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac 2247 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac 2248 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 2249 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 2250 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 2251 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 2252 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 2253 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 2254 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 2255 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2256 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2257 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 2258 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c 2259 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2260 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 2261 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 2262 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2263 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 2264 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 2265 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2266 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c 2267 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 2268 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 2269 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 2270 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 2271 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c 2272 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 2273 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 2274 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2275 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 2276 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 2277 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2278 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c 2279 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e 2280 2281 2282 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 2283 // base address: 0x0 2284 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 2285 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 2286 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 2287 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 2288 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 2289 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 2290 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a 2291 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b 2292 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c 2293 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d 2294 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e 2295 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f 2296 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 2297 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 2298 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 2299 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c 2300 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 2301 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 2302 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c 2303 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 2304 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 2305 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c 2306 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d 2307 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 2308 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 2309 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 2310 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c 2311 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e 2312 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 2313 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 2314 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 2315 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 2316 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c 2317 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e 2318 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 2319 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 2320 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 2321 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098 2322 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c 2323 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e 2324 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 2325 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 2326 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 2327 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 2328 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 2329 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac 2330 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac 2331 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 2332 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 2333 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 2334 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 2335 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 2336 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 2337 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 2338 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2339 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2340 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 2341 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c 2342 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2343 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 2344 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 2345 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2346 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 2347 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 2348 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2349 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c 2350 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 2351 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 2352 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 2353 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 2354 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c 2355 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 2356 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 2357 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2358 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 2359 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 2360 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2361 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c 2362 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e 2363 2364 2365 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 2366 // base address: 0x0 2367 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 2368 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 2369 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 2370 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 2371 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 2372 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 2373 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a 2374 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b 2375 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c 2376 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d 2377 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e 2378 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f 2379 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 2380 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 2381 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 2382 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c 2383 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 2384 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 2385 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c 2386 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 2387 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 2388 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c 2389 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d 2390 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 2391 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 2392 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 2393 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c 2394 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e 2395 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 2396 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 2397 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 2398 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 2399 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c 2400 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e 2401 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 2402 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 2403 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 2404 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098 2405 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c 2406 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e 2407 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 2408 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 2409 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 2410 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 2411 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 2412 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac 2413 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac 2414 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 2415 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 2416 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 2417 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 2418 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 2419 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 2420 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 2421 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2422 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2423 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 2424 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c 2425 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2426 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 2427 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 2428 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2429 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 2430 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 2431 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2432 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c 2433 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 2434 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 2435 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 2436 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 2437 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c 2438 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 2439 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 2440 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2441 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 2442 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 2443 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2444 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c 2445 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e 2446 2447 2448 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 2449 // base address: 0x0 2450 #define mmMM_INDEX 0x0000 2451 #define mmMM_INDEX_BASE_IDX 0 2452 #define mmMM_DATA 0x0001 2453 #define mmMM_DATA_BASE_IDX 0 2454 #define mmMM_INDEX_HI 0x0006 2455 #define mmMM_INDEX_HI_BASE_IDX 0 2456 2457 2458 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 2459 // base address: 0x0 2460 #define mmSYSHUB_INDEX_OVLP 0x0008 2461 #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 2462 #define mmSYSHUB_DATA_OVLP 0x0009 2463 #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 2464 #define mmPCIE_INDEX 0x000c 2465 #define mmPCIE_INDEX_BASE_IDX 0 2466 #define mmPCIE_DATA 0x000d 2467 #define mmPCIE_DATA_BASE_IDX 0 2468 #define mmPCIE_INDEX2 0x000e 2469 #define mmPCIE_INDEX2_BASE_IDX 0 2470 #define mmPCIE_DATA2 0x000f 2471 #define mmPCIE_DATA2_BASE_IDX 0 2472 #define mmSBIOS_SCRATCH_0 0x0034 2473 #define mmSBIOS_SCRATCH_0_BASE_IDX 1 2474 #define mmSBIOS_SCRATCH_1 0x0035 2475 #define mmSBIOS_SCRATCH_1_BASE_IDX 1 2476 #define mmSBIOS_SCRATCH_2 0x0036 2477 #define mmSBIOS_SCRATCH_2_BASE_IDX 1 2478 #define mmSBIOS_SCRATCH_3 0x0037 2479 #define mmSBIOS_SCRATCH_3_BASE_IDX 1 2480 #define mmBIOS_SCRATCH_0 0x0038 2481 #define mmBIOS_SCRATCH_0_BASE_IDX 1 2482 #define mmBIOS_SCRATCH_1 0x0039 2483 #define mmBIOS_SCRATCH_1_BASE_IDX 1 2484 #define mmBIOS_SCRATCH_2 0x003a 2485 #define mmBIOS_SCRATCH_2_BASE_IDX 1 2486 #define mmBIOS_SCRATCH_3 0x003b 2487 #define mmBIOS_SCRATCH_3_BASE_IDX 1 2488 #define mmBIOS_SCRATCH_4 0x003c 2489 #define mmBIOS_SCRATCH_4_BASE_IDX 1 2490 #define mmBIOS_SCRATCH_5 0x003d 2491 #define mmBIOS_SCRATCH_5_BASE_IDX 1 2492 #define mmBIOS_SCRATCH_6 0x003e 2493 #define mmBIOS_SCRATCH_6_BASE_IDX 1 2494 #define mmBIOS_SCRATCH_7 0x003f 2495 #define mmBIOS_SCRATCH_7_BASE_IDX 1 2496 #define mmBIOS_SCRATCH_8 0x0040 2497 #define mmBIOS_SCRATCH_8_BASE_IDX 1 2498 #define mmBIOS_SCRATCH_9 0x0041 2499 #define mmBIOS_SCRATCH_9_BASE_IDX 1 2500 #define mmBIOS_SCRATCH_10 0x0042 2501 #define mmBIOS_SCRATCH_10_BASE_IDX 1 2502 #define mmBIOS_SCRATCH_11 0x0043 2503 #define mmBIOS_SCRATCH_11_BASE_IDX 1 2504 #define mmBIOS_SCRATCH_12 0x0044 2505 #define mmBIOS_SCRATCH_12_BASE_IDX 1 2506 #define mmBIOS_SCRATCH_13 0x0045 2507 #define mmBIOS_SCRATCH_13_BASE_IDX 1 2508 #define mmBIOS_SCRATCH_14 0x0046 2509 #define mmBIOS_SCRATCH_14_BASE_IDX 1 2510 #define mmBIOS_SCRATCH_15 0x0047 2511 #define mmBIOS_SCRATCH_15_BASE_IDX 1 2512 #define mmBIF_RLC_INTR_CNTL 0x004c 2513 #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 2514 #define mmBIF_VCE_INTR_CNTL 0x004d 2515 #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 2516 #define mmBIF_UVD_INTR_CNTL 0x004e 2517 #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 2518 #define mmGFX_MMIOREG_CAM_ADDR0 0x006c 2519 #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 2520 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 2521 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 2522 #define mmGFX_MMIOREG_CAM_ADDR1 0x006e 2523 #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 2524 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 2525 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 2526 #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 2527 #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 2528 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 2529 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 2530 #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 2531 #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 2532 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 2533 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 2534 #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 2535 #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 2536 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 2537 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 2538 #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 2539 #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 2540 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 2541 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 2542 #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 2543 #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 2544 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 2545 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 2546 #define mmGFX_MMIOREG_CAM_ADDR7 0x007a 2547 #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 2548 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 2549 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 2550 #define mmGFX_MMIOREG_CAM_CNTL 0x007c 2551 #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 2552 #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d 2553 #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 2554 #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e 2555 #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 2556 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 2557 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 2558 2559 2560 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec 2561 // base address: 0x0 2562 #define mmSYSHUB_INDEX 0x0008 2563 #define mmSYSHUB_INDEX_BASE_IDX 0 2564 #define mmSYSHUB_DATA 0x0009 2565 #define mmSYSHUB_DATA_BASE_IDX 0 2566 2567 2568 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 2569 // base address: 0x0 2570 #define mmRCC_BIF_STRAP0 0x0000 2571 #define mmRCC_BIF_STRAP0_BASE_IDX 2 2572 #define mmRCC_DEV0_EPF0_STRAP0 0x0011 2573 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 2574 2575 2576 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 2577 // base address: 0x0 2578 #define mmEP_PCIE_SCRATCH 0x0025 2579 #define mmEP_PCIE_SCRATCH_BASE_IDX 2 2580 #define mmEP_PCIE_CNTL 0x0027 2581 #define mmEP_PCIE_CNTL_BASE_IDX 2 2582 #define mmEP_PCIE_INT_CNTL 0x0028 2583 #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 2584 #define mmEP_PCIE_INT_STATUS 0x0029 2585 #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 2586 #define mmEP_PCIE_RX_CNTL2 0x002a 2587 #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 2588 #define mmEP_PCIE_BUS_CNTL 0x002b 2589 #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 2590 #define mmEP_PCIE_CFG_CNTL 0x002c 2591 #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 2592 #define mmEP_PCIE_TX_LTR_CNTL 0x002e 2593 #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 2594 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002f 2595 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2596 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002f 2597 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2598 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002f 2599 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2600 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002f 2601 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2602 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0030 2603 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2604 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0030 2605 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2606 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0030 2607 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2608 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0030 2609 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2610 #define mmEP_PCIE_F0_DPA_CAP 0x0034 2611 #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 2612 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0035 2613 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 2614 #define mmEP_PCIE_F0_DPA_CNTL 0x0035 2615 #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 2616 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0035 2617 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2618 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0036 2619 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2620 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0036 2621 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2622 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0036 2623 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2624 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0036 2625 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2626 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0037 2627 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2628 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0037 2629 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2630 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0037 2631 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2632 #define mmEP_PCIE_PME_CONTROL 0x0037 2633 #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 2634 #define mmEP_PCIEP_RESERVED 0x0038 2635 #define mmEP_PCIEP_RESERVED_BASE_IDX 2 2636 #define mmEP_PCIE_TX_CNTL 0x003a 2637 #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 2638 #define mmEP_PCIE_TX_REQUESTER_ID 0x003b 2639 #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 2640 #define mmEP_PCIE_ERR_CNTL 0x003c 2641 #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 2642 #define mmEP_PCIE_RX_CNTL 0x003d 2643 #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 2644 #define mmEP_PCIE_LC_SPEED_CNTL 0x003e 2645 #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 2646 2647 2648 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 2649 // base address: 0x0 2650 #define mmDN_PCIE_RESERVED 0x0040 2651 #define mmDN_PCIE_RESERVED_BASE_IDX 2 2652 #define mmDN_PCIE_SCRATCH 0x0041 2653 #define mmDN_PCIE_SCRATCH_BASE_IDX 2 2654 #define mmDN_PCIE_CNTL 0x0043 2655 #define mmDN_PCIE_CNTL_BASE_IDX 2 2656 #define mmDN_PCIE_CONFIG_CNTL 0x0044 2657 #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 2658 #define mmDN_PCIE_RX_CNTL2 0x0045 2659 #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 2660 #define mmDN_PCIE_BUS_CNTL 0x0046 2661 #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 2662 #define mmDN_PCIE_CFG_CNTL 0x0047 2663 #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 2664 2665 2666 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 2667 // base address: 0x0 2668 #define mmPCIE_ERR_CNTL 0x004f 2669 #define mmPCIE_ERR_CNTL_BASE_IDX 2 2670 #define mmPCIE_RX_CNTL 0x0050 2671 #define mmPCIE_RX_CNTL_BASE_IDX 2 2672 #define mmPCIE_LC_SPEED_CNTL 0x0051 2673 #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 2674 #define mmPCIE_LC_CNTL2 0x0052 2675 #define mmPCIE_LC_CNTL2_BASE_IDX 2 2676 #define mmLTR_MSG_INFO_FROM_EP 0x0054 2677 #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 2678 2679 2680 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 2681 // base address: 0x3480 2682 #define mmRCC_ERR_LOG 0x0085 2683 #define mmRCC_ERR_LOG_BASE_IDX 2 2684 #define mmRCC_DOORBELL_APER_EN 0x00c0 2685 #define mmRCC_DOORBELL_APER_EN_BASE_IDX 2 2686 #define mmRCC_CONFIG_MEMSIZE 0x00c3 2687 #define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2 2688 #define mmRCC_CONFIG_RESERVED 0x00c4 2689 #define mmRCC_CONFIG_RESERVED_BASE_IDX 2 2690 #define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5 2691 #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2692 2693 2694 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 2695 // base address: 0x0 2696 #define mmRCC_ERR_INT_CNTL 0x0086 2697 #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 2698 #define mmRCC_BACO_CNTL_MISC 0x0087 2699 #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 2700 #define mmRCC_RESET_EN 0x0088 2701 #define mmRCC_RESET_EN_BASE_IDX 2 2702 #define mmRCC_VDM_SUPPORT 0x0089 2703 #define mmRCC_VDM_SUPPORT_BASE_IDX 2 2704 #define mmRCC_MARGIN_PARAM_CNTL0 0x008a 2705 #define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 2706 #define mmRCC_MARGIN_PARAM_CNTL1 0x008b 2707 #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 2708 #define mmRCC_PEER_REG_RANGE0 0x00be 2709 #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 2710 #define mmRCC_PEER_REG_RANGE1 0x00bf 2711 #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 2712 #define mmRCC_BUS_CNTL 0x00c1 2713 #define mmRCC_BUS_CNTL_BASE_IDX 2 2714 #define mmRCC_CONFIG_CNTL 0x00c2 2715 #define mmRCC_CONFIG_CNTL_BASE_IDX 2 2716 #define mmRCC_CONFIG_F0_BASE 0x00c6 2717 #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 2718 #define mmRCC_CONFIG_APER_SIZE 0x00c7 2719 #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 2720 #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 2721 #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 2722 #define mmRCC_XDMA_LO 0x00c9 2723 #define mmRCC_XDMA_LO_BASE_IDX 2 2724 #define mmRCC_XDMA_HI 0x00ca 2725 #define mmRCC_XDMA_HI_BASE_IDX 2 2726 #define mmRCC_FEATURES_CONTROL_MISC 0x00cb 2727 #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 2728 #define mmRCC_BUSNUM_CNTL1 0x00cc 2729 #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 2730 #define mmRCC_BUSNUM_LIST0 0x00cd 2731 #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 2732 #define mmRCC_BUSNUM_LIST1 0x00ce 2733 #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 2734 #define mmRCC_BUSNUM_CNTL2 0x00cf 2735 #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 2736 #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 2737 #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 2738 #define mmRCC_HOST_BUSNUM 0x00d1 2739 #define mmRCC_HOST_BUSNUM_BASE_IDX 2 2740 #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 2741 #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 2742 #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 2743 #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 2744 #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 2745 #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 2746 #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 2747 #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 2748 #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 2749 #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 2750 #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 2751 #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 2752 #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 2753 #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 2754 #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 2755 #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 2756 #define mmRCC_CMN_LINK_CNTL 0x00de 2757 #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 2758 #define mmRCC_EP_REQUESTERID_RESTORE 0x00df 2759 #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 2760 #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 2761 #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 2762 #define mmRCC_MH_ARB_CNTL 0x00e1 2763 #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 2764 2765 2766 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 2767 // base address: 0x0 2768 #define mmBIF_MM_INDACCESS_CNTL 0x00e6 2769 #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 2770 #define mmBUS_CNTL 0x00e7 2771 #define mmBUS_CNTL_BASE_IDX 2 2772 #define mmBIF_SCRATCH0 0x00e8 2773 #define mmBIF_SCRATCH0_BASE_IDX 2 2774 #define mmBIF_SCRATCH1 0x00e9 2775 #define mmBIF_SCRATCH1_BASE_IDX 2 2776 #define mmBX_RESET_EN 0x00ed 2777 #define mmBX_RESET_EN_BASE_IDX 2 2778 #define mmMM_CFGREGS_CNTL 0x00ee 2779 #define mmMM_CFGREGS_CNTL_BASE_IDX 2 2780 #define mmBX_RESET_CNTL 0x00f0 2781 #define mmBX_RESET_CNTL_BASE_IDX 2 2782 #define mmINTERRUPT_CNTL 0x00f1 2783 #define mmINTERRUPT_CNTL_BASE_IDX 2 2784 #define mmINTERRUPT_CNTL2 0x00f2 2785 #define mmINTERRUPT_CNTL2_BASE_IDX 2 2786 #define mmCLKREQB_PAD_CNTL 0x00f8 2787 #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 2788 #define mmBIF_FEATURES_CONTROL_MISC 0x00fb 2789 #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 2790 #define mmBIF_DOORBELL_CNTL 0x00fc 2791 #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 2792 #define mmBIF_DOORBELL_INT_CNTL 0x00fd 2793 #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 2794 #define mmBIF_FB_EN 0x00ff 2795 #define mmBIF_FB_EN_BASE_IDX 2 2796 #define mmBIF_BUSY_DELAY_CNTR 0x0100 2797 #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2 2798 #define mmBIF_MST_TRANS_PENDING_VF 0x0109 2799 #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 2800 #define mmBIF_SLV_TRANS_PENDING_VF 0x010a 2801 #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 2802 #define mmBACO_CNTL 0x010b 2803 #define mmBACO_CNTL_BASE_IDX 2 2804 #define mmBIF_BACO_EXIT_TIME0 0x010c 2805 #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 2806 #define mmBIF_BACO_EXIT_TIMER1 0x010d 2807 #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 2808 #define mmBIF_BACO_EXIT_TIMER2 0x010e 2809 #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 2810 #define mmBIF_BACO_EXIT_TIMER3 0x010f 2811 #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 2812 #define mmBIF_BACO_EXIT_TIMER4 0x0110 2813 #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 2814 #define mmMEM_TYPE_CNTL 0x0111 2815 #define mmMEM_TYPE_CNTL_BASE_IDX 2 2816 #define mmNBIF_GFX_ADDR_LUT_CNTL 0x0113 2817 #define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 2818 #define mmNBIF_GFX_ADDR_LUT_0 0x0114 2819 #define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX 2 2820 #define mmNBIF_GFX_ADDR_LUT_1 0x0115 2821 #define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX 2 2822 #define mmNBIF_GFX_ADDR_LUT_2 0x0116 2823 #define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX 2 2824 #define mmNBIF_GFX_ADDR_LUT_3 0x0117 2825 #define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX 2 2826 #define mmNBIF_GFX_ADDR_LUT_4 0x0118 2827 #define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX 2 2828 #define mmNBIF_GFX_ADDR_LUT_5 0x0119 2829 #define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX 2 2830 #define mmNBIF_GFX_ADDR_LUT_6 0x011a 2831 #define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX 2 2832 #define mmNBIF_GFX_ADDR_LUT_7 0x011b 2833 #define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX 2 2834 #define mmNBIF_GFX_ADDR_LUT_8 0x011c 2835 #define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX 2 2836 #define mmNBIF_GFX_ADDR_LUT_9 0x011d 2837 #define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX 2 2838 #define mmNBIF_GFX_ADDR_LUT_10 0x011e 2839 #define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX 2 2840 #define mmNBIF_GFX_ADDR_LUT_11 0x011f 2841 #define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX 2 2842 #define mmNBIF_GFX_ADDR_LUT_12 0x0120 2843 #define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX 2 2844 #define mmNBIF_GFX_ADDR_LUT_13 0x0121 2845 #define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX 2 2846 #define mmNBIF_GFX_ADDR_LUT_14 0x0122 2847 #define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX 2 2848 #define mmNBIF_GFX_ADDR_LUT_15 0x0123 2849 #define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX 2 2850 #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d 2851 #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 2852 #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e 2853 #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 2854 #define mmBIF_RB_CNTL 0x012f 2855 #define mmBIF_RB_CNTL_BASE_IDX 2 2856 #define mmBIF_RB_BASE 0x0130 2857 #define mmBIF_RB_BASE_BASE_IDX 2 2858 #define mmBIF_RB_RPTR 0x0131 2859 #define mmBIF_RB_RPTR_BASE_IDX 2 2860 #define mmBIF_RB_WPTR 0x0132 2861 #define mmBIF_RB_WPTR_BASE_IDX 2 2862 #define mmBIF_RB_WPTR_ADDR_HI 0x0133 2863 #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 2864 #define mmBIF_RB_WPTR_ADDR_LO 0x0134 2865 #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 2866 #define mmMAILBOX_INDEX 0x0135 2867 #define mmMAILBOX_INDEX_BASE_IDX 2 2868 #define mmBIF_MP1_INTR_CTRL 0x0142 2869 #define mmBIF_MP1_INTR_CTRL_BASE_IDX 2 2870 #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 2871 #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 2872 #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 2873 #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 2874 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 2875 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 2876 #define mmBIF_PERSTB_PAD_CNTL 0x0148 2877 #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 2878 #define mmBIF_PX_EN_PAD_CNTL 0x0149 2879 #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 2880 #define mmBIF_REFPADKIN_PAD_CNTL 0x014a 2881 #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 2882 #define mmBIF_CLKREQB_PAD_CNTL 0x014b 2883 #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 2884 #define mmBIF_PWRBRK_PAD_CNTL 0x014c 2885 #define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX 2 2886 #define mmBIF_WAKEB_PAD_CNTL 0x014d 2887 #define mmBIF_WAKEB_PAD_CNTL_BASE_IDX 2 2888 2889 2890 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 2891 // base address: 0x0 2892 #define mmBIF_BME_STATUS 0x00eb 2893 #define mmBIF_BME_STATUS_BASE_IDX 2 2894 #define mmBIF_ATOMIC_ERR_LOG 0x00ec 2895 #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 2 2896 #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2897 #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2898 #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2899 #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2900 #define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2901 #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2902 #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2903 #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2904 #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2905 #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2906 #define mmGPU_HDP_FLUSH_REQ 0x0106 2907 #define mmGPU_HDP_FLUSH_REQ_BASE_IDX 2 2908 #define mmGPU_HDP_FLUSH_DONE 0x0107 2909 #define mmGPU_HDP_FLUSH_DONE_BASE_IDX 2 2910 #define mmBIF_TRANS_PENDING 0x0108 2911 #define mmBIF_TRANS_PENDING_BASE_IDX 2 2912 #define mmNBIF_GFX_ADDR_LUT_BYPASS 0x0112 2913 #define mmNBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2914 #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 2915 #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2916 #define mmMAILBOX_MSGBUF_TRN_DW1 0x0137 2917 #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2918 #define mmMAILBOX_MSGBUF_TRN_DW2 0x0138 2919 #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2920 #define mmMAILBOX_MSGBUF_TRN_DW3 0x0139 2921 #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2922 #define mmMAILBOX_MSGBUF_RCV_DW0 0x013a 2923 #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2924 #define mmMAILBOX_MSGBUF_RCV_DW1 0x013b 2925 #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2926 #define mmMAILBOX_MSGBUF_RCV_DW2 0x013c 2927 #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2928 #define mmMAILBOX_MSGBUF_RCV_DW3 0x013d 2929 #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2930 #define mmMAILBOX_CONTROL 0x013e 2931 #define mmMAILBOX_CONTROL_BASE_IDX 2 2932 #define mmMAILBOX_INT_CNTL 0x013f 2933 #define mmMAILBOX_INT_CNTL_BASE_IDX 2 2934 #define mmBIF_VMHV_MAILBOX 0x0140 2935 #define mmBIF_VMHV_MAILBOX_BASE_IDX 2 2936 2937 2938 // addressBlock: nbio_nbif0_gdc_GDCDEC 2939 // base address: 0x0 2940 #define mmNGDC_SDP_PORT_CTRL 0x01c2 2941 #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 2942 #define mmSHUB_REGS_IF_CTL 0x01c3 2943 #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 2944 #define mmNGDC_MGCG_CTRL 0x01ca 2945 #define mmNGDC_MGCG_CTRL_BASE_IDX 2 2946 #define mmNGDC_RESERVED_0 0x01cb 2947 #define mmNGDC_RESERVED_0_BASE_IDX 2 2948 #define mmNGDC_RESERVED_1 0x01cc 2949 #define mmNGDC_RESERVED_1_BASE_IDX 2 2950 #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd 2951 #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 2952 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 2953 #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 2954 #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 2955 #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 2956 #define mmBIF_IH_DOORBELL_RANGE 0x01d2 2957 #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 2958 #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 2959 #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 2960 #define mmBIF_ACV_DOORBELL_RANGE 0x01d4 2961 #define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX 2 2962 #define mmBIF_DOORBELL_FENCE_CNTL 0x01de 2963 #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 2964 #define mmS2A_MISC_CNTL 0x01df 2965 #define mmS2A_MISC_CNTL_BASE_IDX 2 2966 2967 2968 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 2969 // base address: 0x0 2970 #define mmGFXMSIX_VECT0_ADDR_LO 0x0400 2971 #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2972 #define mmGFXMSIX_VECT0_ADDR_HI 0x0401 2973 #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2974 #define mmGFXMSIX_VECT0_MSG_DATA 0x0402 2975 #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2976 #define mmGFXMSIX_VECT0_CONTROL 0x0403 2977 #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 3 2978 #define mmGFXMSIX_VECT1_ADDR_LO 0x0404 2979 #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2980 #define mmGFXMSIX_VECT1_ADDR_HI 0x0405 2981 #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2982 #define mmGFXMSIX_VECT1_MSG_DATA 0x0406 2983 #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2984 #define mmGFXMSIX_VECT1_CONTROL 0x0407 2985 #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 3 2986 #define mmGFXMSIX_VECT2_ADDR_LO 0x0408 2987 #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2988 #define mmGFXMSIX_VECT2_ADDR_HI 0x0409 2989 #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2990 #define mmGFXMSIX_VECT2_MSG_DATA 0x040a 2991 #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2992 #define mmGFXMSIX_VECT2_CONTROL 0x040b 2993 #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 3 2994 #define mmGFXMSIX_PBA 0x0800 2995 #define mmGFXMSIX_PBA_BASE_IDX 3 2996 2997 2998 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 2999 // base address: 0x0 3000 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 3001 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 3002 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 3003 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 3004 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 3005 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 3006 3007 3008 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 3009 // base address: 0x0 3010 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 3011 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 3012 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 3013 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 3014 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 3015 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3016 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 3017 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 3018 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3019 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3020 3021 3022 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 3023 // base address: 0x0 3024 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 3025 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 3026 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 3027 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3028 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3029 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3030 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3031 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3032 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3033 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3034 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3035 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3036 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3037 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3038 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 3039 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3040 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 3041 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3042 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 3043 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 3044 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3045 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3046 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 3047 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3048 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 3049 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3050 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 3051 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3052 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 3053 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3054 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 3055 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3056 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 3057 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3058 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 3059 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3060 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 3061 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3062 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 3063 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 3064 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 3065 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 3066 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 3067 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 3068 3069 3070 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 3071 // base address: 0x0 3072 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 3073 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3074 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 3075 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3076 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 3077 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3078 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 3079 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3080 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 3081 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3082 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 3083 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3084 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 3085 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3086 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 3087 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3088 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 3089 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3090 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 3091 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3092 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a 3093 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3094 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b 3095 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3096 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 3097 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 3098 3099 3100 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 3101 // base address: 0x0 3102 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 3103 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 3104 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 3105 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 3106 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 3107 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 3108 3109 3110 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 3111 // base address: 0x0 3112 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 3113 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 3114 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 3115 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 3116 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 3117 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3118 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 3119 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 3120 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3121 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3122 3123 3124 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 3125 // base address: 0x0 3126 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 3127 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 3128 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 3129 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3130 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3131 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3132 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3133 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3134 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3135 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3136 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3137 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3138 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3139 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3140 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 3141 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3142 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 3143 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3144 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 3145 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 3146 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3147 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3148 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 3149 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3150 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 3151 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3152 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 3153 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3154 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 3155 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3156 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 3157 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3158 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 3159 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3160 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 3161 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3162 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 3163 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3164 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 3165 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 3166 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 3167 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 3168 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 3169 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 3170 3171 3172 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 3173 // base address: 0x0 3174 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 3175 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3176 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 3177 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3178 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 3179 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3180 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 3181 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3182 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 3183 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3184 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 3185 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3186 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 3187 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3188 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 3189 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3190 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 3191 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3192 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 3193 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3194 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a 3195 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3196 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b 3197 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3198 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 3199 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 3200 3201 3202 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 3203 // base address: 0x0 3204 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 3205 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 3206 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 3207 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 3208 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 3209 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 3210 3211 3212 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 3213 // base address: 0x0 3214 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 3215 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 3216 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 3217 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 3218 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 3219 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3220 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 3221 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 3222 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3223 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3224 3225 3226 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 3227 // base address: 0x0 3228 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 3229 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 3230 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 3231 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3232 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3233 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3234 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3235 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3236 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3237 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3238 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3239 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3240 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3241 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3242 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 3243 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3244 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 3245 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3246 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 3247 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 3248 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3249 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3250 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 3251 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3252 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 3253 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3254 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 3255 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3256 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 3257 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3258 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 3259 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3260 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 3261 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3262 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 3263 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3264 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 3265 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3266 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 3267 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 3268 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 3269 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 3270 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 3271 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 3272 3273 3274 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 3275 // base address: 0x0 3276 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 3277 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3278 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 3279 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3280 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 3281 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3282 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 3283 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3284 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 3285 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3286 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 3287 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3288 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 3289 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3290 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 3291 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3292 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 3293 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3294 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 3295 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3296 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a 3297 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3298 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b 3299 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3300 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 3301 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 3302 3303 3304 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 3305 // base address: 0x0 3306 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 3307 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 3308 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 3309 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 3310 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 3311 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 3312 3313 3314 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 3315 // base address: 0x0 3316 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 3317 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 3318 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 3319 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 3320 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 3321 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3322 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 3323 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 3324 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3325 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3326 3327 3328 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 3329 // base address: 0x0 3330 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 3331 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 3332 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 3333 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3334 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3335 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3336 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3337 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3338 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3339 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3340 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3341 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3342 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3343 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3344 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 3345 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3346 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 3347 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3348 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 3349 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 3350 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3351 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3352 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 3353 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3354 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 3355 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3356 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 3357 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3358 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 3359 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3360 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 3361 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3362 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 3363 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3364 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 3365 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3366 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 3367 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3368 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 3369 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 3370 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 3371 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 3372 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 3373 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 3374 3375 3376 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 3377 // base address: 0x0 3378 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 3379 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3380 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 3381 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3382 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 3383 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3384 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 3385 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3386 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 3387 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3388 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 3389 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3390 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 3391 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3392 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 3393 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3394 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 3395 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3396 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 3397 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3398 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a 3399 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3400 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b 3401 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3402 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 3403 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 3404 3405 3406 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 3407 // base address: 0x0 3408 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 3409 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 3410 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 3411 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 3412 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 3413 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 3414 3415 3416 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 3417 // base address: 0x0 3418 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 3419 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 3420 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 3421 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 3422 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 3423 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3424 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 3425 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 3426 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3427 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3428 3429 3430 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 3431 // base address: 0x0 3432 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 3433 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 3434 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 3435 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3436 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3437 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3438 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3439 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3440 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3441 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3442 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3443 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3444 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3445 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3446 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 3447 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3448 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 3449 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3450 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 3451 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 3452 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3453 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3454 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 3455 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3456 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 3457 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3458 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 3459 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3460 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 3461 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3462 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 3463 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3464 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 3465 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3466 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 3467 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3468 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 3469 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3470 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 3471 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 3472 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 3473 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 3474 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 3475 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 3476 3477 3478 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 3479 // base address: 0x0 3480 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 3481 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3482 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 3483 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3484 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 3485 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3486 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 3487 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3488 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 3489 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3490 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 3491 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3492 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 3493 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3494 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 3495 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3496 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 3497 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3498 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 3499 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3500 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a 3501 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3502 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b 3503 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3504 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 3505 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 3506 3507 3508 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 3509 // base address: 0x0 3510 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 3511 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 3512 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 3513 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 3514 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 3515 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 3516 3517 3518 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 3519 // base address: 0x0 3520 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 3521 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 3522 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 3523 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 3524 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 3525 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3526 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 3527 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 3528 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3529 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3530 3531 3532 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 3533 // base address: 0x0 3534 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 3535 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 3536 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 3537 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3538 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3539 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3540 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3541 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3542 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3543 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3544 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3545 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3546 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3547 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3548 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 3549 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3550 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 3551 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3552 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 3553 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 3554 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3555 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3556 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 3557 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3558 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 3559 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3560 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 3561 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3562 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 3563 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3564 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 3565 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3566 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 3567 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3568 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 3569 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3570 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 3571 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3572 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 3573 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 3574 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 3575 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 3576 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 3577 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 3578 3579 3580 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 3581 // base address: 0x0 3582 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 3583 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3584 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 3585 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3586 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 3587 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3588 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 3589 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3590 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 3591 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3592 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 3593 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3594 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 3595 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3596 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 3597 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3598 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 3599 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3600 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 3601 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3602 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a 3603 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3604 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b 3605 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3606 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 3607 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 3608 3609 3610 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 3611 // base address: 0x0 3612 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 3613 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 3614 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 3615 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 3616 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 3617 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 3618 3619 3620 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 3621 // base address: 0x0 3622 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 3623 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 3624 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 3625 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 3626 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 3627 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3628 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 3629 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 3630 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3631 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3632 3633 3634 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 3635 // base address: 0x0 3636 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 3637 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 3638 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 3639 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3640 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3641 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3642 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3643 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3644 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3645 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3646 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3647 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3648 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3649 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3650 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 3651 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3652 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 3653 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3654 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 3655 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 3656 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3657 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3658 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 3659 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3660 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 3661 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3662 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 3663 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3664 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 3665 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3666 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 3667 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3668 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 3669 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3670 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 3671 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3672 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 3673 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3674 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 3675 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 3676 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 3677 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 3678 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 3679 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 3680 3681 3682 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 3683 // base address: 0x0 3684 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 3685 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3686 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 3687 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3688 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 3689 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3690 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 3691 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3692 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 3693 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3694 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 3695 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3696 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 3697 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3698 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 3699 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3700 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 3701 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3702 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 3703 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3704 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a 3705 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3706 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b 3707 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3708 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 3709 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 3710 3711 3712 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 3713 // base address: 0x0 3714 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 3715 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 3716 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 3717 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 3718 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 3719 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 3720 3721 3722 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 3723 // base address: 0x0 3724 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 3725 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 3726 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 3727 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 3728 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 3729 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3730 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 3731 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 3732 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3733 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3734 3735 3736 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 3737 // base address: 0x0 3738 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 3739 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 3740 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 3741 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3742 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3743 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3744 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3745 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3746 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3747 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3748 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3749 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3750 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3751 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3752 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 3753 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3754 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 3755 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3756 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 3757 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 3758 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3759 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3760 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 3761 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3762 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 3763 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3764 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 3765 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3766 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 3767 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3768 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 3769 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3770 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 3771 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3772 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 3773 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3774 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 3775 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3776 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 3777 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 3778 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 3779 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 3780 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 3781 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 3782 3783 3784 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 3785 // base address: 0x0 3786 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 3787 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3788 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 3789 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3790 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 3791 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3792 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 3793 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3794 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 3795 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3796 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 3797 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3798 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 3799 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3800 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 3801 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3802 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 3803 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3804 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 3805 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3806 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a 3807 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3808 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b 3809 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3810 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 3811 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 3812 3813 3814 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 3815 // base address: 0x0 3816 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 3817 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 3818 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 3819 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 3820 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 3821 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 3822 3823 3824 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 3825 // base address: 0x0 3826 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 3827 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 3828 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 3829 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 3830 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 3831 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3832 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 3833 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 3834 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3835 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3836 3837 3838 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 3839 // base address: 0x0 3840 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 3841 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 3842 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 3843 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3844 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3845 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3846 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3847 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3848 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3849 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3850 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3851 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3852 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3853 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3854 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 3855 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3856 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 3857 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3858 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 3859 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 3860 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3861 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3862 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 3863 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3864 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 3865 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3866 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 3867 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3868 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 3869 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3870 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 3871 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3872 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 3873 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3874 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 3875 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3876 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 3877 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3878 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 3879 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 3880 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 3881 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 3882 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 3883 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 3884 3885 3886 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 3887 // base address: 0x0 3888 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 3889 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3890 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 3891 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3892 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 3893 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3894 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 3895 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3896 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 3897 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3898 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 3899 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3900 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 3901 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3902 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 3903 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3904 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 3905 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3906 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 3907 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3908 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a 3909 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3910 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b 3911 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3912 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 3913 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 3914 3915 3916 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 3917 // base address: 0x0 3918 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 3919 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 3920 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 3921 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 3922 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 3923 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 3924 3925 3926 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 3927 // base address: 0x0 3928 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 3929 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 3930 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 3931 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 3932 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 3933 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3934 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 3935 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 3936 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3937 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3938 3939 3940 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 3941 // base address: 0x0 3942 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 3943 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 3944 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 3945 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3946 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3947 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3948 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3949 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3950 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3951 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3952 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3953 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3954 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3955 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3956 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 3957 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3958 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 3959 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3960 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 3961 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 3962 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3963 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3964 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 3965 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3966 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 3967 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3968 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 3969 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3970 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 3971 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3972 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 3973 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3974 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 3975 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3976 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 3977 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3978 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 3979 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3980 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 3981 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 3982 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 3983 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 3984 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 3985 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 3986 3987 3988 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 3989 // base address: 0x0 3990 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 3991 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3992 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 3993 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3994 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 3995 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3996 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 3997 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3998 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 3999 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4000 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 4001 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4002 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 4003 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4004 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 4005 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4006 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 4007 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4008 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 4009 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4010 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a 4011 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4012 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b 4013 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4014 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 4015 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 4016 4017 4018 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 4019 // base address: 0x0 4020 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 4021 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 4022 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 4023 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 4024 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 4025 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 4026 4027 4028 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 4029 // base address: 0x0 4030 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 4031 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 4032 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 4033 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 4034 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 4035 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4036 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 4037 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 4038 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4039 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4040 4041 4042 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 4043 // base address: 0x0 4044 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 4045 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 4046 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 4047 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4048 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4049 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4050 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4051 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4052 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4053 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4054 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4055 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4056 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4057 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4058 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 4059 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4060 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 4061 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4062 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 4063 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 4064 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4065 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4066 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 4067 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4068 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 4069 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4070 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 4071 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4072 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 4073 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4074 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 4075 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4076 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 4077 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4078 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 4079 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4080 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 4081 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4082 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 4083 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 4084 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 4085 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 4086 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 4087 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 4088 4089 4090 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 4091 // base address: 0x0 4092 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 4093 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4094 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 4095 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4096 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 4097 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4098 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 4099 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4100 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 4101 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4102 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 4103 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4104 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 4105 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4106 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 4107 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4108 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 4109 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4110 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 4111 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4112 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a 4113 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4114 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b 4115 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4116 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 4117 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 4118 4119 4120 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 4121 // base address: 0x0 4122 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 4123 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 4124 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 4125 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 4126 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 4127 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 4128 4129 4130 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 4131 // base address: 0x0 4132 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 4133 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 4134 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 4135 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 4136 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 4137 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4138 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 4139 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 4140 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4141 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4142 4143 4144 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 4145 // base address: 0x0 4146 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 4147 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 4148 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 4149 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4150 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4151 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4152 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4153 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4154 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4155 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4156 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4157 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4158 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4159 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4160 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 4161 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4162 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 4163 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4164 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 4165 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 4166 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4167 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4168 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 4169 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4170 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 4171 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4172 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 4173 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4174 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 4175 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4176 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 4177 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4178 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 4179 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4180 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 4181 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4182 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 4183 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4184 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 4185 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 4186 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 4187 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 4188 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 4189 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 4190 4191 4192 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 4193 // base address: 0x0 4194 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 4195 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4196 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 4197 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4198 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 4199 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4200 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 4201 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4202 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 4203 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4204 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 4205 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4206 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 4207 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4208 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 4209 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4210 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 4211 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4212 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 4213 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4214 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a 4215 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4216 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b 4217 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4218 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 4219 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 4220 4221 4222 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 4223 // base address: 0x0 4224 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 4225 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 4226 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 4227 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 4228 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 4229 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 4230 4231 4232 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 4233 // base address: 0x0 4234 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 4235 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 4236 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 4237 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 4238 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 4239 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4240 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 4241 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 4242 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4243 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4244 4245 4246 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 4247 // base address: 0x0 4248 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 4249 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 4250 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 4251 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4252 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4253 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4254 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4255 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4256 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4257 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4258 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4259 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4260 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4261 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4262 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 4263 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4264 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 4265 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4266 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 4267 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 4268 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4269 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4270 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 4271 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4272 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 4273 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4274 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 4275 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4276 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 4277 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4278 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 4279 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4280 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 4281 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4282 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 4283 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4284 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 4285 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4286 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 4287 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 4288 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 4289 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 4290 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 4291 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 4292 4293 4294 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 4295 // base address: 0x0 4296 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 4297 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4298 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 4299 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4300 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 4301 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4302 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 4303 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4304 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 4305 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4306 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 4307 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4308 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 4309 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4310 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 4311 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4312 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 4313 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4314 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 4315 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4316 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a 4317 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4318 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b 4319 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4320 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 4321 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 4322 4323 4324 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 4325 // base address: 0x0 4326 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 4327 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 4328 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 4329 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 4330 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 4331 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 4332 4333 4334 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 4335 // base address: 0x0 4336 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 4337 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 4338 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 4339 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 4340 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 4341 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4342 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 4343 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 4344 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4345 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4346 4347 4348 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 4349 // base address: 0x0 4350 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 4351 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 4352 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 4353 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4354 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4355 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4356 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4357 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4358 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4359 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4360 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4361 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4362 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4363 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4364 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 4365 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4366 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 4367 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4368 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 4369 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 4370 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4371 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4372 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 4373 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4374 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 4375 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4376 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 4377 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4378 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 4379 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4380 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 4381 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4382 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 4383 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4384 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 4385 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4386 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 4387 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4388 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 4389 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 4390 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 4391 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 4392 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 4393 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 4394 4395 4396 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 4397 // base address: 0x0 4398 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 4399 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4400 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 4401 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4402 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 4403 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4404 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 4405 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4406 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 4407 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4408 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 4409 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4410 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 4411 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4412 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 4413 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4414 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 4415 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4416 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 4417 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4418 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a 4419 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4420 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b 4421 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4422 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 4423 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 4424 4425 4426 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 4427 // base address: 0x0 4428 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 4429 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 4430 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 4431 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 4432 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 4433 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 4434 4435 4436 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 4437 // base address: 0x0 4438 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 4439 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 4440 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 4441 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 4442 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 4443 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4444 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 4445 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 4446 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4447 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4448 4449 4450 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 4451 // base address: 0x0 4452 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 4453 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 4454 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 4455 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4456 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4457 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4458 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4459 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4460 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4461 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4462 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4463 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4464 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4465 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4466 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 4467 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4468 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 4469 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4470 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 4471 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 4472 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4473 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4474 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 4475 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4476 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 4477 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4478 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 4479 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4480 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 4481 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4482 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 4483 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4484 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 4485 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4486 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 4487 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4488 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 4489 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4490 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 4491 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 4492 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 4493 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 4494 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 4495 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 4496 4497 4498 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 4499 // base address: 0x0 4500 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 4501 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4502 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 4503 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4504 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 4505 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4506 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 4507 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4508 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 4509 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4510 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 4511 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4512 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 4513 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4514 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 4515 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4516 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 4517 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4518 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 4519 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4520 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a 4521 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4522 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b 4523 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4524 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 4525 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 4526 4527 4528 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 4529 // base address: 0x0 4530 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 4531 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 4532 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 4533 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 4534 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 4535 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 4536 4537 4538 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 4539 // base address: 0x0 4540 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 4541 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 4542 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 4543 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 4544 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 4545 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4546 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 4547 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 4548 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4549 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4550 4551 4552 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 4553 // base address: 0x0 4554 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 4555 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 4556 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 4557 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4558 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4559 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4560 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4561 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4562 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4563 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4564 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4565 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4566 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4567 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4568 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 4569 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4570 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 4571 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4572 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 4573 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 4574 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4575 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4576 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 4577 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4578 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 4579 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4580 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 4581 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4582 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 4583 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4584 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 4585 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4586 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 4587 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4588 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 4589 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4590 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 4591 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4592 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 4593 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 4594 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 4595 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 4596 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 4597 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 4598 4599 4600 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 4601 // base address: 0x0 4602 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 4603 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4604 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 4605 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4606 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 4607 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4608 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 4609 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4610 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 4611 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4612 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 4613 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4614 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 4615 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4616 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 4617 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4618 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 4619 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4620 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 4621 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4622 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a 4623 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4624 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b 4625 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4626 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 4627 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 4628 4629 #endif 4630