1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _sdma_4_4_2_SH_MASK_HEADER 24 #define _sdma_4_4_2_SH_MASK_HEADER 25 26 27 // addressBlock: aid_sdma_insts_sdma0_sdmadec 28 //SDMA_UCODE_ADDR 29 #define SDMA_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA_UCODE_ADDR__VALUE_MASK 0x00003FFFL 31 //SDMA_UCODE_DATA 32 #define SDMA_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA_F32_CNTL 35 #define SDMA_F32_CNTL__HALT__SHIFT 0x0 36 #define SDMA_F32_CNTL__STEP__SHIFT 0x1 37 #define SDMA_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 38 #define SDMA_F32_CNTL__RESET__SHIFT 0x8 39 #define SDMA_F32_CNTL__CHECKSUM_CLR__SHIFT 0x9 40 #define SDMA_F32_CNTL__HALT_MASK 0x00000001L 41 #define SDMA_F32_CNTL__STEP_MASK 0x00000002L 42 #define SDMA_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL 43 #define SDMA_F32_CNTL__RESET_MASK 0x00000100L 44 #define SDMA_F32_CNTL__CHECKSUM_CLR_MASK 0x00000200L 45 //SDMA_MMHUB_CNTL 46 #define SDMA_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 47 #define SDMA_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 48 //SDMA_MMHUB_TRUSTLVL 49 #define SDMA_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 50 #define SDMA_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x4 51 #define SDMA_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x8 52 #define SDMA_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0xc 53 #define SDMA_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0x10 54 #define SDMA_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0x14 55 #define SDMA_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x18 56 #define SDMA_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x1c 57 #define SDMA_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x0000000FL 58 #define SDMA_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x000000F0L 59 #define SDMA_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x00000F00L 60 #define SDMA_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x0000F000L 61 #define SDMA_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x000F0000L 62 #define SDMA_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00F00000L 63 #define SDMA_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x0F000000L 64 #define SDMA_MMHUB_TRUSTLVL__SECFLAG7_MASK 0xF0000000L 65 //SDMA_VM_CNTL 66 #define SDMA_VM_CNTL__CMD__SHIFT 0x0 67 #define SDMA_VM_CNTL__CMD_MASK 0x0000000FL 68 //SDMA_VM_CTX_LO 69 #define SDMA_VM_CTX_LO__ADDR__SHIFT 0x2 70 #define SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 71 //SDMA_VM_CTX_HI 72 #define SDMA_VM_CTX_HI__ADDR__SHIFT 0x0 73 #define SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 74 //SDMA_ACTIVE_FCN_ID 75 #define SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0 76 #define SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 77 #define SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x1f 78 #define SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 79 #define SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 80 #define SDMA_ACTIVE_FCN_ID__VF_MASK 0x80000000L 81 //SDMA_VM_CTX_CNTL 82 #define SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0 83 #define SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4 84 #define SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L 85 #define SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L 86 //SDMA_VIRT_RESET_REQ 87 #define SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0 88 #define SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f 89 #define SDMA_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 90 #define SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L 91 //SDMA_VF_ENABLE 92 #define SDMA_VF_ENABLE__VF_ENABLE__SHIFT 0x0 93 #define SDMA_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 94 //SDMA_CONTEXT_REG_TYPE0 95 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_CNTL__SHIFT 0x0 96 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE__SHIFT 0x1 97 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_HI__SHIFT 0x2 98 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR__SHIFT 0x3 99 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_HI__SHIFT 0x4 100 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR__SHIFT 0x5 101 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_HI__SHIFT 0x6 102 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 103 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 104 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 105 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_CNTL__SHIFT 0xa 106 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_RPTR__SHIFT 0xb 107 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_OFFSET__SHIFT 0xc 108 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_LO__SHIFT 0xd 109 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_HI__SHIFT 0xe 110 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_SIZE__SHIFT 0xf 111 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_SKIP_CNTL__SHIFT 0x10 112 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_STATUS__SHIFT 0x11 113 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_DOORBELL__SHIFT 0x12 114 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_CNTL__SHIFT 0x13 115 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_CNTL_MASK 0x00000001L 116 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_MASK 0x00000002L 117 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_HI_MASK 0x00000004L 118 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_MASK 0x00000008L 119 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_HI_MASK 0x00000010L 120 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_MASK 0x00000020L 121 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_HI_MASK 0x00000040L 122 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 123 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 124 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 125 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_CNTL_MASK 0x00000400L 126 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_RPTR_MASK 0x00000800L 127 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_OFFSET_MASK 0x00001000L 128 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_LO_MASK 0x00002000L 129 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_HI_MASK 0x00004000L 130 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_SIZE_MASK 0x00008000L 131 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_SKIP_CNTL_MASK 0x00010000L 132 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_STATUS_MASK 0x00020000L 133 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_DOORBELL_MASK 0x00040000L 134 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_CNTL_MASK 0x00080000L 135 //SDMA_CONTEXT_REG_TYPE1 136 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_STATUS__SHIFT 0x8 137 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_LOG__SHIFT 0x9 138 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_WATERMARK__SHIFT 0xa 139 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_OFFSET__SHIFT 0xb 140 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_LO__SHIFT 0xc 141 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_HI__SHIFT 0xd 142 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_IB_SUB_REMAIN__SHIFT 0xf 143 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_PREEMPT__SHIFT 0x10 144 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DUMMY_REG__SHIFT 0x11 145 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 146 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 147 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_AQL_CNTL__SHIFT 0x14 148 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 149 #define SDMA_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 150 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_STATUS_MASK 0x00000100L 151 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_LOG_MASK 0x00000200L 152 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_WATERMARK_MASK 0x00000400L 153 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_OFFSET_MASK 0x00000800L 154 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_LO_MASK 0x00001000L 155 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_HI_MASK 0x00002000L 156 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_IB_SUB_REMAIN_MASK 0x00008000L 157 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_PREEMPT_MASK 0x00010000L 158 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DUMMY_REG_MASK 0x00020000L 159 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 160 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 161 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_AQL_CNTL_MASK 0x00100000L 162 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 163 #define SDMA_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 164 //SDMA_CONTEXT_REG_TYPE2 165 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA0__SHIFT 0x0 166 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA1__SHIFT 0x1 167 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA2__SHIFT 0x2 168 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA3__SHIFT 0x3 169 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA4__SHIFT 0x4 170 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA5__SHIFT 0x5 171 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA6__SHIFT 0x6 172 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA7__SHIFT 0x7 173 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA8__SHIFT 0x8 174 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA9__SHIFT 0x9 175 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA10__SHIFT 0xa 176 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_CNTL__SHIFT 0xb 177 #define SDMA_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xe 178 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA0_MASK 0x00000001L 179 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA1_MASK 0x00000002L 180 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA2_MASK 0x00000004L 181 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA3_MASK 0x00000008L 182 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA4_MASK 0x00000010L 183 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA5_MASK 0x00000020L 184 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA6_MASK 0x00000040L 185 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA7_MASK 0x00000080L 186 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA8_MASK 0x00000100L 187 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA9_MASK 0x00000200L 188 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA10_MASK 0x00000400L 189 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_CNTL_MASK 0x00000800L 190 #define SDMA_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFC000L 191 //SDMA_CONTEXT_REG_TYPE3 192 #define SDMA_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 193 #define SDMA_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 194 //SDMA_PUB_REG_TYPE0 195 #define SDMA_PUB_REG_TYPE0__SDMA_UCODE_ADDR__SHIFT 0x0 196 #define SDMA_PUB_REG_TYPE0__SDMA_UCODE_DATA__SHIFT 0x1 197 #define SDMA_PUB_REG_TYPE0__SDMA_F32_CNTL__SHIFT 0x2 198 #define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_CNTL__SHIFT 0x5 199 #define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_TRUSTLVL__SHIFT 0x6 200 #define SDMA_PUB_REG_TYPE0__RESERVED_14_10__SHIFT 0xa 201 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CNTL__SHIFT 0x10 202 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_LO__SHIFT 0x11 203 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_HI__SHIFT 0x12 204 #define SDMA_PUB_REG_TYPE0__SDMA_ACTIVE_FCN_ID__SHIFT 0x13 205 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_CNTL__SHIFT 0x14 206 #define SDMA_PUB_REG_TYPE0__SDMA_VIRT_RESET_REQ__SHIFT 0x15 207 #define SDMA_PUB_REG_TYPE0__SDMA_VF_ENABLE__SHIFT 0x16 208 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE0__SHIFT 0x17 209 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE1__SHIFT 0x18 210 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE2__SHIFT 0x19 211 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE3__SHIFT 0x1a 212 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE0__SHIFT 0x1b 213 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE1__SHIFT 0x1c 214 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE2__SHIFT 0x1d 215 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE3__SHIFT 0x1e 216 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_GROUP_BOUNDARY__SHIFT 0x1f 217 #define SDMA_PUB_REG_TYPE0__SDMA_UCODE_ADDR_MASK 0x00000001L 218 #define SDMA_PUB_REG_TYPE0__SDMA_UCODE_DATA_MASK 0x00000002L 219 #define SDMA_PUB_REG_TYPE0__SDMA_F32_CNTL_MASK 0x00000004L 220 #define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_CNTL_MASK 0x00000020L 221 #define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_TRUSTLVL_MASK 0x00000040L 222 #define SDMA_PUB_REG_TYPE0__RESERVED_14_10_MASK 0x00007C00L 223 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CNTL_MASK 0x00010000L 224 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_LO_MASK 0x00020000L 225 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_HI_MASK 0x00040000L 226 #define SDMA_PUB_REG_TYPE0__SDMA_ACTIVE_FCN_ID_MASK 0x00080000L 227 #define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_CNTL_MASK 0x00100000L 228 #define SDMA_PUB_REG_TYPE0__SDMA_VIRT_RESET_REQ_MASK 0x00200000L 229 #define SDMA_PUB_REG_TYPE0__SDMA_VF_ENABLE_MASK 0x00400000L 230 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE0_MASK 0x00800000L 231 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE1_MASK 0x01000000L 232 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE2_MASK 0x02000000L 233 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE3_MASK 0x04000000L 234 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE0_MASK 0x08000000L 235 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE1_MASK 0x10000000L 236 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE2_MASK 0x20000000L 237 #define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE3_MASK 0x40000000L 238 #define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_GROUP_BOUNDARY_MASK 0x80000000L 239 //SDMA_PUB_REG_TYPE1 240 #define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI__SHIFT 0x0 241 #define SDMA_PUB_REG_TYPE1__SDMA_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 242 #define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH__SHIFT 0x2 243 #define SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH__SHIFT 0x3 244 #define SDMA_PUB_REG_TYPE1__SDMA_PROGRAM__SHIFT 0x4 245 #define SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG__SHIFT 0x5 246 #define SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG__SHIFT 0x6 247 #define SDMA_PUB_REG_TYPE1__SDMA_RD_BURST_CNTL__SHIFT 0x7 248 #define SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG__SHIFT 0x8 249 #define SDMA_PUB_REG_TYPE1__SDMA_UCODE_CHECKSUM__SHIFT 0x9 250 #define SDMA_PUB_REG_TYPE1__RESERVED_10_10__SHIFT 0xa 251 #define SDMA_PUB_REG_TYPE1__SDMA_FREEZE__SHIFT 0xb 252 #define SDMA_PUB_REG_TYPE1__SDMA_PHASE0_QUANTUM__SHIFT 0xc 253 #define SDMA_PUB_REG_TYPE1__SDMA_PHASE1_QUANTUM__SHIFT 0xd 254 #define SDMA_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 255 #define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 256 #define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 257 #define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 258 #define SDMA_PUB_REG_TYPE1__CC_SDMA_EDC_CONFIG__SHIFT 0x12 259 #define SDMA_PUB_REG_TYPE1__SDMA_BA_THRESHOLD__SHIFT 0x13 260 #define SDMA_PUB_REG_TYPE1__SDMA_ID__SHIFT 0x14 261 #define SDMA_PUB_REG_TYPE1__SDMA_VERSION__SHIFT 0x15 262 #define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER__SHIFT 0x16 263 #define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER2__SHIFT 0x17 264 #define SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG__SHIFT 0x18 265 #define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL__SHIFT 0x19 266 #define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO__SHIFT 0x1a 267 #define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI__SHIFT 0x1b 268 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL__SHIFT 0x1c 269 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK__SHIFT 0x1d 270 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_RD_STATUS__SHIFT 0x1e 271 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WR_STATUS__SHIFT 0x1f 272 #define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI_MASK 0x00000001L 273 #define SDMA_PUB_REG_TYPE1__SDMA_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 274 #define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_MASK 0x00000004L 275 #define SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH_MASK 0x00000008L 276 #define SDMA_PUB_REG_TYPE1__SDMA_PROGRAM_MASK 0x00000010L 277 #define SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG_MASK 0x00000020L 278 #define SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG_MASK 0x00000040L 279 #define SDMA_PUB_REG_TYPE1__SDMA_RD_BURST_CNTL_MASK 0x00000080L 280 #define SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG_MASK 0x00000100L 281 #define SDMA_PUB_REG_TYPE1__SDMA_UCODE_CHECKSUM_MASK 0x00000200L 282 #define SDMA_PUB_REG_TYPE1__RESERVED_10_10_MASK 0x00000400L 283 #define SDMA_PUB_REG_TYPE1__SDMA_FREEZE_MASK 0x00000800L 284 #define SDMA_PUB_REG_TYPE1__SDMA_PHASE0_QUANTUM_MASK 0x00001000L 285 #define SDMA_PUB_REG_TYPE1__SDMA_PHASE1_QUANTUM_MASK 0x00002000L 286 #define SDMA_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 287 #define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 288 #define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 289 #define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 290 #define SDMA_PUB_REG_TYPE1__CC_SDMA_EDC_CONFIG_MASK 0x00040000L 291 #define SDMA_PUB_REG_TYPE1__SDMA_BA_THRESHOLD_MASK 0x00080000L 292 #define SDMA_PUB_REG_TYPE1__SDMA_ID_MASK 0x00100000L 293 #define SDMA_PUB_REG_TYPE1__SDMA_VERSION_MASK 0x00200000L 294 #define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER_MASK 0x00400000L 295 #define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER2_MASK 0x00800000L 296 #define SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG_MASK 0x01000000L 297 #define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL_MASK 0x02000000L 298 #define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO_MASK 0x04000000L 299 #define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI_MASK 0x08000000L 300 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL_MASK 0x10000000L 301 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK_MASK 0x20000000L 302 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_RD_STATUS_MASK 0x40000000L 303 #define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WR_STATUS_MASK 0x80000000L 304 //SDMA_PUB_REG_TYPE2 305 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0__SHIFT 0x0 306 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1__SHIFT 0x1 307 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2__SHIFT 0x2 308 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0__SHIFT 0x3 309 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1__SHIFT 0x4 310 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0__SHIFT 0x5 311 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1__SHIFT 0x6 312 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_TIMEOUT__SHIFT 0x7 313 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_PAGE__SHIFT 0x8 314 #define SDMA_PUB_REG_TYPE2__SDMA_POWER_CNTL_IDLE__SHIFT 0x9 315 #define SDMA_PUB_REG_TYPE2__SDMA_RELAX_ORDERING_LUT__SHIFT 0xa 316 #define SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2__SHIFT 0xb 317 #define SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG__SHIFT 0xc 318 #define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_LO__SHIFT 0xd 319 #define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_HI__SHIFT 0xe 320 #define SDMA_PUB_REG_TYPE2__SDMA_PHASE2_QUANTUM__SHIFT 0xf 321 #define SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG__SHIFT 0x10 322 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0__SHIFT 0x11 323 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1__SHIFT 0x12 324 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2__SHIFT 0x13 325 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3__SHIFT 0x14 326 #define SDMA_PUB_REG_TYPE2__SDMA_F32_COUNTER__SHIFT 0x15 327 #define SDMA_PUB_REG_TYPE2__RESERVED_22_22__SHIFT 0x16 328 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER0_CFG__SHIFT 0x17 329 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER1_CFG__SHIFT 0x18 330 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT 0x19 331 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_MISC_CNTL__SHIFT 0x1a 332 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_LO__SHIFT 0x1b 333 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_HI__SHIFT 0x1c 334 #define SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL__SHIFT 0x1d 335 #define SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG__SHIFT 0x1e 336 #define SDMA_PUB_REG_TYPE2__SDMA_ULV_CNTL__SHIFT 0x1f 337 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0_MASK 0x00000001L 338 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1_MASK 0x00000002L 339 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2_MASK 0x00000004L 340 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0_MASK 0x00000008L 341 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1_MASK 0x00000010L 342 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0_MASK 0x00000020L 343 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1_MASK 0x00000040L 344 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_TIMEOUT_MASK 0x00000080L 345 #define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_PAGE_MASK 0x00000100L 346 #define SDMA_PUB_REG_TYPE2__SDMA_POWER_CNTL_IDLE_MASK 0x00000200L 347 #define SDMA_PUB_REG_TYPE2__SDMA_RELAX_ORDERING_LUT_MASK 0x00000400L 348 #define SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2_MASK 0x00000800L 349 #define SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG_MASK 0x00001000L 350 #define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_LO_MASK 0x00002000L 351 #define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_HI_MASK 0x00004000L 352 #define SDMA_PUB_REG_TYPE2__SDMA_PHASE2_QUANTUM_MASK 0x00008000L 353 #define SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG_MASK 0x00010000L 354 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0_MASK 0x00020000L 355 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1_MASK 0x00040000L 356 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2_MASK 0x00080000L 357 #define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3_MASK 0x00100000L 358 #define SDMA_PUB_REG_TYPE2__SDMA_F32_COUNTER_MASK 0x00200000L 359 #define SDMA_PUB_REG_TYPE2__RESERVED_22_22_MASK 0x00400000L 360 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER0_CFG_MASK 0x00800000L 361 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER1_CFG_MASK 0x01000000L 362 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK 0x02000000L 363 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_MISC_CNTL_MASK 0x04000000L 364 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_LO_MASK 0x08000000L 365 #define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_HI_MASK 0x10000000L 366 #define SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL_MASK 0x20000000L 367 #define SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG_MASK 0x40000000L 368 #define SDMA_PUB_REG_TYPE2__SDMA_ULV_CNTL_MASK 0x80000000L 369 //SDMA_PUB_REG_TYPE3 370 #define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_DATA__SHIFT 0x0 371 #define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_INDEX__SHIFT 0x1 372 #define SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 373 #define SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG__SHIFT 0x3 374 #define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA__SHIFT 0x4 375 #define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR__SHIFT 0x5 376 #define SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL__SHIFT 0x6 377 #define SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS__SHIFT 0x7 378 #define SDMA_PUB_REG_TYPE3__SDMA_CLK_STATUS__SHIFT 0x8 379 #define SDMA_PUB_REG_TYPE3__SDMA_POWER_CNTL__SHIFT 0xb 380 #define SDMA_PUB_REG_TYPE3__SDMA_CLK_CTRL__SHIFT 0xc 381 #define SDMA_PUB_REG_TYPE3__SDMA_CNTL__SHIFT 0xd 382 #define SDMA_PUB_REG_TYPE3__SDMA_CHICKEN_BITS__SHIFT 0xe 383 #define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG__SHIFT 0xf 384 #define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG_READ__SHIFT 0x10 385 #define SDMA_PUB_REG_TYPE3__RESERVED__SHIFT 0x13 386 #define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_DATA_MASK 0x00000001L 387 #define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 388 #define SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L 389 #define SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG_MASK 0x00000008L 390 #define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA_MASK 0x00000010L 391 #define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR_MASK 0x00000020L 392 #define SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL_MASK 0x00000040L 393 #define SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS_MASK 0x00000080L 394 #define SDMA_PUB_REG_TYPE3__SDMA_CLK_STATUS_MASK 0x00000100L 395 #define SDMA_PUB_REG_TYPE3__SDMA_POWER_CNTL_MASK 0x00000800L 396 #define SDMA_PUB_REG_TYPE3__SDMA_CLK_CTRL_MASK 0x00001000L 397 #define SDMA_PUB_REG_TYPE3__SDMA_CNTL_MASK 0x00002000L 398 #define SDMA_PUB_REG_TYPE3__SDMA_CHICKEN_BITS_MASK 0x00004000L 399 #define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG_MASK 0x00008000L 400 #define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG_READ_MASK 0x00010000L 401 #define SDMA_PUB_REG_TYPE3__RESERVED_MASK 0xFFF80000L 402 //SDMA_CONTEXT_GROUP_BOUNDARY 403 #define SDMA_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 404 #define SDMA_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 405 //SDMA_RB_RPTR_FETCH_HI 406 #define SDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 407 #define SDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 408 //SDMA_SEM_WAIT_FAIL_TIMER_CNTL 409 #define SDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 410 #define SDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 411 //SDMA_RB_RPTR_FETCH 412 #define SDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 413 #define SDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 414 //SDMA_IB_OFFSET_FETCH 415 #define SDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 416 #define SDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 417 //SDMA_PROGRAM 418 #define SDMA_PROGRAM__STREAM__SHIFT 0x0 419 #define SDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL 420 //SDMA_STATUS_REG 421 #define SDMA_STATUS_REG__IDLE__SHIFT 0x0 422 #define SDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 423 #define SDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 424 #define SDMA_STATUS_REG__RB_FULL__SHIFT 0x3 425 #define SDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 426 #define SDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 427 #define SDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 428 #define SDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 429 #define SDMA_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 430 #define SDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 431 #define SDMA_STATUS_REG__EX_IDLE__SHIFT 0xa 432 #define SDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 433 #define SDMA_STATUS_REG__PACKET_READY__SHIFT 0xc 434 #define SDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 435 #define SDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe 436 #define SDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 437 #define SDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 438 #define SDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 439 #define SDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 440 #define SDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 441 #define SDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 442 #define SDMA_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 443 #define SDMA_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 444 #define SDMA_STATUS_REG__DRM_IDLE__SHIFT 0x17 445 #define SDMA_STATUS_REG__DRM_MASK_FULL__SHIFT 0x18 446 #define SDMA_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 447 #define SDMA_STATUS_REG__SEM_IDLE__SHIFT 0x1a 448 #define SDMA_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 449 #define SDMA_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 450 #define SDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e 451 #define SDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 452 #define SDMA_STATUS_REG__IDLE_MASK 0x00000001L 453 #define SDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L 454 #define SDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L 455 #define SDMA_STATUS_REG__RB_FULL_MASK 0x00000008L 456 #define SDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 457 #define SDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 458 #define SDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 459 #define SDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 460 #define SDMA_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 461 #define SDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L 462 #define SDMA_STATUS_REG__EX_IDLE_MASK 0x00000400L 463 #define SDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 464 #define SDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L 465 #define SDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 466 #define SDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 467 #define SDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 468 #define SDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 469 #define SDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 470 #define SDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 471 #define SDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 472 #define SDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 473 #define SDMA_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 474 #define SDMA_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 475 #define SDMA_STATUS_REG__DRM_IDLE_MASK 0x00800000L 476 #define SDMA_STATUS_REG__DRM_MASK_FULL_MASK 0x01000000L 477 #define SDMA_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 478 #define SDMA_STATUS_REG__SEM_IDLE_MASK 0x04000000L 479 #define SDMA_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 480 #define SDMA_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 481 #define SDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L 482 #define SDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 483 //SDMA_STATUS1_REG 484 #define SDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 485 #define SDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 486 #define SDMA_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 487 #define SDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 488 #define SDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 489 #define SDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 490 #define SDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 491 #define SDMA_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x7 492 #define SDMA_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x8 493 #define SDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 494 #define SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 495 #define SDMA_STATUS1_REG__CE_DRM_FULL__SHIFT 0xb 496 #define SDMA_STATUS1_REG__CE_DRM1_FULL__SHIFT 0xc 497 #define SDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 498 #define SDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 499 #define SDMA_STATUS1_REG__EX_START__SHIFT 0xf 500 #define SDMA_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0x10 501 #define SDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 502 #define SDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 503 #define SDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 504 #define SDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 505 #define SDMA_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 506 #define SDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 507 #define SDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 508 #define SDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 509 #define SDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 510 #define SDMA_STATUS1_REG__CE_DRM_IDLE_MASK 0x00000080L 511 #define SDMA_STATUS1_REG__CE_DRM1_IDLE_MASK 0x00000100L 512 #define SDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 513 #define SDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 514 #define SDMA_STATUS1_REG__CE_DRM_FULL_MASK 0x00000800L 515 #define SDMA_STATUS1_REG__CE_DRM1_FULL_MASK 0x00001000L 516 #define SDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 517 #define SDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 518 #define SDMA_STATUS1_REG__EX_START_MASK 0x00008000L 519 #define SDMA_STATUS1_REG__DRM_CTX_RESTORE_MASK 0x00010000L 520 #define SDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 521 #define SDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 522 //SDMA_RD_BURST_CNTL 523 #define SDMA_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 524 #define SDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 525 #define SDMA_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 526 #define SDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 527 //SDMA_HBM_PAGE_CONFIG 528 #define SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 529 #define SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 530 //SDMA_UCODE_CHECKSUM 531 #define SDMA_UCODE_CHECKSUM__DATA__SHIFT 0x0 532 #define SDMA_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 533 //SDMA_FREEZE 534 #define SDMA_FREEZE__PREEMPT__SHIFT 0x0 535 #define SDMA_FREEZE__FREEZE__SHIFT 0x4 536 #define SDMA_FREEZE__FROZEN__SHIFT 0x5 537 #define SDMA_FREEZE__F32_FREEZE__SHIFT 0x6 538 #define SDMA_FREEZE__PREEMPT_MASK 0x00000001L 539 #define SDMA_FREEZE__FREEZE_MASK 0x00000010L 540 #define SDMA_FREEZE__FROZEN_MASK 0x00000020L 541 #define SDMA_FREEZE__F32_FREEZE_MASK 0x00000040L 542 //SDMA_PHASE0_QUANTUM 543 #define SDMA_PHASE0_QUANTUM__UNIT__SHIFT 0x0 544 #define SDMA_PHASE0_QUANTUM__VALUE__SHIFT 0x8 545 #define SDMA_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 546 #define SDMA_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 547 #define SDMA_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 548 #define SDMA_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 549 //SDMA_PHASE1_QUANTUM 550 #define SDMA_PHASE1_QUANTUM__UNIT__SHIFT 0x0 551 #define SDMA_PHASE1_QUANTUM__VALUE__SHIFT 0x8 552 #define SDMA_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 553 #define SDMA_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 554 #define SDMA_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 555 #define SDMA_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 556 //SDMA_POWER_GATING 557 #define SDMA_POWER_GATING__SDMA_POWER_OFF_CONDITION__SHIFT 0x0 558 #define SDMA_POWER_GATING__SDMA_POWER_ON_CONDITION__SHIFT 0x1 559 #define SDMA_POWER_GATING__SDMA_POWER_OFF_REQ__SHIFT 0x2 560 #define SDMA_POWER_GATING__SDMA_POWER_ON_REQ__SHIFT 0x3 561 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 562 #define SDMA_POWER_GATING__SDMA_POWER_OFF_CONDITION_MASK 0x00000001L 563 #define SDMA_POWER_GATING__SDMA_POWER_ON_CONDITION_MASK 0x00000002L 564 #define SDMA_POWER_GATING__SDMA_POWER_OFF_REQ_MASK 0x00000004L 565 #define SDMA_POWER_GATING__SDMA_POWER_ON_REQ_MASK 0x00000008L 566 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 567 //SDMA_PGFSM_CONFIG 568 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 569 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 570 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 571 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 572 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 573 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 574 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 575 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 576 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 577 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 578 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 579 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 580 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 581 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 582 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 583 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 584 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 585 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 586 //SDMA_PGFSM_WRITE 587 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 588 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 589 //SDMA_PGFSM_READ 590 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 591 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 592 //CC_SDMA_EDC_CONFIG 593 #define CC_SDMA_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 594 #define CC_SDMA_EDC_CONFIG__DIS_EDC__SHIFT 0x1 595 #define CC_SDMA_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L 596 #define CC_SDMA_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 597 //SDMA_BA_THRESHOLD 598 #define SDMA_BA_THRESHOLD__READ_THRES__SHIFT 0x0 599 #define SDMA_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 600 #define SDMA_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 601 #define SDMA_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 602 //SDMA_ID 603 #define SDMA_ID__DEVICE_ID__SHIFT 0x0 604 #define SDMA_ID__DEVICE_ID_MASK 0x000000FFL 605 //SDMA_VERSION 606 #define SDMA_VERSION__MINVER__SHIFT 0x0 607 #define SDMA_VERSION__MAJVER__SHIFT 0x8 608 #define SDMA_VERSION__REV__SHIFT 0x10 609 #define SDMA_VERSION__MINVER_MASK 0x0000007FL 610 #define SDMA_VERSION__MAJVER_MASK 0x00007F00L 611 #define SDMA_VERSION__REV_MASK 0x003F0000L 612 //SDMA_EDC_COUNTER 613 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 614 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 615 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 616 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 617 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 618 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 619 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 620 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 621 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 622 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 623 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 624 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 625 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 626 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 627 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 628 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 629 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 630 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 631 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 632 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 633 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 634 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 635 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 636 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 637 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 638 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 639 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 640 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 641 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 642 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 643 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 644 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 645 //SDMA_EDC_COUNTER2 646 #define SDMA_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 647 #define SDMA_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 648 #define SDMA_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 649 #define SDMA_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 650 #define SDMA_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 651 #define SDMA_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 652 #define SDMA_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 653 #define SDMA_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 654 #define SDMA_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 655 #define SDMA_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 656 #define SDMA_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L 657 #define SDMA_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 658 #define SDMA_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L 659 #define SDMA_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 660 #define SDMA_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 661 #define SDMA_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 662 #define SDMA_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 663 #define SDMA_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 664 #define SDMA_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 665 #define SDMA_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 666 //SDMA_STATUS2_REG 667 #define SDMA_STATUS2_REG__ID__SHIFT 0x0 668 #define SDMA_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 669 #define SDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 670 #define SDMA_STATUS2_REG__ID_MASK 0x00000007L 671 #define SDMA_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 672 #define SDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 673 //SDMA_ATOMIC_CNTL 674 #define SDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 675 #define SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 676 #define SDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 677 #define SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 678 //SDMA_ATOMIC_PREOP_LO 679 #define SDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 680 #define SDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 681 //SDMA_ATOMIC_PREOP_HI 682 #define SDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 683 #define SDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 684 //SDMA_UTCL1_CNTL 685 #define SDMA_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 686 #define SDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 687 #define SDMA_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 688 #define SDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 689 #define SDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 690 #define SDMA_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 691 #define SDMA_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 692 #define SDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 693 #define SDMA_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 694 #define SDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 695 #define SDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 696 #define SDMA_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 697 //SDMA_UTCL1_WATERMK 698 #define SDMA_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 699 #define SDMA_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 700 #define SDMA_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 701 #define SDMA_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 702 #define SDMA_UTCL1_WATERMK__RESERVED__SHIFT 0x10 703 #define SDMA_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 704 #define SDMA_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 705 #define SDMA_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 706 #define SDMA_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 707 #define SDMA_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 708 //SDMA_UTCL1_RD_STATUS 709 #define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 710 #define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 711 #define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 712 #define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 713 #define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 714 #define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 715 #define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 716 #define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 717 #define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 718 #define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 719 #define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 720 #define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 721 #define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 722 #define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 723 #define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 724 #define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 725 #define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 726 #define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 727 #define SDMA_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 728 #define SDMA_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 729 #define SDMA_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 730 #define SDMA_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 731 #define SDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 732 #define SDMA_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 733 #define SDMA_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 734 #define SDMA_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 735 #define SDMA_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 736 #define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 737 #define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 738 #define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 739 #define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 740 #define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 741 #define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 742 #define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 743 #define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 744 #define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 745 #define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 746 #define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 747 #define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 748 #define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 749 #define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 750 #define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 751 #define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 752 #define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 753 #define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 754 #define SDMA_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 755 #define SDMA_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 756 #define SDMA_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 757 #define SDMA_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 758 #define SDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 759 #define SDMA_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 760 #define SDMA_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 761 #define SDMA_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 762 #define SDMA_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 763 //SDMA_UTCL1_WR_STATUS 764 #define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 765 #define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 766 #define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 767 #define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 768 #define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 769 #define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 770 #define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 771 #define SDMA_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0x7 772 #define SDMA_UTCL1_WR_STATUS__RESERVED_8__SHIFT 0x8 773 #define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 774 #define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 775 #define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 776 #define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 777 #define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 778 #define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 779 #define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 780 #define SDMA_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0x10 781 #define SDMA_UTCL1_WR_STATUS__RESERVED_17__SHIFT 0x11 782 #define SDMA_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 783 #define SDMA_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 784 #define SDMA_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 785 #define SDMA_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 786 #define SDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 787 #define SDMA_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 788 #define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 789 #define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 790 #define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 791 #define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 792 #define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 793 #define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 794 #define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 795 #define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 796 #define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 797 #define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 798 #define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 799 #define SDMA_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00000080L 800 #define SDMA_UTCL1_WR_STATUS__RESERVED_8_MASK 0x00000100L 801 #define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 802 #define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 803 #define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 804 #define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 805 #define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 806 #define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 807 #define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 808 #define SDMA_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00010000L 809 #define SDMA_UTCL1_WR_STATUS__RESERVED_17_MASK 0x00020000L 810 #define SDMA_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 811 #define SDMA_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 812 #define SDMA_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 813 #define SDMA_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 814 #define SDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 815 #define SDMA_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 816 #define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 817 #define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 818 #define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 819 #define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 820 //SDMA_UTCL1_INV0 821 #define SDMA_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 822 #define SDMA_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 823 #define SDMA_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 824 #define SDMA_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 825 #define SDMA_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 826 #define SDMA_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 827 #define SDMA_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 828 #define SDMA_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 829 #define SDMA_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 830 #define SDMA_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 831 #define SDMA_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 832 #define SDMA_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 833 #define SDMA_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 834 #define SDMA_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 835 #define SDMA_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 836 #define SDMA_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 837 #define SDMA_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 838 #define SDMA_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 839 #define SDMA_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 840 #define SDMA_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 841 #define SDMA_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 842 #define SDMA_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 843 #define SDMA_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 844 #define SDMA_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 845 #define SDMA_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 846 #define SDMA_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 847 #define SDMA_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 848 #define SDMA_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 849 //SDMA_UTCL1_INV1 850 #define SDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 851 #define SDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 852 //SDMA_UTCL1_INV2 853 #define SDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 854 #define SDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 855 //SDMA_UTCL1_RD_XNACK0 856 #define SDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 857 #define SDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 858 //SDMA_UTCL1_RD_XNACK1 859 #define SDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 860 #define SDMA_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 861 #define SDMA_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 862 #define SDMA_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 863 #define SDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 864 #define SDMA_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 865 #define SDMA_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 866 #define SDMA_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 867 //SDMA_UTCL1_WR_XNACK0 868 #define SDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 869 #define SDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 870 //SDMA_UTCL1_WR_XNACK1 871 #define SDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 872 #define SDMA_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 873 #define SDMA_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 874 #define SDMA_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 875 #define SDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 876 #define SDMA_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 877 #define SDMA_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 878 #define SDMA_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 879 //SDMA_UTCL1_TIMEOUT 880 #define SDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 881 #define SDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 882 #define SDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 883 #define SDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 884 //SDMA_UTCL1_PAGE 885 #define SDMA_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 886 #define SDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 887 #define SDMA_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5 888 #define SDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 889 #define SDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 890 #define SDMA_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0xa 891 #define SDMA_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 892 #define SDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 893 #define SDMA_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L 894 #define SDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 895 #define SDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 896 #define SDMA_UTCL1_PAGE__LLC_NOALLOC_MASK 0x00000400L 897 //SDMA_POWER_CNTL_IDLE 898 #define SDMA_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 899 #define SDMA_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 900 #define SDMA_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 901 #define SDMA_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 902 #define SDMA_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 903 #define SDMA_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 904 //SDMA_RELAX_ORDERING_LUT 905 #define SDMA_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 906 #define SDMA_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 907 #define SDMA_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 908 #define SDMA_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 909 #define SDMA_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 910 #define SDMA_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 911 #define SDMA_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 912 #define SDMA_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 913 #define SDMA_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 914 #define SDMA_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 915 #define SDMA_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 916 #define SDMA_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 917 #define SDMA_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 918 #define SDMA_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 919 #define SDMA_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 920 #define SDMA_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 921 #define SDMA_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 922 #define SDMA_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 923 #define SDMA_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 924 #define SDMA_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 925 #define SDMA_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 926 #define SDMA_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 927 #define SDMA_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 928 #define SDMA_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 929 #define SDMA_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 930 #define SDMA_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 931 #define SDMA_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 932 #define SDMA_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 933 #define SDMA_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 934 #define SDMA_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 935 #define SDMA_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 936 #define SDMA_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 937 #define SDMA_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 938 #define SDMA_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 939 #define SDMA_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 940 #define SDMA_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 941 #define SDMA_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 942 #define SDMA_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 943 //SDMA_CHICKEN_BITS_2 944 #define SDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 945 #define SDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 946 #define SDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 947 #define SDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 948 //SDMA_STATUS3_REG 949 #define SDMA_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 950 #define SDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 951 #define SDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 952 #define SDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 953 #define SDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 954 #define SDMA_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 955 #define SDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 956 #define SDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 957 #define SDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 958 #define SDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 959 //SDMA_PHYSICAL_ADDR_LO 960 #define SDMA_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 961 #define SDMA_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 962 #define SDMA_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 963 #define SDMA_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 964 #define SDMA_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 965 #define SDMA_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 966 #define SDMA_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 967 #define SDMA_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 968 //SDMA_PHYSICAL_ADDR_HI 969 #define SDMA_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 970 #define SDMA_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 971 //SDMA_PHASE2_QUANTUM 972 #define SDMA_PHASE2_QUANTUM__UNIT__SHIFT 0x0 973 #define SDMA_PHASE2_QUANTUM__VALUE__SHIFT 0x8 974 #define SDMA_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 975 #define SDMA_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 976 #define SDMA_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 977 #define SDMA_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 978 //SDMA_ERROR_LOG 979 #define SDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 980 #define SDMA_ERROR_LOG__STATUS__SHIFT 0x10 981 #define SDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 982 #define SDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L 983 //SDMA_PUB_DUMMY_REG0 984 #define SDMA_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 985 #define SDMA_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 986 //SDMA_PUB_DUMMY_REG1 987 #define SDMA_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 988 #define SDMA_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 989 //SDMA_PUB_DUMMY_REG2 990 #define SDMA_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 991 #define SDMA_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 992 //SDMA_PUB_DUMMY_REG3 993 #define SDMA_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 994 #define SDMA_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 995 //SDMA_F32_COUNTER 996 #define SDMA_F32_COUNTER__VALUE__SHIFT 0x0 997 #define SDMA_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 998 //SDMA_PERFCNT_PERFCOUNTER0_CFG 999 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1000 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1001 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1002 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1003 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1004 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1005 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1006 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1007 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1008 #define SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1009 //SDMA_PERFCNT_PERFCOUNTER1_CFG 1010 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1011 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1012 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1013 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1014 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1015 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1016 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1017 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1018 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1019 #define SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1020 //SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 1021 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1022 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1023 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1024 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1025 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1026 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1027 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1028 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1029 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1030 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1031 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1032 #define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1033 //SDMA_PERFCNT_MISC_CNTL 1034 #define SDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 1035 #define SDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10 1036 #define SDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 1037 #define SDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L 1038 //SDMA_PERFCNT_PERFCOUNTER_LO 1039 #define SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1040 #define SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1041 //SDMA_PERFCNT_PERFCOUNTER_HI 1042 #define SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1043 #define SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1044 #define SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1045 #define SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1046 //SDMA_CRD_CNTL 1047 #define SDMA_CRD_CNTL__DRM_CREDIT__SHIFT 0x0 1048 #define SDMA_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1049 #define SDMA_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1050 #define SDMA_CRD_CNTL__DRM_CREDIT_MASK 0x0000007FL 1051 #define SDMA_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1052 #define SDMA_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1053 //SDMA_GPU_IOV_VIOLATION_LOG 1054 #define SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1055 #define SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1056 #define SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1057 #define SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 1058 #define SDMA_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 1059 #define SDMA_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 1060 #define SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1061 #define SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1062 #define SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 1063 #define SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L 1064 #define SDMA_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L 1065 #define SDMA_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L 1066 //SDMA_ULV_CNTL 1067 #define SDMA_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1068 #define SDMA_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1069 #define SDMA_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1070 #define SDMA_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1071 #define SDMA_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1072 #define SDMA_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1073 #define SDMA_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1074 #define SDMA_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1075 #define SDMA_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1076 #define SDMA_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1077 #define SDMA_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1078 #define SDMA_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1079 //SDMA_EA_DBIT_ADDR_DATA 1080 #define SDMA_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1081 #define SDMA_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1082 //SDMA_EA_DBIT_ADDR_INDEX 1083 #define SDMA_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1084 #define SDMA_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1085 //SDMA_GPU_IOV_VIOLATION_LOG2 1086 #define SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 1087 #define SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 1088 //SDMA_STATUS4_REG 1089 #define SDMA_STATUS4_REG__IDLE__SHIFT 0x0 1090 #define SDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 1091 #define SDMA_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 1092 #define SDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 1093 #define SDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 1094 #define SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 1095 #define SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 1096 #define SDMA_STATUS4_REG__REG_POLLING__SHIFT 0x8 1097 #define SDMA_STATUS4_REG__MEM_POLLING__SHIFT 0x9 1098 #define SDMA_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 1099 #define SDMA_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 1100 #define SDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 1101 #define SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 1102 #define SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 1103 #define SDMA_STATUS4_REG__VM_HOLE_STATUS__SHIFT 0x14 1104 #define SDMA_STATUS4_REG__IDLE_MASK 0x00000001L 1105 #define SDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 1106 #define SDMA_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 1107 #define SDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 1108 #define SDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 1109 #define SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 1110 #define SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 1111 #define SDMA_STATUS4_REG__REG_POLLING_MASK 0x00000100L 1112 #define SDMA_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 1113 #define SDMA_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 1114 #define SDMA_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 1115 #define SDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 1116 #define SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 1117 #define SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L 1118 #define SDMA_STATUS4_REG__VM_HOLE_STATUS_MASK 0x00100000L 1119 //SDMA_SCRATCH_RAM_DATA 1120 #define SDMA_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 1121 #define SDMA_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 1122 //SDMA_SCRATCH_RAM_ADDR 1123 #define SDMA_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 1124 #define SDMA_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 1125 //SDMA_CE_CTRL 1126 #define SDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 1127 #define SDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 1128 #define SDMA_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 1129 #define SDMA_CE_CTRL__RESERVED__SHIFT 0x8 1130 #define SDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 1131 #define SDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 1132 #define SDMA_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 1133 #define SDMA_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 1134 //SDMA_RAS_STATUS 1135 #define SDMA_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 1136 #define SDMA_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 1137 #define SDMA_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 1138 #define SDMA_RAS_STATUS__WPTR_ATOMIC_ECC__SHIFT 0x3 1139 #define SDMA_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 1140 #define SDMA_RAS_STATUS__SRAM_ECC__SHIFT 0x5 1141 #define SDMA_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 1142 #define SDMA_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 1143 #define SDMA_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa 1144 #define SDMA_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb 1145 #define SDMA_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc 1146 #define SDMA_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd 1147 #define SDMA_RAS_STATUS__ECC_PWRMGT_INT_BUSY__SHIFT 0xe 1148 #define SDMA_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L 1149 #define SDMA_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L 1150 #define SDMA_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L 1151 #define SDMA_RAS_STATUS__WPTR_ATOMIC_ECC_MASK 0x00000008L 1152 #define SDMA_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L 1153 #define SDMA_RAS_STATUS__SRAM_ECC_MASK 0x00000020L 1154 #define SDMA_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 1155 #define SDMA_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 1156 #define SDMA_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L 1157 #define SDMA_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L 1158 #define SDMA_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L 1159 #define SDMA_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L 1160 #define SDMA_RAS_STATUS__ECC_PWRMGT_INT_BUSY_MASK 0x00004000L 1161 //SDMA_CLK_STATUS 1162 #define SDMA_CLK_STATUS__DYN_CLK__SHIFT 0x0 1163 #define SDMA_CLK_STATUS__PTR_CLK__SHIFT 0x1 1164 #define SDMA_CLK_STATUS__REG_CLK__SHIFT 0x2 1165 #define SDMA_CLK_STATUS__F32_CLK__SHIFT 0x3 1166 #define SDMA_CLK_STATUS__CE_CLK__SHIFT 0x4 1167 #define SDMA_CLK_STATUS__PERF_CLK__SHIFT 0x5 1168 #define SDMA_CLK_STATUS__DYN_CLK_MASK 0x00000001L 1169 #define SDMA_CLK_STATUS__PTR_CLK_MASK 0x00000002L 1170 #define SDMA_CLK_STATUS__REG_CLK_MASK 0x00000004L 1171 #define SDMA_CLK_STATUS__F32_CLK_MASK 0x00000008L 1172 #define SDMA_CLK_STATUS__CE_CLK_MASK 0x00000010L 1173 #define SDMA_CLK_STATUS__PERF_CLK_MASK 0x00000020L 1174 //SDMA_POWER_CNTL 1175 #define SDMA_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 1176 #define SDMA_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 1177 #define SDMA_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 1178 #define SDMA_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 1179 #define SDMA_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 1180 #define SDMA_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 1181 #define SDMA_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 1182 #define SDMA_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 1183 #define SDMA_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 1184 #define SDMA_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 1185 #define SDMA_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 1186 #define SDMA_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 1187 #define SDMA_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 1188 #define SDMA_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 1189 #define SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 1190 #define SDMA_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 1191 #define SDMA_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 1192 #define SDMA_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 1193 #define SDMA_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 1194 #define SDMA_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 1195 //SDMA_CLK_CTRL 1196 #define SDMA_CLK_CTRL__ON_DELAY__SHIFT 0x0 1197 #define SDMA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1198 #define SDMA_CLK_CTRL__RESERVED__SHIFT 0xc 1199 #define SDMA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 1200 #define SDMA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 1201 #define SDMA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 1202 #define SDMA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 1203 #define SDMA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 1204 #define SDMA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1205 #define SDMA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 1206 #define SDMA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 1207 #define SDMA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1208 #define SDMA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1209 #define SDMA_CLK_CTRL__RESERVED_MASK 0x00FFF000L 1210 #define SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1211 #define SDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 1212 #define SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 1213 #define SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1214 #define SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1215 #define SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 1216 #define SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 1217 #define SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 1218 //SDMA_CNTL 1219 #define SDMA_CNTL__TRAP_ENABLE__SHIFT 0x0 1220 #define SDMA_CNTL__UTC_L1_ENABLE__SHIFT 0x1 1221 #define SDMA_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 1222 #define SDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 1223 #define SDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 1224 #define SDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 1225 #define SDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 1226 #define SDMA_CNTL__REG_WRITE_PROTECT_INT_ENABLE__SHIFT 0x7 1227 #define SDMA_CNTL__INVALID_DOORBELL_INT_ENABLE__SHIFT 0x8 1228 #define SDMA_CNTL__VM_HOLE_INT_ENABLE__SHIFT 0x9 1229 #define SDMA_CNTL__DRAM_ECC_INT_ENABLE__SHIFT 0xa 1230 #define SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb 1231 #define SDMA_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc 1232 #define SDMA_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd 1233 #define SDMA_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe 1234 #define SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 1235 #define SDMA_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 1236 #define SDMA_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x13 1237 #define SDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 1238 #define SDMA_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 1239 #define SDMA_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 1240 #define SDMA_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f 1241 #define SDMA_CNTL__TRAP_ENABLE_MASK 0x00000001L 1242 #define SDMA_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 1243 #define SDMA_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 1244 #define SDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 1245 #define SDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 1246 #define SDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 1247 #define SDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 1248 #define SDMA_CNTL__REG_WRITE_PROTECT_INT_ENABLE_MASK 0x00000080L 1249 #define SDMA_CNTL__INVALID_DOORBELL_INT_ENABLE_MASK 0x00000100L 1250 #define SDMA_CNTL__VM_HOLE_INT_ENABLE_MASK 0x00000200L 1251 #define SDMA_CNTL__DRAM_ECC_INT_ENABLE_MASK 0x00000400L 1252 #define SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L 1253 #define SDMA_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L 1254 #define SDMA_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L 1255 #define SDMA_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L 1256 #define SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 1257 #define SDMA_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 1258 #define SDMA_CNTL__DRM_RESTORE_ENABLE_MASK 0x00080000L 1259 #define SDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 1260 #define SDMA_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 1261 #define SDMA_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 1262 #define SDMA_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L 1263 //SDMA_CHICKEN_BITS 1264 #define SDMA_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 1265 #define SDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 1266 #define SDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 1267 #define SDMA_CHICKEN_BITS__F32_MGCG_ENABLE__SHIFT 0x3 1268 #define SDMA_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 1269 #define SDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 1270 #define SDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 1271 #define SDMA_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 1272 #define SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 1273 #define SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 1274 #define SDMA_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a 1275 #define SDMA_CHICKEN_BITS__RESERVED__SHIFT 0x1b 1276 #define SDMA_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 1277 #define SDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 1278 #define SDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 1279 #define SDMA_CHICKEN_BITS__F32_MGCG_ENABLE_MASK 0x00000008L 1280 #define SDMA_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 1281 #define SDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 1282 #define SDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 1283 #define SDMA_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 1284 #define SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 1285 #define SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 1286 #define SDMA_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L 1287 #define SDMA_CHICKEN_BITS__RESERVED_MASK 0xF8000000L 1288 //SDMA_GB_ADDR_CONFIG 1289 #define SDMA_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1290 #define SDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1291 #define SDMA_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1292 #define SDMA_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 1293 #define SDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 1294 #define SDMA_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 1295 #define SDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1296 #define SDMA_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 1297 #define SDMA_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 1298 #define SDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 1299 //SDMA_GB_ADDR_CONFIG_READ 1300 #define SDMA_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 1301 #define SDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1302 #define SDMA_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1303 #define SDMA_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 1304 #define SDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 1305 #define SDMA_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 1306 #define SDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1307 #define SDMA_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 1308 #define SDMA_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 1309 #define SDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 1310 //SDMA_GFX_RB_CNTL 1311 #define SDMA_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1312 #define SDMA_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1313 #define SDMA_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1314 #define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1315 #define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1316 #define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1317 #define SDMA_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1318 #define SDMA_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1319 #define SDMA_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1320 #define SDMA_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1321 #define SDMA_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1322 #define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1323 #define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1324 #define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1325 #define SDMA_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1326 #define SDMA_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1327 //SDMA_GFX_RB_BASE 1328 #define SDMA_GFX_RB_BASE__ADDR__SHIFT 0x0 1329 #define SDMA_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1330 //SDMA_GFX_RB_BASE_HI 1331 #define SDMA_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1332 #define SDMA_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1333 //SDMA_GFX_RB_RPTR 1334 #define SDMA_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1335 #define SDMA_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1336 //SDMA_GFX_RB_RPTR_HI 1337 #define SDMA_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1338 #define SDMA_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1339 //SDMA_GFX_RB_WPTR 1340 #define SDMA_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1341 #define SDMA_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1342 //SDMA_GFX_RB_WPTR_HI 1343 #define SDMA_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1344 #define SDMA_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1345 //SDMA_GFX_RB_WPTR_POLL_CNTL 1346 #define SDMA_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1347 #define SDMA_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1348 #define SDMA_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1349 #define SDMA_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1350 #define SDMA_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1351 #define SDMA_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1352 #define SDMA_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1353 #define SDMA_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1354 #define SDMA_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1355 #define SDMA_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1356 //SDMA_GFX_RB_RPTR_ADDR_HI 1357 #define SDMA_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1358 #define SDMA_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1359 //SDMA_GFX_RB_RPTR_ADDR_LO 1360 #define SDMA_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1361 #define SDMA_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1362 #define SDMA_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1363 #define SDMA_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1364 //SDMA_GFX_IB_CNTL 1365 #define SDMA_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1366 #define SDMA_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1367 #define SDMA_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1368 #define SDMA_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1369 #define SDMA_GFX_IB_CNTL__IB_PRIV__SHIFT 0x1f 1370 #define SDMA_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1371 #define SDMA_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1372 #define SDMA_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1373 #define SDMA_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1374 #define SDMA_GFX_IB_CNTL__IB_PRIV_MASK 0x80000000L 1375 //SDMA_GFX_IB_RPTR 1376 #define SDMA_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1377 #define SDMA_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1378 //SDMA_GFX_IB_OFFSET 1379 #define SDMA_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1380 #define SDMA_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1381 //SDMA_GFX_IB_BASE_LO 1382 #define SDMA_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1383 #define SDMA_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1384 //SDMA_GFX_IB_BASE_HI 1385 #define SDMA_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1386 #define SDMA_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1387 //SDMA_GFX_IB_SIZE 1388 #define SDMA_GFX_IB_SIZE__SIZE__SHIFT 0x0 1389 #define SDMA_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1390 //SDMA_GFX_SKIP_CNTL 1391 #define SDMA_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1392 #define SDMA_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1393 //SDMA_GFX_CONTEXT_STATUS 1394 #define SDMA_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1395 #define SDMA_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1396 #define SDMA_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1397 #define SDMA_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1398 #define SDMA_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1399 #define SDMA_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1400 #define SDMA_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1401 #define SDMA_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1402 #define SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1403 #define SDMA_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1404 #define SDMA_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1405 #define SDMA_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1406 #define SDMA_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1407 #define SDMA_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1408 #define SDMA_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1409 #define SDMA_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1410 //SDMA_GFX_DOORBELL 1411 #define SDMA_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1412 #define SDMA_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1413 #define SDMA_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1414 #define SDMA_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1415 //SDMA_GFX_CONTEXT_CNTL 1416 #define SDMA_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1417 #define SDMA_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 1418 #define SDMA_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1419 #define SDMA_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L 1420 //SDMA_GFX_STATUS 1421 #define SDMA_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1422 #define SDMA_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1423 #define SDMA_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1424 #define SDMA_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1425 //SDMA_GFX_DOORBELL_LOG 1426 #define SDMA_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1427 #define SDMA_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1428 #define SDMA_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1429 #define SDMA_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1430 //SDMA_GFX_WATERMARK 1431 #define SDMA_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1432 #define SDMA_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1433 #define SDMA_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1434 #define SDMA_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1435 //SDMA_GFX_DOORBELL_OFFSET 1436 #define SDMA_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1437 #define SDMA_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1438 //SDMA_GFX_CSA_ADDR_LO 1439 #define SDMA_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1440 #define SDMA_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1441 //SDMA_GFX_CSA_ADDR_HI 1442 #define SDMA_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1443 #define SDMA_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1444 //SDMA_GFX_IB_SUB_REMAIN 1445 #define SDMA_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1446 #define SDMA_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1447 //SDMA_GFX_PREEMPT 1448 #define SDMA_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1449 #define SDMA_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1450 //SDMA_GFX_DUMMY_REG 1451 #define SDMA_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1452 #define SDMA_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1453 //SDMA_GFX_RB_WPTR_POLL_ADDR_HI 1454 #define SDMA_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1455 #define SDMA_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1456 //SDMA_GFX_RB_WPTR_POLL_ADDR_LO 1457 #define SDMA_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1458 #define SDMA_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1459 //SDMA_GFX_RB_AQL_CNTL 1460 #define SDMA_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1461 #define SDMA_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1462 #define SDMA_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1463 #define SDMA_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1464 #define SDMA_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1465 #define SDMA_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1466 //SDMA_GFX_MINOR_PTR_UPDATE 1467 #define SDMA_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1468 #define SDMA_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1469 //SDMA_GFX_MIDCMD_DATA0 1470 #define SDMA_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1471 #define SDMA_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1472 //SDMA_GFX_MIDCMD_DATA1 1473 #define SDMA_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1474 #define SDMA_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1475 //SDMA_GFX_MIDCMD_DATA2 1476 #define SDMA_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1477 #define SDMA_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1478 //SDMA_GFX_MIDCMD_DATA3 1479 #define SDMA_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1480 #define SDMA_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1481 //SDMA_GFX_MIDCMD_DATA4 1482 #define SDMA_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1483 #define SDMA_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1484 //SDMA_GFX_MIDCMD_DATA5 1485 #define SDMA_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1486 #define SDMA_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1487 //SDMA_GFX_MIDCMD_DATA6 1488 #define SDMA_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1489 #define SDMA_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1490 //SDMA_GFX_MIDCMD_DATA7 1491 #define SDMA_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1492 #define SDMA_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1493 //SDMA_GFX_MIDCMD_DATA8 1494 #define SDMA_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1495 #define SDMA_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1496 //SDMA_GFX_MIDCMD_DATA9 1497 #define SDMA_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 1498 #define SDMA_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1499 //SDMA_GFX_MIDCMD_DATA10 1500 #define SDMA_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 1501 #define SDMA_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1502 //SDMA_GFX_MIDCMD_CNTL 1503 #define SDMA_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1504 #define SDMA_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1505 #define SDMA_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1506 #define SDMA_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1507 #define SDMA_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1508 #define SDMA_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1509 #define SDMA_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1510 #define SDMA_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1511 //SDMA_PAGE_RB_CNTL 1512 #define SDMA_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1513 #define SDMA_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1514 #define SDMA_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1515 #define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1516 #define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1517 #define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1518 #define SDMA_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1519 #define SDMA_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1520 #define SDMA_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1521 #define SDMA_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1522 #define SDMA_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1523 #define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1524 #define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1525 #define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1526 #define SDMA_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1527 #define SDMA_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1528 //SDMA_PAGE_RB_BASE 1529 #define SDMA_PAGE_RB_BASE__ADDR__SHIFT 0x0 1530 #define SDMA_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1531 //SDMA_PAGE_RB_BASE_HI 1532 #define SDMA_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1533 #define SDMA_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1534 //SDMA_PAGE_RB_RPTR 1535 #define SDMA_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1536 #define SDMA_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1537 //SDMA_PAGE_RB_RPTR_HI 1538 #define SDMA_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1539 #define SDMA_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1540 //SDMA_PAGE_RB_WPTR 1541 #define SDMA_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1542 #define SDMA_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1543 //SDMA_PAGE_RB_WPTR_HI 1544 #define SDMA_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1545 #define SDMA_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1546 //SDMA_PAGE_RB_WPTR_POLL_CNTL 1547 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1548 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1549 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1550 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1551 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1552 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1553 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1554 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1555 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1556 #define SDMA_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1557 //SDMA_PAGE_RB_RPTR_ADDR_HI 1558 #define SDMA_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1559 #define SDMA_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1560 //SDMA_PAGE_RB_RPTR_ADDR_LO 1561 #define SDMA_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1562 #define SDMA_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1563 #define SDMA_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1564 #define SDMA_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1565 //SDMA_PAGE_IB_CNTL 1566 #define SDMA_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1567 #define SDMA_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1568 #define SDMA_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1569 #define SDMA_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1570 #define SDMA_PAGE_IB_CNTL__IB_PRIV__SHIFT 0x1f 1571 #define SDMA_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1572 #define SDMA_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1573 #define SDMA_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1574 #define SDMA_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1575 #define SDMA_PAGE_IB_CNTL__IB_PRIV_MASK 0x80000000L 1576 //SDMA_PAGE_IB_RPTR 1577 #define SDMA_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1578 #define SDMA_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1579 //SDMA_PAGE_IB_OFFSET 1580 #define SDMA_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1581 #define SDMA_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1582 //SDMA_PAGE_IB_BASE_LO 1583 #define SDMA_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1584 #define SDMA_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1585 //SDMA_PAGE_IB_BASE_HI 1586 #define SDMA_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1587 #define SDMA_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1588 //SDMA_PAGE_IB_SIZE 1589 #define SDMA_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1590 #define SDMA_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1591 //SDMA_PAGE_SKIP_CNTL 1592 #define SDMA_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1593 #define SDMA_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1594 //SDMA_PAGE_CONTEXT_STATUS 1595 #define SDMA_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1596 #define SDMA_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1597 #define SDMA_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1598 #define SDMA_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1599 #define SDMA_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1600 #define SDMA_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1601 #define SDMA_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1602 #define SDMA_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1603 #define SDMA_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1604 #define SDMA_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1605 #define SDMA_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1606 #define SDMA_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1607 #define SDMA_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1608 #define SDMA_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1609 #define SDMA_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1610 #define SDMA_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1611 //SDMA_PAGE_DOORBELL 1612 #define SDMA_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1613 #define SDMA_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1614 #define SDMA_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1615 #define SDMA_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1616 //SDMA_PAGE_STATUS 1617 #define SDMA_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1618 #define SDMA_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1619 #define SDMA_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1620 #define SDMA_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1621 //SDMA_PAGE_DOORBELL_LOG 1622 #define SDMA_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1623 #define SDMA_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1624 #define SDMA_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1625 #define SDMA_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1626 //SDMA_PAGE_WATERMARK 1627 #define SDMA_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1628 #define SDMA_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1629 #define SDMA_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1630 #define SDMA_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1631 //SDMA_PAGE_DOORBELL_OFFSET 1632 #define SDMA_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1633 #define SDMA_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1634 //SDMA_PAGE_CSA_ADDR_LO 1635 #define SDMA_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1636 #define SDMA_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1637 //SDMA_PAGE_CSA_ADDR_HI 1638 #define SDMA_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1639 #define SDMA_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1640 //SDMA_PAGE_IB_SUB_REMAIN 1641 #define SDMA_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1642 #define SDMA_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1643 //SDMA_PAGE_PREEMPT 1644 #define SDMA_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1645 #define SDMA_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1646 //SDMA_PAGE_DUMMY_REG 1647 #define SDMA_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1648 #define SDMA_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1649 //SDMA_PAGE_RB_WPTR_POLL_ADDR_HI 1650 #define SDMA_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1651 #define SDMA_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1652 //SDMA_PAGE_RB_WPTR_POLL_ADDR_LO 1653 #define SDMA_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1654 #define SDMA_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1655 //SDMA_PAGE_RB_AQL_CNTL 1656 #define SDMA_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1657 #define SDMA_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1658 #define SDMA_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1659 #define SDMA_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1660 #define SDMA_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1661 #define SDMA_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1662 //SDMA_PAGE_MINOR_PTR_UPDATE 1663 #define SDMA_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1664 #define SDMA_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1665 //SDMA_PAGE_MIDCMD_DATA0 1666 #define SDMA_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1667 #define SDMA_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1668 //SDMA_PAGE_MIDCMD_DATA1 1669 #define SDMA_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1670 #define SDMA_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1671 //SDMA_PAGE_MIDCMD_DATA2 1672 #define SDMA_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1673 #define SDMA_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1674 //SDMA_PAGE_MIDCMD_DATA3 1675 #define SDMA_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1676 #define SDMA_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1677 //SDMA_PAGE_MIDCMD_DATA4 1678 #define SDMA_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1679 #define SDMA_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1680 //SDMA_PAGE_MIDCMD_DATA5 1681 #define SDMA_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1682 #define SDMA_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1683 //SDMA_PAGE_MIDCMD_DATA6 1684 #define SDMA_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1685 #define SDMA_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1686 //SDMA_PAGE_MIDCMD_DATA7 1687 #define SDMA_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1688 #define SDMA_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1689 //SDMA_PAGE_MIDCMD_DATA8 1690 #define SDMA_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1691 #define SDMA_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1692 //SDMA_PAGE_MIDCMD_DATA9 1693 #define SDMA_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 1694 #define SDMA_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1695 //SDMA_PAGE_MIDCMD_DATA10 1696 #define SDMA_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 1697 #define SDMA_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1698 //SDMA_PAGE_MIDCMD_CNTL 1699 #define SDMA_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1700 #define SDMA_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1701 #define SDMA_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1702 #define SDMA_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1703 #define SDMA_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1704 #define SDMA_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1705 #define SDMA_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1706 #define SDMA_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1707 //SDMA_RLC0_RB_CNTL 1708 #define SDMA_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1709 #define SDMA_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1710 #define SDMA_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1711 #define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1712 #define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1713 #define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1714 #define SDMA_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1715 #define SDMA_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1716 #define SDMA_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1717 #define SDMA_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1718 #define SDMA_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1719 #define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1720 #define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1721 #define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1722 #define SDMA_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1723 #define SDMA_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1724 //SDMA_RLC0_RB_BASE 1725 #define SDMA_RLC0_RB_BASE__ADDR__SHIFT 0x0 1726 #define SDMA_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1727 //SDMA_RLC0_RB_BASE_HI 1728 #define SDMA_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1729 #define SDMA_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1730 //SDMA_RLC0_RB_RPTR 1731 #define SDMA_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1732 #define SDMA_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1733 //SDMA_RLC0_RB_RPTR_HI 1734 #define SDMA_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1735 #define SDMA_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1736 //SDMA_RLC0_RB_WPTR 1737 #define SDMA_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1738 #define SDMA_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1739 //SDMA_RLC0_RB_WPTR_HI 1740 #define SDMA_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1741 #define SDMA_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1742 //SDMA_RLC0_RB_WPTR_POLL_CNTL 1743 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1744 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1745 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1746 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1747 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1748 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1749 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1750 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1751 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1752 #define SDMA_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1753 //SDMA_RLC0_RB_RPTR_ADDR_HI 1754 #define SDMA_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1755 #define SDMA_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1756 //SDMA_RLC0_RB_RPTR_ADDR_LO 1757 #define SDMA_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1758 #define SDMA_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1759 #define SDMA_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1760 #define SDMA_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1761 //SDMA_RLC0_IB_CNTL 1762 #define SDMA_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1763 #define SDMA_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1764 #define SDMA_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1765 #define SDMA_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1766 #define SDMA_RLC0_IB_CNTL__IB_PRIV__SHIFT 0x1f 1767 #define SDMA_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1768 #define SDMA_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1769 #define SDMA_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1770 #define SDMA_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1771 #define SDMA_RLC0_IB_CNTL__IB_PRIV_MASK 0x80000000L 1772 //SDMA_RLC0_IB_RPTR 1773 #define SDMA_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1774 #define SDMA_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1775 //SDMA_RLC0_IB_OFFSET 1776 #define SDMA_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1777 #define SDMA_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1778 //SDMA_RLC0_IB_BASE_LO 1779 #define SDMA_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1780 #define SDMA_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1781 //SDMA_RLC0_IB_BASE_HI 1782 #define SDMA_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1783 #define SDMA_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1784 //SDMA_RLC0_IB_SIZE 1785 #define SDMA_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1786 #define SDMA_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1787 //SDMA_RLC0_SKIP_CNTL 1788 #define SDMA_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1789 #define SDMA_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1790 //SDMA_RLC0_CONTEXT_STATUS 1791 #define SDMA_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1792 #define SDMA_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1793 #define SDMA_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1794 #define SDMA_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1795 #define SDMA_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1796 #define SDMA_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1797 #define SDMA_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1798 #define SDMA_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1799 #define SDMA_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1800 #define SDMA_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1801 #define SDMA_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1802 #define SDMA_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1803 #define SDMA_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1804 #define SDMA_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1805 #define SDMA_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1806 #define SDMA_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1807 //SDMA_RLC0_DOORBELL 1808 #define SDMA_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1809 #define SDMA_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1810 #define SDMA_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1811 #define SDMA_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1812 //SDMA_RLC0_STATUS 1813 #define SDMA_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1814 #define SDMA_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1815 #define SDMA_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1816 #define SDMA_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1817 //SDMA_RLC0_DOORBELL_LOG 1818 #define SDMA_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1819 #define SDMA_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1820 #define SDMA_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1821 #define SDMA_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1822 //SDMA_RLC0_WATERMARK 1823 #define SDMA_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1824 #define SDMA_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1825 #define SDMA_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1826 #define SDMA_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1827 //SDMA_RLC0_DOORBELL_OFFSET 1828 #define SDMA_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1829 #define SDMA_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1830 //SDMA_RLC0_CSA_ADDR_LO 1831 #define SDMA_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1832 #define SDMA_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1833 //SDMA_RLC0_CSA_ADDR_HI 1834 #define SDMA_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1835 #define SDMA_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1836 //SDMA_RLC0_IB_SUB_REMAIN 1837 #define SDMA_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1838 #define SDMA_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1839 //SDMA_RLC0_PREEMPT 1840 #define SDMA_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1841 #define SDMA_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1842 //SDMA_RLC0_DUMMY_REG 1843 #define SDMA_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1844 #define SDMA_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1845 //SDMA_RLC0_RB_WPTR_POLL_ADDR_HI 1846 #define SDMA_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1847 #define SDMA_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1848 //SDMA_RLC0_RB_WPTR_POLL_ADDR_LO 1849 #define SDMA_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1850 #define SDMA_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1851 //SDMA_RLC0_RB_AQL_CNTL 1852 #define SDMA_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1853 #define SDMA_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1854 #define SDMA_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1855 #define SDMA_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1856 #define SDMA_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1857 #define SDMA_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1858 //SDMA_RLC0_MINOR_PTR_UPDATE 1859 #define SDMA_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1860 #define SDMA_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1861 //SDMA_RLC0_MIDCMD_DATA0 1862 #define SDMA_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1863 #define SDMA_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1864 //SDMA_RLC0_MIDCMD_DATA1 1865 #define SDMA_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1866 #define SDMA_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1867 //SDMA_RLC0_MIDCMD_DATA2 1868 #define SDMA_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1869 #define SDMA_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1870 //SDMA_RLC0_MIDCMD_DATA3 1871 #define SDMA_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1872 #define SDMA_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1873 //SDMA_RLC0_MIDCMD_DATA4 1874 #define SDMA_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1875 #define SDMA_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1876 //SDMA_RLC0_MIDCMD_DATA5 1877 #define SDMA_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1878 #define SDMA_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1879 //SDMA_RLC0_MIDCMD_DATA6 1880 #define SDMA_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1881 #define SDMA_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1882 //SDMA_RLC0_MIDCMD_DATA7 1883 #define SDMA_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1884 #define SDMA_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1885 //SDMA_RLC0_MIDCMD_DATA8 1886 #define SDMA_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1887 #define SDMA_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1888 //SDMA_RLC0_MIDCMD_DATA9 1889 #define SDMA_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 1890 #define SDMA_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1891 //SDMA_RLC0_MIDCMD_DATA10 1892 #define SDMA_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 1893 #define SDMA_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1894 //SDMA_RLC0_MIDCMD_CNTL 1895 #define SDMA_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1896 #define SDMA_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1897 #define SDMA_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1898 #define SDMA_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1899 #define SDMA_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1900 #define SDMA_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1901 #define SDMA_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1902 #define SDMA_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1903 //SDMA_RLC1_RB_CNTL 1904 #define SDMA_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1905 #define SDMA_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1906 #define SDMA_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1907 #define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1908 #define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1909 #define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1910 #define SDMA_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1911 #define SDMA_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1912 #define SDMA_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1913 #define SDMA_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1914 #define SDMA_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1915 #define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1916 #define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1917 #define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1918 #define SDMA_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1919 #define SDMA_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1920 //SDMA_RLC1_RB_BASE 1921 #define SDMA_RLC1_RB_BASE__ADDR__SHIFT 0x0 1922 #define SDMA_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1923 //SDMA_RLC1_RB_BASE_HI 1924 #define SDMA_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1925 #define SDMA_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1926 //SDMA_RLC1_RB_RPTR 1927 #define SDMA_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1928 #define SDMA_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1929 //SDMA_RLC1_RB_RPTR_HI 1930 #define SDMA_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1931 #define SDMA_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1932 //SDMA_RLC1_RB_WPTR 1933 #define SDMA_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1934 #define SDMA_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1935 //SDMA_RLC1_RB_WPTR_HI 1936 #define SDMA_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1937 #define SDMA_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1938 //SDMA_RLC1_RB_WPTR_POLL_CNTL 1939 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1940 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1941 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1942 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1943 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1944 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1945 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1946 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1947 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1948 #define SDMA_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1949 //SDMA_RLC1_RB_RPTR_ADDR_HI 1950 #define SDMA_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1951 #define SDMA_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1952 //SDMA_RLC1_RB_RPTR_ADDR_LO 1953 #define SDMA_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1954 #define SDMA_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1955 #define SDMA_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1956 #define SDMA_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1957 //SDMA_RLC1_IB_CNTL 1958 #define SDMA_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1959 #define SDMA_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1960 #define SDMA_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1961 #define SDMA_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1962 #define SDMA_RLC1_IB_CNTL__IB_PRIV__SHIFT 0x1f 1963 #define SDMA_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1964 #define SDMA_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1965 #define SDMA_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1966 #define SDMA_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1967 #define SDMA_RLC1_IB_CNTL__IB_PRIV_MASK 0x80000000L 1968 //SDMA_RLC1_IB_RPTR 1969 #define SDMA_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1970 #define SDMA_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1971 //SDMA_RLC1_IB_OFFSET 1972 #define SDMA_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1973 #define SDMA_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1974 //SDMA_RLC1_IB_BASE_LO 1975 #define SDMA_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1976 #define SDMA_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1977 //SDMA_RLC1_IB_BASE_HI 1978 #define SDMA_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1979 #define SDMA_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1980 //SDMA_RLC1_IB_SIZE 1981 #define SDMA_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1982 #define SDMA_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1983 //SDMA_RLC1_SKIP_CNTL 1984 #define SDMA_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1985 #define SDMA_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1986 //SDMA_RLC1_CONTEXT_STATUS 1987 #define SDMA_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1988 #define SDMA_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1989 #define SDMA_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1990 #define SDMA_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1991 #define SDMA_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1992 #define SDMA_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1993 #define SDMA_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1994 #define SDMA_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1995 #define SDMA_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1996 #define SDMA_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1997 #define SDMA_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1998 #define SDMA_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1999 #define SDMA_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2000 #define SDMA_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2001 #define SDMA_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2002 #define SDMA_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2003 //SDMA_RLC1_DOORBELL 2004 #define SDMA_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 2005 #define SDMA_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 2006 #define SDMA_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 2007 #define SDMA_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 2008 //SDMA_RLC1_STATUS 2009 #define SDMA_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2010 #define SDMA_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2011 #define SDMA_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2012 #define SDMA_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2013 //SDMA_RLC1_DOORBELL_LOG 2014 #define SDMA_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2015 #define SDMA_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 2016 #define SDMA_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2017 #define SDMA_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2018 //SDMA_RLC1_WATERMARK 2019 #define SDMA_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2020 #define SDMA_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2021 #define SDMA_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2022 #define SDMA_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2023 //SDMA_RLC1_DOORBELL_OFFSET 2024 #define SDMA_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2025 #define SDMA_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2026 //SDMA_RLC1_CSA_ADDR_LO 2027 #define SDMA_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 2028 #define SDMA_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2029 //SDMA_RLC1_CSA_ADDR_HI 2030 #define SDMA_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 2031 #define SDMA_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2032 //SDMA_RLC1_IB_SUB_REMAIN 2033 #define SDMA_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2034 #define SDMA_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2035 //SDMA_RLC1_PREEMPT 2036 #define SDMA_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 2037 #define SDMA_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2038 //SDMA_RLC1_DUMMY_REG 2039 #define SDMA_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 2040 #define SDMA_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2041 //SDMA_RLC1_RB_WPTR_POLL_ADDR_HI 2042 #define SDMA_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2043 #define SDMA_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2044 //SDMA_RLC1_RB_WPTR_POLL_ADDR_LO 2045 #define SDMA_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2046 #define SDMA_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2047 //SDMA_RLC1_RB_AQL_CNTL 2048 #define SDMA_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2049 #define SDMA_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2050 #define SDMA_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2051 #define SDMA_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2052 #define SDMA_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2053 #define SDMA_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2054 //SDMA_RLC1_MINOR_PTR_UPDATE 2055 #define SDMA_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2056 #define SDMA_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2057 //SDMA_RLC1_MIDCMD_DATA0 2058 #define SDMA_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 2059 #define SDMA_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2060 //SDMA_RLC1_MIDCMD_DATA1 2061 #define SDMA_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 2062 #define SDMA_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2063 //SDMA_RLC1_MIDCMD_DATA2 2064 #define SDMA_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 2065 #define SDMA_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2066 //SDMA_RLC1_MIDCMD_DATA3 2067 #define SDMA_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 2068 #define SDMA_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2069 //SDMA_RLC1_MIDCMD_DATA4 2070 #define SDMA_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 2071 #define SDMA_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2072 //SDMA_RLC1_MIDCMD_DATA5 2073 #define SDMA_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 2074 #define SDMA_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2075 //SDMA_RLC1_MIDCMD_DATA6 2076 #define SDMA_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 2077 #define SDMA_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2078 //SDMA_RLC1_MIDCMD_DATA7 2079 #define SDMA_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 2080 #define SDMA_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2081 //SDMA_RLC1_MIDCMD_DATA8 2082 #define SDMA_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 2083 #define SDMA_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2084 //SDMA_RLC1_MIDCMD_DATA9 2085 #define SDMA_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 2086 #define SDMA_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2087 //SDMA_RLC1_MIDCMD_DATA10 2088 #define SDMA_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 2089 #define SDMA_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2090 //SDMA_RLC1_MIDCMD_CNTL 2091 #define SDMA_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2092 #define SDMA_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2093 #define SDMA_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2094 #define SDMA_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2095 #define SDMA_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2096 #define SDMA_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2097 #define SDMA_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2098 #define SDMA_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2099 //SDMA_RLC2_RB_CNTL 2100 #define SDMA_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 2101 #define SDMA_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 2102 #define SDMA_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2103 #define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2104 #define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2105 #define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2106 #define SDMA_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 2107 #define SDMA_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 2108 #define SDMA_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2109 #define SDMA_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2110 #define SDMA_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2111 #define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2112 #define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2113 #define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2114 #define SDMA_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 2115 #define SDMA_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 2116 //SDMA_RLC2_RB_BASE 2117 #define SDMA_RLC2_RB_BASE__ADDR__SHIFT 0x0 2118 #define SDMA_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2119 //SDMA_RLC2_RB_BASE_HI 2120 #define SDMA_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 2121 #define SDMA_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2122 //SDMA_RLC2_RB_RPTR 2123 #define SDMA_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 2124 #define SDMA_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2125 //SDMA_RLC2_RB_RPTR_HI 2126 #define SDMA_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 2127 #define SDMA_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2128 //SDMA_RLC2_RB_WPTR 2129 #define SDMA_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 2130 #define SDMA_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2131 //SDMA_RLC2_RB_WPTR_HI 2132 #define SDMA_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 2133 #define SDMA_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2134 //SDMA_RLC2_RB_WPTR_POLL_CNTL 2135 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2136 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2137 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2138 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2139 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2140 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2141 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2142 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2143 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2144 #define SDMA_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2145 //SDMA_RLC2_RB_RPTR_ADDR_HI 2146 #define SDMA_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2147 #define SDMA_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2148 //SDMA_RLC2_RB_RPTR_ADDR_LO 2149 #define SDMA_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2150 #define SDMA_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2151 #define SDMA_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2152 #define SDMA_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2153 //SDMA_RLC2_IB_CNTL 2154 #define SDMA_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 2155 #define SDMA_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2156 #define SDMA_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2157 #define SDMA_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 2158 #define SDMA_RLC2_IB_CNTL__IB_PRIV__SHIFT 0x1f 2159 #define SDMA_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2160 #define SDMA_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2161 #define SDMA_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2162 #define SDMA_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2163 #define SDMA_RLC2_IB_CNTL__IB_PRIV_MASK 0x80000000L 2164 //SDMA_RLC2_IB_RPTR 2165 #define SDMA_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 2166 #define SDMA_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2167 //SDMA_RLC2_IB_OFFSET 2168 #define SDMA_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 2169 #define SDMA_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2170 //SDMA_RLC2_IB_BASE_LO 2171 #define SDMA_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 2172 #define SDMA_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2173 //SDMA_RLC2_IB_BASE_HI 2174 #define SDMA_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 2175 #define SDMA_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2176 //SDMA_RLC2_IB_SIZE 2177 #define SDMA_RLC2_IB_SIZE__SIZE__SHIFT 0x0 2178 #define SDMA_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 2179 //SDMA_RLC2_SKIP_CNTL 2180 #define SDMA_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2181 #define SDMA_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2182 //SDMA_RLC2_CONTEXT_STATUS 2183 #define SDMA_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2184 #define SDMA_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 2185 #define SDMA_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2186 #define SDMA_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2187 #define SDMA_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2188 #define SDMA_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2189 #define SDMA_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2190 #define SDMA_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2191 #define SDMA_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2192 #define SDMA_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2193 #define SDMA_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2194 #define SDMA_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2195 #define SDMA_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2196 #define SDMA_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2197 #define SDMA_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2198 #define SDMA_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2199 //SDMA_RLC2_DOORBELL 2200 #define SDMA_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 2201 #define SDMA_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 2202 #define SDMA_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 2203 #define SDMA_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 2204 //SDMA_RLC2_STATUS 2205 #define SDMA_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2206 #define SDMA_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2207 #define SDMA_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2208 #define SDMA_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2209 //SDMA_RLC2_DOORBELL_LOG 2210 #define SDMA_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2211 #define SDMA_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 2212 #define SDMA_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2213 #define SDMA_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2214 //SDMA_RLC2_WATERMARK 2215 #define SDMA_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2216 #define SDMA_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2217 #define SDMA_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2218 #define SDMA_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2219 //SDMA_RLC2_DOORBELL_OFFSET 2220 #define SDMA_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2221 #define SDMA_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2222 //SDMA_RLC2_CSA_ADDR_LO 2223 #define SDMA_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 2224 #define SDMA_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2225 //SDMA_RLC2_CSA_ADDR_HI 2226 #define SDMA_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 2227 #define SDMA_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2228 //SDMA_RLC2_IB_SUB_REMAIN 2229 #define SDMA_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2230 #define SDMA_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2231 //SDMA_RLC2_PREEMPT 2232 #define SDMA_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 2233 #define SDMA_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2234 //SDMA_RLC2_DUMMY_REG 2235 #define SDMA_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 2236 #define SDMA_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2237 //SDMA_RLC2_RB_WPTR_POLL_ADDR_HI 2238 #define SDMA_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2239 #define SDMA_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2240 //SDMA_RLC2_RB_WPTR_POLL_ADDR_LO 2241 #define SDMA_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2242 #define SDMA_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2243 //SDMA_RLC2_RB_AQL_CNTL 2244 #define SDMA_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2245 #define SDMA_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2246 #define SDMA_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2247 #define SDMA_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2248 #define SDMA_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2249 #define SDMA_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2250 //SDMA_RLC2_MINOR_PTR_UPDATE 2251 #define SDMA_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2252 #define SDMA_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2253 //SDMA_RLC2_MIDCMD_DATA0 2254 #define SDMA_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2255 #define SDMA_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2256 //SDMA_RLC2_MIDCMD_DATA1 2257 #define SDMA_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2258 #define SDMA_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2259 //SDMA_RLC2_MIDCMD_DATA2 2260 #define SDMA_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2261 #define SDMA_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2262 //SDMA_RLC2_MIDCMD_DATA3 2263 #define SDMA_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2264 #define SDMA_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2265 //SDMA_RLC2_MIDCMD_DATA4 2266 #define SDMA_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2267 #define SDMA_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2268 //SDMA_RLC2_MIDCMD_DATA5 2269 #define SDMA_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2270 #define SDMA_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2271 //SDMA_RLC2_MIDCMD_DATA6 2272 #define SDMA_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2273 #define SDMA_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2274 //SDMA_RLC2_MIDCMD_DATA7 2275 #define SDMA_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2276 #define SDMA_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2277 //SDMA_RLC2_MIDCMD_DATA8 2278 #define SDMA_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2279 #define SDMA_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2280 //SDMA_RLC2_MIDCMD_DATA9 2281 #define SDMA_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 2282 #define SDMA_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2283 //SDMA_RLC2_MIDCMD_DATA10 2284 #define SDMA_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 2285 #define SDMA_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2286 //SDMA_RLC2_MIDCMD_CNTL 2287 #define SDMA_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2288 #define SDMA_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2289 #define SDMA_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2290 #define SDMA_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2291 #define SDMA_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2292 #define SDMA_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2293 #define SDMA_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2294 #define SDMA_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2295 //SDMA_RLC3_RB_CNTL 2296 #define SDMA_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2297 #define SDMA_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2298 #define SDMA_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2299 #define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2300 #define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2301 #define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2302 #define SDMA_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2303 #define SDMA_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2304 #define SDMA_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2305 #define SDMA_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2306 #define SDMA_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2307 #define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2308 #define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2309 #define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2310 #define SDMA_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2311 #define SDMA_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2312 //SDMA_RLC3_RB_BASE 2313 #define SDMA_RLC3_RB_BASE__ADDR__SHIFT 0x0 2314 #define SDMA_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2315 //SDMA_RLC3_RB_BASE_HI 2316 #define SDMA_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2317 #define SDMA_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2318 //SDMA_RLC3_RB_RPTR 2319 #define SDMA_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2320 #define SDMA_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2321 //SDMA_RLC3_RB_RPTR_HI 2322 #define SDMA_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2323 #define SDMA_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2324 //SDMA_RLC3_RB_WPTR 2325 #define SDMA_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2326 #define SDMA_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2327 //SDMA_RLC3_RB_WPTR_HI 2328 #define SDMA_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2329 #define SDMA_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2330 //SDMA_RLC3_RB_WPTR_POLL_CNTL 2331 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2332 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2333 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2334 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2335 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2336 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2337 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2338 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2339 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2340 #define SDMA_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2341 //SDMA_RLC3_RB_RPTR_ADDR_HI 2342 #define SDMA_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2343 #define SDMA_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2344 //SDMA_RLC3_RB_RPTR_ADDR_LO 2345 #define SDMA_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2346 #define SDMA_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2347 #define SDMA_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2348 #define SDMA_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2349 //SDMA_RLC3_IB_CNTL 2350 #define SDMA_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2351 #define SDMA_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2352 #define SDMA_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2353 #define SDMA_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2354 #define SDMA_RLC3_IB_CNTL__IB_PRIV__SHIFT 0x1f 2355 #define SDMA_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2356 #define SDMA_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2357 #define SDMA_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2358 #define SDMA_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2359 #define SDMA_RLC3_IB_CNTL__IB_PRIV_MASK 0x80000000L 2360 //SDMA_RLC3_IB_RPTR 2361 #define SDMA_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2362 #define SDMA_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2363 //SDMA_RLC3_IB_OFFSET 2364 #define SDMA_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2365 #define SDMA_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2366 //SDMA_RLC3_IB_BASE_LO 2367 #define SDMA_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2368 #define SDMA_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2369 //SDMA_RLC3_IB_BASE_HI 2370 #define SDMA_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2371 #define SDMA_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2372 //SDMA_RLC3_IB_SIZE 2373 #define SDMA_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2374 #define SDMA_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2375 //SDMA_RLC3_SKIP_CNTL 2376 #define SDMA_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2377 #define SDMA_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2378 //SDMA_RLC3_CONTEXT_STATUS 2379 #define SDMA_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2380 #define SDMA_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2381 #define SDMA_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2382 #define SDMA_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2383 #define SDMA_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2384 #define SDMA_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2385 #define SDMA_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2386 #define SDMA_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2387 #define SDMA_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2388 #define SDMA_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2389 #define SDMA_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2390 #define SDMA_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2391 #define SDMA_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2392 #define SDMA_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2393 #define SDMA_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2394 #define SDMA_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2395 //SDMA_RLC3_DOORBELL 2396 #define SDMA_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2397 #define SDMA_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2398 #define SDMA_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2399 #define SDMA_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2400 //SDMA_RLC3_STATUS 2401 #define SDMA_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2402 #define SDMA_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2403 #define SDMA_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2404 #define SDMA_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2405 //SDMA_RLC3_DOORBELL_LOG 2406 #define SDMA_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2407 #define SDMA_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2408 #define SDMA_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2409 #define SDMA_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2410 //SDMA_RLC3_WATERMARK 2411 #define SDMA_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2412 #define SDMA_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2413 #define SDMA_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2414 #define SDMA_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2415 //SDMA_RLC3_DOORBELL_OFFSET 2416 #define SDMA_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2417 #define SDMA_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2418 //SDMA_RLC3_CSA_ADDR_LO 2419 #define SDMA_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2420 #define SDMA_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2421 //SDMA_RLC3_CSA_ADDR_HI 2422 #define SDMA_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2423 #define SDMA_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2424 //SDMA_RLC3_IB_SUB_REMAIN 2425 #define SDMA_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2426 #define SDMA_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2427 //SDMA_RLC3_PREEMPT 2428 #define SDMA_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2429 #define SDMA_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2430 //SDMA_RLC3_DUMMY_REG 2431 #define SDMA_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2432 #define SDMA_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2433 //SDMA_RLC3_RB_WPTR_POLL_ADDR_HI 2434 #define SDMA_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2435 #define SDMA_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2436 //SDMA_RLC3_RB_WPTR_POLL_ADDR_LO 2437 #define SDMA_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2438 #define SDMA_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2439 //SDMA_RLC3_RB_AQL_CNTL 2440 #define SDMA_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2441 #define SDMA_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2442 #define SDMA_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2443 #define SDMA_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2444 #define SDMA_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2445 #define SDMA_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2446 //SDMA_RLC3_MINOR_PTR_UPDATE 2447 #define SDMA_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2448 #define SDMA_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2449 //SDMA_RLC3_MIDCMD_DATA0 2450 #define SDMA_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2451 #define SDMA_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2452 //SDMA_RLC3_MIDCMD_DATA1 2453 #define SDMA_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2454 #define SDMA_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2455 //SDMA_RLC3_MIDCMD_DATA2 2456 #define SDMA_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2457 #define SDMA_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2458 //SDMA_RLC3_MIDCMD_DATA3 2459 #define SDMA_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2460 #define SDMA_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2461 //SDMA_RLC3_MIDCMD_DATA4 2462 #define SDMA_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2463 #define SDMA_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2464 //SDMA_RLC3_MIDCMD_DATA5 2465 #define SDMA_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2466 #define SDMA_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2467 //SDMA_RLC3_MIDCMD_DATA6 2468 #define SDMA_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2469 #define SDMA_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2470 //SDMA_RLC3_MIDCMD_DATA7 2471 #define SDMA_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2472 #define SDMA_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2473 //SDMA_RLC3_MIDCMD_DATA8 2474 #define SDMA_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2475 #define SDMA_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2476 //SDMA_RLC3_MIDCMD_DATA9 2477 #define SDMA_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 2478 #define SDMA_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2479 //SDMA_RLC3_MIDCMD_DATA10 2480 #define SDMA_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 2481 #define SDMA_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2482 //SDMA_RLC3_MIDCMD_CNTL 2483 #define SDMA_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2484 #define SDMA_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2485 #define SDMA_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2486 #define SDMA_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2487 #define SDMA_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2488 #define SDMA_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2489 #define SDMA_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2490 #define SDMA_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2491 //SDMA_RLC4_RB_CNTL 2492 #define SDMA_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2493 #define SDMA_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2494 #define SDMA_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2495 #define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2496 #define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2497 #define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2498 #define SDMA_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2499 #define SDMA_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2500 #define SDMA_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2501 #define SDMA_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2502 #define SDMA_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2503 #define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2504 #define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2505 #define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2506 #define SDMA_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2507 #define SDMA_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2508 //SDMA_RLC4_RB_BASE 2509 #define SDMA_RLC4_RB_BASE__ADDR__SHIFT 0x0 2510 #define SDMA_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2511 //SDMA_RLC4_RB_BASE_HI 2512 #define SDMA_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2513 #define SDMA_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2514 //SDMA_RLC4_RB_RPTR 2515 #define SDMA_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2516 #define SDMA_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2517 //SDMA_RLC4_RB_RPTR_HI 2518 #define SDMA_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2519 #define SDMA_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2520 //SDMA_RLC4_RB_WPTR 2521 #define SDMA_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2522 #define SDMA_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2523 //SDMA_RLC4_RB_WPTR_HI 2524 #define SDMA_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2525 #define SDMA_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2526 //SDMA_RLC4_RB_WPTR_POLL_CNTL 2527 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2528 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2529 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2530 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2531 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2532 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2533 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2534 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2535 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2536 #define SDMA_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2537 //SDMA_RLC4_RB_RPTR_ADDR_HI 2538 #define SDMA_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2539 #define SDMA_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2540 //SDMA_RLC4_RB_RPTR_ADDR_LO 2541 #define SDMA_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2542 #define SDMA_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2543 #define SDMA_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2544 #define SDMA_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2545 //SDMA_RLC4_IB_CNTL 2546 #define SDMA_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2547 #define SDMA_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2548 #define SDMA_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2549 #define SDMA_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2550 #define SDMA_RLC4_IB_CNTL__IB_PRIV__SHIFT 0x1f 2551 #define SDMA_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2552 #define SDMA_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2553 #define SDMA_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2554 #define SDMA_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2555 #define SDMA_RLC4_IB_CNTL__IB_PRIV_MASK 0x80000000L 2556 //SDMA_RLC4_IB_RPTR 2557 #define SDMA_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2558 #define SDMA_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2559 //SDMA_RLC4_IB_OFFSET 2560 #define SDMA_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2561 #define SDMA_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2562 //SDMA_RLC4_IB_BASE_LO 2563 #define SDMA_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2564 #define SDMA_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2565 //SDMA_RLC4_IB_BASE_HI 2566 #define SDMA_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2567 #define SDMA_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2568 //SDMA_RLC4_IB_SIZE 2569 #define SDMA_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2570 #define SDMA_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2571 //SDMA_RLC4_SKIP_CNTL 2572 #define SDMA_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2573 #define SDMA_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2574 //SDMA_RLC4_CONTEXT_STATUS 2575 #define SDMA_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2576 #define SDMA_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2577 #define SDMA_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2578 #define SDMA_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2579 #define SDMA_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2580 #define SDMA_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2581 #define SDMA_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2582 #define SDMA_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2583 #define SDMA_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2584 #define SDMA_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2585 #define SDMA_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2586 #define SDMA_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2587 #define SDMA_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2588 #define SDMA_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2589 #define SDMA_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2590 #define SDMA_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2591 //SDMA_RLC4_DOORBELL 2592 #define SDMA_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2593 #define SDMA_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2594 #define SDMA_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2595 #define SDMA_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2596 //SDMA_RLC4_STATUS 2597 #define SDMA_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2598 #define SDMA_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2599 #define SDMA_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2600 #define SDMA_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2601 //SDMA_RLC4_DOORBELL_LOG 2602 #define SDMA_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2603 #define SDMA_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2604 #define SDMA_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2605 #define SDMA_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2606 //SDMA_RLC4_WATERMARK 2607 #define SDMA_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2608 #define SDMA_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2609 #define SDMA_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2610 #define SDMA_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2611 //SDMA_RLC4_DOORBELL_OFFSET 2612 #define SDMA_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2613 #define SDMA_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2614 //SDMA_RLC4_CSA_ADDR_LO 2615 #define SDMA_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2616 #define SDMA_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2617 //SDMA_RLC4_CSA_ADDR_HI 2618 #define SDMA_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2619 #define SDMA_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2620 //SDMA_RLC4_IB_SUB_REMAIN 2621 #define SDMA_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2622 #define SDMA_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2623 //SDMA_RLC4_PREEMPT 2624 #define SDMA_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2625 #define SDMA_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2626 //SDMA_RLC4_DUMMY_REG 2627 #define SDMA_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2628 #define SDMA_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2629 //SDMA_RLC4_RB_WPTR_POLL_ADDR_HI 2630 #define SDMA_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2631 #define SDMA_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2632 //SDMA_RLC4_RB_WPTR_POLL_ADDR_LO 2633 #define SDMA_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2634 #define SDMA_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2635 //SDMA_RLC4_RB_AQL_CNTL 2636 #define SDMA_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2637 #define SDMA_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2638 #define SDMA_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2639 #define SDMA_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2640 #define SDMA_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2641 #define SDMA_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2642 //SDMA_RLC4_MINOR_PTR_UPDATE 2643 #define SDMA_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2644 #define SDMA_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2645 //SDMA_RLC4_MIDCMD_DATA0 2646 #define SDMA_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2647 #define SDMA_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2648 //SDMA_RLC4_MIDCMD_DATA1 2649 #define SDMA_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2650 #define SDMA_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2651 //SDMA_RLC4_MIDCMD_DATA2 2652 #define SDMA_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2653 #define SDMA_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2654 //SDMA_RLC4_MIDCMD_DATA3 2655 #define SDMA_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2656 #define SDMA_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2657 //SDMA_RLC4_MIDCMD_DATA4 2658 #define SDMA_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2659 #define SDMA_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2660 //SDMA_RLC4_MIDCMD_DATA5 2661 #define SDMA_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2662 #define SDMA_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2663 //SDMA_RLC4_MIDCMD_DATA6 2664 #define SDMA_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2665 #define SDMA_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2666 //SDMA_RLC4_MIDCMD_DATA7 2667 #define SDMA_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2668 #define SDMA_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2669 //SDMA_RLC4_MIDCMD_DATA8 2670 #define SDMA_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2671 #define SDMA_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2672 //SDMA_RLC4_MIDCMD_DATA9 2673 #define SDMA_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 2674 #define SDMA_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2675 //SDMA_RLC4_MIDCMD_DATA10 2676 #define SDMA_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 2677 #define SDMA_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2678 //SDMA_RLC4_MIDCMD_CNTL 2679 #define SDMA_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2680 #define SDMA_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2681 #define SDMA_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2682 #define SDMA_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2683 #define SDMA_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2684 #define SDMA_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2685 #define SDMA_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2686 #define SDMA_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2687 //SDMA_RLC5_RB_CNTL 2688 #define SDMA_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2689 #define SDMA_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2690 #define SDMA_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2691 #define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2692 #define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2693 #define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2694 #define SDMA_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2695 #define SDMA_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2696 #define SDMA_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2697 #define SDMA_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2698 #define SDMA_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2699 #define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2700 #define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2701 #define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2702 #define SDMA_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2703 #define SDMA_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2704 //SDMA_RLC5_RB_BASE 2705 #define SDMA_RLC5_RB_BASE__ADDR__SHIFT 0x0 2706 #define SDMA_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2707 //SDMA_RLC5_RB_BASE_HI 2708 #define SDMA_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2709 #define SDMA_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2710 //SDMA_RLC5_RB_RPTR 2711 #define SDMA_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2712 #define SDMA_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2713 //SDMA_RLC5_RB_RPTR_HI 2714 #define SDMA_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2715 #define SDMA_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2716 //SDMA_RLC5_RB_WPTR 2717 #define SDMA_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2718 #define SDMA_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2719 //SDMA_RLC5_RB_WPTR_HI 2720 #define SDMA_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2721 #define SDMA_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2722 //SDMA_RLC5_RB_WPTR_POLL_CNTL 2723 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2724 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2725 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2726 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2727 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2728 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2729 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2730 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2731 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2732 #define SDMA_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2733 //SDMA_RLC5_RB_RPTR_ADDR_HI 2734 #define SDMA_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2735 #define SDMA_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2736 //SDMA_RLC5_RB_RPTR_ADDR_LO 2737 #define SDMA_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2738 #define SDMA_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2739 #define SDMA_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2740 #define SDMA_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2741 //SDMA_RLC5_IB_CNTL 2742 #define SDMA_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2743 #define SDMA_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2744 #define SDMA_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2745 #define SDMA_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2746 #define SDMA_RLC5_IB_CNTL__IB_PRIV__SHIFT 0x1f 2747 #define SDMA_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2748 #define SDMA_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2749 #define SDMA_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2750 #define SDMA_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2751 #define SDMA_RLC5_IB_CNTL__IB_PRIV_MASK 0x80000000L 2752 //SDMA_RLC5_IB_RPTR 2753 #define SDMA_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2754 #define SDMA_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2755 //SDMA_RLC5_IB_OFFSET 2756 #define SDMA_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2757 #define SDMA_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2758 //SDMA_RLC5_IB_BASE_LO 2759 #define SDMA_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2760 #define SDMA_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2761 //SDMA_RLC5_IB_BASE_HI 2762 #define SDMA_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2763 #define SDMA_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2764 //SDMA_RLC5_IB_SIZE 2765 #define SDMA_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2766 #define SDMA_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2767 //SDMA_RLC5_SKIP_CNTL 2768 #define SDMA_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2769 #define SDMA_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2770 //SDMA_RLC5_CONTEXT_STATUS 2771 #define SDMA_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2772 #define SDMA_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2773 #define SDMA_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2774 #define SDMA_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2775 #define SDMA_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2776 #define SDMA_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2777 #define SDMA_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2778 #define SDMA_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2779 #define SDMA_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2780 #define SDMA_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2781 #define SDMA_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2782 #define SDMA_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2783 #define SDMA_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2784 #define SDMA_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2785 #define SDMA_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2786 #define SDMA_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2787 //SDMA_RLC5_DOORBELL 2788 #define SDMA_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2789 #define SDMA_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2790 #define SDMA_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2791 #define SDMA_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2792 //SDMA_RLC5_STATUS 2793 #define SDMA_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2794 #define SDMA_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2795 #define SDMA_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2796 #define SDMA_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2797 //SDMA_RLC5_DOORBELL_LOG 2798 #define SDMA_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2799 #define SDMA_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2800 #define SDMA_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2801 #define SDMA_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2802 //SDMA_RLC5_WATERMARK 2803 #define SDMA_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2804 #define SDMA_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2805 #define SDMA_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2806 #define SDMA_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2807 //SDMA_RLC5_DOORBELL_OFFSET 2808 #define SDMA_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2809 #define SDMA_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2810 //SDMA_RLC5_CSA_ADDR_LO 2811 #define SDMA_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2812 #define SDMA_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2813 //SDMA_RLC5_CSA_ADDR_HI 2814 #define SDMA_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2815 #define SDMA_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2816 //SDMA_RLC5_IB_SUB_REMAIN 2817 #define SDMA_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2818 #define SDMA_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2819 //SDMA_RLC5_PREEMPT 2820 #define SDMA_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2821 #define SDMA_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2822 //SDMA_RLC5_DUMMY_REG 2823 #define SDMA_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2824 #define SDMA_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2825 //SDMA_RLC5_RB_WPTR_POLL_ADDR_HI 2826 #define SDMA_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2827 #define SDMA_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2828 //SDMA_RLC5_RB_WPTR_POLL_ADDR_LO 2829 #define SDMA_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2830 #define SDMA_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2831 //SDMA_RLC5_RB_AQL_CNTL 2832 #define SDMA_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2833 #define SDMA_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2834 #define SDMA_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2835 #define SDMA_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2836 #define SDMA_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2837 #define SDMA_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2838 //SDMA_RLC5_MINOR_PTR_UPDATE 2839 #define SDMA_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2840 #define SDMA_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2841 //SDMA_RLC5_MIDCMD_DATA0 2842 #define SDMA_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2843 #define SDMA_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2844 //SDMA_RLC5_MIDCMD_DATA1 2845 #define SDMA_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2846 #define SDMA_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2847 //SDMA_RLC5_MIDCMD_DATA2 2848 #define SDMA_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2849 #define SDMA_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2850 //SDMA_RLC5_MIDCMD_DATA3 2851 #define SDMA_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2852 #define SDMA_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2853 //SDMA_RLC5_MIDCMD_DATA4 2854 #define SDMA_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2855 #define SDMA_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2856 //SDMA_RLC5_MIDCMD_DATA5 2857 #define SDMA_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2858 #define SDMA_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2859 //SDMA_RLC5_MIDCMD_DATA6 2860 #define SDMA_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2861 #define SDMA_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2862 //SDMA_RLC5_MIDCMD_DATA7 2863 #define SDMA_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2864 #define SDMA_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2865 //SDMA_RLC5_MIDCMD_DATA8 2866 #define SDMA_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2867 #define SDMA_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2868 //SDMA_RLC5_MIDCMD_DATA9 2869 #define SDMA_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 2870 #define SDMA_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2871 //SDMA_RLC5_MIDCMD_DATA10 2872 #define SDMA_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 2873 #define SDMA_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2874 //SDMA_RLC5_MIDCMD_CNTL 2875 #define SDMA_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2876 #define SDMA_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2877 #define SDMA_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2878 #define SDMA_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2879 #define SDMA_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2880 #define SDMA_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2881 #define SDMA_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2882 #define SDMA_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2883 //SDMA_RLC6_RB_CNTL 2884 #define SDMA_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2885 #define SDMA_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2886 #define SDMA_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2887 #define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2888 #define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2889 #define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2890 #define SDMA_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2891 #define SDMA_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2892 #define SDMA_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2893 #define SDMA_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2894 #define SDMA_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2895 #define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2896 #define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2897 #define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2898 #define SDMA_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2899 #define SDMA_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2900 //SDMA_RLC6_RB_BASE 2901 #define SDMA_RLC6_RB_BASE__ADDR__SHIFT 0x0 2902 #define SDMA_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2903 //SDMA_RLC6_RB_BASE_HI 2904 #define SDMA_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2905 #define SDMA_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2906 //SDMA_RLC6_RB_RPTR 2907 #define SDMA_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2908 #define SDMA_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2909 //SDMA_RLC6_RB_RPTR_HI 2910 #define SDMA_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2911 #define SDMA_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2912 //SDMA_RLC6_RB_WPTR 2913 #define SDMA_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2914 #define SDMA_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2915 //SDMA_RLC6_RB_WPTR_HI 2916 #define SDMA_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2917 #define SDMA_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2918 //SDMA_RLC6_RB_WPTR_POLL_CNTL 2919 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2920 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2921 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2922 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2923 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2924 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2925 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2926 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2927 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2928 #define SDMA_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2929 //SDMA_RLC6_RB_RPTR_ADDR_HI 2930 #define SDMA_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2931 #define SDMA_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2932 //SDMA_RLC6_RB_RPTR_ADDR_LO 2933 #define SDMA_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2934 #define SDMA_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2935 #define SDMA_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2936 #define SDMA_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2937 //SDMA_RLC6_IB_CNTL 2938 #define SDMA_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2939 #define SDMA_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2940 #define SDMA_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2941 #define SDMA_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2942 #define SDMA_RLC6_IB_CNTL__IB_PRIV__SHIFT 0x1f 2943 #define SDMA_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2944 #define SDMA_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2945 #define SDMA_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2946 #define SDMA_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2947 #define SDMA_RLC6_IB_CNTL__IB_PRIV_MASK 0x80000000L 2948 //SDMA_RLC6_IB_RPTR 2949 #define SDMA_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2950 #define SDMA_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2951 //SDMA_RLC6_IB_OFFSET 2952 #define SDMA_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2953 #define SDMA_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2954 //SDMA_RLC6_IB_BASE_LO 2955 #define SDMA_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2956 #define SDMA_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2957 //SDMA_RLC6_IB_BASE_HI 2958 #define SDMA_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2959 #define SDMA_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2960 //SDMA_RLC6_IB_SIZE 2961 #define SDMA_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2962 #define SDMA_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2963 //SDMA_RLC6_SKIP_CNTL 2964 #define SDMA_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2965 #define SDMA_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2966 //SDMA_RLC6_CONTEXT_STATUS 2967 #define SDMA_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2968 #define SDMA_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2969 #define SDMA_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2970 #define SDMA_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2971 #define SDMA_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2972 #define SDMA_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2973 #define SDMA_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2974 #define SDMA_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2975 #define SDMA_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2976 #define SDMA_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2977 #define SDMA_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2978 #define SDMA_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2979 #define SDMA_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2980 #define SDMA_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2981 #define SDMA_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2982 #define SDMA_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2983 //SDMA_RLC6_DOORBELL 2984 #define SDMA_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2985 #define SDMA_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2986 #define SDMA_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2987 #define SDMA_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2988 //SDMA_RLC6_STATUS 2989 #define SDMA_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2990 #define SDMA_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2991 #define SDMA_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2992 #define SDMA_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2993 //SDMA_RLC6_DOORBELL_LOG 2994 #define SDMA_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2995 #define SDMA_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2996 #define SDMA_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2997 #define SDMA_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2998 //SDMA_RLC6_WATERMARK 2999 #define SDMA_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3000 #define SDMA_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3001 #define SDMA_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 3002 #define SDMA_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 3003 //SDMA_RLC6_DOORBELL_OFFSET 3004 #define SDMA_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 3005 #define SDMA_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 3006 //SDMA_RLC6_CSA_ADDR_LO 3007 #define SDMA_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 3008 #define SDMA_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3009 //SDMA_RLC6_CSA_ADDR_HI 3010 #define SDMA_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 3011 #define SDMA_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3012 //SDMA_RLC6_IB_SUB_REMAIN 3013 #define SDMA_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3014 #define SDMA_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 3015 //SDMA_RLC6_PREEMPT 3016 #define SDMA_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 3017 #define SDMA_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 3018 //SDMA_RLC6_DUMMY_REG 3019 #define SDMA_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 3020 #define SDMA_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 3021 //SDMA_RLC6_RB_WPTR_POLL_ADDR_HI 3022 #define SDMA_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 3023 #define SDMA_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3024 //SDMA_RLC6_RB_WPTR_POLL_ADDR_LO 3025 #define SDMA_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 3026 #define SDMA_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3027 //SDMA_RLC6_RB_AQL_CNTL 3028 #define SDMA_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 3029 #define SDMA_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 3030 #define SDMA_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 3031 #define SDMA_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 3032 #define SDMA_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 3033 #define SDMA_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 3034 //SDMA_RLC6_MINOR_PTR_UPDATE 3035 #define SDMA_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 3036 #define SDMA_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 3037 //SDMA_RLC6_MIDCMD_DATA0 3038 #define SDMA_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 3039 #define SDMA_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 3040 //SDMA_RLC6_MIDCMD_DATA1 3041 #define SDMA_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 3042 #define SDMA_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 3043 //SDMA_RLC6_MIDCMD_DATA2 3044 #define SDMA_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 3045 #define SDMA_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 3046 //SDMA_RLC6_MIDCMD_DATA3 3047 #define SDMA_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 3048 #define SDMA_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 3049 //SDMA_RLC6_MIDCMD_DATA4 3050 #define SDMA_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 3051 #define SDMA_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 3052 //SDMA_RLC6_MIDCMD_DATA5 3053 #define SDMA_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 3054 #define SDMA_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 3055 //SDMA_RLC6_MIDCMD_DATA6 3056 #define SDMA_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 3057 #define SDMA_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 3058 //SDMA_RLC6_MIDCMD_DATA7 3059 #define SDMA_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 3060 #define SDMA_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 3061 //SDMA_RLC6_MIDCMD_DATA8 3062 #define SDMA_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 3063 #define SDMA_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 3064 //SDMA_RLC6_MIDCMD_DATA9 3065 #define SDMA_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 3066 #define SDMA_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 3067 //SDMA_RLC6_MIDCMD_DATA10 3068 #define SDMA_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 3069 #define SDMA_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 3070 //SDMA_RLC6_MIDCMD_CNTL 3071 #define SDMA_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3072 #define SDMA_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3073 #define SDMA_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3074 #define SDMA_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3075 #define SDMA_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 3076 #define SDMA_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 3077 #define SDMA_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 3078 #define SDMA_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 3079 //SDMA_RLC7_RB_CNTL 3080 #define SDMA_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 3081 #define SDMA_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 3082 #define SDMA_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 3083 #define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 3084 #define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 3085 #define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 3086 #define SDMA_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 3087 #define SDMA_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 3088 #define SDMA_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 3089 #define SDMA_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 3090 #define SDMA_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 3091 #define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 3092 #define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 3093 #define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 3094 #define SDMA_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 3095 #define SDMA_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 3096 //SDMA_RLC7_RB_BASE 3097 #define SDMA_RLC7_RB_BASE__ADDR__SHIFT 0x0 3098 #define SDMA_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 3099 //SDMA_RLC7_RB_BASE_HI 3100 #define SDMA_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 3101 #define SDMA_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 3102 //SDMA_RLC7_RB_RPTR 3103 #define SDMA_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 3104 #define SDMA_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 3105 //SDMA_RLC7_RB_RPTR_HI 3106 #define SDMA_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 3107 #define SDMA_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 3108 //SDMA_RLC7_RB_WPTR 3109 #define SDMA_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 3110 #define SDMA_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 3111 //SDMA_RLC7_RB_WPTR_HI 3112 #define SDMA_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 3113 #define SDMA_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 3114 //SDMA_RLC7_RB_WPTR_POLL_CNTL 3115 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 3116 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 3117 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 3118 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 3119 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3120 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 3121 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 3122 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 3123 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 3124 #define SDMA_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3125 //SDMA_RLC7_RB_RPTR_ADDR_HI 3126 #define SDMA_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 3127 #define SDMA_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3128 //SDMA_RLC7_RB_RPTR_ADDR_LO 3129 #define SDMA_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 3130 #define SDMA_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 3131 #define SDMA_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 3132 #define SDMA_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3133 //SDMA_RLC7_IB_CNTL 3134 #define SDMA_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 3135 #define SDMA_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 3136 #define SDMA_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 3137 #define SDMA_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 3138 #define SDMA_RLC7_IB_CNTL__IB_PRIV__SHIFT 0x1f 3139 #define SDMA_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 3140 #define SDMA_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 3141 #define SDMA_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 3142 #define SDMA_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 3143 #define SDMA_RLC7_IB_CNTL__IB_PRIV_MASK 0x80000000L 3144 //SDMA_RLC7_IB_RPTR 3145 #define SDMA_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 3146 #define SDMA_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 3147 //SDMA_RLC7_IB_OFFSET 3148 #define SDMA_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 3149 #define SDMA_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 3150 //SDMA_RLC7_IB_BASE_LO 3151 #define SDMA_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 3152 #define SDMA_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 3153 //SDMA_RLC7_IB_BASE_HI 3154 #define SDMA_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 3155 #define SDMA_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 3156 //SDMA_RLC7_IB_SIZE 3157 #define SDMA_RLC7_IB_SIZE__SIZE__SHIFT 0x0 3158 #define SDMA_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 3159 //SDMA_RLC7_SKIP_CNTL 3160 #define SDMA_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 3161 #define SDMA_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 3162 //SDMA_RLC7_CONTEXT_STATUS 3163 #define SDMA_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 3164 #define SDMA_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 3165 #define SDMA_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 3166 #define SDMA_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 3167 #define SDMA_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 3168 #define SDMA_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 3169 #define SDMA_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 3170 #define SDMA_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 3171 #define SDMA_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 3172 #define SDMA_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 3173 #define SDMA_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 3174 #define SDMA_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 3175 #define SDMA_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 3176 #define SDMA_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 3177 #define SDMA_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 3178 #define SDMA_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 3179 //SDMA_RLC7_DOORBELL 3180 #define SDMA_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 3181 #define SDMA_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 3182 #define SDMA_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 3183 #define SDMA_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 3184 //SDMA_RLC7_STATUS 3185 #define SDMA_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 3186 #define SDMA_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 3187 #define SDMA_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 3188 #define SDMA_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 3189 //SDMA_RLC7_DOORBELL_LOG 3190 #define SDMA_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 3191 #define SDMA_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 3192 #define SDMA_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 3193 #define SDMA_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 3194 //SDMA_RLC7_WATERMARK 3195 #define SDMA_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3196 #define SDMA_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3197 #define SDMA_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 3198 #define SDMA_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 3199 //SDMA_RLC7_DOORBELL_OFFSET 3200 #define SDMA_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 3201 #define SDMA_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 3202 //SDMA_RLC7_CSA_ADDR_LO 3203 #define SDMA_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 3204 #define SDMA_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3205 //SDMA_RLC7_CSA_ADDR_HI 3206 #define SDMA_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 3207 #define SDMA_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3208 //SDMA_RLC7_IB_SUB_REMAIN 3209 #define SDMA_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3210 #define SDMA_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 3211 //SDMA_RLC7_PREEMPT 3212 #define SDMA_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 3213 #define SDMA_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 3214 //SDMA_RLC7_DUMMY_REG 3215 #define SDMA_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 3216 #define SDMA_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 3217 //SDMA_RLC7_RB_WPTR_POLL_ADDR_HI 3218 #define SDMA_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 3219 #define SDMA_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3220 //SDMA_RLC7_RB_WPTR_POLL_ADDR_LO 3221 #define SDMA_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 3222 #define SDMA_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3223 //SDMA_RLC7_RB_AQL_CNTL 3224 #define SDMA_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 3225 #define SDMA_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 3226 #define SDMA_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 3227 #define SDMA_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 3228 #define SDMA_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 3229 #define SDMA_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 3230 //SDMA_RLC7_MINOR_PTR_UPDATE 3231 #define SDMA_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 3232 #define SDMA_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 3233 //SDMA_RLC7_MIDCMD_DATA0 3234 #define SDMA_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 3235 #define SDMA_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 3236 //SDMA_RLC7_MIDCMD_DATA1 3237 #define SDMA_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 3238 #define SDMA_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 3239 //SDMA_RLC7_MIDCMD_DATA2 3240 #define SDMA_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 3241 #define SDMA_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 3242 //SDMA_RLC7_MIDCMD_DATA3 3243 #define SDMA_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 3244 #define SDMA_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 3245 //SDMA_RLC7_MIDCMD_DATA4 3246 #define SDMA_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 3247 #define SDMA_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 3248 //SDMA_RLC7_MIDCMD_DATA5 3249 #define SDMA_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 3250 #define SDMA_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 3251 //SDMA_RLC7_MIDCMD_DATA6 3252 #define SDMA_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 3253 #define SDMA_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 3254 //SDMA_RLC7_MIDCMD_DATA7 3255 #define SDMA_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 3256 #define SDMA_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 3257 //SDMA_RLC7_MIDCMD_DATA8 3258 #define SDMA_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 3259 #define SDMA_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 3260 //SDMA_RLC7_MIDCMD_DATA9 3261 #define SDMA_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 3262 #define SDMA_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 3263 //SDMA_RLC7_MIDCMD_DATA10 3264 #define SDMA_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 3265 #define SDMA_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 3266 //SDMA_RLC7_MIDCMD_CNTL 3267 #define SDMA_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3268 #define SDMA_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3269 #define SDMA_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3270 #define SDMA_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3271 #define SDMA_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 3272 #define SDMA_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 3273 #define SDMA_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 3274 #define SDMA_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 3275 3276 #endif 3277