1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _sdma0_4_2_2_SH_MASK_HEADER 22 #define _sdma0_4_2_2_SH_MASK_HEADER 23 24 25 // addressBlock: sdma0_sdma0dec 26 //SDMA0_UCODE_ADDR 27 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 //SDMA0_UCODE_DATA 30 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 //SDMA0_VM_CNTL 33 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35 //SDMA0_VM_CTX_LO 36 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 //SDMA0_VM_CTX_HI 39 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 //SDMA0_ACTIVE_FCN_ID 42 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 //SDMA0_VM_CTX_CNTL 49 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 //SDMA0_VIRT_RESET_REQ 54 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 //SDMA0_VF_ENABLE 59 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 //SDMA0_CONTEXT_REG_TYPE0 62 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 //SDMA0_CONTEXT_REG_TYPE1 103 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 //SDMA0_CONTEXT_REG_TYPE2 134 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 //SDMA0_CONTEXT_REG_TYPE3 157 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 //SDMA0_PUB_REG_TYPE0 160 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162 #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 180 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189 #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196 #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L 207 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 //SDMA0_PUB_REG_TYPE1 215 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279 //SDMA0_PUB_REG_TYPE2 280 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 303 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 304 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 305 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 306 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 308 #define SDMA0_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c 309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 311 #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 313 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 314 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 315 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 316 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 317 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 318 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 319 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 320 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 321 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 322 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 323 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 324 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 325 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 328 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 329 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 330 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 331 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 332 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 333 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 334 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 335 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 336 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 340 #define SDMA0_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L 341 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 343 #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 //SDMA0_PUB_REG_TYPE3 345 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 348 #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 349 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 350 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 351 #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L 352 #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L 353 //SDMA0_MMHUB_CNTL 354 #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 355 #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 356 //SDMA0_CONTEXT_GROUP_BOUNDARY 357 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 358 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 359 //SDMA0_POWER_CNTL 360 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 361 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 362 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 363 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 364 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 365 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 366 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 367 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 368 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 369 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 370 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 371 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 372 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 373 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 374 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 375 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 376 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 377 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 378 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 379 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 380 //SDMA0_CLK_CTRL 381 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 382 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 383 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 384 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 385 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 386 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 387 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 388 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 389 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 390 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 391 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 392 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 393 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 394 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 395 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 396 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 397 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 398 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 399 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 400 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 401 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 402 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 403 //SDMA0_CNTL 404 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 405 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 406 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 407 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 408 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 409 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 410 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 411 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 412 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 413 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 414 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 415 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 416 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 417 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 418 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 419 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 420 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 421 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 422 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 423 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 424 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 425 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 426 //SDMA0_CHICKEN_BITS 427 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 428 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 429 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 430 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 431 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 432 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 433 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 434 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 435 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 436 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 437 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 438 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 439 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 440 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 441 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 442 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 443 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 444 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 445 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 446 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 447 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 448 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 449 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 450 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 451 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 452 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 453 //SDMA0_GB_ADDR_CONFIG 454 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 455 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 456 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 457 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 458 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 459 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 460 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 461 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 462 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 463 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 464 //SDMA0_GB_ADDR_CONFIG_READ 465 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 466 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 467 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 468 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 469 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 470 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 471 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 472 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 473 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 474 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 475 //SDMA0_RB_RPTR_FETCH_HI 476 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 477 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 478 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 479 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 480 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 481 //SDMA0_RB_RPTR_FETCH 482 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 483 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 484 //SDMA0_IB_OFFSET_FETCH 485 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 486 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 487 //SDMA0_PROGRAM 488 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 489 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 490 //SDMA0_STATUS_REG 491 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 492 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 493 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 494 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 495 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 496 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 497 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 498 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 499 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 500 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 501 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 502 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 503 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 504 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 505 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 506 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 507 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 508 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 509 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 510 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 511 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 512 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 513 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 514 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 515 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 516 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 517 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 518 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 519 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 520 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 521 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 522 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 523 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 524 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 525 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 526 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 527 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 528 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 529 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 530 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 531 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 532 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 533 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 534 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 535 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 536 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 537 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 538 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 539 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 540 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 541 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 542 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 543 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 544 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 545 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 546 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 547 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 548 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 549 //SDMA0_STATUS1_REG 550 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 551 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 552 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 553 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 554 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 555 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 556 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 557 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 558 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 559 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 560 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 561 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 562 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 563 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 564 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 565 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 566 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 567 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 568 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 569 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 570 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 571 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 572 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 573 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 574 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 575 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 576 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 577 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 578 //SDMA0_RD_BURST_CNTL 579 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 580 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 581 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 582 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 583 //SDMA0_HBM_PAGE_CONFIG 584 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 585 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 586 //SDMA0_UCODE_CHECKSUM 587 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 588 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 589 //SDMA0_F32_CNTL 590 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 591 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 592 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 593 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 594 //SDMA0_FREEZE 595 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 596 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 597 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 598 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 599 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 600 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 601 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 602 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 603 //SDMA0_PHASE0_QUANTUM 604 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 605 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 606 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 607 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 608 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 609 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 610 //SDMA0_PHASE1_QUANTUM 611 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 612 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 613 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 614 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 615 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 616 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 617 //SDMA_POWER_GATING 618 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 619 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 620 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 621 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 622 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 623 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 624 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 625 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 626 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 627 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 628 //SDMA_PGFSM_CONFIG 629 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 630 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 631 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 632 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 633 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 634 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 635 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 636 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 637 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 638 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 639 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 640 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 641 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 642 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 643 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 644 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 645 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 646 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 647 //SDMA_PGFSM_WRITE 648 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 649 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 650 //SDMA_PGFSM_READ 651 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 652 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 653 //SDMA0_EDC_CONFIG 654 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 655 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 656 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 657 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 658 //SDMA0_BA_THRESHOLD 659 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 660 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 661 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 662 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 663 //SDMA0_ID 664 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 665 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 666 //SDMA0_VERSION 667 #define SDMA0_VERSION__MINVER__SHIFT 0x0 668 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 669 #define SDMA0_VERSION__REV__SHIFT 0x10 670 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 671 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 672 #define SDMA0_VERSION__REV_MASK 0x003F0000L 673 //SDMA0_EDC_COUNTER 674 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 675 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 676 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 677 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 678 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 679 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 680 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 681 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 682 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 683 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 684 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 685 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 686 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 687 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 688 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 689 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 690 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 691 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 692 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 693 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 694 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 695 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 696 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 697 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 698 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 699 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 700 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 701 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 702 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 703 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 704 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 705 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 706 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 707 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 708 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 709 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 710 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 711 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 712 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 713 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 714 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 715 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 716 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 717 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 718 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 719 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 720 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 721 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 722 //SDMA0_EDC_COUNTER_CLEAR 723 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 724 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 725 //SDMA0_STATUS2_REG 726 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 727 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 728 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 729 #define SDMA0_STATUS2_REG__ID_MASK 0x00000007L 730 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 731 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 732 //SDMA0_ATOMIC_CNTL 733 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 734 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 735 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 736 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 737 //SDMA0_ATOMIC_PREOP_LO 738 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 739 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 740 //SDMA0_ATOMIC_PREOP_HI 741 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 742 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 743 //SDMA0_UTCL1_CNTL 744 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 745 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 746 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 747 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 748 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 749 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 750 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 751 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 752 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 753 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 754 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 755 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 756 //SDMA0_UTCL1_WATERMK 757 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 758 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 759 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 760 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 761 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 762 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 763 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 764 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 765 //SDMA0_UTCL1_RD_STATUS 766 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 767 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 768 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 769 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 770 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 771 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 772 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 773 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 774 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 775 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 776 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 777 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 778 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 779 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 780 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 781 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 782 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 783 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 784 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 785 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 786 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 787 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 788 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 789 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 790 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 791 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 792 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 793 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 794 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 795 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 796 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 797 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 798 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 799 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 800 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 801 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 802 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 803 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 804 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 805 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 806 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 807 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 808 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 809 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 810 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 811 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 812 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 813 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 814 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 815 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 816 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 817 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 818 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 819 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 820 //SDMA0_UTCL1_WR_STATUS 821 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 822 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 823 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 824 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 825 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 826 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 827 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 828 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 829 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 830 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 831 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 832 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 833 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 834 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 835 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 836 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 837 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 838 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 839 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 840 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 841 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 842 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 843 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 844 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 845 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 846 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 847 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 848 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 849 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 850 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 851 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 852 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 853 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 854 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 855 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 856 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 857 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 858 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 859 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 860 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 861 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 862 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 863 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 864 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 865 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 866 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 867 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 868 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 869 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 870 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 871 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 872 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 873 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 874 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 875 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 876 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 877 //SDMA0_UTCL1_INV0 878 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 879 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 880 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 881 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 882 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 883 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 884 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 885 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 886 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 887 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 888 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 889 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 890 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 891 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 892 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 893 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 894 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 895 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 896 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 897 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 898 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 899 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 900 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 901 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 902 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 903 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 904 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 905 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 906 //SDMA0_UTCL1_INV1 907 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 908 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 909 //SDMA0_UTCL1_INV2 910 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 911 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 912 //SDMA0_UTCL1_RD_XNACK0 913 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 914 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 915 //SDMA0_UTCL1_RD_XNACK1 916 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 917 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 918 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 919 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 920 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 921 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 922 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 923 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 924 //SDMA0_UTCL1_WR_XNACK0 925 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 926 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 927 //SDMA0_UTCL1_WR_XNACK1 928 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 929 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 930 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 931 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 932 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 933 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 934 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 935 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 936 //SDMA0_UTCL1_TIMEOUT 937 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 938 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 939 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 940 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 941 //SDMA0_UTCL1_PAGE 942 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 943 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 944 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 945 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 946 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 947 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 948 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 949 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 950 //SDMA0_POWER_CNTL_IDLE 951 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 952 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 953 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 954 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 955 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 956 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 957 //SDMA0_RELAX_ORDERING_LUT 958 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 959 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 960 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 961 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 962 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 963 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 964 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 965 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 966 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 967 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 968 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 969 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 970 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 971 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 972 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 973 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 974 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 975 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 976 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 977 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 978 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 979 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 980 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 981 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 982 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 983 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 984 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 985 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 986 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 987 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 988 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 989 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 990 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 991 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 992 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 993 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 994 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 995 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 996 //SDMA0_CHICKEN_BITS_2 997 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 998 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 999 //SDMA0_STATUS3_REG 1000 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 1001 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 1002 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 1003 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 1004 #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 1005 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 1006 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 1007 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 1008 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 1009 #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 1010 //SDMA0_PHYSICAL_ADDR_LO 1011 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 1012 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 1013 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 1014 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 1015 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 1016 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 1017 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 1018 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 1019 //SDMA0_PHYSICAL_ADDR_HI 1020 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 1021 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 1022 //SDMA0_PHASE2_QUANTUM 1023 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1024 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1025 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1026 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1027 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1028 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1029 //SDMA0_ERROR_LOG 1030 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1031 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1032 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1033 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1034 //SDMA0_PUB_DUMMY_REG0 1035 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1036 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1037 //SDMA0_PUB_DUMMY_REG1 1038 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1039 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1040 //SDMA0_PUB_DUMMY_REG2 1041 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1042 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1043 //SDMA0_PUB_DUMMY_REG3 1044 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1045 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1046 //SDMA0_F32_COUNTER 1047 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1048 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1049 //SDMA0_UNBREAKABLE 1050 #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1051 #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1052 //SDMA0_PERFMON_CNTL 1053 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1054 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1055 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1056 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1057 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1058 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1059 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1060 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1061 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1062 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1063 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1064 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1065 //SDMA0_PERFCOUNTER0_RESULT 1066 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1067 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1068 //SDMA0_PERFCOUNTER1_RESULT 1069 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1070 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1071 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1072 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1073 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1074 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1075 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1076 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1077 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1078 //SDMA0_CRD_CNTL 1079 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1080 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1081 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1082 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1083 //SDMA0_GPU_IOV_VIOLATION_LOG 1084 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1085 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1086 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1087 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 1088 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 1089 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 1090 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1091 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1092 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 1093 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L 1094 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L 1095 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L 1096 //SDMA0_ULV_CNTL 1097 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1098 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1099 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1100 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1101 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1102 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1103 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1104 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1105 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1106 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1107 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1108 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1109 //SDMA0_EA_DBIT_ADDR_DATA 1110 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1111 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1112 //SDMA0_EA_DBIT_ADDR_INDEX 1113 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1114 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1115 //SDMA0_GPU_IOV_VIOLATION_LOG2 1116 #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 1117 #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL 1118 //SDMA0_GFX_RB_CNTL 1119 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1120 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1121 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1122 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1123 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1124 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1125 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1126 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1127 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1128 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1129 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1130 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1131 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1132 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1133 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1134 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1135 //SDMA0_GFX_RB_BASE 1136 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1137 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1138 //SDMA0_GFX_RB_BASE_HI 1139 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1140 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1141 //SDMA0_GFX_RB_RPTR 1142 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1143 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1144 //SDMA0_GFX_RB_RPTR_HI 1145 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1146 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1147 //SDMA0_GFX_RB_WPTR 1148 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1149 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1150 //SDMA0_GFX_RB_WPTR_HI 1151 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1152 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1153 //SDMA0_GFX_RB_WPTR_POLL_CNTL 1154 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1155 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1156 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1157 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1158 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1159 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1160 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1161 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1162 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1163 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1164 //SDMA0_GFX_RB_RPTR_ADDR_HI 1165 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1166 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1167 //SDMA0_GFX_RB_RPTR_ADDR_LO 1168 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1169 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1170 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1171 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1172 //SDMA0_GFX_IB_CNTL 1173 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1174 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1175 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1176 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1177 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1178 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1179 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1180 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1181 //SDMA0_GFX_IB_RPTR 1182 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1183 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1184 //SDMA0_GFX_IB_OFFSET 1185 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1186 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1187 //SDMA0_GFX_IB_BASE_LO 1188 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1189 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1190 //SDMA0_GFX_IB_BASE_HI 1191 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1192 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1193 //SDMA0_GFX_IB_SIZE 1194 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1195 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1196 //SDMA0_GFX_SKIP_CNTL 1197 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1198 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1199 //SDMA0_GFX_CONTEXT_STATUS 1200 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1201 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1202 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1203 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1204 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1205 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1206 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1207 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1208 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1209 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1210 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1211 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1212 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1213 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1214 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1215 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1216 //SDMA0_GFX_DOORBELL 1217 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1218 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1219 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1220 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1221 //SDMA0_GFX_CONTEXT_CNTL 1222 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1223 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1224 //SDMA0_GFX_STATUS 1225 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1226 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1227 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1228 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1229 //SDMA0_GFX_DOORBELL_LOG 1230 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1231 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1232 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1233 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1234 //SDMA0_GFX_WATERMARK 1235 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1236 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1237 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1238 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1239 //SDMA0_GFX_DOORBELL_OFFSET 1240 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1241 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1242 //SDMA0_GFX_CSA_ADDR_LO 1243 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1244 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1245 //SDMA0_GFX_CSA_ADDR_HI 1246 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1247 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1248 //SDMA0_GFX_IB_SUB_REMAIN 1249 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1250 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1251 //SDMA0_GFX_PREEMPT 1252 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1253 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1254 //SDMA0_GFX_DUMMY_REG 1255 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1256 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1257 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1258 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1259 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1260 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1261 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1262 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1263 //SDMA0_GFX_RB_AQL_CNTL 1264 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1265 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1266 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1267 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1268 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1269 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1270 //SDMA0_GFX_MINOR_PTR_UPDATE 1271 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1272 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1273 //SDMA0_GFX_MIDCMD_DATA0 1274 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1275 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1276 //SDMA0_GFX_MIDCMD_DATA1 1277 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1278 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1279 //SDMA0_GFX_MIDCMD_DATA2 1280 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1281 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1282 //SDMA0_GFX_MIDCMD_DATA3 1283 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1284 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1285 //SDMA0_GFX_MIDCMD_DATA4 1286 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1287 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1288 //SDMA0_GFX_MIDCMD_DATA5 1289 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1290 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1291 //SDMA0_GFX_MIDCMD_DATA6 1292 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1293 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1294 //SDMA0_GFX_MIDCMD_DATA7 1295 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1296 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1297 //SDMA0_GFX_MIDCMD_DATA8 1298 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1299 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1300 //SDMA0_GFX_MIDCMD_CNTL 1301 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1302 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1303 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1304 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1305 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1306 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1307 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1308 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1309 //SDMA0_PAGE_RB_CNTL 1310 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1311 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1312 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1313 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1314 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1315 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1316 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1317 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1318 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1319 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1320 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1321 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1322 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1323 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1324 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1325 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1326 //SDMA0_PAGE_RB_BASE 1327 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1328 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1329 //SDMA0_PAGE_RB_BASE_HI 1330 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1331 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1332 //SDMA0_PAGE_RB_RPTR 1333 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1334 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1335 //SDMA0_PAGE_RB_RPTR_HI 1336 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1337 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1338 //SDMA0_PAGE_RB_WPTR 1339 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1340 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1341 //SDMA0_PAGE_RB_WPTR_HI 1342 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1343 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1344 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1345 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1346 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1347 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1348 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1349 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1350 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1351 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1352 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1353 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1354 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1355 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1356 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1357 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1358 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1359 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1360 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1361 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1362 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1363 //SDMA0_PAGE_IB_CNTL 1364 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1365 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1366 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1367 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1368 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1369 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1370 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1371 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1372 //SDMA0_PAGE_IB_RPTR 1373 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1374 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1375 //SDMA0_PAGE_IB_OFFSET 1376 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1377 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1378 //SDMA0_PAGE_IB_BASE_LO 1379 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1380 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1381 //SDMA0_PAGE_IB_BASE_HI 1382 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1383 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1384 //SDMA0_PAGE_IB_SIZE 1385 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1386 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1387 //SDMA0_PAGE_SKIP_CNTL 1388 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1389 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1390 //SDMA0_PAGE_CONTEXT_STATUS 1391 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1392 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1393 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1394 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1395 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1396 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1397 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1398 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1399 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1400 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1401 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1402 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1403 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1404 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1405 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1406 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1407 //SDMA0_PAGE_DOORBELL 1408 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1409 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1410 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1411 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1412 //SDMA0_PAGE_STATUS 1413 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1414 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1415 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1416 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1417 //SDMA0_PAGE_DOORBELL_LOG 1418 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1419 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1420 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1421 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1422 //SDMA0_PAGE_WATERMARK 1423 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1424 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1425 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1426 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1427 //SDMA0_PAGE_DOORBELL_OFFSET 1428 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1429 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1430 //SDMA0_PAGE_CSA_ADDR_LO 1431 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1432 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1433 //SDMA0_PAGE_CSA_ADDR_HI 1434 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1435 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1436 //SDMA0_PAGE_IB_SUB_REMAIN 1437 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1438 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1439 //SDMA0_PAGE_PREEMPT 1440 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1441 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1442 //SDMA0_PAGE_DUMMY_REG 1443 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1444 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1445 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1446 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1447 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1448 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1449 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1450 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1451 //SDMA0_PAGE_RB_AQL_CNTL 1452 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1453 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1454 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1455 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1456 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1457 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1458 //SDMA0_PAGE_MINOR_PTR_UPDATE 1459 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1460 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1461 //SDMA0_PAGE_MIDCMD_DATA0 1462 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1463 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1464 //SDMA0_PAGE_MIDCMD_DATA1 1465 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1466 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1467 //SDMA0_PAGE_MIDCMD_DATA2 1468 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1469 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1470 //SDMA0_PAGE_MIDCMD_DATA3 1471 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1472 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1473 //SDMA0_PAGE_MIDCMD_DATA4 1474 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1475 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1476 //SDMA0_PAGE_MIDCMD_DATA5 1477 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1478 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1479 //SDMA0_PAGE_MIDCMD_DATA6 1480 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1481 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1482 //SDMA0_PAGE_MIDCMD_DATA7 1483 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1484 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1485 //SDMA0_PAGE_MIDCMD_DATA8 1486 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1487 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1488 //SDMA0_PAGE_MIDCMD_CNTL 1489 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1490 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1491 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1492 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1493 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1494 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1495 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1496 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1497 //SDMA0_RLC0_RB_CNTL 1498 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1499 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1500 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1501 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1502 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1503 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1504 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1505 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1506 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1507 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1508 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1509 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1510 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1511 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1512 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1513 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1514 //SDMA0_RLC0_RB_BASE 1515 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1516 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1517 //SDMA0_RLC0_RB_BASE_HI 1518 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1519 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1520 //SDMA0_RLC0_RB_RPTR 1521 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1522 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1523 //SDMA0_RLC0_RB_RPTR_HI 1524 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1525 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1526 //SDMA0_RLC0_RB_WPTR 1527 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1528 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1529 //SDMA0_RLC0_RB_WPTR_HI 1530 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1531 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1532 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1533 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1534 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1535 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1536 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1537 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1538 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1539 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1540 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1541 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1542 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1543 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1544 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1545 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1546 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1547 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1548 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1549 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1550 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1551 //SDMA0_RLC0_IB_CNTL 1552 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1553 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1554 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1555 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1556 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1557 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1558 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1559 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1560 //SDMA0_RLC0_IB_RPTR 1561 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1562 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1563 //SDMA0_RLC0_IB_OFFSET 1564 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1565 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1566 //SDMA0_RLC0_IB_BASE_LO 1567 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1568 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1569 //SDMA0_RLC0_IB_BASE_HI 1570 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1571 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1572 //SDMA0_RLC0_IB_SIZE 1573 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1574 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1575 //SDMA0_RLC0_SKIP_CNTL 1576 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1577 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1578 //SDMA0_RLC0_CONTEXT_STATUS 1579 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1580 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1581 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1582 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1583 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1584 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1585 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1586 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1587 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1588 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1589 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1590 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1591 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1592 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1593 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1594 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1595 //SDMA0_RLC0_DOORBELL 1596 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1597 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1598 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1599 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1600 //SDMA0_RLC0_STATUS 1601 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1602 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1603 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1604 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1605 //SDMA0_RLC0_DOORBELL_LOG 1606 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1607 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1608 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1609 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1610 //SDMA0_RLC0_WATERMARK 1611 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1612 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1613 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1614 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1615 //SDMA0_RLC0_DOORBELL_OFFSET 1616 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1617 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1618 //SDMA0_RLC0_CSA_ADDR_LO 1619 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1620 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1621 //SDMA0_RLC0_CSA_ADDR_HI 1622 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1623 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1624 //SDMA0_RLC0_IB_SUB_REMAIN 1625 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1626 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1627 //SDMA0_RLC0_PREEMPT 1628 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1629 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1630 //SDMA0_RLC0_DUMMY_REG 1631 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1632 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1633 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1634 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1635 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1636 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1637 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1638 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1639 //SDMA0_RLC0_RB_AQL_CNTL 1640 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1641 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1642 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1643 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1644 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1645 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1646 //SDMA0_RLC0_MINOR_PTR_UPDATE 1647 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1648 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1649 //SDMA0_RLC0_MIDCMD_DATA0 1650 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1651 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1652 //SDMA0_RLC0_MIDCMD_DATA1 1653 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1654 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1655 //SDMA0_RLC0_MIDCMD_DATA2 1656 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1657 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1658 //SDMA0_RLC0_MIDCMD_DATA3 1659 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1660 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1661 //SDMA0_RLC0_MIDCMD_DATA4 1662 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1663 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1664 //SDMA0_RLC0_MIDCMD_DATA5 1665 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1666 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1667 //SDMA0_RLC0_MIDCMD_DATA6 1668 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1669 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1670 //SDMA0_RLC0_MIDCMD_DATA7 1671 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1672 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1673 //SDMA0_RLC0_MIDCMD_DATA8 1674 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1675 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1676 //SDMA0_RLC0_MIDCMD_CNTL 1677 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1678 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1679 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1680 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1681 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1682 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1683 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1684 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1685 //SDMA0_RLC1_RB_CNTL 1686 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1687 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1688 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1689 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1690 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1691 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1692 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1693 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1694 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1695 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1696 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1697 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1698 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1699 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1700 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1701 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1702 //SDMA0_RLC1_RB_BASE 1703 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1704 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1705 //SDMA0_RLC1_RB_BASE_HI 1706 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1707 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1708 //SDMA0_RLC1_RB_RPTR 1709 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1710 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1711 //SDMA0_RLC1_RB_RPTR_HI 1712 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1713 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1714 //SDMA0_RLC1_RB_WPTR 1715 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1716 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1717 //SDMA0_RLC1_RB_WPTR_HI 1718 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1719 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1720 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1721 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1722 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1723 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1724 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1725 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1726 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1727 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1728 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1729 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1730 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1731 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1732 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1733 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1734 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1735 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1736 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1737 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1738 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1739 //SDMA0_RLC1_IB_CNTL 1740 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1741 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1742 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1743 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1744 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1745 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1746 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1747 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1748 //SDMA0_RLC1_IB_RPTR 1749 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1750 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1751 //SDMA0_RLC1_IB_OFFSET 1752 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1753 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1754 //SDMA0_RLC1_IB_BASE_LO 1755 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1756 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1757 //SDMA0_RLC1_IB_BASE_HI 1758 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1759 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1760 //SDMA0_RLC1_IB_SIZE 1761 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1762 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1763 //SDMA0_RLC1_SKIP_CNTL 1764 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1765 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1766 //SDMA0_RLC1_CONTEXT_STATUS 1767 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1768 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1769 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1770 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1771 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1772 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1773 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1774 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1775 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1776 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1777 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1778 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1779 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1780 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1781 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1782 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1783 //SDMA0_RLC1_DOORBELL 1784 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1785 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1786 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1787 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1788 //SDMA0_RLC1_STATUS 1789 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1790 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1791 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1792 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1793 //SDMA0_RLC1_DOORBELL_LOG 1794 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1795 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1796 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1797 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1798 //SDMA0_RLC1_WATERMARK 1799 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1800 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1801 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1802 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1803 //SDMA0_RLC1_DOORBELL_OFFSET 1804 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1805 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1806 //SDMA0_RLC1_CSA_ADDR_LO 1807 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1808 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1809 //SDMA0_RLC1_CSA_ADDR_HI 1810 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1811 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1812 //SDMA0_RLC1_IB_SUB_REMAIN 1813 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1814 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1815 //SDMA0_RLC1_PREEMPT 1816 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1817 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1818 //SDMA0_RLC1_DUMMY_REG 1819 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1820 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1821 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1822 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1823 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1824 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1825 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1826 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1827 //SDMA0_RLC1_RB_AQL_CNTL 1828 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1829 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1830 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1831 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1832 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1833 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1834 //SDMA0_RLC1_MINOR_PTR_UPDATE 1835 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1836 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1837 //SDMA0_RLC1_MIDCMD_DATA0 1838 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1839 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1840 //SDMA0_RLC1_MIDCMD_DATA1 1841 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1842 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1843 //SDMA0_RLC1_MIDCMD_DATA2 1844 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1845 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1846 //SDMA0_RLC1_MIDCMD_DATA3 1847 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1848 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1849 //SDMA0_RLC1_MIDCMD_DATA4 1850 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1851 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1852 //SDMA0_RLC1_MIDCMD_DATA5 1853 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1854 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1855 //SDMA0_RLC1_MIDCMD_DATA6 1856 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1857 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1858 //SDMA0_RLC1_MIDCMD_DATA7 1859 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1860 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1861 //SDMA0_RLC1_MIDCMD_DATA8 1862 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1863 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1864 //SDMA0_RLC1_MIDCMD_CNTL 1865 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1866 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1867 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1868 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1869 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1870 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1871 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1872 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1873 //SDMA0_RLC2_RB_CNTL 1874 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1875 #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1876 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1877 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1878 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1879 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1880 #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1881 #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1882 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1883 #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1884 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1885 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1886 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1887 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1888 #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1889 #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1890 //SDMA0_RLC2_RB_BASE 1891 #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1892 #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1893 //SDMA0_RLC2_RB_BASE_HI 1894 #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1895 #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1896 //SDMA0_RLC2_RB_RPTR 1897 #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1898 #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1899 //SDMA0_RLC2_RB_RPTR_HI 1900 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1901 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1902 //SDMA0_RLC2_RB_WPTR 1903 #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1904 #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1905 //SDMA0_RLC2_RB_WPTR_HI 1906 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1907 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1908 //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1909 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1910 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1911 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1912 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1913 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1914 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1915 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1916 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1917 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1918 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1919 //SDMA0_RLC2_RB_RPTR_ADDR_HI 1920 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1921 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1922 //SDMA0_RLC2_RB_RPTR_ADDR_LO 1923 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1924 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1925 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1926 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1927 //SDMA0_RLC2_IB_CNTL 1928 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1929 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1930 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1931 #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1932 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1933 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1934 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1935 #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1936 //SDMA0_RLC2_IB_RPTR 1937 #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1938 #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1939 //SDMA0_RLC2_IB_OFFSET 1940 #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1941 #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1942 //SDMA0_RLC2_IB_BASE_LO 1943 #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1944 #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1945 //SDMA0_RLC2_IB_BASE_HI 1946 #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1947 #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1948 //SDMA0_RLC2_IB_SIZE 1949 #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1950 #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1951 //SDMA0_RLC2_SKIP_CNTL 1952 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1953 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1954 //SDMA0_RLC2_CONTEXT_STATUS 1955 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1956 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1957 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1958 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1959 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1960 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1961 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1962 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1963 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1964 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1965 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1966 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1967 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1968 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1969 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1970 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1971 //SDMA0_RLC2_DOORBELL 1972 #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1973 #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1974 #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1975 #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1976 //SDMA0_RLC2_STATUS 1977 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1978 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1979 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1980 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1981 //SDMA0_RLC2_DOORBELL_LOG 1982 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1983 #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1984 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1985 #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1986 //SDMA0_RLC2_WATERMARK 1987 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1988 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1989 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1990 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1991 //SDMA0_RLC2_DOORBELL_OFFSET 1992 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1993 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1994 //SDMA0_RLC2_CSA_ADDR_LO 1995 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1996 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1997 //SDMA0_RLC2_CSA_ADDR_HI 1998 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1999 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2000 //SDMA0_RLC2_IB_SUB_REMAIN 2001 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2002 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2003 //SDMA0_RLC2_PREEMPT 2004 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 2005 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2006 //SDMA0_RLC2_DUMMY_REG 2007 #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 2008 #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2009 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 2010 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2011 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2012 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 2013 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2014 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2015 //SDMA0_RLC2_RB_AQL_CNTL 2016 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2017 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2018 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2019 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2020 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2021 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2022 //SDMA0_RLC2_MINOR_PTR_UPDATE 2023 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2024 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2025 //SDMA0_RLC2_MIDCMD_DATA0 2026 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2027 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2028 //SDMA0_RLC2_MIDCMD_DATA1 2029 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2030 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2031 //SDMA0_RLC2_MIDCMD_DATA2 2032 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2033 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2034 //SDMA0_RLC2_MIDCMD_DATA3 2035 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2036 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2037 //SDMA0_RLC2_MIDCMD_DATA4 2038 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2039 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2040 //SDMA0_RLC2_MIDCMD_DATA5 2041 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2042 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2043 //SDMA0_RLC2_MIDCMD_DATA6 2044 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2045 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2046 //SDMA0_RLC2_MIDCMD_DATA7 2047 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2048 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2049 //SDMA0_RLC2_MIDCMD_DATA8 2050 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2051 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2052 //SDMA0_RLC2_MIDCMD_CNTL 2053 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2054 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2055 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2056 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2057 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2058 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2059 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2060 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2061 //SDMA0_RLC3_RB_CNTL 2062 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2063 #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2064 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2065 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2066 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2067 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2068 #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2069 #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2070 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2071 #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2072 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2073 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2074 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2075 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2076 #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2077 #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2078 //SDMA0_RLC3_RB_BASE 2079 #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 2080 #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2081 //SDMA0_RLC3_RB_BASE_HI 2082 #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2083 #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2084 //SDMA0_RLC3_RB_RPTR 2085 #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2086 #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2087 //SDMA0_RLC3_RB_RPTR_HI 2088 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2089 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2090 //SDMA0_RLC3_RB_WPTR 2091 #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2092 #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2093 //SDMA0_RLC3_RB_WPTR_HI 2094 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2095 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2096 //SDMA0_RLC3_RB_WPTR_POLL_CNTL 2097 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2098 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2099 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2100 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2101 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2102 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2103 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2104 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2105 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2106 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2107 //SDMA0_RLC3_RB_RPTR_ADDR_HI 2108 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2109 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2110 //SDMA0_RLC3_RB_RPTR_ADDR_LO 2111 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2112 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2113 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2114 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2115 //SDMA0_RLC3_IB_CNTL 2116 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2117 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2118 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2119 #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2120 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2121 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2122 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2123 #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2124 //SDMA0_RLC3_IB_RPTR 2125 #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2126 #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2127 //SDMA0_RLC3_IB_OFFSET 2128 #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2129 #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2130 //SDMA0_RLC3_IB_BASE_LO 2131 #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2132 #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2133 //SDMA0_RLC3_IB_BASE_HI 2134 #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2135 #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2136 //SDMA0_RLC3_IB_SIZE 2137 #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2138 #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2139 //SDMA0_RLC3_SKIP_CNTL 2140 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2141 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2142 //SDMA0_RLC3_CONTEXT_STATUS 2143 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2144 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2145 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2146 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2147 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2148 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2149 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2150 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2151 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2152 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2153 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2154 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2155 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2156 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2157 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2158 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2159 //SDMA0_RLC3_DOORBELL 2160 #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2161 #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2162 #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2163 #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2164 //SDMA0_RLC3_STATUS 2165 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2166 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2167 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2168 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2169 //SDMA0_RLC3_DOORBELL_LOG 2170 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2171 #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2172 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2173 #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2174 //SDMA0_RLC3_WATERMARK 2175 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2176 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2177 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2178 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2179 //SDMA0_RLC3_DOORBELL_OFFSET 2180 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2181 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2182 //SDMA0_RLC3_CSA_ADDR_LO 2183 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2184 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2185 //SDMA0_RLC3_CSA_ADDR_HI 2186 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2187 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2188 //SDMA0_RLC3_IB_SUB_REMAIN 2189 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2190 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2191 //SDMA0_RLC3_PREEMPT 2192 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2193 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2194 //SDMA0_RLC3_DUMMY_REG 2195 #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2196 #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2197 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2198 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2199 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2200 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2201 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2202 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2203 //SDMA0_RLC3_RB_AQL_CNTL 2204 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2205 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2206 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2207 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2208 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2209 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2210 //SDMA0_RLC3_MINOR_PTR_UPDATE 2211 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2212 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2213 //SDMA0_RLC3_MIDCMD_DATA0 2214 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2215 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2216 //SDMA0_RLC3_MIDCMD_DATA1 2217 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2218 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2219 //SDMA0_RLC3_MIDCMD_DATA2 2220 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2221 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2222 //SDMA0_RLC3_MIDCMD_DATA3 2223 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2224 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2225 //SDMA0_RLC3_MIDCMD_DATA4 2226 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2227 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2228 //SDMA0_RLC3_MIDCMD_DATA5 2229 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2230 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2231 //SDMA0_RLC3_MIDCMD_DATA6 2232 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2233 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2234 //SDMA0_RLC3_MIDCMD_DATA7 2235 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2236 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2237 //SDMA0_RLC3_MIDCMD_DATA8 2238 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2239 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2240 //SDMA0_RLC3_MIDCMD_CNTL 2241 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2242 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2243 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2244 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2245 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2246 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2247 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2248 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2249 //SDMA0_RLC4_RB_CNTL 2250 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2251 #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2252 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2253 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2254 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2255 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2256 #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2257 #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2258 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2259 #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2260 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2261 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2262 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2263 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2264 #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2265 #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2266 //SDMA0_RLC4_RB_BASE 2267 #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2268 #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2269 //SDMA0_RLC4_RB_BASE_HI 2270 #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2271 #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2272 //SDMA0_RLC4_RB_RPTR 2273 #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2274 #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2275 //SDMA0_RLC4_RB_RPTR_HI 2276 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2277 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2278 //SDMA0_RLC4_RB_WPTR 2279 #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2280 #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2281 //SDMA0_RLC4_RB_WPTR_HI 2282 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2283 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2284 //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2285 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2286 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2287 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2288 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2289 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2290 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2291 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2292 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2293 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2294 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2295 //SDMA0_RLC4_RB_RPTR_ADDR_HI 2296 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2297 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2298 //SDMA0_RLC4_RB_RPTR_ADDR_LO 2299 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2300 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2301 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2302 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2303 //SDMA0_RLC4_IB_CNTL 2304 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2305 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2306 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2307 #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2308 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2309 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2310 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2311 #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2312 //SDMA0_RLC4_IB_RPTR 2313 #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2314 #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2315 //SDMA0_RLC4_IB_OFFSET 2316 #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2317 #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2318 //SDMA0_RLC4_IB_BASE_LO 2319 #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2320 #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2321 //SDMA0_RLC4_IB_BASE_HI 2322 #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2323 #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2324 //SDMA0_RLC4_IB_SIZE 2325 #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2326 #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2327 //SDMA0_RLC4_SKIP_CNTL 2328 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2329 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2330 //SDMA0_RLC4_CONTEXT_STATUS 2331 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2332 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2333 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2334 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2335 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2336 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2337 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2338 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2339 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2340 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2341 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2342 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2343 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2344 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2345 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2346 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2347 //SDMA0_RLC4_DOORBELL 2348 #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2349 #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2350 #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2351 #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2352 //SDMA0_RLC4_STATUS 2353 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2354 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2355 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2356 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2357 //SDMA0_RLC4_DOORBELL_LOG 2358 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2359 #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2360 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2361 #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2362 //SDMA0_RLC4_WATERMARK 2363 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2364 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2365 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2366 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2367 //SDMA0_RLC4_DOORBELL_OFFSET 2368 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2369 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2370 //SDMA0_RLC4_CSA_ADDR_LO 2371 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2372 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2373 //SDMA0_RLC4_CSA_ADDR_HI 2374 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2375 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2376 //SDMA0_RLC4_IB_SUB_REMAIN 2377 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2378 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2379 //SDMA0_RLC4_PREEMPT 2380 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2381 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2382 //SDMA0_RLC4_DUMMY_REG 2383 #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2384 #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2385 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2386 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2387 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2388 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2389 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2390 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2391 //SDMA0_RLC4_RB_AQL_CNTL 2392 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2393 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2394 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2395 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2396 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2397 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2398 //SDMA0_RLC4_MINOR_PTR_UPDATE 2399 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2400 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2401 //SDMA0_RLC4_MIDCMD_DATA0 2402 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2403 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2404 //SDMA0_RLC4_MIDCMD_DATA1 2405 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2406 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2407 //SDMA0_RLC4_MIDCMD_DATA2 2408 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2409 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2410 //SDMA0_RLC4_MIDCMD_DATA3 2411 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2412 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2413 //SDMA0_RLC4_MIDCMD_DATA4 2414 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2415 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2416 //SDMA0_RLC4_MIDCMD_DATA5 2417 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2418 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2419 //SDMA0_RLC4_MIDCMD_DATA6 2420 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2421 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2422 //SDMA0_RLC4_MIDCMD_DATA7 2423 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2424 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2425 //SDMA0_RLC4_MIDCMD_DATA8 2426 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2427 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2428 //SDMA0_RLC4_MIDCMD_CNTL 2429 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2430 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2431 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2432 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2433 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2434 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2435 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2436 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2437 //SDMA0_RLC5_RB_CNTL 2438 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2439 #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2440 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2441 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2442 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2443 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2444 #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2445 #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2446 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2447 #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2448 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2449 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2450 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2451 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2452 #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2453 #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2454 //SDMA0_RLC5_RB_BASE 2455 #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2456 #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2457 //SDMA0_RLC5_RB_BASE_HI 2458 #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2459 #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2460 //SDMA0_RLC5_RB_RPTR 2461 #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2462 #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2463 //SDMA0_RLC5_RB_RPTR_HI 2464 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2465 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2466 //SDMA0_RLC5_RB_WPTR 2467 #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2468 #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2469 //SDMA0_RLC5_RB_WPTR_HI 2470 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2471 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2472 //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2473 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2474 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2475 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2476 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2477 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2478 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2479 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2480 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2481 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2482 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2483 //SDMA0_RLC5_RB_RPTR_ADDR_HI 2484 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2485 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2486 //SDMA0_RLC5_RB_RPTR_ADDR_LO 2487 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2488 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2489 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2490 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2491 //SDMA0_RLC5_IB_CNTL 2492 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2493 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2494 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2495 #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2496 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2497 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2498 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2499 #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2500 //SDMA0_RLC5_IB_RPTR 2501 #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2502 #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2503 //SDMA0_RLC5_IB_OFFSET 2504 #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2505 #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2506 //SDMA0_RLC5_IB_BASE_LO 2507 #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2508 #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2509 //SDMA0_RLC5_IB_BASE_HI 2510 #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2511 #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2512 //SDMA0_RLC5_IB_SIZE 2513 #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2514 #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2515 //SDMA0_RLC5_SKIP_CNTL 2516 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2517 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2518 //SDMA0_RLC5_CONTEXT_STATUS 2519 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2520 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2521 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2522 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2523 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2524 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2525 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2526 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2527 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2528 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2529 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2530 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2531 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2532 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2533 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2534 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2535 //SDMA0_RLC5_DOORBELL 2536 #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2537 #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2538 #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2539 #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2540 //SDMA0_RLC5_STATUS 2541 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2542 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2543 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2544 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2545 //SDMA0_RLC5_DOORBELL_LOG 2546 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2547 #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2548 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2549 #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2550 //SDMA0_RLC5_WATERMARK 2551 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2552 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2553 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2554 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2555 //SDMA0_RLC5_DOORBELL_OFFSET 2556 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2557 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2558 //SDMA0_RLC5_CSA_ADDR_LO 2559 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2560 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2561 //SDMA0_RLC5_CSA_ADDR_HI 2562 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2563 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2564 //SDMA0_RLC5_IB_SUB_REMAIN 2565 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2566 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2567 //SDMA0_RLC5_PREEMPT 2568 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2569 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2570 //SDMA0_RLC5_DUMMY_REG 2571 #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2572 #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2573 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2574 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2575 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2576 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2577 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2578 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2579 //SDMA0_RLC5_RB_AQL_CNTL 2580 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2581 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2582 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2583 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2584 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2585 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2586 //SDMA0_RLC5_MINOR_PTR_UPDATE 2587 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2588 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2589 //SDMA0_RLC5_MIDCMD_DATA0 2590 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2591 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2592 //SDMA0_RLC5_MIDCMD_DATA1 2593 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2594 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2595 //SDMA0_RLC5_MIDCMD_DATA2 2596 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2597 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2598 //SDMA0_RLC5_MIDCMD_DATA3 2599 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2600 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2601 //SDMA0_RLC5_MIDCMD_DATA4 2602 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2603 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2604 //SDMA0_RLC5_MIDCMD_DATA5 2605 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2606 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2607 //SDMA0_RLC5_MIDCMD_DATA6 2608 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2609 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2610 //SDMA0_RLC5_MIDCMD_DATA7 2611 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2612 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2613 //SDMA0_RLC5_MIDCMD_DATA8 2614 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2615 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2616 //SDMA0_RLC5_MIDCMD_CNTL 2617 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2618 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2619 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2620 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2621 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2622 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2623 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2624 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2625 //SDMA0_RLC6_RB_CNTL 2626 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2627 #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2628 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2629 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2630 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2631 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2632 #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2633 #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2634 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2635 #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2636 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2637 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2638 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2639 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2640 #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2641 #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2642 //SDMA0_RLC6_RB_BASE 2643 #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2644 #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2645 //SDMA0_RLC6_RB_BASE_HI 2646 #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2647 #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2648 //SDMA0_RLC6_RB_RPTR 2649 #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2650 #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2651 //SDMA0_RLC6_RB_RPTR_HI 2652 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2653 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2654 //SDMA0_RLC6_RB_WPTR 2655 #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2656 #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2657 //SDMA0_RLC6_RB_WPTR_HI 2658 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2659 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2660 //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2661 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2662 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2663 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2664 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2665 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2666 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2667 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2668 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2669 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2670 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2671 //SDMA0_RLC6_RB_RPTR_ADDR_HI 2672 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2673 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2674 //SDMA0_RLC6_RB_RPTR_ADDR_LO 2675 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2676 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2677 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2678 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2679 //SDMA0_RLC6_IB_CNTL 2680 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2681 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2682 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2683 #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2684 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2685 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2686 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2687 #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2688 //SDMA0_RLC6_IB_RPTR 2689 #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2690 #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2691 //SDMA0_RLC6_IB_OFFSET 2692 #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2693 #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2694 //SDMA0_RLC6_IB_BASE_LO 2695 #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2696 #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2697 //SDMA0_RLC6_IB_BASE_HI 2698 #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2699 #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2700 //SDMA0_RLC6_IB_SIZE 2701 #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2702 #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2703 //SDMA0_RLC6_SKIP_CNTL 2704 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2705 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2706 //SDMA0_RLC6_CONTEXT_STATUS 2707 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2708 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2709 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2710 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2711 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2712 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2713 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2714 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2715 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2716 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2717 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2718 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2719 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2720 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2721 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2722 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2723 //SDMA0_RLC6_DOORBELL 2724 #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2725 #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2726 #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2727 #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2728 //SDMA0_RLC6_STATUS 2729 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2730 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2731 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2732 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2733 //SDMA0_RLC6_DOORBELL_LOG 2734 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2735 #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2736 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2737 #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2738 //SDMA0_RLC6_WATERMARK 2739 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2740 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2741 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2742 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2743 //SDMA0_RLC6_DOORBELL_OFFSET 2744 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2745 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2746 //SDMA0_RLC6_CSA_ADDR_LO 2747 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2748 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2749 //SDMA0_RLC6_CSA_ADDR_HI 2750 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2751 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2752 //SDMA0_RLC6_IB_SUB_REMAIN 2753 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2754 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2755 //SDMA0_RLC6_PREEMPT 2756 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2757 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2758 //SDMA0_RLC6_DUMMY_REG 2759 #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2760 #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2761 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2762 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2763 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2764 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2765 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2766 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2767 //SDMA0_RLC6_RB_AQL_CNTL 2768 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2769 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2770 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2771 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2772 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2773 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2774 //SDMA0_RLC6_MINOR_PTR_UPDATE 2775 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2776 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2777 //SDMA0_RLC6_MIDCMD_DATA0 2778 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2779 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2780 //SDMA0_RLC6_MIDCMD_DATA1 2781 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2782 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2783 //SDMA0_RLC6_MIDCMD_DATA2 2784 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2785 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2786 //SDMA0_RLC6_MIDCMD_DATA3 2787 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2788 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2789 //SDMA0_RLC6_MIDCMD_DATA4 2790 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2791 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2792 //SDMA0_RLC6_MIDCMD_DATA5 2793 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2794 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2795 //SDMA0_RLC6_MIDCMD_DATA6 2796 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2797 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2798 //SDMA0_RLC6_MIDCMD_DATA7 2799 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2800 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2801 //SDMA0_RLC6_MIDCMD_DATA8 2802 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2803 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2804 //SDMA0_RLC6_MIDCMD_CNTL 2805 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2806 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2807 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2808 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2809 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2810 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2811 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2812 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2813 //SDMA0_RLC7_RB_CNTL 2814 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2815 #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2816 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2817 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2818 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2819 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2820 #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2821 #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2822 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2823 #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2824 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2825 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2826 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2827 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2828 #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2829 #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2830 //SDMA0_RLC7_RB_BASE 2831 #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2832 #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2833 //SDMA0_RLC7_RB_BASE_HI 2834 #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2835 #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2836 //SDMA0_RLC7_RB_RPTR 2837 #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2838 #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2839 //SDMA0_RLC7_RB_RPTR_HI 2840 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2841 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2842 //SDMA0_RLC7_RB_WPTR 2843 #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2844 #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2845 //SDMA0_RLC7_RB_WPTR_HI 2846 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2847 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2848 //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2849 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2850 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2851 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2852 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2853 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2854 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2855 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2856 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2857 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2858 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2859 //SDMA0_RLC7_RB_RPTR_ADDR_HI 2860 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2861 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2862 //SDMA0_RLC7_RB_RPTR_ADDR_LO 2863 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2864 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2865 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2866 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2867 //SDMA0_RLC7_IB_CNTL 2868 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2869 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2870 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2871 #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2872 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2873 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2874 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2875 #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2876 //SDMA0_RLC7_IB_RPTR 2877 #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2878 #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2879 //SDMA0_RLC7_IB_OFFSET 2880 #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2881 #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2882 //SDMA0_RLC7_IB_BASE_LO 2883 #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2884 #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2885 //SDMA0_RLC7_IB_BASE_HI 2886 #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2887 #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2888 //SDMA0_RLC7_IB_SIZE 2889 #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2890 #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2891 //SDMA0_RLC7_SKIP_CNTL 2892 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2893 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2894 //SDMA0_RLC7_CONTEXT_STATUS 2895 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2896 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2897 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2898 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2899 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2900 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2901 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2902 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2903 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2904 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2905 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2906 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2907 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2908 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2909 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2910 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2911 //SDMA0_RLC7_DOORBELL 2912 #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2913 #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2914 #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2915 #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2916 //SDMA0_RLC7_STATUS 2917 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2918 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2919 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2920 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2921 //SDMA0_RLC7_DOORBELL_LOG 2922 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2923 #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2924 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2925 #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2926 //SDMA0_RLC7_WATERMARK 2927 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2928 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2929 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2930 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2931 //SDMA0_RLC7_DOORBELL_OFFSET 2932 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2933 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2934 //SDMA0_RLC7_CSA_ADDR_LO 2935 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2936 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2937 //SDMA0_RLC7_CSA_ADDR_HI 2938 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2939 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2940 //SDMA0_RLC7_IB_SUB_REMAIN 2941 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2942 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2943 //SDMA0_RLC7_PREEMPT 2944 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2945 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2946 //SDMA0_RLC7_DUMMY_REG 2947 #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2948 #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2949 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2950 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2951 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2952 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2953 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2954 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2955 //SDMA0_RLC7_RB_AQL_CNTL 2956 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2957 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2958 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2959 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2960 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2961 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2962 //SDMA0_RLC7_MINOR_PTR_UPDATE 2963 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2964 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2965 //SDMA0_RLC7_MIDCMD_DATA0 2966 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2967 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2968 //SDMA0_RLC7_MIDCMD_DATA1 2969 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2970 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2971 //SDMA0_RLC7_MIDCMD_DATA2 2972 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2973 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2974 //SDMA0_RLC7_MIDCMD_DATA3 2975 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2976 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2977 //SDMA0_RLC7_MIDCMD_DATA4 2978 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2979 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2980 //SDMA0_RLC7_MIDCMD_DATA5 2981 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2982 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2983 //SDMA0_RLC7_MIDCMD_DATA6 2984 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2985 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2986 //SDMA0_RLC7_MIDCMD_DATA7 2987 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2988 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2989 //SDMA0_RLC7_MIDCMD_DATA8 2990 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2991 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2992 //SDMA0_RLC7_MIDCMD_CNTL 2993 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2994 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2995 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2996 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2997 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2998 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2999 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 3000 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 3001 3002 #endif 3003