1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _sdma0_4_2_0_SH_MASK_HEADER 22 #define _sdma0_4_2_0_SH_MASK_HEADER 23 24 25 // addressBlock: sdma0_sdma0dec 26 //SDMA0_UCODE_ADDR 27 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 //SDMA0_UCODE_DATA 30 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 //SDMA0_VM_CNTL 33 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35 //SDMA0_VM_CTX_LO 36 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 //SDMA0_VM_CTX_HI 39 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 //SDMA0_ACTIVE_FCN_ID 42 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 //SDMA0_VM_CTX_CNTL 49 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 //SDMA0_VIRT_RESET_REQ 54 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 //SDMA0_VF_ENABLE 59 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 //SDMA0_CONTEXT_REG_TYPE0 62 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 //SDMA0_CONTEXT_REG_TYPE1 103 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 //SDMA0_CONTEXT_REG_TYPE2 134 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 //SDMA0_CONTEXT_REG_TYPE3 157 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 //SDMA0_PUB_REG_TYPE0 160 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162 #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189 #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196 #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 //SDMA0_PUB_REG_TYPE1 215 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279 //SDMA0_PUB_REG_TYPE2 280 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 303 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 304 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 305 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 306 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 307 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 308 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 309 #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 310 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 311 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 312 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 313 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 314 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 315 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 316 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 317 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 318 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 319 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 320 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 321 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 322 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 323 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 324 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 325 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 326 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 327 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 328 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 329 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 330 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 331 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 332 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 333 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 334 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 335 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 336 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 337 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 338 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 339 #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 340 //SDMA0_PUB_REG_TYPE3 341 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 342 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 343 #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 344 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 345 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 346 #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 347 //SDMA0_MMHUB_CNTL 348 #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 349 #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 350 //SDMA0_CONTEXT_GROUP_BOUNDARY 351 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 352 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 353 //SDMA0_POWER_CNTL 354 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 355 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 356 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 357 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 358 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 364 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 365 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 366 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 367 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 368 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 369 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 370 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 371 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 372 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 373 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 374 //SDMA0_CLK_CTRL 375 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397 //SDMA0_CNTL 398 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420 //SDMA0_CHICKEN_BITS 421 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447 //SDMA0_GB_ADDR_CONFIG 448 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458 //SDMA0_GB_ADDR_CONFIG_READ 459 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469 //SDMA0_RB_RPTR_FETCH_HI 470 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475 //SDMA0_RB_RPTR_FETCH 476 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478 //SDMA0_IB_OFFSET_FETCH 479 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481 //SDMA0_PROGRAM 482 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484 //SDMA0_STATUS_REG 485 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543 //SDMA0_STATUS1_REG 544 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572 //SDMA0_RD_BURST_CNTL 573 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 575 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 576 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 577 //SDMA0_HBM_PAGE_CONFIG 578 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 579 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 580 //SDMA0_UCODE_CHECKSUM 581 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 582 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 583 //SDMA0_F32_CNTL 584 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 585 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 586 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 587 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 588 //SDMA0_FREEZE 589 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 590 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 591 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 592 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 593 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 594 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 595 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 596 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 597 //SDMA0_PHASE0_QUANTUM 598 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 599 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 600 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 601 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 602 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 603 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 604 //SDMA0_PHASE1_QUANTUM 605 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 606 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 607 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 608 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 609 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 610 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 611 //SDMA_POWER_GATING 612 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 613 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 614 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 615 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 616 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 617 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 618 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 619 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 620 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 621 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 622 //SDMA_PGFSM_CONFIG 623 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 624 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 625 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 626 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 627 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 628 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 629 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 630 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 631 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 632 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 633 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 634 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 635 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 636 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 637 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 638 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 639 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 640 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 641 //SDMA_PGFSM_WRITE 642 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 643 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 644 //SDMA_PGFSM_READ 645 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 646 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 647 //SDMA0_EDC_CONFIG 648 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 649 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 650 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 651 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 652 //SDMA0_BA_THRESHOLD 653 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 654 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 655 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 656 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 657 //SDMA0_ID 658 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 659 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 660 //SDMA0_VERSION 661 #define SDMA0_VERSION__MINVER__SHIFT 0x0 662 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 663 #define SDMA0_VERSION__REV__SHIFT 0x10 664 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 665 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 666 #define SDMA0_VERSION__REV_MASK 0x003F0000L 667 //SDMA0_EDC_COUNTER 668 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 669 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 670 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 671 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 672 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 673 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 674 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 675 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 676 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 677 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 678 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 679 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 680 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 681 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 682 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 683 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 684 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 685 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 686 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 687 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 688 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 689 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 690 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 691 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 692 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 693 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 694 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 695 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 696 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 697 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 698 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 699 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 700 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 701 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 702 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 703 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 704 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 705 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 706 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 707 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 708 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 709 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 710 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 711 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 712 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 713 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 714 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 715 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 716 //SDMA0_EDC_COUNTER_CLEAR 717 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 718 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 719 //SDMA0_STATUS2_REG 720 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 721 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 722 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 723 #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 724 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 725 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 726 //SDMA0_ATOMIC_CNTL 727 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 728 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 729 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 730 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 731 //SDMA0_ATOMIC_PREOP_LO 732 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 733 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 734 //SDMA0_ATOMIC_PREOP_HI 735 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 736 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 737 //SDMA0_UTCL1_CNTL 738 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 739 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 740 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 741 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 742 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 743 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 744 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 745 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 746 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 747 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 748 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 749 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 750 //SDMA0_UTCL1_WATERMK 751 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 752 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 753 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 754 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 755 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 756 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 757 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 758 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 759 //SDMA0_UTCL1_RD_STATUS 760 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 761 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 762 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 763 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 764 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 765 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 766 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 767 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 768 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 769 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 770 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 771 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 772 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 773 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 774 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 775 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 776 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 777 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 778 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 779 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 780 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 781 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 782 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 783 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 784 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 785 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 786 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 787 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 788 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 789 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 790 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 791 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 792 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 793 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 794 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 795 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 796 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 797 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 798 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 799 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 800 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 801 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 802 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 803 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 804 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 805 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 806 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 807 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 808 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 809 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 810 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 811 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 812 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 813 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 814 //SDMA0_UTCL1_WR_STATUS 815 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 816 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 817 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 818 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 819 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 820 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 821 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 822 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 823 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 824 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 825 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 826 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 827 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 828 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 829 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 830 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 831 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 832 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 833 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 834 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 835 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 836 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 837 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 838 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 839 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 840 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 841 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 842 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 843 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 844 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 845 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 846 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 847 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 848 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 849 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 850 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 851 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 852 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 853 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 854 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 855 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 856 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 857 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 858 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 859 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 860 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 861 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 862 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 863 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 864 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 865 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 866 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 867 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 868 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 869 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 870 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 871 //SDMA0_UTCL1_INV0 872 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 873 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 874 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 875 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 876 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 877 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 878 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 879 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 880 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 881 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 882 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 883 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 884 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 885 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 886 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 887 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 888 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 889 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 890 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 891 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 892 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 893 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 894 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 895 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 896 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 897 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 898 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 899 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 900 //SDMA0_UTCL1_INV1 901 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 902 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 903 //SDMA0_UTCL1_INV2 904 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 905 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 906 //SDMA0_UTCL1_RD_XNACK0 907 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 908 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 909 //SDMA0_UTCL1_RD_XNACK1 910 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 911 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 912 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 913 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 914 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 915 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 916 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 917 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 918 //SDMA0_UTCL1_WR_XNACK0 919 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 920 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 921 //SDMA0_UTCL1_WR_XNACK1 922 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 923 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 924 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 925 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 926 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 927 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 928 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 929 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 930 //SDMA0_UTCL1_TIMEOUT 931 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 932 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 933 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 934 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 935 //SDMA0_UTCL1_PAGE 936 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 937 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 938 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 939 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 940 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 941 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 942 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 943 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 944 //SDMA0_POWER_CNTL_IDLE 945 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 946 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 947 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 948 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 949 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 950 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 951 //SDMA0_RELAX_ORDERING_LUT 952 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 953 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 954 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 955 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 956 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 957 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 958 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 959 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 960 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 961 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 962 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 963 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 964 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 965 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 966 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 967 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 968 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 969 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 970 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 971 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 972 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 973 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 974 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 975 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 976 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 977 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 978 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 979 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 980 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 981 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 982 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 983 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 984 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 985 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 986 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 987 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 988 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 989 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 990 //SDMA0_CHICKEN_BITS_2 991 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 992 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 993 //SDMA0_STATUS3_REG 994 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 995 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 996 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 997 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 998 #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 999 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 1000 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 1001 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 1002 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 1003 #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 1004 //SDMA0_PHYSICAL_ADDR_LO 1005 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 1006 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 1007 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 1008 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 1009 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 1010 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 1011 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 1012 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 1013 //SDMA0_PHYSICAL_ADDR_HI 1014 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 1015 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 1016 //SDMA0_PHASE2_QUANTUM 1017 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1018 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1019 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1020 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1021 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1022 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1023 //SDMA0_ERROR_LOG 1024 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1025 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1026 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1027 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1028 //SDMA0_PUB_DUMMY_REG0 1029 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1030 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1031 //SDMA0_PUB_DUMMY_REG1 1032 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1033 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1034 //SDMA0_PUB_DUMMY_REG2 1035 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1036 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1037 //SDMA0_PUB_DUMMY_REG3 1038 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1039 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1040 //SDMA0_F32_COUNTER 1041 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1042 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1043 //SDMA0_PERFMON_CNTL 1044 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1045 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1046 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1047 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1048 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1049 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1050 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1051 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1052 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1053 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1054 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1055 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1056 //SDMA0_PERFCOUNTER0_RESULT 1057 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1058 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1059 //SDMA0_PERFCOUNTER1_RESULT 1060 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1061 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1062 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1063 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1064 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1065 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1066 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1067 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1068 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1069 //SDMA0_CRD_CNTL 1070 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1071 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1072 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1073 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1074 //SDMA0_GPU_IOV_VIOLATION_LOG 1075 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089 //SDMA0_ULV_CNTL 1090 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1092 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1093 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1094 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1095 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1096 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1097 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1098 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1099 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1100 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1101 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1102 //SDMA0_EA_DBIT_ADDR_DATA 1103 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1104 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1105 //SDMA0_EA_DBIT_ADDR_INDEX 1106 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1107 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1108 //SDMA0_GFX_RB_CNTL 1109 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1110 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1111 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1112 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1113 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1114 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1115 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1116 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1117 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1118 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1119 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1120 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1121 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1122 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1123 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1124 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1125 //SDMA0_GFX_RB_BASE 1126 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1127 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1128 //SDMA0_GFX_RB_BASE_HI 1129 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1130 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1131 //SDMA0_GFX_RB_RPTR 1132 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1133 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1134 //SDMA0_GFX_RB_RPTR_HI 1135 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1136 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1137 //SDMA0_GFX_RB_WPTR 1138 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1139 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1140 //SDMA0_GFX_RB_WPTR_HI 1141 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1142 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1143 //SDMA0_GFX_RB_WPTR_POLL_CNTL 1144 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1145 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1146 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1147 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1148 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1149 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1150 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1151 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1152 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1153 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1154 //SDMA0_GFX_RB_RPTR_ADDR_HI 1155 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1156 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1157 //SDMA0_GFX_RB_RPTR_ADDR_LO 1158 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1159 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1160 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1161 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1162 //SDMA0_GFX_IB_CNTL 1163 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1164 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1165 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1166 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1167 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1168 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1169 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1170 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1171 //SDMA0_GFX_IB_RPTR 1172 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1173 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1174 //SDMA0_GFX_IB_OFFSET 1175 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1176 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1177 //SDMA0_GFX_IB_BASE_LO 1178 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1179 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1180 //SDMA0_GFX_IB_BASE_HI 1181 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1182 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1183 //SDMA0_GFX_IB_SIZE 1184 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1185 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1186 //SDMA0_GFX_SKIP_CNTL 1187 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1188 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1189 //SDMA0_GFX_CONTEXT_STATUS 1190 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1191 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1192 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1193 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1194 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1195 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1196 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1197 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1198 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1199 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1200 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1201 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1202 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1203 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1204 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1205 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1206 //SDMA0_GFX_DOORBELL 1207 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1208 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1209 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1210 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1211 //SDMA0_GFX_CONTEXT_CNTL 1212 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1213 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1214 //SDMA0_GFX_STATUS 1215 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1216 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1217 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1218 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1219 //SDMA0_GFX_DOORBELL_LOG 1220 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1221 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1222 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1223 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1224 //SDMA0_GFX_WATERMARK 1225 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1226 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1227 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1228 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1229 //SDMA0_GFX_DOORBELL_OFFSET 1230 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1231 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1232 //SDMA0_GFX_CSA_ADDR_LO 1233 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1234 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1235 //SDMA0_GFX_CSA_ADDR_HI 1236 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1237 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1238 //SDMA0_GFX_IB_SUB_REMAIN 1239 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1240 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1241 //SDMA0_GFX_PREEMPT 1242 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1243 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1244 //SDMA0_GFX_DUMMY_REG 1245 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1246 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1247 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1248 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1249 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1250 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1251 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1252 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1253 //SDMA0_GFX_RB_AQL_CNTL 1254 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1255 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1256 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1257 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1258 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1259 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1260 //SDMA0_GFX_MINOR_PTR_UPDATE 1261 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1262 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1263 //SDMA0_GFX_MIDCMD_DATA0 1264 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1265 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1266 //SDMA0_GFX_MIDCMD_DATA1 1267 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1268 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1269 //SDMA0_GFX_MIDCMD_DATA2 1270 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1271 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1272 //SDMA0_GFX_MIDCMD_DATA3 1273 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1274 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1275 //SDMA0_GFX_MIDCMD_DATA4 1276 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1277 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1278 //SDMA0_GFX_MIDCMD_DATA5 1279 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1280 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1281 //SDMA0_GFX_MIDCMD_DATA6 1282 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1283 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1284 //SDMA0_GFX_MIDCMD_DATA7 1285 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1286 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1287 //SDMA0_GFX_MIDCMD_DATA8 1288 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1289 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1290 //SDMA0_GFX_MIDCMD_CNTL 1291 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1292 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1293 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1294 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1295 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1296 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1297 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1298 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1299 //SDMA0_PAGE_RB_CNTL 1300 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1301 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1302 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1303 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1304 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1305 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1306 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1307 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1308 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1309 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1310 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1311 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1312 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1313 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1314 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1315 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1316 //SDMA0_PAGE_RB_BASE 1317 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1318 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1319 //SDMA0_PAGE_RB_BASE_HI 1320 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1321 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1322 //SDMA0_PAGE_RB_RPTR 1323 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1324 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1325 //SDMA0_PAGE_RB_RPTR_HI 1326 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1327 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328 //SDMA0_PAGE_RB_WPTR 1329 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1330 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1331 //SDMA0_PAGE_RB_WPTR_HI 1332 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1333 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1334 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1335 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1336 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1337 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1338 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1339 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1340 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1341 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1342 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1343 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1344 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1345 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1346 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1347 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1348 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1349 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1350 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1351 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1352 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1353 //SDMA0_PAGE_IB_CNTL 1354 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1355 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1356 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1357 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1358 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1359 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1360 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1361 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1362 //SDMA0_PAGE_IB_RPTR 1363 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1364 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1365 //SDMA0_PAGE_IB_OFFSET 1366 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1367 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1368 //SDMA0_PAGE_IB_BASE_LO 1369 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1370 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1371 //SDMA0_PAGE_IB_BASE_HI 1372 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1373 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1374 //SDMA0_PAGE_IB_SIZE 1375 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1376 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1377 //SDMA0_PAGE_SKIP_CNTL 1378 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1379 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1380 //SDMA0_PAGE_CONTEXT_STATUS 1381 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1382 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1383 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1384 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1385 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1386 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1387 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1388 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1389 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1390 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1391 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1392 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1393 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1394 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1395 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1396 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1397 //SDMA0_PAGE_DOORBELL 1398 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1399 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1400 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1401 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1402 //SDMA0_PAGE_STATUS 1403 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1404 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1405 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1406 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1407 //SDMA0_PAGE_DOORBELL_LOG 1408 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1409 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1410 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1411 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1412 //SDMA0_PAGE_WATERMARK 1413 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1414 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1415 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1416 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1417 //SDMA0_PAGE_DOORBELL_OFFSET 1418 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1419 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1420 //SDMA0_PAGE_CSA_ADDR_LO 1421 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1422 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1423 //SDMA0_PAGE_CSA_ADDR_HI 1424 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1425 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1426 //SDMA0_PAGE_IB_SUB_REMAIN 1427 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1428 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1429 //SDMA0_PAGE_PREEMPT 1430 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1431 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1432 //SDMA0_PAGE_DUMMY_REG 1433 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1434 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1435 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1436 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1437 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1438 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1439 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1440 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1441 //SDMA0_PAGE_RB_AQL_CNTL 1442 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1443 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1444 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1445 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1446 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1447 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1448 //SDMA0_PAGE_MINOR_PTR_UPDATE 1449 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1450 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1451 //SDMA0_PAGE_MIDCMD_DATA0 1452 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1453 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1454 //SDMA0_PAGE_MIDCMD_DATA1 1455 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1456 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1457 //SDMA0_PAGE_MIDCMD_DATA2 1458 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1459 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1460 //SDMA0_PAGE_MIDCMD_DATA3 1461 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1462 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1463 //SDMA0_PAGE_MIDCMD_DATA4 1464 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1465 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1466 //SDMA0_PAGE_MIDCMD_DATA5 1467 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1468 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1469 //SDMA0_PAGE_MIDCMD_DATA6 1470 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1471 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1472 //SDMA0_PAGE_MIDCMD_DATA7 1473 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1474 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1475 //SDMA0_PAGE_MIDCMD_DATA8 1476 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1477 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1478 //SDMA0_PAGE_MIDCMD_CNTL 1479 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1480 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1481 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1482 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1483 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1484 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1485 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1486 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1487 //SDMA0_RLC0_RB_CNTL 1488 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1489 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1490 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1491 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1492 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1493 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1494 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1495 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1496 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1497 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1498 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1499 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1500 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1501 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1502 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1503 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1504 //SDMA0_RLC0_RB_BASE 1505 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1506 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1507 //SDMA0_RLC0_RB_BASE_HI 1508 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1509 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1510 //SDMA0_RLC0_RB_RPTR 1511 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1512 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1513 //SDMA0_RLC0_RB_RPTR_HI 1514 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1515 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1516 //SDMA0_RLC0_RB_WPTR 1517 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1518 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1519 //SDMA0_RLC0_RB_WPTR_HI 1520 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1521 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1522 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1523 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1524 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1525 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1526 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1527 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1528 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1529 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1530 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1531 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1532 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1533 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1534 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1535 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1536 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1537 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1538 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1539 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1540 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1541 //SDMA0_RLC0_IB_CNTL 1542 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1543 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1544 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1545 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1546 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1547 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1548 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1549 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1550 //SDMA0_RLC0_IB_RPTR 1551 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1552 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1553 //SDMA0_RLC0_IB_OFFSET 1554 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1555 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1556 //SDMA0_RLC0_IB_BASE_LO 1557 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1558 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1559 //SDMA0_RLC0_IB_BASE_HI 1560 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1561 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1562 //SDMA0_RLC0_IB_SIZE 1563 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1564 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1565 //SDMA0_RLC0_SKIP_CNTL 1566 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1567 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1568 //SDMA0_RLC0_CONTEXT_STATUS 1569 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1570 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1571 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1572 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1573 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1574 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1575 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1576 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1577 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1578 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1579 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1580 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1581 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1582 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1583 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1584 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1585 //SDMA0_RLC0_DOORBELL 1586 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1587 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1588 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1589 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1590 //SDMA0_RLC0_STATUS 1591 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1592 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1593 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1594 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1595 //SDMA0_RLC0_DOORBELL_LOG 1596 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1597 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1598 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1599 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1600 //SDMA0_RLC0_WATERMARK 1601 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1602 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1603 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1604 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1605 //SDMA0_RLC0_DOORBELL_OFFSET 1606 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1607 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1608 //SDMA0_RLC0_CSA_ADDR_LO 1609 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1610 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1611 //SDMA0_RLC0_CSA_ADDR_HI 1612 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1613 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1614 //SDMA0_RLC0_IB_SUB_REMAIN 1615 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1616 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1617 //SDMA0_RLC0_PREEMPT 1618 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1619 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1620 //SDMA0_RLC0_DUMMY_REG 1621 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1622 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1623 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1624 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1625 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1626 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1627 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1628 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1629 //SDMA0_RLC0_RB_AQL_CNTL 1630 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1631 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1632 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1633 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1634 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1635 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1636 //SDMA0_RLC0_MINOR_PTR_UPDATE 1637 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1638 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1639 //SDMA0_RLC0_MIDCMD_DATA0 1640 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1641 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1642 //SDMA0_RLC0_MIDCMD_DATA1 1643 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1644 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1645 //SDMA0_RLC0_MIDCMD_DATA2 1646 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1647 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1648 //SDMA0_RLC0_MIDCMD_DATA3 1649 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1650 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1651 //SDMA0_RLC0_MIDCMD_DATA4 1652 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1653 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1654 //SDMA0_RLC0_MIDCMD_DATA5 1655 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1656 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1657 //SDMA0_RLC0_MIDCMD_DATA6 1658 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1659 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1660 //SDMA0_RLC0_MIDCMD_DATA7 1661 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1662 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1663 //SDMA0_RLC0_MIDCMD_DATA8 1664 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1665 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1666 //SDMA0_RLC0_MIDCMD_CNTL 1667 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1668 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1669 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1670 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1671 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1672 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1673 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1674 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1675 //SDMA0_RLC1_RB_CNTL 1676 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1677 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1678 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1679 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1680 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1681 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1682 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1683 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1684 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1685 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1686 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1687 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1688 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1689 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1690 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1691 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1692 //SDMA0_RLC1_RB_BASE 1693 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1694 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1695 //SDMA0_RLC1_RB_BASE_HI 1696 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1697 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1698 //SDMA0_RLC1_RB_RPTR 1699 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1700 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1701 //SDMA0_RLC1_RB_RPTR_HI 1702 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1703 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1704 //SDMA0_RLC1_RB_WPTR 1705 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1706 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1707 //SDMA0_RLC1_RB_WPTR_HI 1708 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1709 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1710 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1711 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1712 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1713 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1714 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1715 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1716 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1717 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1718 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1719 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1720 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1721 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1722 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1723 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1724 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1725 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1726 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1727 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1728 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1729 //SDMA0_RLC1_IB_CNTL 1730 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1731 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1732 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1733 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1734 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1735 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1736 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1737 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1738 //SDMA0_RLC1_IB_RPTR 1739 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1740 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1741 //SDMA0_RLC1_IB_OFFSET 1742 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1743 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1744 //SDMA0_RLC1_IB_BASE_LO 1745 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1746 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1747 //SDMA0_RLC1_IB_BASE_HI 1748 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1749 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1750 //SDMA0_RLC1_IB_SIZE 1751 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1752 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1753 //SDMA0_RLC1_SKIP_CNTL 1754 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1755 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1756 //SDMA0_RLC1_CONTEXT_STATUS 1757 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1758 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1759 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1760 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1761 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1762 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1763 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1764 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1765 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1766 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1767 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1768 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1769 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1770 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1771 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1772 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1773 //SDMA0_RLC1_DOORBELL 1774 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1775 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1776 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1777 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1778 //SDMA0_RLC1_STATUS 1779 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1780 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1781 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1782 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1783 //SDMA0_RLC1_DOORBELL_LOG 1784 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1785 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1786 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1787 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1788 //SDMA0_RLC1_WATERMARK 1789 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1790 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1791 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1792 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1793 //SDMA0_RLC1_DOORBELL_OFFSET 1794 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1795 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1796 //SDMA0_RLC1_CSA_ADDR_LO 1797 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1798 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1799 //SDMA0_RLC1_CSA_ADDR_HI 1800 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1801 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802 //SDMA0_RLC1_IB_SUB_REMAIN 1803 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1804 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1805 //SDMA0_RLC1_PREEMPT 1806 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1807 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1808 //SDMA0_RLC1_DUMMY_REG 1809 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1810 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1811 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1812 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1813 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1814 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1815 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1816 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1817 //SDMA0_RLC1_RB_AQL_CNTL 1818 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1819 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1820 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1821 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1822 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1823 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1824 //SDMA0_RLC1_MINOR_PTR_UPDATE 1825 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1826 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1827 //SDMA0_RLC1_MIDCMD_DATA0 1828 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1829 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1830 //SDMA0_RLC1_MIDCMD_DATA1 1831 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1832 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1833 //SDMA0_RLC1_MIDCMD_DATA2 1834 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1835 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1836 //SDMA0_RLC1_MIDCMD_DATA3 1837 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1838 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1839 //SDMA0_RLC1_MIDCMD_DATA4 1840 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1841 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1842 //SDMA0_RLC1_MIDCMD_DATA5 1843 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1844 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1845 //SDMA0_RLC1_MIDCMD_DATA6 1846 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1847 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1848 //SDMA0_RLC1_MIDCMD_DATA7 1849 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1850 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1851 //SDMA0_RLC1_MIDCMD_DATA8 1852 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1853 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1854 //SDMA0_RLC1_MIDCMD_CNTL 1855 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1856 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1857 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1858 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1859 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1860 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1861 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1862 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1863 //SDMA0_RLC2_RB_CNTL 1864 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1865 #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1866 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1867 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1868 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1869 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1870 #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1871 #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1872 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1873 #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1874 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1875 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1876 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1877 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1878 #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1879 #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1880 //SDMA0_RLC2_RB_BASE 1881 #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1882 #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1883 //SDMA0_RLC2_RB_BASE_HI 1884 #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1885 #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1886 //SDMA0_RLC2_RB_RPTR 1887 #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1888 #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1889 //SDMA0_RLC2_RB_RPTR_HI 1890 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1891 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1892 //SDMA0_RLC2_RB_WPTR 1893 #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1894 #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1895 //SDMA0_RLC2_RB_WPTR_HI 1896 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1897 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1898 //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1899 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1900 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1901 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1902 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1903 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1904 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1905 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1906 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1907 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1908 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1909 //SDMA0_RLC2_RB_RPTR_ADDR_HI 1910 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1911 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1912 //SDMA0_RLC2_RB_RPTR_ADDR_LO 1913 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1914 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1915 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1916 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1917 //SDMA0_RLC2_IB_CNTL 1918 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1919 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1920 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1921 #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1922 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1923 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1924 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1925 #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1926 //SDMA0_RLC2_IB_RPTR 1927 #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1928 #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1929 //SDMA0_RLC2_IB_OFFSET 1930 #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1931 #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1932 //SDMA0_RLC2_IB_BASE_LO 1933 #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1934 #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1935 //SDMA0_RLC2_IB_BASE_HI 1936 #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1937 #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1938 //SDMA0_RLC2_IB_SIZE 1939 #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1940 #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1941 //SDMA0_RLC2_SKIP_CNTL 1942 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1943 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1944 //SDMA0_RLC2_CONTEXT_STATUS 1945 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1946 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1947 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1948 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1949 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1950 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1951 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1952 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1953 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1954 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1955 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1956 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1957 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1958 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1959 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1960 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1961 //SDMA0_RLC2_DOORBELL 1962 #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1963 #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1964 #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1965 #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1966 //SDMA0_RLC2_STATUS 1967 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1968 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1969 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1970 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1971 //SDMA0_RLC2_DOORBELL_LOG 1972 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1973 #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1974 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1975 #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1976 //SDMA0_RLC2_WATERMARK 1977 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1978 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1979 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1980 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1981 //SDMA0_RLC2_DOORBELL_OFFSET 1982 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1983 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1984 //SDMA0_RLC2_CSA_ADDR_LO 1985 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1986 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1987 //SDMA0_RLC2_CSA_ADDR_HI 1988 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1989 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1990 //SDMA0_RLC2_IB_SUB_REMAIN 1991 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1992 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1993 //SDMA0_RLC2_PREEMPT 1994 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1995 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1996 //SDMA0_RLC2_DUMMY_REG 1997 #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1998 #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1999 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 2000 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2001 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2002 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 2003 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2004 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2005 //SDMA0_RLC2_RB_AQL_CNTL 2006 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2007 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2008 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2009 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2010 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2011 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2012 //SDMA0_RLC2_MINOR_PTR_UPDATE 2013 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2014 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2015 //SDMA0_RLC2_MIDCMD_DATA0 2016 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2017 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2018 //SDMA0_RLC2_MIDCMD_DATA1 2019 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2020 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2021 //SDMA0_RLC2_MIDCMD_DATA2 2022 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2023 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2024 //SDMA0_RLC2_MIDCMD_DATA3 2025 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2026 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2027 //SDMA0_RLC2_MIDCMD_DATA4 2028 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2029 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2030 //SDMA0_RLC2_MIDCMD_DATA5 2031 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2032 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2033 //SDMA0_RLC2_MIDCMD_DATA6 2034 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2035 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2036 //SDMA0_RLC2_MIDCMD_DATA7 2037 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2038 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2039 //SDMA0_RLC2_MIDCMD_DATA8 2040 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2041 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2042 //SDMA0_RLC2_MIDCMD_CNTL 2043 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2044 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2045 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2046 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2047 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2048 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2049 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2050 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2051 //SDMA0_RLC3_RB_CNTL 2052 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2053 #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2054 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2055 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2056 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2057 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2058 #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2059 #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2060 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2061 #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2062 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2063 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2064 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2065 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2066 #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2067 #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2068 //SDMA0_RLC3_RB_BASE 2069 #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 2070 #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2071 //SDMA0_RLC3_RB_BASE_HI 2072 #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2073 #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2074 //SDMA0_RLC3_RB_RPTR 2075 #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2076 #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2077 //SDMA0_RLC3_RB_RPTR_HI 2078 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2079 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2080 //SDMA0_RLC3_RB_WPTR 2081 #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2082 #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2083 //SDMA0_RLC3_RB_WPTR_HI 2084 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2085 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2086 //SDMA0_RLC3_RB_WPTR_POLL_CNTL 2087 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2088 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2089 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2090 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2091 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2092 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2093 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2094 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2095 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2096 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2097 //SDMA0_RLC3_RB_RPTR_ADDR_HI 2098 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2099 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2100 //SDMA0_RLC3_RB_RPTR_ADDR_LO 2101 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2102 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2103 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2104 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2105 //SDMA0_RLC3_IB_CNTL 2106 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2107 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2108 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2109 #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2110 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2111 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2112 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2113 #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2114 //SDMA0_RLC3_IB_RPTR 2115 #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2116 #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2117 //SDMA0_RLC3_IB_OFFSET 2118 #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2119 #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2120 //SDMA0_RLC3_IB_BASE_LO 2121 #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2122 #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2123 //SDMA0_RLC3_IB_BASE_HI 2124 #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2125 #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2126 //SDMA0_RLC3_IB_SIZE 2127 #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2128 #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2129 //SDMA0_RLC3_SKIP_CNTL 2130 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2131 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2132 //SDMA0_RLC3_CONTEXT_STATUS 2133 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2134 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2135 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2136 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2137 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2138 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2139 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2140 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2141 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2142 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2143 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2144 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2145 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2146 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2147 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2148 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2149 //SDMA0_RLC3_DOORBELL 2150 #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2151 #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2152 #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2153 #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2154 //SDMA0_RLC3_STATUS 2155 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2156 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2157 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2158 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2159 //SDMA0_RLC3_DOORBELL_LOG 2160 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2161 #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2162 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2163 #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2164 //SDMA0_RLC3_WATERMARK 2165 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2166 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2167 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2168 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2169 //SDMA0_RLC3_DOORBELL_OFFSET 2170 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2171 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2172 //SDMA0_RLC3_CSA_ADDR_LO 2173 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2174 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2175 //SDMA0_RLC3_CSA_ADDR_HI 2176 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2177 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2178 //SDMA0_RLC3_IB_SUB_REMAIN 2179 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2180 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2181 //SDMA0_RLC3_PREEMPT 2182 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2183 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2184 //SDMA0_RLC3_DUMMY_REG 2185 #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2186 #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2187 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2188 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2189 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2190 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2191 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2192 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2193 //SDMA0_RLC3_RB_AQL_CNTL 2194 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2195 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2196 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2197 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2198 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2199 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2200 //SDMA0_RLC3_MINOR_PTR_UPDATE 2201 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2202 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2203 //SDMA0_RLC3_MIDCMD_DATA0 2204 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2205 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2206 //SDMA0_RLC3_MIDCMD_DATA1 2207 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2208 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2209 //SDMA0_RLC3_MIDCMD_DATA2 2210 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2211 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2212 //SDMA0_RLC3_MIDCMD_DATA3 2213 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2214 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2215 //SDMA0_RLC3_MIDCMD_DATA4 2216 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2217 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2218 //SDMA0_RLC3_MIDCMD_DATA5 2219 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2220 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2221 //SDMA0_RLC3_MIDCMD_DATA6 2222 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2223 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2224 //SDMA0_RLC3_MIDCMD_DATA7 2225 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2226 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2227 //SDMA0_RLC3_MIDCMD_DATA8 2228 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2229 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2230 //SDMA0_RLC3_MIDCMD_CNTL 2231 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2232 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2233 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2234 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2235 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2236 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2237 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2238 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2239 //SDMA0_RLC4_RB_CNTL 2240 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2241 #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2242 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2243 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2244 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2245 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2246 #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2247 #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2248 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2249 #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2250 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2251 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2252 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2253 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2254 #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2255 #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2256 //SDMA0_RLC4_RB_BASE 2257 #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2258 #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2259 //SDMA0_RLC4_RB_BASE_HI 2260 #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2261 #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2262 //SDMA0_RLC4_RB_RPTR 2263 #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2264 #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2265 //SDMA0_RLC4_RB_RPTR_HI 2266 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2267 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2268 //SDMA0_RLC4_RB_WPTR 2269 #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2270 #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2271 //SDMA0_RLC4_RB_WPTR_HI 2272 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2273 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2274 //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2275 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2276 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2277 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2278 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2279 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2280 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2281 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2282 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2283 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2284 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2285 //SDMA0_RLC4_RB_RPTR_ADDR_HI 2286 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2287 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2288 //SDMA0_RLC4_RB_RPTR_ADDR_LO 2289 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2290 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2291 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2292 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2293 //SDMA0_RLC4_IB_CNTL 2294 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2295 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2296 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2297 #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2298 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2299 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2300 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2301 #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2302 //SDMA0_RLC4_IB_RPTR 2303 #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2304 #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2305 //SDMA0_RLC4_IB_OFFSET 2306 #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2307 #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2308 //SDMA0_RLC4_IB_BASE_LO 2309 #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2310 #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2311 //SDMA0_RLC4_IB_BASE_HI 2312 #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2313 #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2314 //SDMA0_RLC4_IB_SIZE 2315 #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2316 #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2317 //SDMA0_RLC4_SKIP_CNTL 2318 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2319 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2320 //SDMA0_RLC4_CONTEXT_STATUS 2321 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2322 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2323 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2324 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2325 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2326 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2327 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2328 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2329 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2330 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2331 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2332 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2333 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2334 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2335 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2336 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2337 //SDMA0_RLC4_DOORBELL 2338 #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2339 #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2340 #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2341 #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2342 //SDMA0_RLC4_STATUS 2343 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2344 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2345 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2346 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2347 //SDMA0_RLC4_DOORBELL_LOG 2348 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2349 #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2350 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2351 #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2352 //SDMA0_RLC4_WATERMARK 2353 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2354 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2355 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2356 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2357 //SDMA0_RLC4_DOORBELL_OFFSET 2358 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2359 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2360 //SDMA0_RLC4_CSA_ADDR_LO 2361 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2362 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2363 //SDMA0_RLC4_CSA_ADDR_HI 2364 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2365 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2366 //SDMA0_RLC4_IB_SUB_REMAIN 2367 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2368 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2369 //SDMA0_RLC4_PREEMPT 2370 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2371 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2372 //SDMA0_RLC4_DUMMY_REG 2373 #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2374 #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2375 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2376 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2377 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2378 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2379 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2380 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2381 //SDMA0_RLC4_RB_AQL_CNTL 2382 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2383 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2384 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2385 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2386 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2387 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2388 //SDMA0_RLC4_MINOR_PTR_UPDATE 2389 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2390 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2391 //SDMA0_RLC4_MIDCMD_DATA0 2392 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2393 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2394 //SDMA0_RLC4_MIDCMD_DATA1 2395 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2396 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2397 //SDMA0_RLC4_MIDCMD_DATA2 2398 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2399 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2400 //SDMA0_RLC4_MIDCMD_DATA3 2401 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2402 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2403 //SDMA0_RLC4_MIDCMD_DATA4 2404 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2405 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2406 //SDMA0_RLC4_MIDCMD_DATA5 2407 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2408 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2409 //SDMA0_RLC4_MIDCMD_DATA6 2410 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2411 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2412 //SDMA0_RLC4_MIDCMD_DATA7 2413 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2414 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2415 //SDMA0_RLC4_MIDCMD_DATA8 2416 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2417 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2418 //SDMA0_RLC4_MIDCMD_CNTL 2419 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2420 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2421 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2422 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2423 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2424 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2425 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2426 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2427 //SDMA0_RLC5_RB_CNTL 2428 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2429 #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2430 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2431 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2432 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2433 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2434 #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2435 #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2436 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2437 #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2438 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2439 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2440 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2441 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2442 #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2443 #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2444 //SDMA0_RLC5_RB_BASE 2445 #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2446 #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2447 //SDMA0_RLC5_RB_BASE_HI 2448 #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2449 #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2450 //SDMA0_RLC5_RB_RPTR 2451 #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2452 #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2453 //SDMA0_RLC5_RB_RPTR_HI 2454 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2455 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2456 //SDMA0_RLC5_RB_WPTR 2457 #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2458 #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2459 //SDMA0_RLC5_RB_WPTR_HI 2460 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2461 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2462 //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2463 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2464 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2465 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2466 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2467 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2468 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2469 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2470 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2471 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2472 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2473 //SDMA0_RLC5_RB_RPTR_ADDR_HI 2474 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2475 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2476 //SDMA0_RLC5_RB_RPTR_ADDR_LO 2477 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2478 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2479 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2480 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2481 //SDMA0_RLC5_IB_CNTL 2482 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2483 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2484 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2485 #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2486 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2487 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2488 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2489 #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2490 //SDMA0_RLC5_IB_RPTR 2491 #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2492 #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2493 //SDMA0_RLC5_IB_OFFSET 2494 #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2495 #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2496 //SDMA0_RLC5_IB_BASE_LO 2497 #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2498 #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2499 //SDMA0_RLC5_IB_BASE_HI 2500 #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2501 #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2502 //SDMA0_RLC5_IB_SIZE 2503 #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2504 #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2505 //SDMA0_RLC5_SKIP_CNTL 2506 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2507 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2508 //SDMA0_RLC5_CONTEXT_STATUS 2509 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2510 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2511 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2512 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2513 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2514 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2515 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2516 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2517 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2518 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2519 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2520 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2521 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2522 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2523 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2524 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2525 //SDMA0_RLC5_DOORBELL 2526 #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2527 #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2528 #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2529 #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2530 //SDMA0_RLC5_STATUS 2531 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2532 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2533 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2534 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2535 //SDMA0_RLC5_DOORBELL_LOG 2536 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2537 #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2538 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2539 #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2540 //SDMA0_RLC5_WATERMARK 2541 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2542 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2543 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2544 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2545 //SDMA0_RLC5_DOORBELL_OFFSET 2546 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2547 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2548 //SDMA0_RLC5_CSA_ADDR_LO 2549 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2550 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2551 //SDMA0_RLC5_CSA_ADDR_HI 2552 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2553 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2554 //SDMA0_RLC5_IB_SUB_REMAIN 2555 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2556 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2557 //SDMA0_RLC5_PREEMPT 2558 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2559 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2560 //SDMA0_RLC5_DUMMY_REG 2561 #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2562 #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2563 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2564 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2565 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2566 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2567 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2568 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2569 //SDMA0_RLC5_RB_AQL_CNTL 2570 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2571 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2572 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2573 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2574 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2575 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2576 //SDMA0_RLC5_MINOR_PTR_UPDATE 2577 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2578 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2579 //SDMA0_RLC5_MIDCMD_DATA0 2580 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2581 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2582 //SDMA0_RLC5_MIDCMD_DATA1 2583 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2584 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2585 //SDMA0_RLC5_MIDCMD_DATA2 2586 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2587 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2588 //SDMA0_RLC5_MIDCMD_DATA3 2589 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2590 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2591 //SDMA0_RLC5_MIDCMD_DATA4 2592 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2593 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2594 //SDMA0_RLC5_MIDCMD_DATA5 2595 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2596 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2597 //SDMA0_RLC5_MIDCMD_DATA6 2598 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2599 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2600 //SDMA0_RLC5_MIDCMD_DATA7 2601 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2602 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2603 //SDMA0_RLC5_MIDCMD_DATA8 2604 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2605 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2606 //SDMA0_RLC5_MIDCMD_CNTL 2607 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2608 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2609 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2610 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2611 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2612 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2613 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2614 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2615 //SDMA0_RLC6_RB_CNTL 2616 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2617 #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2618 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2619 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2620 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2621 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2622 #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2623 #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2624 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2625 #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2626 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2627 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2628 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2629 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2630 #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2631 #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2632 //SDMA0_RLC6_RB_BASE 2633 #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2634 #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2635 //SDMA0_RLC6_RB_BASE_HI 2636 #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2637 #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2638 //SDMA0_RLC6_RB_RPTR 2639 #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2640 #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2641 //SDMA0_RLC6_RB_RPTR_HI 2642 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2643 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2644 //SDMA0_RLC6_RB_WPTR 2645 #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2646 #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2647 //SDMA0_RLC6_RB_WPTR_HI 2648 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2649 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2650 //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2651 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2652 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2653 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2654 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2655 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2656 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2657 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2658 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2659 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2660 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2661 //SDMA0_RLC6_RB_RPTR_ADDR_HI 2662 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2663 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2664 //SDMA0_RLC6_RB_RPTR_ADDR_LO 2665 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2666 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2667 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2668 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2669 //SDMA0_RLC6_IB_CNTL 2670 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2671 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2672 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2673 #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2674 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2675 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2676 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2677 #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2678 //SDMA0_RLC6_IB_RPTR 2679 #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2680 #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2681 //SDMA0_RLC6_IB_OFFSET 2682 #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2683 #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2684 //SDMA0_RLC6_IB_BASE_LO 2685 #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2686 #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2687 //SDMA0_RLC6_IB_BASE_HI 2688 #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2689 #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2690 //SDMA0_RLC6_IB_SIZE 2691 #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2692 #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2693 //SDMA0_RLC6_SKIP_CNTL 2694 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2695 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2696 //SDMA0_RLC6_CONTEXT_STATUS 2697 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2698 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2699 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2700 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2701 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2702 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2703 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2704 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2705 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2706 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2707 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2708 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2709 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2710 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2711 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2712 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2713 //SDMA0_RLC6_DOORBELL 2714 #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2715 #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2716 #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2717 #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2718 //SDMA0_RLC6_STATUS 2719 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2720 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2721 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2722 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2723 //SDMA0_RLC6_DOORBELL_LOG 2724 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2725 #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2726 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2727 #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2728 //SDMA0_RLC6_WATERMARK 2729 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2730 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2731 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2732 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2733 //SDMA0_RLC6_DOORBELL_OFFSET 2734 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2735 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2736 //SDMA0_RLC6_CSA_ADDR_LO 2737 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2738 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2739 //SDMA0_RLC6_CSA_ADDR_HI 2740 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2741 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2742 //SDMA0_RLC6_IB_SUB_REMAIN 2743 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2744 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2745 //SDMA0_RLC6_PREEMPT 2746 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2747 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2748 //SDMA0_RLC6_DUMMY_REG 2749 #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2750 #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2751 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2752 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2753 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2754 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2755 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2756 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2757 //SDMA0_RLC6_RB_AQL_CNTL 2758 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2759 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2760 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2761 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2762 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2763 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2764 //SDMA0_RLC6_MINOR_PTR_UPDATE 2765 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2766 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2767 //SDMA0_RLC6_MIDCMD_DATA0 2768 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2769 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2770 //SDMA0_RLC6_MIDCMD_DATA1 2771 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2772 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2773 //SDMA0_RLC6_MIDCMD_DATA2 2774 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2775 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2776 //SDMA0_RLC6_MIDCMD_DATA3 2777 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2778 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2779 //SDMA0_RLC6_MIDCMD_DATA4 2780 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2781 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2782 //SDMA0_RLC6_MIDCMD_DATA5 2783 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2784 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2785 //SDMA0_RLC6_MIDCMD_DATA6 2786 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2787 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2788 //SDMA0_RLC6_MIDCMD_DATA7 2789 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2790 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2791 //SDMA0_RLC6_MIDCMD_DATA8 2792 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2793 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2794 //SDMA0_RLC6_MIDCMD_CNTL 2795 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2796 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2797 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2798 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2799 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2800 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2801 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2802 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2803 //SDMA0_RLC7_RB_CNTL 2804 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2805 #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2806 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2807 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2808 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2809 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2810 #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2811 #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2812 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2813 #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2814 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2815 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2816 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2817 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2818 #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2819 #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2820 //SDMA0_RLC7_RB_BASE 2821 #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2822 #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2823 //SDMA0_RLC7_RB_BASE_HI 2824 #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2825 #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2826 //SDMA0_RLC7_RB_RPTR 2827 #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2828 #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2829 //SDMA0_RLC7_RB_RPTR_HI 2830 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2831 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2832 //SDMA0_RLC7_RB_WPTR 2833 #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2834 #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2835 //SDMA0_RLC7_RB_WPTR_HI 2836 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2837 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2838 //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2839 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2840 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2841 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2842 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2843 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2844 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2845 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2846 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2847 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2848 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2849 //SDMA0_RLC7_RB_RPTR_ADDR_HI 2850 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2851 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2852 //SDMA0_RLC7_RB_RPTR_ADDR_LO 2853 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2854 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2855 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2856 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2857 //SDMA0_RLC7_IB_CNTL 2858 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2859 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2860 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2861 #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2862 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2863 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2864 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2865 #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2866 //SDMA0_RLC7_IB_RPTR 2867 #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2868 #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2869 //SDMA0_RLC7_IB_OFFSET 2870 #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2871 #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2872 //SDMA0_RLC7_IB_BASE_LO 2873 #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2874 #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2875 //SDMA0_RLC7_IB_BASE_HI 2876 #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2877 #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2878 //SDMA0_RLC7_IB_SIZE 2879 #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2880 #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2881 //SDMA0_RLC7_SKIP_CNTL 2882 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2883 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2884 //SDMA0_RLC7_CONTEXT_STATUS 2885 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2886 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2887 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2888 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2889 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2890 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2891 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2892 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2893 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2894 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2895 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2896 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2897 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2898 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2899 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2900 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2901 //SDMA0_RLC7_DOORBELL 2902 #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2903 #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2904 #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2905 #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2906 //SDMA0_RLC7_STATUS 2907 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2908 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2909 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2910 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2911 //SDMA0_RLC7_DOORBELL_LOG 2912 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2913 #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2914 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2915 #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2916 //SDMA0_RLC7_WATERMARK 2917 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2918 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2919 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2920 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2921 //SDMA0_RLC7_DOORBELL_OFFSET 2922 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2923 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2924 //SDMA0_RLC7_CSA_ADDR_LO 2925 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2926 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2927 //SDMA0_RLC7_CSA_ADDR_HI 2928 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2929 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2930 //SDMA0_RLC7_IB_SUB_REMAIN 2931 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2932 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2933 //SDMA0_RLC7_PREEMPT 2934 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2935 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2936 //SDMA0_RLC7_DUMMY_REG 2937 #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2938 #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2939 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2940 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2941 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2942 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2943 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2944 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2945 //SDMA0_RLC7_RB_AQL_CNTL 2946 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2947 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2948 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2949 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2950 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2951 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2952 //SDMA0_RLC7_MINOR_PTR_UPDATE 2953 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2954 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2955 //SDMA0_RLC7_MIDCMD_DATA0 2956 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2957 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2958 //SDMA0_RLC7_MIDCMD_DATA1 2959 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2960 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2961 //SDMA0_RLC7_MIDCMD_DATA2 2962 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2963 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2964 //SDMA0_RLC7_MIDCMD_DATA3 2965 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2966 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2967 //SDMA0_RLC7_MIDCMD_DATA4 2968 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2969 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2970 //SDMA0_RLC7_MIDCMD_DATA5 2971 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2972 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2973 //SDMA0_RLC7_MIDCMD_DATA6 2974 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2975 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2976 //SDMA0_RLC7_MIDCMD_DATA7 2977 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2978 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2979 //SDMA0_RLC7_MIDCMD_DATA8 2980 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2981 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2982 //SDMA0_RLC7_MIDCMD_CNTL 2983 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2984 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2985 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2986 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2987 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2988 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2989 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2990 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2991 2992 #endif 2993