1 /* 2 * Copyright (C) 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _smuio_10_0_2_SH_MASK_HEADER 22 23 // addressBlock: smuio_smuio_misc_SmuSmuioDec 24 //SMUIO_MCM_CONFIG 25 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 26 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 27 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5 28 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6 29 #define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 30 #define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 31 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 32 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL 33 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L 34 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L 35 #define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L 36 #define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L 37 //IP_DISCOVERY_VERSION 38 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 39 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 40 //IO_SMUIO_PINSTRAP 41 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0 42 #define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3 43 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L 44 #define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L 45 //SCRATCH_REGISTER0 46 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 47 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 48 //SCRATCH_REGISTER1 49 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 50 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 51 //SCRATCH_REGISTER2 52 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 53 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 54 //SCRATCH_REGISTER3 55 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 56 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 57 //SCRATCH_REGISTER4 58 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 59 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 60 //SCRATCH_REGISTER5 61 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 62 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 63 //SCRATCH_REGISTER6 64 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 65 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 66 //SCRATCH_REGISTER7 67 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 68 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 69 70 // addressBlock: smuio_smuio_reset_SmuSmuioDec 71 //SMUIO_MP_RESET_INTR 72 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 73 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L 74 //SMUIO_SOC_HALT 75 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 76 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 77 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L 78 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L 79 //SMUIO_GFX_MISC_CNTL 80 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 81 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 82 #define SMUIO_GFX_MISC_CNTL__PWR_GFX_DLDO_CLK_SWITCH__SHIFT 0x3 83 #define SMUIO_GFX_MISC_CNTL__PWR_GFX_RLC_CGPG_EN__SHIFT 0x4 84 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 85 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 86 #define SMUIO_GFX_MISC_CNTL__PWR_GFX_DLDO_CLK_SWITCH_MASK 0x00000008L 87 #define SMUIO_GFX_MISC_CNTL__PWR_GFX_RLC_CGPG_EN_MASK 0x00000010L 88 89 // addressBlock: smuio_smuio_ccxctrl_SmuSmuioDec 90 //PWROK_REFCLK_GAP_CYCLES 91 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 92 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 93 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 94 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 95 //GOLDEN_TSC_INCREMENT_UPPER 96 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 97 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 98 //GOLDEN_TSC_INCREMENT_LOWER 99 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 100 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 101 //GOLDEN_TSC_COUNT_UPPER 102 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 103 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 104 //GOLDEN_TSC_COUNT_LOWER 105 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 106 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 107 //GFX_GOLDEN_TSC_SHADOW_UPPER 108 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GfxGoldenTscShadowUpper__SHIFT 0x0 109 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GfxGoldenTscShadowUpper_MASK 0x00FFFFFFL 110 //GFX_GOLDEN_TSC_SHADOW_LOWER 111 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GfxGoldenTscShadowLower__SHIFT 0x0 112 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GfxGoldenTscShadowLower_MASK 0xFFFFFFFFL 113 //SOC_GOLDEN_TSC_SHADOW_UPPER 114 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 115 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL 116 //SOC_GOLDEN_TSC_SHADOW_LOWER 117 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 118 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL 119 //SOC_GAP_PWROK 120 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 121 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 122 123 // addressBlock: smuio_smuio_swtimer_SmuSmuioDec 124 //PWR_VIRT_RESET_REQ 125 #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 126 #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f 127 #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL 128 #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L 129 //PWR_DISP_TIMER_CONTROL 130 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 131 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 132 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 133 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 134 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 135 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 136 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 137 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 138 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 139 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 140 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 141 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 142 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 143 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 144 //PWR_DISP_TIMER2_CONTROL 145 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 146 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 147 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 148 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 149 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 150 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 151 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 152 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 153 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 154 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 155 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 156 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 157 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 158 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 159 //PWR_DISP_TIMER_GLOBAL_CONTROL 160 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 161 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 162 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 163 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 164 //PWR_IH_CONTROL 165 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 166 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 167 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 168 #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f 169 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 170 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 171 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 172 #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L 173 174 // addressBlock: smuio_smuio_svi0_SmuSmuioDec 175 //SMUSVI0_TEL_PLANE0 176 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0 177 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10 178 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL 179 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L 180 //SMUSVI0_PLANE0_CURRENTVID 181 #define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18 182 #define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L 183 184 #endif 185